Photoelectric Detection Convolution Calculation System Based on Programmable Resistor Array

Abstract

This invention discloses a photoelectric detection convolution calculation system based on a programmable resistor array. It comprises a photoelectric detection array, a programmable resistor array, a gating module, a sampling amplification module, a signal filtering module, an analog-to-digital conversion module, and a main control unit. These components work collaboratively through reasonable electrical connections and signal interactions to achieve the detection, weighting, summation, and digital output of optical signals. Structurally, this system avoids the complexity of the dual-device differential structure in memristor arrays, simplifies the peripheral driving and calibration circuits, and leverages the high stability and rapid reconfigurability of the programmable resistor array to achieve the goal of directly performing convolution operations at the photoelectric detection front end, effectively improving the system's response speed, calculation accuracy, and engineering feasibility.

Description

Technical Field

[0001] This invention belongs to the field of photoelectric detection signal processing technology, specifically relating to a photoelectric detection convolution calculation system based on a programmable resistor array. Background Technology

[0002] In photoelectric detection applications requiring real-time processing, such as machine vision, remote sensing imaging, and industrial inspection, architectures combining sensing and computing are gradually becoming a research hotspot. The main idea behind these systems is to directly perform calculations such as convolution and weighted summation at the front end of the optical signal detection, thereby reducing the transmission of raw data between the detection and processing ends, lowering latency and power consumption, and improving overall processing efficiency.

[0003] Currently, the closest existing technology to the technical solution of this invention is a photoelectric detection convolution calculation system based on a memristor array (such as the technology in patent application CN116090481A). This technology generally connects the memristor array directly to the output of the photodetector array, using the conductivity state of the memristor to represent the weight of the convolution kernel. The photocurrent output by the photodetector directly enters the memristor array, where it is weighted according to the conductivity value of different units. Finally, the weighted sum is converged at the column or row ports of the array, and then the current signal is converted into a voltage signal by a transimpedance amplifier, and the convolution result is output by an analog-to-digital converter. Memristor arrays can achieve highly parallel computation in the analog domain, so theoretically, high-speed, low-power convolution operations can be achieved.

[0004] However, this type of memristor-based integrated computing system has significant shortcomings in practical applications: First, the weight writing process of memristors is slow, usually requiring programming unit by unit through voltage pulses and repeated measurement and calibration to achieve the target value. This significantly reduces efficiency in scenarios requiring frequent replacement of convolution kernels or parallel computation with multiple convolution kernels. Second, memristors are prone to random fluctuations and drifts in their conductivity state during programming, resulting in poor consistency between different devices. Even after calibration at the factory, long-term use may still cause weight values ​​to shift due to factors such as temperature changes and material aging, thus affecting calculation accuracy. In addition, to achieve positive and negative weights, memristor arrays usually need to adopt a dual-device differential structure, which not only increases the number of devices but also introduces additional noise and leakage paths, reducing the system's signal-to-noise ratio and stability.

[0005] More importantly, memristor arrays, when integrated on a large scale, are affected by array wiring resistance, uneven current distribution, and leakage paths. These factors can disrupt the ideal linear weighting relationship, leading to deviations in the convolution results. Although these deviations can be corrected by adding calibration circuits and compensation algorithms, this significantly increases system design complexity and power consumption, hindering its widespread adoption in engineering applications. Furthermore, the manufacturing process of memristors is not yet fully mature, making it difficult to guarantee device consistency and long-term reliability. Uncertainties also exist regarding mass production and batch repeatability. These factors all contribute to limiting their large-scale application in photoelectric detection convolutional computation.

[0006] In summary, while existing memristor-based inductive computing technologies conceptually offer advantages such as front-end parallel computing and reduced data transfer, they suffer from significant shortcomings in terms of weight update speed, computational stability, system linearity, and engineering feasibility. Therefore, a novel system architecture is needed that can perform convolution calculations at the probe end, allows for repeatable and rapid weight updates, and possesses high computational stability and ease of engineering implementation, in order to overcome the deficiencies of the existing technologies. Summary of the Invention

[0007] In view of the above, the present invention provides a photoelectric detection convolution calculation system based on a programmable resistor array, which can directly complete the convolution calculation at the front end of the photoelectric detection and maintain high calculation accuracy under the premise of reconfigurable weights. It provides more efficient and reliable hardware support for applications such as real-time image processing and target recognition, and has the characteristics of fast reconfigurable weights, high calculation stability and easy engineering implementation.

[0008] A photoelectric detection convolution calculation system based on a programmable resistor array includes:

[0009] A photoelectric detection array is used to receive optical signals from the target and convert them into photocurrent.

[0010] The gating module selects the corresponding detection units within the convolution window from the photoelectric detection array to participate in the computation via a switch.

[0011] A programmable resistor array is used to weight and summarize the photocurrent output by the selected detector unit;

[0012] The sampling and amplification module is used to convert the weighted and summarized current signal into a voltage signal and amplify it;

[0013] The signal filtering module is used to filter the amplified voltage signal;

[0014] The analog-to-digital converter module is used to convert the filtered voltage signal into a digital signal;

[0015] The main control unit is used to read the digital signal for subsequent processing and to complete the photoelectric convolution calculation task.

[0016] Furthermore, the photoelectric detection array consists of multiple detection units arranged in an array. The detection units convert the light signal into a photocurrent signal by sensing the light intensity of the incident light. The gating module consists of multiple gating switches arranged in an array, with the array size being the same as that of the photoelectric detection array. Each detection unit is connected to a corresponding gating switch, and each gating switch receives an independent control signal, which is output by the main control unit through a parallel bus. The programmable resistor array consists of multiple programmable resistor units arranged in an array, with the array size being the same as that of the photoelectric detection array. The output terminal of each detection unit is connected to a corresponding programmable resistor unit, and the programmable resistor unit is used to store the weight values ​​of the convolution kernel.

[0017] Furthermore, the programmable resistor unit is a digital potentiometer, and the gating switch is a MOS (metal-oxide-semiconductor) switching transistor.

[0018] Furthermore, the main control unit adopts an FPGA (Field Programmable Gate Array), which is responsible for the overall control and coordination of the system, including the switching control of the gating module, the weight programming of the programmable resistor array, and the reading and subsequent processing of the digital sampling results.

[0019] Furthermore, the FPGA performs weight programming on the programmable resistor array via SPI (Serial Peripheral Interface), adjusts the weight by changing the resistance value of the programmable resistor unit, and writes to multiple rows of programmable resistor units in a parallel control manner.

[0020] Furthermore, the sampling amplification module includes a transimpedance amplifier (TIA) and a differential amplifier circuit. The transimpedance amplifier is used to convert the current signal into a voltage signal, and the differential amplifier circuit is used to amplify the voltage signal. The signal filtering module adopts an active RC (resistor-capacitor) filter.

[0021] Furthermore, regarding the convolution operation of the photoelectric detection front end, the main control unit adopts an inter-row parallel sampling operation method. That is, according to the size of the convolution kernel, the gating module selects the detection unit in the corresponding convolution window of the photoelectric detection array. The photocurrent output by the detection unit in the convolution window is weighted with the corresponding programmable resistor unit. The weighted photocurrent is naturally added at the circuit junction node according to Kirchhoff's current law to form a weighted summed current signal. Then, after voltage conversion, amplification, filtering, and analog-to-digital conversion, it is sampled and read by the main control unit. The main control unit switches to the next convolution window according to the step size and repeats the above process until the entire photoelectric detection array is traversed.

[0022] Furthermore, the workflow of the photoelectric detection convolution calculation system is as follows: First, the main control unit programs the programmable resistor array with weights to enable it to have preset convolution weights. The photoelectric detection array receives the optical signal from the target and converts it into photocurrent. Based on this, the main control unit controls the gating module to select the detection unit in the corresponding convolution window from the photoelectric detection array through a switch. The photocurrent output by the selected detection unit enters the programmable resistor array sequentially and is weighted according to the preset weights. Multiple weighted currents are combined in the circuit and input to the sampling amplification module, where they are converted into voltage signals and amplified. The amplified voltage signal is filtered by the signal filtering module to suppress noise and interference. The filtered voltage signal enters the analog-to-digital conversion module to be converted into a digital signal and read by the main control unit. Finally, the main control unit performs subsequent calculations and outputs the obtained digital convolution result to complete the photoelectric convolution calculation task.

[0023] This invention aims to solve the following technical problems existing in the prior art:

[0024] 1. Improve weight update speed: Existing memristor weight programming relies on cell-by-cell pulse writing and multiple measurement corrections, resulting in slow update speed; one of the objectives of this invention is to achieve rapid setting and reconstruction of convolution calculation weights at the probe end to meet the needs of multi-convolution kernel switching and real-time calculation scenarios.

[0025] 2. Improve computational accuracy and consistency: Memristors are susceptible to random fluctuations, drift, and temperature changes, leading to inconsistent weights between different units. This invention aims to reduce the interference of device physical characteristics on computational results and ensure the accuracy and repeatability of convolution weighted summation.

[0026] 3. Improve system linearity and stability: Large-scale memristor arrays are affected by non-ideal factors such as wiring resistance, uneven current distribution, and leakage paths during the weighted summation process; the goal of this invention is to reduce the impact of these nonlinear effects on the convolution results and improve the stability of the system during long-term operation and under different working environments.

[0027] 4. Reduce engineering implementation difficulty: Memristor arrays often require complex dual-device differential structures and supporting driving and calibration circuits, which increases the complexity of system design and manufacturing; this invention aims to reduce the complexity of peripheral circuits, reduce the difficulty of mass production and integration, and improve engineering feasibility by optimizing the architecture design.

[0028] Compared with existing memristor-based photoelectric detection convolution calculation systems, this invention has certain advantages in implementation and operation characteristics. By using a programmable resistor array as the convolution weight unit, combined with a gating switch array and a centralized control module, this invention can directly complete the convolution weighting operation at the photoelectric detection end, reducing the delay in data transmission and back-end processing, and helping to improve the overall response speed.

[0029] Regarding weight setting, the digital potentiometer in this invention can directly set the resistance value through a digital communication interface. The weight update process is simple and fast, and it is suitable for flexible switching between different convolution kernels. Compared with memristors that need to be set by pulse writing, this method can complete the weight configuration faster in small-scale convolution calculations.

[0030] In terms of system implementation, this invention can be built using conventional electronic components, the devices are easy to obtain, the construction process is simple, and it is easy to complete the system construction and functional verification under laboratory conditions. This provides an engineering implementation path for the prototype development of an integrated system of photoelectric detection and convolution calculation, and it is also easy to adjust and expand the structure according to application requirements.

[0031] In terms of operational stability, the digital potentiometer in this invention maintains stable performance after the resistance value is set, and is not easily affected by the external environment or the historical state of the device. Combined with transimpedance amplification and differential amplification processing, it helps to obtain a more stable convolution output signal.

[0032] In summary, this invention provides a photoelectric detection convolutional computation architecture with higher weight update efficiency, computational stability, and engineering feasibility. It is an easy-to-implement, fast-configurable, and relatively stable photoelectric detection convolutional computation scheme, suitable for hardware implementation in prototype verification, functional research, and specific small-scale applications. Attached Figure Description

[0033] Figure 1 This is a block diagram of the overall architecture of the photoelectric detection convolution calculation system based on a programmable resistor array in Embodiment 1 of the present invention.

[0034] Figure 2 This is a schematic diagram of the workflow of the photoelectric detection convolution calculation system in Embodiment 1 of the present invention.

[0035] Figure 3 This is a schematic diagram of the photoelectric detection array structure in the system of Embodiment 2 of the present invention.

[0036] Figure 4 This is a schematic diagram of the digital potentiometer array structure in the system of Embodiment 2 of the present invention. Detailed Implementation

[0037] To describe the present invention in more detail, the technical solution of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0038] Example 1

[0039] This embodiment provides a photoelectric detection convolution calculation system based on a programmable resistor array. This system can directly perform convolution operations at the photoelectric detection end, reducing the amount of data transmission required by traditional methods of first acquiring data and then calculating, and improving the integrated realization capability of photoelectric detection and calculation. Figure 1 As shown, the system as a whole includes a photoelectric detection array, a MOS gating array, a digital potentiometer array, a sampling amplification module, a signal filtering module, an analog-to-digital conversion module, and a main control unit. The modules are interconnected by electrical signals and complete the entire process of photoelectric convolution calculation under the unified coordination of the main control unit.

[0040] The photodetector array receives optical signals from the target and converts them into photocurrent output as the system's input source. A MOS gating array is configured correspondingly to the photodetector array and, under the control of the main control unit, can select any detector unit or combination within the array, allowing the pixel current within the convolution window to be selected and output. A digital potentiometer array is connected to the MOS gating array and is used to weight the selected photocurrent. The weight values ​​are set by the main control unit through a weight programming signal, thus realizing the weighting operations required for convolution calculation. The sampling amplification module includes a transimpedance amplifier (TIA) and a differential amplifier circuit, converting the total current after multiple weighted currents into a voltage signal and amplifying it for subsequent signal processing. The signal filtering module filters the voltage signal to suppress noise and interference, ensuring the stability of the convolution result. The analog-to-digital converter module converts the filtered analog voltage signal into a digital signal output and transmits it to the main control unit. The main control unit is responsible for the overall control and coordination of the system, including the switching control of the MOS gating array, the weight programming of the digital potentiometer array, and the reading and subsequent processing of the output results from the analog-to-digital converter module, thereby completing the photoelectric convolution calculation task.

[0041] In this embodiment, the photodetector array consists of multiple photodetector units. Each unit can directly output photocurrent under illumination without requiring an additional bias power supply. The output of each unit is connected in series with a digital potentiometer, which stores and implements the weight values ​​of the convolution kernel. By changing its resistance value, the contribution of the unit in the weighted summation is adjusted. The resistance value of the digital potentiometer is programmed by the main control unit through a digital interface (such as the SPI protocol), thereby enabling rapid setting and dynamic updating of the weights.

[0042] To achieve selective weighted operations across different convolution regions, a gating switch element is placed between the photodetector unit and the digital potentiometer. This embodiment employs a MOS switch structure arranged in a matrix. The control terminal of the MOS switch is connected to the main control unit, which can open or close any combination of detector unit paths according to operational requirements, thereby selecting detector units at any position in the photodetector array to form a convolution window. The gating array can be implemented using a multi-channel analog switch array or address decoding to reduce the number of control pins and improve array controllability.

[0043] During convolution calculations, the main control unit sequentially writes weights to the digital potentiometer array via a digital interface according to preset convolution kernel parameters. Simultaneously, the MOS gate array activates the corresponding switches within the convolution window, causing the photocurrent output by the detection unit within the window to be weighted sequentially through its corresponding digital potentiometer. The weighted current signals are naturally added at the circuit junction node according to Kirchhoff's current law, forming a weighted sum of current signals. This total current signal enters the transimpedance amplifier, converting the current into a voltage signal for subsequent signal processing. To suppress common-mode interference and improve signal resolution, the output of the transimpedance amplifier is connected to a differential amplifier circuit, extracting the effective signal through differential processing to eliminate the effects of environmental noise and circuit drift. The amplified voltage signal is then input to the analog-to-digital converter (ADC), converting the analog convolution result into a digital signal for subsequent processing.

[0044] The entire system's workflow is centrally managed by the main control unit, which uses an FPGA as its core controller. This unit is responsible for tasks such as writing programmable resistor weights, controlling the gating module's switching, acquiring ADC data, and transmitting data via external interfaces. Leveraging the FPGA's parallel processing capabilities and flexible logic configuration, it enables functions such as rapid kernel switching, multi-region parallel convolution operations, and real-time output of convolution results. By integrating weighting and convolution functions at the detection end, this system avoids the extensive analog signal acquisition and backend data processing requirements of traditional architectures. It combines photoelectric detection with convolution calculation, providing more efficient basic computing capabilities for subsequent applications such as target recognition and signal processing.

[0045] The system workflow in this embodiment is as follows: Figure 2As shown: First, the main control unit uses an FPGA to program the digital potentiometer array with preset convolution weights. Then, the photodetector array receives the optical signal from the target and converts it into a photocurrent output. Based on this, the FPGA controls a MOS gating array to select the detector unit within the convolution window, allowing the photocurrent within the window to be transmitted to the subsequent processing module. The selected photocurrents sequentially enter the digital potentiometer array and are weighted according to preset weights. Multiple weighted currents converge in the circuit and are input to a transimpedance amplifier, where they are converted into a voltage signal. This voltage signal is then filtered by an active RC filter to suppress noise and interference, ensuring signal stability. The filtered analog voltage signal enters the analog-to-digital converter module, is converted into a digital signal, and is read and processed by the FPGA. Finally, the FPGA performs subsequent calculations and outputs the obtained digital convolution result, realizing the convolution calculation function of the photodetector.

[0046] In the specific implementation, the MOS gating array and the photodetector array are of the same size, ensuring that each detector unit corresponds to a MOS switch, which can flexibly control the conduction and cutoff of the pixel current and realize the rapid selection of arbitrary convolution windows. The digital potentiometer array is connected to the MOS array and is responsible for applying preset weights to the passing photocurrent. The weights are written by the FPGA through a digital communication interface (such as SPI), which has the characteristics of being programmable and reconfigurable, facilitating rapid switching between different convolution kernels.

[0047] The weighted currents converge in the circuit according to Kirchhoff's current law and are uniformly input to a transimpedance amplifier for current-to-voltage conversion. The converted voltage signal is processed by an active RC filter module, which can suppress high-frequency noise and improve signal quality. The filtered voltage signal enters the analog-to-digital converter module to be converted into a digital signal. The main control unit FPGA is responsible for controlling the weight programming and gating operations, and also for reading the digital convolution results and performing subsequent data processing, such as storage, transmission, or as input to the subsequent neural network.

[0048] Through the above design, the system in this embodiment can directly perform convolution operations at the photoelectric detection end, avoiding the cumbersome process in the traditional architecture where the detection data must first be transmitted to an external processing unit before convolution, thereby improving the computational efficiency to a certain extent, simplifying the system architecture, and providing a feasible hardware implementation scheme for the integration of photoelectric detection and convolution calculation.

[0049] Example 2

[0050] like Figure 3 As shown, in this embodiment, the photoelectric detection array is designed as an 8×8 structure, containing 64 photoelectric detection units P. i,j(i=1,2,…,8,j=1,2,…,8), each photoelectric detection unit P i,j The incident light signal is converted into a current signal and connected to the array row lines through a MOS switch. To ensure flexible selection of the convolution window, the FPGA provides 64 parallel and independent control signals to control the on / off state of the 64 MOS switches in the array one by one, thereby achieving precise selection of pixels within the convolution window. For example, when the convolution window is located in the upper left corner of the array, the FPGA simultaneously selects the MOS switch. 1,1 To MOS 3,3 The corresponding photoelectric unit P 1,1 To P 3,3 When activated, the output current is fed into the subsequent weighting circuit.

[0051] In this embodiment, the digital potentiometer array corresponding to the photoelectric detection array is as follows: Figure 4 As shown, each digital potentiometer D i,j (i=1,2,…,8,j=1,2,…,8) are connected one-to-one with the output current of the corresponding detection unit to implement resistance weighting. To improve programming efficiency, this embodiment adopts an 8-channel SPI parallel control method. Specifically, the FPGA uses 8 independent SPI channels to correspond to the 8 rows of the potentiometer array. The 8 potentiometer units in each row are written sequentially during programming, while different rows can be programmed in parallel. For example, when it is necessary to program the first three potentiometers of the first three rows simultaneously, the FPGA will activate SPI_1 to SPI_3 in parallel to program the D potentiometers. 1,1 D 2,1 D 3,1 Programming was performed, and then the data was written to D in parallel. 1,2 D 2,2 D 3,2 Then write D sequentially 1,3 D 2,3 D 3,3 This approach can significantly reduce the time overhead of writing convolution kernels and improve the overall operating speed of the system.

[0052] In convolution operations, taking a 3×3 convolution kernel as an example, the convolution stride is 1 and padding is 0. For the input image matrix... The convolution kernel matrix is ​​denoted as The output of the convolution operation is The calculation formula is as follows:

[0053]

[0054] in: This represents the photocurrent covered by the convolution window in the input array. This represents the weight value at the corresponding position of the convolution kernel.

[0055] In terms of hardware implementation, the convolution kernel weights This is achieved by programming the resistance values ​​of digital potentiometers. The FPGA first maps the nine weight values ​​of the convolution kernel to the corresponding digital potentiometers and writes them quickly via the SPI interface. Then, the FPGA controls the MOS gate array to activate the corresponding 3×3 photodetector unit, causing its output photocurrent to enter the potentiometer array for weighting. The weighted current is collected in the column lines and input to the TIA, converted into a voltage signal, filtered and digitized by the ADC, and then read by the FPGA. The FPGA then controls the movement direction of the window according to the convolution stride and repeats the above process until the entire array is traversed to obtain a 6×6 output feature map.

[0056] With this circuit implementation, the convolution kernel performs multiplication and addition operations at the hardware level. Furthermore, through the independent control of 64 MOS channels and parallel programming of 8 SPI channels in the FPGA, the flexibility of window selection is ensured, and the weight writing speed is greatly improved, thereby enhancing the overall efficiency of convolution calculation.

[0057] Furthermore, the photoelectric detection convolution calculation system in this embodiment can not only perform fixed 3×3 convolution kernel operations, but also support various convolution specifications through the flexible control mechanism of the FPGA. Specifically, since the FPGA has the ability to independently control 64 MOS switches point by point, the size of the convolution window is not limited to a fixed 3×3, but can be flexibly expanded as needed. For example, when a 5×5 convolution is required, the FPGA only needs to simultaneously select 25 corresponding detector units and map the convolution kernel weights to the corresponding 25 digital potentiometers to complete the hardware-level weighting and accumulation; similarly, 7×7 or larger convolution kernels can also be implemented in the same way.

[0058] This system is also fully adaptable to convolution stepping. When the FPGA controls the MOS switch, it can select the magnitude of window movement according to the set step value. For example, when the step is 2, each activated probe unit will jump two pixels to the right or down, thus directly realizing the requirement of step convolution.

[0059] Regarding padding, since the FPGA not only controls the MOS switches but also handles the digital processing of the convolution results, it can flexibly implement zero padding or other forms of boundary processing. For example, with padding=1, windows located at the image edge may not completely cover the convolution kernel. In this case, the FPGA only needs to weight and accumulate the actually detected current, then pad the missing parts with zeros in the digital domain and participate in the calculation to obtain a result that is completely consistent with the theoretical convolution. This approach utilizes the point-by-point control characteristics of the FPGA and uses back-end digital logic to fill in the boundary pixels that the hardware cannot detect, making the system fully compatible with various convolution parameter settings commonly used in convolutional neural networks.

[0060] In summary, the photoelectric detection convolution calculation system in this embodiment, with its combined mechanism of "FPGA single-point control MOS switch + digital potentiometer weighting + FPGA back-end flexible calculation", can support arbitrary convolution kernel size, arbitrary step value and arbitrary padding strategy, thus possessing high versatility and scalability, and can meet the diverse needs of different deep neural network structures for convolution calculation.

[0061] The above description of the embodiments is provided to enable those skilled in the art to understand and apply the present invention. Those skilled in the art can readily make various modifications to the above embodiments and apply the general principles described herein to other embodiments without creative effort. Therefore, the present invention is not limited to the above embodiments, and any improvements and modifications made to the present invention by those skilled in the art based on the disclosure thereof should be within the scope of protection of the present invention.

Claims

1. A photoelectric detection convolution calculation system based on a programmable resistor array, characterized in that, include: A photoelectric detection array is used to receive optical signals from the target and convert them into photocurrent. The gating module selects the corresponding detection units within the convolution window from the photoelectric detection array to participate in the computation via a switch. A programmable resistor array is used to weight and summarize the photocurrent output by the selected detector unit; The sampling and amplification module is used to convert the weighted and summarized current signal into a voltage signal and amplify it; The signal filtering module is used to filter the amplified voltage signal; The analog-to-digital converter module is used to convert the filtered voltage signal into a digital signal; The main control unit is used to read the digital signal for subsequent processing and to complete the photoelectric convolution calculation task; The photoelectric detection array consists of multiple detection units arranged in an array. Each detection unit converts an optical signal into a photocurrent signal by sensing the intensity of incident light. The gating module consists of multiple gating switches arranged in an array, with the array size matching that of the photoelectric detection array. Each detection unit is connected to a corresponding gating switch, and each gating switch receives an independent control signal, which is output by the main control unit via a parallel bus. The programmable resistor array consists of multiple programmable resistor units arranged in an array, with the array size matching that of the photoelectric detection array. The output of each detection unit is connected to a corresponding programmable resistor unit, which stores the weight values ​​of the convolution kernel.

2. The photoelectric detection convolution calculation system based on a programmable resistor array according to claim 1, characterized in that: The programmable resistor unit is a digital potentiometer, and the gating switch is a MOS switching transistor.

3. The photoelectric detection convolution calculation system based on a programmable resistor array according to claim 1, characterized in that: The main control unit uses an FPGA, which is responsible for the overall control and coordination of the system, including the switching control of the gating module, the weight programming of the programmable resistor array, and the reading and subsequent processing of the digital sampling results.

4. The photoelectric detection convolution calculation system based on a programmable resistor array according to claim 3, characterized in that: The FPGA performs weight programming on the programmable resistor array through the SPI interface, adjusts the weight by changing the resistance value of the programmable resistor unit, and writes to multiple rows of programmable resistor units in a parallel control manner.

5. The photoelectric detection convolution calculation system based on a programmable resistor array according to claim 1, characterized in that: The sampling amplification module includes a transimpedance amplifier and a differential amplifier circuit. The transimpedance amplifier is used to convert the current signal into a voltage signal, and the differential amplifier circuit is used to amplify the voltage signal. The signal filtering module uses an active RC filter.

6. The photoelectric detection convolution calculation system based on a programmable resistor array according to claim 1, characterized in that: Regarding the convolution operation of the photoelectric detection front end, the main control unit adopts an inter-row parallel sampling operation method. That is, according to the size of the convolution kernel, the gating module selects the detection unit in the corresponding convolution window of the photoelectric detection array. The photocurrent output by the detection unit in the convolution window is weighted with the corresponding programmable resistor unit. The weighted photocurrent is naturally added at the circuit junction node according to Kirchhoff's current law to form a weighted summed current signal. Then, after voltage conversion, amplification, filtering, and analog-to-digital conversion, the signal is sampled and read by the main control unit. The main control unit switches to the next convolution window according to the step size and repeats the above process until the entire photoelectric detection array is traversed.

7. The photoelectric detection convolution calculation system based on a programmable resistor array according to claim 1, characterized in that: The system's workflow is as follows: First, the main control unit programs the programmable resistor array with preset convolution weights. The photoelectric detection array receives the optical signal from the target and converts it into photocurrent. Based on this, the main control unit controls the gating module to select the corresponding detection unit within the convolution window of the photoelectric detection array via a switch. The photocurrent output by the selected detection unit enters the programmable resistor array sequentially and is weighted according to the preset weights. Multiple weighted currents converge in the circuit and are input to the sampling amplification module, where they are converted into voltage signals and amplified. The amplified voltage signal is then filtered by the signal filtering module to suppress noise and interference. The filtered voltage signal enters the analog-to-digital conversion module to be converted into a digital signal, which is then read by the main control unit. Finally, the main control unit performs subsequent calculations and outputs the obtained digital convolution result, completing the photoelectric convolution calculation task.

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