Flash memory data decoding recovery method and device, electronic device, and storage medium

Abstract

The application discloses a flash memory data decoding recovery method and device, electronic equipment and storage medium, and relates to the technical field of flash memory data decoding recovery method and device, electronic equipment and storage medium. The method comprises the following steps: determining a first data page to be decoded from a plurality of data storage pages of a data storage block of a flash memory; performing first data reading processing and first hard decoding processing on the first data page to obtain an initial hard decoding condition of the first data page; when the first hard decoding processing fails, re-determining a target decoding mode according to the initial hard decoding condition; wherein the target decoding mode is a hard decoding mode or a soft decoding mode; performing second data reading processing and data decoding processing on the first data page according to the target decoding mode to obtain flash memory decoding recovery data of the first data page, and completing decoding of the first data page. The application can effectively improve the data decoding recovery efficiency and decoding reliability of the data block.

Description

Technical Field

[0001] This application relates to the field of flash memory technology, and in particular to a flash memory data decoding and recovery method and apparatus, electronic device, and storage medium. Background Technology

[0002] NAND Flash memory, or non-volatile memory, is a widely used storage product today, characterized by its high speed and non-volatility. NAND flash memory stores data by storing charge in storage cells; that is, internally, data is represented by stored charge. In actual use, changes in various internal and external conditions (such as high and low temperatures, read interference) will cause changes in the amount of charge stored in the flash memory cells, leading to data bit flips. If the accumulated change in stored charge reaches a certain level, accessing the NAND flash memory using the default read operation may not yield correct data. Therefore, an error correction unit in the flash memory controller is usually required to correct the data. Generally, NAND flash manufacturers allow adjustment of the read voltage used to determine the cell state. By adjusting the read voltage, the data can be correctly recovered; this process is usually called read retry. The manufacturer typically provides a retry table, which is traversed to recover data when the default read fails. Currently, the LDPC algorithm is the mainstream error correction algorithm for flash memory. LDPC has two decoding modes: hardware decoding and software decoding. In software decoding mode, additional soft information needs to be acquired, resulting in strong decoding capabilities but higher latency. Therefore, hard decoding has low latency but relatively weak decoding capability. When recovering flash memory data, since the number of erroneous bits in the flash memory cannot be assessed in advance, the current approach is to first traverse all reread tables for hard decoding, and then traverse all reread tables for software decoding. Although this can make full use of the decoding capability of the error correction module, in practical applications, the current approach is too time-consuming, easily causing timeouts and low data recovery efficiency. Summary of the Invention

[0003] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a flash memory data decoding and recovery method, apparatus, electronic device, and storage medium, which can flexibly select either a hard decoding mode or a soft decoding mode to re-decode data pages based on the initial hard decoding situation during the flash memory error correction process, thereby effectively improving the data decoding and recovery efficiency and decoding reliability of data blocks.

[0004] In a first aspect, embodiments of this application provide a flash memory data decoding and recovery method, including:

[0005] The first data page to be decoded is determined from multiple data storage pages of the flash memory's data storage block;

[0006] Perform a first data reading process and a first hardware decoding process on the first data page to obtain the initial hardware decoding status of the first data page;

[0007] If the first hardware decoding process fails, the target decoding mode is re-determined based on the initial hardware decoding situation; wherein, the target decoding mode is: hardware decoding mode or software decoding mode;

[0008] According to the target decoding mode, the first data page is subjected to second data reading processing and data decoding processing to obtain the flash memory decoding recovery data of the first data page, and the decoding of the first data page is completed.

[0009] In a second aspect, embodiments of this application provide a flash memory data decoding and recovery apparatus, including at least one processor and a memory for communicatively connecting to the at least one processor; the memory stores instructions executable by the at least one processor, which, when executed by the at least one processor, enable the at least one processor to perform the flash memory data decoding and recovery method as described in any one of the embodiments of the first aspect.

[0010] Thirdly, embodiments of this application provide an electronic device, including a flash data decoding and recovery device as described in the second aspect embodiment.

[0011] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions for causing a computer to perform the flash memory data decoding and recovery method as described in any one of the embodiments of the first aspect.

[0012] This application embodiment includes the following steps: In the process of decoding and recovering flash data during flash memory error correction, firstly, a first data page to be decoded is determined from multiple data storage pages of the flash memory's data storage block; secondly, the first data page undergoes a first data read process and a first hardware decoding process to obtain the initial hardware decoding status of the first data page; the initial hardware decoding status provides a reliable reference for flexibly selecting a suitable target decoding mode to re-read and decode the data; then, if the first hardware decoding process fails, the target decoding mode is re-determined based on the initial hardware decoding status; wherein, the target decoding mode is either a hardware decoding mode or a software decoding mode; finally, the first data page undergoes a second data read process and a data decoding process based on the target decoding mode to obtain the flash memory decoded recovery data of the first data page, thus completing the decoding of the first data page; by flexibly selecting a suitable target decoding mode to re-read and decode the data, time consumption is reduced, and data recovery efficiency is effectively improved. In other words, this application embodiment can flexibly select a hardware decoding mode or a software decoding mode to re-decode the data page based on the initial hardware decoding status during the flash memory error correction process, thereby effectively improving the data decoding recovery efficiency and decoding reliability of the data block.

[0013] Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the description and the accompanying drawings. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the architecture of a flash memory data decoding and recovery system provided in one embodiment of this application;

[0015] Figure 2 This is a schematic flowchart of a flash memory data decoding and recovery method provided in one embodiment of this application;

[0016] Figure 3 This is a schematic diagram illustrating the initial hardware decoding of a data storage page according to an embodiment of this application;

[0017] Figure 4 This is a schematic diagram of the overall process of a flash memory data decoding and recovery method provided in one embodiment of this application;

[0018] Figure 5 This is a schematic diagram of the hardware structure of an electronic device provided in one embodiment of this application. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments.

[0020] It should be noted that although a logical order is shown in the flowcharts in this application, in some cases, the steps shown or described may be performed in a different order than that shown in the flowcharts. In the description of this application, "several" means one or more, and "more" means two or more. The terms "first" and "second" are used only to distinguish technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of technical features indicated, or implicitly indicating the order in which the technical features are indicated.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0022] First, let me explain some of the terms used in this application:

[0023] NAND Flash is a non-volatile random access storage medium that uses floating gate transistors as storage units to store data.

[0024] Triple-Level Cell (TLC) NAND flash memory devices are currently the mainstream storage type on the market. A single TLC cell can store 3 bits of data, so the number of electrons in its floating gate transistor has 8 states. The intervals between these states are reduced, and read / write interference and data retention can lead to accidental injection or loss of electrons, reducing the fault tolerance of the flash memory and deteriorating the stability and reliability of the stored data.

[0025] This application provides a flash memory data decoding and recovery method, a flash memory data decoding and recovery apparatus, an electronic device, and a computer-readable storage medium, relating to a flash memory data decoding and recovery method and apparatus, an electronic device, and a storage medium. The method includes: determining a first data page to be decoded from multiple data storage pages of a data storage block in a flash memory; performing a first data read process and a first hardware decoding process on the first data page to obtain an initial hardware decoding state of the first data page; if the first hardware decoding process fails, re-determining a target decoding mode based on the initial hardware decoding state; wherein the target decoding mode is either a hardware decoding mode or a software decoding mode; performing a second data read process and a data decoding process on the first data page according to the target decoding mode to obtain flash memory decoding recovery data of the first data page, thus completing the decoding of the first data page. This application can effectively improve the data decoding and recovery efficiency and decoding reliability of data blocks.

[0026] The embodiments of this application will be further described below with reference to the accompanying drawings.

[0027] like Figure 1 As shown, the flash memory data decoding and recovery system 100 includes a flash memory 110 and a controller 120, with the flash memory 110 and controller 120 electrically connected. The flash memory 110's storage units include multiple data storage blocks, and each data storage block includes multiple data storage pages. The controller 120 executes the flash memory data decoding and recovery method provided in this embodiment, enabling it to flexibly select either a hard decoding mode or a soft decoding mode to re-decode data pages based on the initial hard decoding situation during the flash memory error correction process, thereby effectively improving the data decoding and recovery efficiency and decoding reliability of data blocks.

[0028] Those skilled in the art will understand that the system structure shown in the figures does not constitute a limitation on the embodiments of this application, and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0029] The system embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0030] It will be understood by those skilled in the art that the system architecture and application scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. It is known by those skilled in the art that with the evolution of system architecture and the emergence of new application scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0031] Based on the above system structure, various embodiments of the flash memory data decoding and recovery method of this application are proposed below.

[0032] Firstly, such as Figure 2 As shown, the flash memory data decoding and recovery method may include, but is not limited to, steps S110 to S140.

[0033] Step S110: Determine the first data page to be decoded from multiple data storage pages of the data storage block of the flash memory.

[0034] Step S120: Perform first data reading processing and first hardware decoding processing on the first data page to obtain the initial hardware decoding status of the first data page.

[0035] Step S130: When the first hardware decoding process fails, the target decoding mode is re-determined based on the initial hardware decoding situation; wherein, the target decoding mode is: hardware decoding mode or software decoding mode.

[0036] Step S140: Perform second data reading and data decoding processing on the first data page according to the target decoding mode to obtain the flash memory decoding recovery data of the first data page, and complete the decoding of the first data page.

[0037] Specifically, there are three possible initial hardware decoding scenarios: all decoding is correct, all decoding is incorrect, and partial decoding is successful.

[0038] Combination Figure 3 To further illustrate the initial hardware decoding situation, consider the following example. Assume a data storage page to be decoded contains four codewords. During the first hardware decoding process, each codeword is decoded sequentially or in parallel to obtain its decoding status. The initial hardware decoding status of the data storage page is then determined based on these statuses. If all four codewords are decoded successfully (OK), the initial hardware decoding status is determined as: all decoded correctly. If all four codewords are decoded incorrectly (Fail), the initial hardware decoding status is determined as: all decoded incorrectly. If the decoding status of all four codewords includes both "OK" and "Fail," the initial hardware decoding status is determined as: partially successful decoding.

[0039] In one embodiment, after performing a first data reading process and a first hardware decoding process on the first data page, if the initial hardware decoding result is that all decodings are correct, the decoding of the first data page ends; after the first data page is decoded, the second data page to be decoded is determined sequentially from multiple data storage pages of the data storage block, and then steps S120 to S140 are performed on the second data page.

[0040] The embodiments of this application implement a switching mechanism between hardware decoding and software decoding in the flash memory error correction process through steps S120 to S140, so as to balance strong decoding capability and high decoding efficiency in the decoding process of data storage blocks.

[0041] Through steps S110 to S140, in the process of decoding and recovering flash data in the flash memory error correction process, firstly, the first data page to be decoded is determined from multiple data storage pages of the flash memory's data storage block; secondly, the first data page undergoes a first data read process and a first hardware decoding process to obtain the initial hardware decoding status of the first data page; the initial hardware decoding status provides a reliable reference for flexibly selecting a suitable target decoding mode to re-read and decode data; then, if the first hardware decoding process fails, the target decoding mode is re-determined based on the initial hardware decoding status; wherein, the target decoding mode is either a hardware decoding mode or a software decoding mode; finally, the first data page undergoes a second data read process and a data decoding process based on the target decoding mode to obtain the flash memory decoded recovery data of the first data page, thus completing the decoding of the first data page; by flexibly selecting a suitable target decoding mode to re-read and decode data, the time consumption is reduced, and the data recovery efficiency is effectively improved. In other words, the embodiments of this application can flexibly select either hard decoding mode or soft decoding mode to re-decode data pages according to the initial hard decoding situation during the flash memory error correction process, thereby effectively improving the data decoding recovery efficiency and decoding reliability of data blocks.

[0042] According to some embodiments of this application, step S120 is further described. Step S120: Perform first data reading processing and first hardware decoding processing on the first data page to obtain the initial hardware decoding situation, including but not limited to steps S121 to S123.

[0043] Step S121: Determine the first rereading voltage parameter from multiple sets of candidate rereading voltage parameters in the preset rereading table.

[0044] Step S122: Perform first data reading processing on the first data page according to the first reread voltage parameter to obtain the first data to be decoded.

[0045] Step S123: Perform the first hardware decoding process on the first data to be decoded to obtain the initial hardware decoding status.

[0046] Specifically, step S121 is further explained as follows: the preset reread table includes multiple sets of candidate reread voltage parameters to facilitate data reading. This application does not impose specific restrictions on the values ​​of the multiple sets of candidate reread voltage parameters included in the preset reread table.

[0047] Specifically, the Nth candidate reread voltage parameter is determined as the first reread voltage parameter from multiple sets of candidate reread voltage parameters in the preset reread table, where N is a positive integer.

[0048] Through steps S121 to S123, the initial hardware decoding status is obtained, thus providing a reliable reference for flexibly selecting a suitable target decoding mode to reread and decode the data.

[0049] According to some embodiments of this application, step S130 is further described, wherein the target decoding mode is re-determined based on the initial hard decoding situation, including but not limited to steps S131 to S132.

[0050] Step S131: When the initial hardware decoding situation is: all decoding errors, determine the target decoding mode as hardware decoding mode.

[0051] Step S132: When the initial hardware decoding status is: the decoding part is successful, perform statistical analysis on the decoded data obtained after the first hardware decoding process to obtain the ratio between the number of bit values ​​0 and the number of bit values ​​1; determine the target decoding mode based on the comparison result of the ratio with the preset value range.

[0052] According to some embodiments of this application, step S132 is further described, wherein determining the target decoding mode based on the comparison result of the ratio and the preset value range includes: when the comparison result is that the ratio is within the preset value range, determining the target decoding mode as a soft decoding mode; when the comparison result is that the ratio is not within the preset value range, determining the target decoding mode as a hard decoding mode.

[0053] In one embodiment, the preset value range is (48%, 52%).

[0054] Through steps S131 to S132, the suitable target decoding mode is determined to be either hardware decoding mode or software decoding mode, which provides a reference for subsequent data decoding and helps to effectively improve data recovery efficiency.

[0055] According to some embodiments of this application, step S140 is further described. Step S140: Perform second data reading processing and data decoding processing on the first data page according to the target decoding mode to obtain the flash memory decoding recovery data of the first data page, including but not limited to steps S210 to S230.

[0056] Step S210: When the target decoding mode is hard decoding mode, the second reread voltage parameter is obtained sequentially from multiple sets of candidate reread voltage parameters in the preset reread table.

[0057] Step S220: Perform second data reading processing on the first data page according to the second reread voltage parameter to obtain the second data to be decoded.

[0058] Step S230: Perform a second hardware decoding process on the second data to be decoded to obtain the flash memory decoding recovery data of the first data page.

[0059] Specifically, in step S210, when the target decoding mode is hard decoding mode, the N+1th candidate rereading voltage parameter is determined as the second rereading voltage parameter from multiple sets of candidate rereading voltage parameters in the preset rereading table in sequence, where N is a positive integer.

[0060] Through steps S210 to S230, after evaluating the initial hard decoding situation after the first hard decoding process and determining that the hard decoding mode should continue to be used, the first data page is processed by the second data reading process using the new second reread voltage parameters to obtain the second data to be decoded; the second data to be decoded is processed by the second hard decoding process to obtain the flash memory decoding recovery data of the first data page. Taking advantage of the low latency when reading data in the hard decoding mode, the data recovery efficiency of the first data page is improved, which is conducive to improving the data recovery efficiency of the data storage block.

[0061] According to some embodiments of this application, step S140 is further described. Step S140: Perform second data reading processing and data decoding processing on the first data page according to the target decoding mode to obtain the flash memory decoding recovery data of the first data page, including but not limited to steps S310 to S320.

[0062] Step S310: When the target decoding mode is software decoding mode, the decoding error data obtained after the first hardware decoding process is processed by the second data reading process to obtain software information.

[0063] Step S320: Perform software decoding on the soft information to obtain the flash memory decoding recovery data of the first data page.

[0064] Specifically, the second data reading process refers to: setting the same preset rereading voltage offset value, applying the same offset rule (uniformly increasing / decreasing the preset rereading voltage offset value ΔV) to all read cells to ensure consistent reading conditions; performing multiple reads on the same data cell based on multiple different reference voltages, resulting in multiple reading results; and calculating the probability (or log-likelihood ratio LLR) that the data cell stores "0" or "1" based on the reading results. Specifically, soft information refers to the probability (or log-likelihood ratio LLR) that the data cell stores "0" or "1". For example: applying three reference voltage reads with different offsets to the same data cell, recording the reading results under V_ref-ΔV; recording the reading results under the reference voltage V_ref; recording the reading results under V_ref+ΔV; and calculating soft information.

[0065] Specifically, soft decoding processing refers to decoding soft information based on a preset soft decoding algorithm. This application embodiment does not impose specific restrictions on the soft decoding algorithm used.

[0066] It should be emphasized that software decoding has strong decoding capabilities, and the success rate of software decoding is close to 100%.

[0067] Through steps S310 to S320, after evaluating the initial hard decoding situation after the first hard decoding process and determining that the soft decoding mode should continue to be used, the first reread voltage parameter is used to perform the second data reading process on the first data page to obtain the second data to be decoded. The second data to be decoded is then soft-decoded to obtain the flash memory decoding recovery data of the first data page. By taking advantage of the strong decoding capability of the soft decoding mode, the decoding reliability of the first data page is ensured, which is conducive to improving the decoding reliability of the data storage block.

[0068] According to some embodiments of this application, the flash memory data decoding and recovery method also includes, but is not limited to, steps S510 to S550.

[0069] Step S510: After decoding the first data page, determine the second data page to be decoded from the multiple data storage pages of the data storage block in sequence.

[0070] Step S520: Perform the first data reading process and the first hardware decoding process on the second data page to obtain the initial hardware decoding status of the second data page.

[0071] Step S530: When the first hardware decoding process fails, the target decoding mode is re-determined based on the initial hardware decoding situation.

[0072] Step S540: Perform second data reading and data decoding processing on the second data page according to the target decoding mode to obtain the flash memory decoding recovery data of the second data page, and complete the decoding of the second data page.

[0073] Step S550: Continue decoding all data storage pages in the data block to obtain the decoded and recovered flash memory data of the data storage block.

[0074] It is understood that the switching mechanism between hardware decoding and software decoding in the flash memory error correction process implemented in steps S520 to S540 is the same as that in steps S120 to S140. The specific processes of the first data reading process, the first hardware decoding process, the determination of the target decoding mode, the second data reading process, and the data decoding process are the same as those in the above embodiments, and will not be repeated here.

[0075] Through steps S510 to S550, based on the switching mechanism between hardware decoding and software decoding in the flash memory error correction process, after decoding each data storage page of the data storage block, the decoding of all data storage pages in the data block is completed, and the decoded and recovered flash memory data of the data storage block is obtained; in the decoding process of the data storage block, both strong decoding capability and high decoding efficiency can be taken into account.

[0076] Combination Figure 4 To illustrate, let's take a typical TLC flash memory data recovery scenario as an example to illustrate the overall flowchart of the flash memory data decoding and recovery method provided in this application embodiment.

[0077] Before verifying the flash memory data decoding and recovery method, firstly, a TLC block is selected, its data is erased, and then filled with data sequentially. This TLC block is then subjected to data retention and read interference scenarios, as well as high and low temperatures, to increase the number of error bits in the flash memory. This TLC block is then identified as the data storage block to be decoded and recovered. The overall process of the flash memory data decoding and recovery method is as follows.

[0078] Step S401: Determine the TLC block of data storage to be decoded and recovered.

[0079] Step S402: Determine the Kth page of data storage as the data page to be decoded from the data storage block.

[0080] Step S403: Use the Nth set of rereading voltage parameters in the preset rereading table to read the data page to be decoded and obtain the data to be decoded.

[0081] Step S404: Perform hardware decoding on the data to be decoded.

[0082] Step S405: Determine whether all the data pages to be decoded are decoded correctly; if yes, proceed to step S406; if no, proceed to step S409.

[0083] Step S406: Determine whether each data storage page in the data storage block has been decoded correctly. If yes, proceed to step S408; otherwise, proceed to step S407.

[0084] Step S407: Let K = K + 1, and then execute step S402.

[0085] Step S408: End decoding.

[0086] Step S409: Determine whether the current data page to be decoded has been completely decoded with errors; if yes, proceed to step S410; if no, proceed to step S411.

[0087] Step S410: Let N = N + 1, and then execute step S403.

[0088] Step S411: If the decoding is successful, calculate the ratio between the number of 0 bits and the number of 1 bits.

[0089] Step S412: Determine whether the ratio is within the preset range; if yes, proceed to step S413; if no, proceed to step S410.

[0090] Step S413: Perform corresponding software decoding on the decoded error data after hardware decoding. If the software decoding is successful, proceed to step S406. The specific process of "corresponding software decoding" is shown in steps S310 to S320, and will not be repeated here.

[0091] In summary, it is important to emphasize that this application implements a switching strategy between hardware code and software decoding in the flash memory error correction process. The flash memory data decoding and recovery method of this application is an intelligent method for switching decoding modes. Under certain conditions, it switches from hardware decoding to the corresponding software decoding, which can quickly correct data. This ensures the efficiency of the data recovery process while fully utilizing the decoding capabilities of the error correction module. Therefore, it effectively improves data recovery efficiency and reduces read latency.

[0092] like Figure 5 As shown, the present invention also provides a flash memory data decoding and recovery device, comprising:

[0093] The processor 501 can be implemented using a general-purpose central processing unit (CPU), microprocessor, application specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this application.

[0094] The memory 502 can be implemented as a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 502 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 502 and is called and executed by the processor 501 using the flash memory data decoding and recovery method of the embodiments of this application.

[0095] The input / output interface 503 is used to implement information input and output;

[0096] The communication interface 504 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0097] Bus 505 transmits information between various components of the device (e.g., processor 501, memory 502, input / output interface 503, and communication interface 504);

[0098] The processor 501, memory 502, input / output interface 503, and communication interface 504 are connected to each other within the device via bus 505.

[0099] This application also provides an electronic device, including the flash memory data decoding and recovery device described above.

[0100] This application also provides a storage medium, which is a computer-readable storage medium, storing a computer program that, when executed by a processor, implements the above-described flash memory data decoding and recovery method.

[0101] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof. The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separate, and may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0102] It will be understood by those skilled in the art that all or some of the steps and systems in the methods disclosed above can be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, as is known to those skilled in the art, communication media typically include computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0103] The above provides a detailed description of the preferred embodiments of this application. However, this application is not limited to the above-described embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of this application. All such equivalent modifications or substitutions are included within the scope defined by this application.

Claims

1. A flash memory data decoding and recovery method, characterized in that, include: The first data page to be decoded is determined from multiple data storage pages of the flash memory's data storage block; Perform a first data reading process and a first hardware decoding process on the first data page to obtain the initial hardware decoding status of the first data page; If the first hardware decoding process fails, the target decoding mode is re-determined based on the initial hardware decoding situation; wherein, the target decoding mode is: hardware decoding mode or software decoding mode; According to the target decoding mode, the first data page is subjected to second data reading processing and data decoding processing to obtain the flash memory decoding recovery data of the first data page, and the decoding of the first data page is completed. The step of re-determining the target decoding mode based on the initial hardware decoding situation includes: When the initial hardware decoding is successful, the decoded data obtained after the first hardware decoding process is statistically analyzed to obtain the ratio between the number of bit values ​​0 and the number of bit values ​​1; based on the comparison result of the ratio with the preset value range, the target decoding mode is determined.

2. The flash memory data decoding and recovery method according to claim 1, characterized in that, The step of performing a first data reading process and a first hardware decoding process on the first data page to obtain the initial hardware decoding status includes: The first reread voltage parameter is determined from multiple sets of candidate reread voltage parameters in the preset reread table; The first data page is processed by first data reading based on the first reread voltage parameter to obtain the first data to be decoded. The first hardware decoding process is performed on the first data to be decoded to obtain the initial hardware decoding status.

3. The flash memory data decoding and recovery method according to claim 1, characterized in that, The step of re-determining the target decoding mode based on the initial hardware decoding situation includes: When the initial hardware decoding condition is: all decoding errors, the target decoding mode is determined to be hardware decoding mode.

4. The flash memory data decoding and recovery method according to claim 3, characterized in that, Determining the target decoding mode based on the comparison result between the ratio and a preset value range includes: When the comparison result is that the ratio is within a preset range, the target decoding mode is determined to be a software decoding mode. When the comparison result is that the ratio is not within the preset range, the target decoding mode is determined to be a hard decoding mode.

5. The flash memory data decoding and recovery method according to claim 2, characterized in that, The step of performing a second data reading process and a data decoding process on the first data page according to the target decoding mode to obtain the flash memory decoding recovery data of the first data page includes: When the target decoding mode is hard decoding mode, the second reread voltage parameter is obtained sequentially from multiple sets of candidate reread voltage parameters in the preset reread table; The first data page is processed by second data reading based on the second reread voltage parameter to obtain the second data to be decoded. The second data to be decoded is subjected to a second hardware decoding process to obtain the flash memory decoding recovery data of the first data page.

6. The flash memory data decoding and recovery method according to claim 1, characterized in that, The step of performing a second data reading process and a data decoding process on the first data page according to the target decoding mode to obtain the flash memory decoding recovery data of the first data page includes: When the target decoding mode is software decoding mode, the decoding error data obtained after the first hardware decoding process is subjected to a second data reading process to obtain soft information. The soft information is then subjected to soft decoding to obtain the flash memory decoding recovery data of the first data page.

7. The flash memory data decoding and recovery method according to claim 2, characterized in that, The method further includes: After decoding the first data page, the second data page to be decoded is determined sequentially from multiple data storage pages of the data storage block; Perform a first data reading process and a first hardware decoding process on the second data page to obtain the initial hardware decoding status of the second data page; If the first hardware decoding process fails, the target decoding mode is re-determined based on the initial hardware decoding situation; According to the target decoding mode, the second data page is subjected to second data reading processing and data decoding processing to obtain the flash memory decoding recovery data of the second data page, and the decoding of the second data page is completed; The decoding process continues until all data storage pages in the data block are decoded, resulting in the decoded and recovered flash memory data of the data storage block.

8. A flash memory data decoding and recovery device, characterized in that, The device includes at least one processor and a memory for communicatively connecting to the at least one processor; the memory stores instructions executable by the at least one processor, which, when executed by the at least one processor, enable the at least one processor to perform the flash memory data decoding and recovery method as described in any one of claims 1 to 7.

9. An electronic device, characterized in that, Includes the flash memory data decoding and recovery device as described in claim 8.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions for causing a computer to perform the flash memory data decoding and recovery method as described in any one of claims 1 to 7.

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