Ka-band active phased-array antenna system

Abstract

The invention discloses a Ka-band active phased-array antenna system, which belongs to the technical field of phased-array antennae and comprises an active phased-array sub-array and a signal processing unit arranged in a split manner, the active phased array sub-array adopts a tiled flat integrated structure and is integrated with an antenna array surface, a TR assembly and a beam forming device; the signal processing unit comprises a baseband processing circuit; and the active phased array sub-array is connected with the signal processing unit through a coaxial connector and a coaxial cable, and is used for transmitting a radio frequency signal, a control signal and a direct current power supply. According to the invention, the requirements of small size, long communication distance, omnidirectional coverage of wave beams and limited wiring space in a high-integration scene are met.

Description

Technical Field

[0001] This application relates to a Ka-band active phased array antenna system, belonging to the field of phased array antenna technology. Background Technology

[0002] In communication applications, phased array antennas, with their three major technical features of flexible beamforming, spatial power combining, and spatial filtering, improve the communication quality of wireless communication systems, increase system flexibility, and reduce the impact of interference signals on the system.

[0003] In 2017, Chen Junquan, He Haidan, and others designed a Ka-band "Wat-type" active phased array antenna. Their paper, titled "Design of a Ka-band 'Wat-type' Active Phased Array Antenna," was published in *Modern Electronics Technology*, Vol. 40, No. 7, 2017, pp. 43-47, DOI: 10.16652 / j.issn.1004-373x.2017.07.012. Employing multi-functional integrated chip technology, they achieved higher-density chip integration within the TR component, simplified peripheral circuit design, improved lateral spatial integration, and solved the problem of limited space, thus realizing the design of the "Wat-type" TR component. Simultaneously, the overall architecture of the "Wat-type" active phased array antenna adopted a modular subarray design, simplifying the vertical interconnection of the system and improving its testability, maintainability, and scalability. The antenna has a 16×16 size, an operating bandwidth of 27.0 GHz ± 1.0 GHz, an antenna gain of 24.6 dBi within the scanning range, and an effective isotropic radiated power (EIRP) of 38.4 dBW for the phased array system. The antenna has three external electrical interfaces: an RF (radiofrequency) interface, a control interface, and a power interface.

[0004] In 2019, Zheng Xu, Chengxiang Hao, and others from the University of Chinese Academy of Sciences proposed a novel design for a small Ku-band active electronically scanned antenna array. The paper, titled "A Compact Ku-Band Active Electronically Steerable Antenna with Low-Cost 3D T / R Module," was authored by Zheng Xu, Chengxiang Hao, Kuiwen Xu, and Shichang Chen. It was published in the journal *Wireless Communications and Mobile Computing* in 2019 (Volume 2019, Article ID 5287679, DOI: https: / / doi.org / 10.1155 / 2019 / 5287679). This antenna array features a low-cost and integrated T / R 3D module. The entire system employs a vertically interconnected three-dimensional multilayer technology to construct a hermetically packaged RF module. 3D T / R technology significantly improves system integration and reduces implementation cost and size by assembling different multifunctional modules into a complete multilayer board. Furthermore, a broadband circularly polarized antenna array was designed in LTCC and connected to the proposed T / R module to form a complete active phased array. The antenna has an 8×8 size, a beam scanning angle of ±60°, and an EIRP ≥ 24.4 dBW. The antenna has three external electrical interfaces: an excitation interface, a control interface, and a power interface.

[0005] In 2020, Yusheng Yin, Zhe Zhang, and others proposed a 256-element phased-array antenna for 5G applications in the 24-29.5 GHz band. The paper, titled "A 24-29.5 GHz 256-Element 5G Phased-Array with 65.5 dBm Peak EIRP and 256-QAM Modulation," was published at the 2020 IEEE / MTT-S International Microwave Symposium. The authors are Yusheng Yin, Zhe Zhang, Tumay Kanar, Samet Zihir, and Gabriel M. Rebeiz. (Information from IMS), Publication Year: 2020, Document Identifier: Conference Paper Number 978-1-7281-6815-9, Pages: 687-690, Access Platform: IEEE Xplore (full text available through this platform). This array is based on a commercially available 2×2 TRX beamformer chip, designed using SiGe BiCMOS technology, and employs 6-bit phase control and 8-bit gain control. After calibration, the phased array achieves a sidelobe level of -20 dB and can scan up to ±60° in the azimuth plane, with an EIRP of 65.5 dBm. The antenna has three external electrical interfaces: an RF high-frequency interface, a control interface, and a power interface.

[0006] In 2022, Liu Weiwei, Han Wei, and others from Xi'an Jiaotong University applied for a patent for a K-band scalable tile-type subarray, phased array antenna, and satellite system, with publication number CN115173081B. The patent shows that each K-band multi-channel tile-type component has a subarray digital phased array antenna on its first side and a first radio frequency interface and a first power supply control interface on its second side; the K-band tile-type frequency converter is equipped with multiple second radio frequency interfaces and multiple second power supply control interfaces; multiple K-band multi-channel tile-type components and K-band tile-type frequency converters are connected through the first radio frequency interface and the second radio frequency interface, and the first power supply control interface and the second power supply control interface are connected.

[0007] Currently, most phased array antennas are based on discrete component brick-type TR (Transmitter-Receiver) modules or tile-type TR modules, employing MCM (Multi-Chip Module) technology. This results in complex manufacturing processes, high costs, and significant thickness, making it difficult to achieve a thin and lightweight design and modular structure for phased array antennas. Therefore, simplifying the phased array antenna topology and achieving thinness and modularity is the mainstream trend in current phased array antenna development. Many conventional phased array antennas employ a separate architecture for RF signals, IF signals, control signals, reference clock signals, LO local oscillator, and power supply, using multiple external interfaces, typically including: high-frequency interface, control interface, LO local oscillator interface, and power supply interface. Too many interfaces lead to increased costs and reduced scalability and reliability. Furthermore, too many interfaces make it difficult to achieve miniaturization and high integration of active phased array antennas, hindering their adaptation to highly integrated applications. Summary of the Invention

[0008] According to one aspect of this application, a Ka-band active phased array antenna system is provided, which addresses the requirements of small size, long communication distance, omnidirectional beam coverage, and limited wiring space in highly integrated scenarios.

[0009] A Ka-band active phased array antenna system, characterized in that it comprises: an active phased array subarray and a separately configured signal processing unit; The active phased array subarray adopts a tiled flat integrated structure and integrates antenna array, TR components and beamforming devices; The signal processing unit includes a baseband processing circuit; The active phased array subarray is connected to the signal processing unit via a coaxial connector and a coaxial cable for transmitting radio frequency signals, control signals, and DC power.

[0010] Furthermore, the active phased array subarray also includes integrated control and interface circuitry; The control and interface circuit includes a control processor; The control processor is electrically connected to the TR component and the beamforming device, and is used to send beam control commands to the TR component and the beamforming device and receive their status information.

[0011] Furthermore, the control and interface circuit also includes the following coupled components: The first interface integrated circuit is connected to the signal processing unit via the coaxial cable and is used to receive control signals from the signal processing unit. The first control circuit is electrically connected to the first interface integrated circuit and the control processor, and is used to convert and distribute control signals; The first intermediate frequency circuit is electrically connected to the TR component and the beamforming device, and is used to process the transmission and reception of intermediate frequency signals with the TR component and the beamforming device. A clock circuit is used to provide a reference clock signal for the control and interface circuit. The PLL is electrically connected to the clock circuit, the TR component, and the beamforming device, and is used to generate a local oscillator signal based on the reference clock signal and provide it to the TR component and the beamforming device. The first control circuit is also electrically connected to the first intermediate frequency circuit, the clock circuit and the PLL, respectively, for coordinating and controlling the working timing of each circuit.

[0012] Furthermore, the first control circuit integrates a modem; The modem is electrically connected to the first interface integrated circuit and the control processor, and is used to perform OOK modulation and demodulation on the control signals transmitted through the first interface integrated circuit.

[0013] Furthermore, the first control circuit is connected to the control processor via an SPI interface, and the control processor configures the first control circuit to a bidirectional synchronous data signal interface mode via the SPI interface. The control processor is an FPGA or a microcontroller; The SPI interface includes four signal lines: data input, data output, clock, and chip select. The first control circuit contains a set of data registers that can be read and written through the SPI interface, used to configure the working mode, read status information, and digital RSSI values.

[0014] Furthermore, the signal processing unit also includes a coupled component: Second interface integrated circuit; The second control circuit is electrically connected to the baseband processing circuit and the second interface integrated circuit, and is used to forward control commands and status information; The second intermediate frequency circuit is electrically connected to the baseband processing circuit and the second interface integrated circuit, and is used to convert between baseband signals and intermediate frequency signals; A reference clock circuit, electrically connected to the baseband processing circuit and the second intermediate frequency circuit, is used to provide a reference clock for signal processing; The second interface integrated circuit is electrically connected to the second intermediate frequency circuit and the second control circuit, and is connected to the first interface integrated circuit in the active phased array subarray via a coaxial cable, for aggregating and transmitting radio frequency intermediate frequency signals, control signals and DC power.

[0015] Furthermore, the antenna array is an integrated multilayer dielectric printed circuit board structure; The integrated multilayer dielectric printed circuit board structure includes, from top to bottom, a passive antenna array, a multifunctional integrated motherboard, and components disposed on the multifunctional integrated motherboard. The multi-functional integrated motherboard integrates control wiring, power supply network and beamforming network; The TR components, beamforming devices, and control and interface circuits are integrated on the multi-functional integrated motherboard.

[0016] Furthermore, the system also includes a heat dissipation plate, which is disposed at the bottom of the antenna array.

[0017] Furthermore, the TR component and beamforming device include multiple TR channels arranged in parallel, and each TR channel integrates an amplifier, a digitally controlled phase shifter and a digitally controlled attenuator that are electrically connected in sequence; In the transmission operation state, the intermediate frequency signal input to the TR channel is amplified by the amplifier, and after the phase and amplitude are adjusted by the digitally controlled phase shifter and the digitally controlled phase shifter, it is synthesized by the power combiner and radiated through the antenna array. In the receiving state, the signal received by the antenna array is decomposed into each TR channel by the power combiner, and then sequentially passed through the digitally controlled attenuator, digitally controlled phase shifter and amplifier for amplitude and phase adjustment and low-noise amplification before outputting the intermediate frequency signal.

[0018] Furthermore, the signal processing unit provides a reference clock signal and DC power to the active phased array subarray via the coaxial cable.

[0019] The beneficial effects that this application can produce include: This application provides a Ka-band active phased array antenna system that employs a separate design for the active phased array subarray and the signal processing unit. The active phased array subarray utilizes a tiled flat panel integrated structure, resulting in high integration and a compact structure. The signal processing unit is equipped with baseband processing circuitry to ensure signal processing capabilities. The two are connected via coaxial connectors and coaxial cables, enabling efficient transmission of radio frequency signals, control signals, and DC power. This design enhances the system's flexibility and maintainability, optimizes the performance of each component, and reduces the overall system complexity and cost. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of a Ka-band active phased array antenna system according to one embodiment of this application; Figure 2 This is a block diagram of a Ka-band active phased array antenna system according to one embodiment of this application; Figure 3This is a block diagram of the second control circuit in a Ka-band active phased array antenna system according to one embodiment of this application; Figure 4 This is a block diagram of the first control circuit in a Ka-band active phased array antenna system according to one embodiment of this application; Figure 5 This is a block diagram of the second interface integrated circuit in a Ka-band active phased array antenna system according to one embodiment of this application; Figure 6 This is a block diagram of the first interface integrated circuit in a Ka-band active phased array antenna system according to one embodiment of this application; Figure 7 This is a diagram of the antenna array structure in a Ka-band active phased array antenna system according to one embodiment of this application; List of components and reference numerals: 1-Active phased array subarray; 2-Signal processing unit; 3-Second interface integrated circuit; 4-First interface integrated circuit; 5-Second control circuit; 6-First control circuit; 7-Second intermediate frequency circuit; 8-First intermediate frequency circuit; 9-Reference clock circuit; 10-Clock circuit; 13-Baseband processing circuit; 14-Control processor; 15-Coaxial cable; 16-PLL; 17-TR component and beamforming device; 18-Antenna array; 18.1-Passive antenna array; 18.2-Multifunctional integrated motherboard; 19-Coaxial connector; 20-Heat dissipation plate. Detailed Implementation

[0021] The present application is described in detail below with reference to the embodiments, but the present application is not limited to these embodiments.

[0022] See Figure 1-7 A Ka-band active phased array antenna system, characterized in that it includes: an active phased array subarray 1 and a separately configured signal processing unit 2; The active phased array subarray 1 adopts a tiled flat integrated structure and integrates an antenna array 18, a TR component and a beamforming device 17. The signal processing unit 2 includes a baseband processing circuit 13; The active phased array subarray 1 is connected to the signal processing unit 2 via a coaxial connector 19 and a coaxial cable 15 for transmitting radio frequency signals, control signals and DC power.

[0023] Specifically, the active phased array subarray includes an antenna array, a transceiver module (TR), and a beamforming device. The antenna array enables spatial radiation and reception of Ka-band radio frequency signals. The TR module (transceiver module) achieves signal amplitude / phase adjustment and, in conjunction with the beamforming device, completes flexible beamforming. A tiled structure integrates the antenna, TR, and beamforming, reducing signal loss and improving integration. The baseband processing circuit filters, demodulates, and decodes the down-converted baseband signal from the received radio frequency signal, or encodes, modulates, and up-converts the transmitted baseband signal. It generates control commands and feeds back the processed valid data. The coaxial connector and coaxial cable simultaneously transmit three types of key signals: radio frequency signals, control signals, and DC power. The coaxial structure reduces transmission loss and interference of high-frequency Ka-band signals, ensuring signal quality.

[0024] Among these technologies, tile-based design is a key technology for miniaturization and high-density integration of phased array antennas. Compared with the traditional brick structure, it offers significant advantages: It integrates the antenna array, TR components, and beamforming devices in a layered or parallel manner within a flat panel space, greatly reducing the subarray volume; the short physical distance between components avoids signal attenuation caused by long-distance interconnections in traditional discrete layouts, improving the transmission efficiency of Ka-band signals; it reduces the number of external connectors, lowering the risk of failure due to loose interfaces and improving system environmental adaptability. Furthermore, the separate setup of the RF front-end and baseband processing allows for flexible adaptation to application scenarios: subarrays can be installed externally or in confined spaces, while signal processing units can be installed internally or away from radiation areas, resolving the layout contradiction of the RF front-end needing to be close to space and the baseband processing needing to be away from interference; the TR components are the main heat source of the phased array, and the subarray can be designed with its own heat dissipation structure; the signal processing unit can use conventional heat dissipation, avoiding localized overheating problems caused by centralized heat dissipation; if a unit fails, it can be disassembled and repaired individually without replacing the entire system, reducing maintenance costs. Ka band belongs to the millimeter-wave band and has the advantages of wide bandwidth, high resolution, and small size. However, it also has the problems of large signal attenuation and susceptibility to interference. This system adapts to the characteristics of Ka band through two design features: the tiled structure shortens the transmission path of Ka band signals within the subarray, reducing high-frequency loss; and the use of coaxial connectors and coaxial cables, whose shielding performance is better than that of ordinary wires, can reduce the impact of external electromagnetic interference (EMI) on Ka band signals during transmission, while reducing the loss of signal radiation outward, thus ensuring the transmission quality of high-frequency signals.

[0025] In this application, the active phased array subarray adopts a tiled flat-panel integrated structure, integrating an active phased array antenna array and TR component beamforming devices. Additionally, integrated with the active phased array antenna array are a first interface integrated circuit, a first control circuit, a first intermediate frequency circuit, and a clock circuit. The active phased array antenna array employs a highly integrated multilayer dielectric printed circuit board with 17 TR components and beamforming devices soldered on it. From top to bottom, it consists of: a passive antenna array, a multi-functional integrated motherboard (control, power supply, beam network), components, and a heat dissipation plate. The active phased array antenna array is connected to the signal processing unit via coaxial connectors and coaxial cables. The active phased array antenna array uses highly integrated TR component beamforming devices, integrating amplifiers, digitally controlled attenuators, digitally controlled phase shifters, power combiners, etc., significantly reducing the number of chips compared to traditional phased arrays, lowering costs, and improving reliability.

[0026] The active phased array subarray 1 also includes an integrated control and interface circuit; The control and interface circuit includes a control processor 14; The control processor 14 is electrically connected to the TR component and the beamforming device 17, and is used to send beam control commands to the TR component and the beamforming device 17 and receive their status information.

[0027] The control and interface circuit also includes the following coupled components: The first interface integrated circuit 4 is connected to the signal processing unit 2 via the coaxial cable 15 and is used to receive control signals from the signal processing unit 2. The first control circuit 6 is electrically connected to the first interface integrated circuit 4 and the control processor 14, and is used to convert and distribute control signals; The first intermediate frequency circuit 8 is electrically connected to the TR component and the beamforming device 17, and is used to process the transmission and reception of intermediate frequency signals between the TR component and the beamforming device 17. Clock circuit 10 is used to provide a reference clock signal for the control and interface circuit; PLL16 is electrically connected to the clock circuit 10 and the TR component and beamforming device 17, and is used to generate a local oscillator signal according to the reference clock signal and provide it to the TR component and beamforming device 17. The first control circuit 6 is also electrically connected to the first intermediate frequency circuit 8, the clock circuit 10 and the PLL 16 respectively, for coordinating and controlling the working timing of each circuit.

[0028] Specifically, the control processor receives upper-level instructions (such as beam pointing, transmit power, and operating mode) from the signal processing unit, parses and converts them, and generates specific control signals for the TR components, beamforming devices, etc. Simultaneously, it is also responsible for collecting the subarray's status information and reporting it to the signal processing unit; the first interface integrated circuit enables reliable transmission of data, control instructions, and status information between the subarray and the signal processing unit. It may include multiple bus interfaces (such as SPI, I...). 2 The control circuit uses various communication technologies (such as C, LVDS, Ethernet, etc.) to convert the parallel data from the control processor into a high-speed serial signal suitable for long-distance transmission, and vice versa. The control signals output by the first control circuit are usually low-voltage, low-current digital signals, which cannot directly drive the high-power devices inside the TR component (such as phase shifters and attenuators). This circuit is responsible for level conversion and power amplification of these weak control signals to generate sufficiently strong drive signals to precisely control the operating state of the TR component. In the receiving link, the first intermediate frequency circuit down-converts the radio frequency (RF) signal output by the TR component to the intermediate frequency (IF) for subsequent filtering, amplification, and digitization. In the transmitting link, it up-converts the IF signal from the signal processing unit to a Ka-band RF signal and then sends it to the TR component for power amplification and radiation. The clock circuit provides a stable and accurate operating clock signal for all digital circuits (such as control processors, interface ICs, and PLLs) within the subarray. Typically composed of high-precision crystal oscillators or temperature-compensated crystal oscillators (TCXOs), the digital system's timing logic is correct. The phase-locked loop (PLL) utilizes a reference frequency provided by the clock circuit to generate one or more highly stable, high-purity local oscillator (LO) signals through phase comparison and feedback. These LO signals are sent to the first intermediate frequency circuit as a reference for frequency conversion, ensuring high frequency and phase consistency between the transmit and receive signals of the entire subarray—a prerequisite for achieving precise beamforming.

[0029] The first interface integrated circuit, serving as the sole high-speed data interaction hub between the active phased array subarray and the separate signal processing unit, establishes a connection with the signal processing unit via a single coaxial cable. The first interface integrated circuit internally integrates: a control signal transceiver module for decoupling and extracting baseband control commands from the coaxial cable and transmitting the control commands to the first control circuit; an intermediate frequency (IF) signal multiplexing / demultiplexing module electrically connected to the first IF circuit, used to multiplex the IF signal with DC power supply on the transmission path and transmit it via the coaxial cable, or demultiplex the IF signal from the signal on the coaxial cable on the receiving path; and a clock recovery module for extracting a clock reference from the composite signal transmitted via the coaxial cable and providing a synchronization reference for the clock circuit.

[0030] It is worth noting that the signal reception process is as follows: the antenna array receives Ka-band electromagnetic waves in space, the signal enters the TR component, and undergoes low-noise amplification (LNA) and preliminary amplitude / phase adjustment; the pre-processed RF signal is sent to the first intermediate frequency (IF) circuit; the PLL generates a stable local oscillator (LO) signal based on the reference clock provided by the clock circuit and provides it to the first IF circuit; the first IF circuit mixes the RF signal with the LO signal and down-converts it to an IF signal; the IF signal is transmitted back to the signal processing unit via a coaxial cable for subsequent filtering, amplification, analog-to-digital conversion (ADC), and baseband signal processing; the signal processing unit calculates the required beam direction based on the target location or communication requirements and generates corresponding control commands; these commands are transmitted to the subarray via a coaxial cable and received and decoded by the first interface integrated circuit. The control processor receives instructions from the interface IC, parses them, and calculates the specific values ​​that the phase shifter and attenuator in each TR component should be set to. The control processor sends these control values ​​to the first control circuit. The first control circuit performs level conversion and power amplification on the control signals to drive the phase shifter and attenuator inside the TR component, precisely adjusting the signal phase and amplitude of each antenna element, thereby achieving beam pointing and shaping. The control processor also collects the operating status (such as temperature and current) of key components such as the TR component through the control circuit. This status information is then fed back to the signal processing unit through the interface IC and coaxial cable to realize system monitoring and fault diagnosis.

[0031] The first control circuit 6 integrates a modem; The modem is electrically connected to the first interface integrated circuit 4 and the control processor 14, and is used to perform OOK modulation and demodulation on the control signals transmitted through the first interface integrated circuit 4.

[0032] Specifically, integrating a modem supporting OOK (On-Off Keying) modulation in the first control circuit provides crucial support for low-complexity, high-reliability control signal transmission within the subarray and between the subarray and the signal processing unit, particularly suited to the real-time and anti-interference requirements of phased array systems. The OOK modulation logic represents digital signals "1" and "0" by the presence or absence of a carrier wave. The specific principle is as follows: when transmitting a digital "1", the modem outputs a carrier signal (such as a specific frequency RF / IF signal); when transmitting a digital "0", the modem outputs a carrier-free signal (i.e., signal amplitude is 0). The receiving end demodulates and reconstructs the original digital signal by detecting the presence of a carrier wave, without the need for complex phase or amplitude discrimination circuits. Its structure is extremely simple, power consumption is low, and demodulation speed is fast, but its noise immunity depends on the signal-to-noise ratio (SNR) of the carrier amplitude and noise.

[0033] The first control circuit converts the weak control signals from the control processor into strong signals that can drive the TR components. The OOK modem plays a crucial role in the reliable encoding and transmission of control commands. Based on beamforming requirements, the control processor generates digital control commands for each TR component, such as the phase shifter phase value and attenuator attenuation. The OOK modem in the first control circuit receives these digital commands, mapping "1" to "carrier" and "0" to "no carrier," generating an OOK modulated signal. The modulated OOK signal is amplified by the power amplifier unit of the first control circuit and then transmitted to the control interface of the TR components to drive the phase shifters and attenuators to complete parameter configuration. In some designs, the TR components will feed back the configuration results via OOK modulation, which is then restored to a digital signal by the OOK demodulator of the first control circuit and sent back to the control processor to confirm successful configuration, forming a closed loop.

[0034] In addition to issuing control commands, the first control circuit also needs to collect the operating status of the TR components (such as temperature, current, and fault alarms) and send it back to the control processor. In this scenario, the OOK modem undertakes the low-power encoding feedback function of the status data: the status sensor of the TR component outputs an analog signal, which is converted into a digital status code (such as binary "1001" for excessive temperature) by the ADC of the first control circuit; the OOK modem modulates the digital status code into a "carrier presence / absence" signal and transmits it to the control processor in a low-power manner; the control processor restores the status information through the OOK demodulator and then reports it to the signal processing unit through the first interface integrated circuit to realize real-time monitoring of the subarray status.

[0035] The first control circuit 6 is connected to the control processor 14 via an SPI interface, and the control processor 14 configures the first control circuit 6 into a bidirectional synchronous data signal interface mode via the SPI interface. The control processor 14 is an FPGA or a microcontroller; The SPI interface includes four signal lines: data input, data output, clock, and chip select. The first control circuit contains a set of data registers that can be read and written through the SPI interface, used to configure the working mode, read status information, and digital RSSI values.

[0036] Specifically, SPI (Serial Peripheral Interface) is a high-speed synchronous serial communication protocol, which serves as a dedicated data channel between the control processor 14 and the first control circuit 6 in this system; SPI is chosen instead of I. 2 Other serial protocols such as C and UART are highly compatible with the requirements of subarray control due to their high-speed synchronization, full-duplex operation, and strong anti-interference capabilities. SPI relies on the SCK clock provided by the master device for synchronization, and its data transmission rate is much higher than that of UART and I.2 C can meet the control processor's need for rapid configuration of the first control circuit; the SDO and SDI lines are independent, and the master and slave devices can send and receive data simultaneously within the same clock cycle. For example, while the control processor sends configuration instructions, the first control circuit sends back status information, which greatly improves the efficiency of data interaction; SPI adopts a differential clock and independent signal line design, and the transmission distance inside the subarray is short, so it is far less affected by external electromagnetic interference than UART, ensuring the reliability of control signal transmission. The control processor configures the first control circuit 6 into a bidirectional synchronous data signal interface mode via the SPI interface. Essentially, this leverages the full-duplex nature of the SPI protocol to provide the first control circuit with the ability to simultaneously receive control commands and receive status data. Bidirectional synchronization utilizes the full-duplex architecture of SPI, combined with the timing control capabilities of the control processor, to achieve synchronous command issuance and data upload. After power-on, the control processor (FPGA / microcontroller) first writes a specific command (such as binary "1010" representing bidirectional synchronous mode) to the "mode configuration register" of the first control circuit via the SPI interface, triggering the first control circuit to switch communication modes. The control processor generates a fixed-frequency SCK clock, which is transmitted to the first control circuit via the SPI clock line. Both sides calibrate their transmit and receive timing based on this clock. After the CS signal is pulled low, the control processor sends data via the SDO line and simultaneously receives data from the first control circuit via the SDI line. Data is transmitted synchronously on each edge of the SCK, achieving bidirectional synchronous interaction. This mode directly serves the precise control and real-time monitoring needs of the subarray, solving the efficiency problem of the traditional unidirectional interface requiring time-sharing for command issuance and status feedback.

[0037] It's worth noting that the integrated modem solution of the first control circuit allows for a more compact system design, saving space, power, and hardware, to realize a smart antenna system. The data modulator can provide OOK modulation. OOK is an ASK modulation using 100% modulation depth. The first control circuit is configured via a 4-wire SPI-compatible interface (PDI, PDO, PCLK, and PSEL) with 8-bit configuration registers, each with a 7-bit address. Read and write bits initiate read and write operations. Full configuration requires sending 33 data frames per 16-bit block (7 address bits, R / W bits, and 8 data bits). The time required for full configuration depends on the PCLK frequency. At a PCLK frequency of 10MHz, full configuration is completed within 53ms. Setting the device to power-down mode requires only sending one frame, taking less than 2ms in this case. All registers are readable. The first control circuit connects to the FPGA microcontroller via a 4-wire SPI. The FPGA programs the 6-channel active phased array antenna control circuitry through a 4-wire serial configuration interface (PDI, PDO, PCLK, PSEL) to different modes of a bidirectional synchronous data signal interface (DIO, DCLK). The FPGA can perform data encoding / decoding and monitor the frequency lock status, carrier detection status, or other status information of the pins. The FPGA can read digital RSSI values ​​and other status information through the four-wire serial interface. The FPGA uses 3 or 4 I / O pins as the configuration interface (PDI, PDO, PCLK, and PSEL). PDO should be connected to the 14 FPGA inputs. PDI, PCLK, and PSEL must be 14 FPGA outputs. If PDI and PDO are connected together and a bidirectional pin is used on the microcontroller, one I / O pin can be reserved. When the configuration interface is not used, the 14 FPGA pins connected to PDI, PDO, and PCLK can be used for other purposes. PDI, PDO, and PCLK are high-impedance inputs as long as PSEL is not activated (actively low). PSEL has an internal pull-up resistor that can be kept open or set to high in power-down mode to prevent trickle current from entering the pull-up.

[0038] The signal processing unit 2 further includes a coupled component: Second interface integrated circuit 3; The second control circuit 5 is electrically connected to the baseband processing circuit 13 and the second interface integrated circuit 3, and is used to forward control commands and status information; The second intermediate frequency circuit 7 is electrically connected to the baseband processing circuit 13 and the second interface integrated circuit 3, and is used to convert between baseband signals and intermediate frequency signals; The reference clock circuit 9 is electrically connected to the baseband processing circuit 13 and the second intermediate frequency circuit 7, and is used to provide a reference clock for signal processing; The second interface integrated circuit 3 is electrically connected to the second intermediate frequency circuit 7 and the second control circuit 5, and is connected to the first interface integrated circuit 4 in the active phased array subarray 1 via a coaxial cable 15, for aggregating and transmitting radio frequency intermediate frequency signals, control signals and DC power.

[0039] Specifically, the second interface integrated circuit and the first interface integrated circuit of the subarray establish bidirectional communication via a coaxial cable to complete the format conversion of signals between the subarray and the signal processing unit (such as serial / parallel conversion, protocol decoding / encoding), and realize the multiplexing / demultiplexing of multiple signals; the second control circuit generates system-level control commands, receives status information fed back by subarray 1 (such as TR component failure, RSSI value), performs fault diagnosis and logic decision-making; controls the operating parameters of the second intermediate frequency circuit and the reference clock circuit; the second intermediate frequency circuit receives the intermediate frequency signal transmitted by the subarray, performs secondary filtering, amplification, and gain control; sends the intermediate frequency signal to be transmitted to subarray 1, performs pre-amplification and spectrum calibration; suppresses noise and interference in the intermediate frequency signal; the reference clock circuit generates a system-level high-precision reference clock, provides clock signals to the subarray through the second interface integrated circuit and coaxial cable, provides a synchronization reference for the subarray's PLL and clock circuit; provides a clock for the baseband processing circuit and the second control circuit inside the signal processing unit, ensuring the timing synchronization of the entire system.

[0040] The second interface integrated circuit serves as a high-speed data interaction hub between the signal processing unit and the separate active phased array subarray. The second interface integrated circuit internally integrates: a control signal modulation module, electrically connected to the second control circuit, for modulating control commands from the baseband processing circuit onto a carrier wave; an intermediate frequency (IF) signal multiplexing / demultiplexing module, electrically connected to the second IF circuit, for multiplexing the IF signal with the modulated control signal and DC power supply on the transmission path and transmitting it to the subarray via a coaxial cable, or demultiplexing the IF signal from the composite signal on the coaxial cable on the receiving path; and a clock embedding module, electrically connected to the reference clock circuit, for embedding a reference clock signal into the composite signal to be transmitted.

[0041] It is worth noting that in the receiving scenario, the antenna array of the subarray receives the Ka-band RF signal, which is amplified and phase-adjusted by the TR component before being sent to the first intermediate frequency (IF) circuit. The first IF circuit down-converts the RF signal to an IF signal and performs preliminary filtering. The IF signal is encoded by the first interface integrated circuit and transmitted to the second interface integrated circuit of the signal processing unit via a coaxial cable. The second interface integrated circuit demultiplexes and restores the signal format before sending it to the second IF circuit. The second IF circuit performs secondary filtering and gain control on the IF signal, and finally sends it to the baseband processing circuit for analog-to-digital conversion and baseband demodulation. In the transmission scenario, the baseband processing circuit generates the baseband signal to be transmitted, which is then converted from digital to analog and sent to the second intermediate frequency (IF) circuit. The second IF circuit modulates the baseband signal to generate an IF signal and pre-amplifies it. The IF signal is multiplexed and encoded by the second interface integrated circuit and then transmitted to the first interface integrated circuit of the subarray via a coaxial cable. The first interface integrated circuit restores the signal and sends it to the first IF circuit. The first IF circuit up-converts the IF signal to a Ka-band radio frequency (RF) signal, sends it to the TR component for power amplification, and finally radiates it into space through the antenna array.

[0042] The antenna array 18 is an integrated multilayer dielectric printed circuit board structure; The integrated multilayer dielectric printed circuit board structure includes, from top to bottom, a passive antenna array 18.1, a multifunctional integrated motherboard 18.2, and components disposed on the multifunctional integrated motherboard; The multi-functional integrated motherboard integrates control wiring, power supply network and beamforming network; The TR component, beamforming device 17, and control and interface circuitry are integrated on the multi-functional integrated motherboard.

[0043] Specifically, the three core networks integrated into the multi-functional integrated motherboard—control routing, power supply network, and beamforming network—directly determine the signal processing efficiency, power supply stability, and beamforming performance of the subarray. The control routing serves as the command channel between the control processor and the beamforming devices of the TR components. It must meet low latency and anti-interference requirements, employing microstrip or stripline designs with impedance controlled at 50Ω. Key routing lines utilize differential pair designs to cancel common-mode interference through differential signals. The configuration commands output by the control processor are transmitted to the control interface of each TR component, while simultaneously transmitting the status feedback signals of the TR components back to the control processor. The control routing is typically located in the inner layers of the motherboard, utilizing the ground planes of the upper and lower layers to form a shielded cavity, further reducing external electromagnetic interference (EMI) and ensuring the accuracy of control command transmission. The power supply network provides a stable DC power supply for the TR components, control, and interface circuits. It needs to address the issues of high current transmission and voltage ripple suppression. A hybrid star and distributed power supply architecture is adopted, with the main power interface located at the edge of the motherboard. Power is distributed to each power distribution point (PDN) via wide copper foil traces, and then filtered by distributed capacitors before being supplied to the TR components, control circuits, and other devices. Decoupling capacitors are placed near the power pins of each device to suppress supply voltage ripple and prevent voltage fluctuations from causing phase drift in the TR components and logic errors in the control circuits. The wide copper foil of the power supply network also serves as an auxiliary heat dissipation function; heat generated by the TR components can be conducted through the pads to the wide copper foil and then diffused to the entire motherboard, reducing the temperature of local hot spots. The beamforming network is the core transmission channel for Ka-band RF signals, responsible for combining or distributing signals from multiple antenna elements. It needs to meet the requirements of low insertion loss and high isolation, and adopts a power divider / combiner array design to adapt to the number of elements in the passive antenna array. For example, in receive mode, the RF signals of 16 antenna elements are amplified by the TR component with low noise, and then combined into one signal through the beamforming network and transmitted to the first intermediate frequency circuit. The beamforming network uses the same high-frequency low-loss substrate as the top antenna to reduce the dielectric loss of Ka-band signals. Key nodes adopt an impedance gradient design to avoid signal reflection. Isolation resistors or grounding slots are set between adjacent power dividers / combiners to improve the isolation between channels, avoid signal crosstalk between different antenna elements, and ensure beamforming accuracy.

[0044] The system also includes a heat dissipation plate 20, which is disposed at the bottom of the antenna array 18.

[0045] The TR component and beamforming device 17 include multiple TR channels arranged in parallel, and each TR channel integrates an amplifier, a digitally controlled phase shifter and a digitally controlled attenuator that are electrically connected in sequence; In the transmission operation state, the intermediate frequency signal input to the TR channel is amplified by the amplifier, and after the phase and amplitude are adjusted by the digitally controlled phase shifter and the digitally controlled phase shifter, it is synthesized by the power combiner and radiated through the antenna array 18. In the receiving state, the signal received by the antenna array 18 is decomposed into each TR channel by the power combiner, and then sequentially passed through the digitally controlled attenuator, digitally controlled phase shifter and amplifier for amplitude and phase adjustment and low-noise amplification before outputting the intermediate frequency signal.

[0046] The signal processing unit 2 provides a reference clock signal and DC power to the active phased array subarray 1 via the coaxial cable 15.

[0047] Specifically, the TR components of the Ka-band phased array are the main heat source. If the heat cannot be dissipated in time, the device temperature will rise, seriously affecting the system performance. The heat dissipation plate is closely attached to the bottom of the antenna array 18 and is in direct contact with the underlying component mounting layer (usually by filling the gap with thermal grease or thermal pads, with a thermal conductivity ≥3W / (m・K)), forming a direct heat conduction path between the device and the heat dissipation plate. The internal structure adopts a microchannel water cooling or vapor chamber and fin design. The microchannel water cooling plate contains dozens of micron-level flow channels, and the coolant circulates in the flow channels, carrying away heat through convection. The vapor chamber design rapidly diffuses heat through the phase change of the internal working fluid, and then combines with the air cooling / liquid cooling system through external fins to adapt to different heat dissipation scenarios. The heat generated by the TR components during operation is transferred through the device housing, thermal interface material, and heat dissipation plate, improving the heat transfer efficiency compared to traditional natural heat dissipation. The heat dissipation plate, through its heat dissipation design, evenly diffuses the local hot spots of multiple TR components on the antenna array to the entire plate, keeping the array temperature fluctuation within ±5°C. It also has vibration and corrosion resistance properties, ensuring continuous and stable heat dissipation under complex operating conditions.

[0048] Furthermore, the amplifier includes a power amplifier and a low-noise amplifier. The PA amplifies the Ka-band signal after intermediate frequency up-conversion to watt-level power. The LNA amplifies the weak Ka-band signal received by the antenna with low noise, suppressing noise interference. The digitally controlled attenuator adjusts the attenuation amount through the SPI instructions of the control processor to precisely control the amplitude of the RF signal. The digitally controlled phase shifter adjusts the phase through SPI instructions to change the phase difference of the RF signal. In the power combiner, in the receiving link, the signals from multiple antenna elements amplified by the LNA and phase-shifted / attenuated are combined into one signal and transmitted to the first intermediate frequency circuit. In the transmitting link, the signal output from the first intermediate frequency circuit is distributed to the PAs of multiple antenna elements.

[0049] Meanwhile, the signal processing unit provides a reference clock signal and DC power to the active phased array subarray via a coaxial cable, solving the problems of subarray energy dependence and clock asynchrony caused by the separate setup. The signal processing unit has a built-in power module that converts the external input power into the DC voltage required by the subarray and transmits it to the subarray through the power core wire of the coaxial cable. It is then distributed to the power supply network via the first interface integrated circuit and finally supplies the TR components, control processor, and other devices. Ripple suppression and overcurrent protection designs are adopted to avoid voltage fluctuations causing phase drift of the TR components or short circuit damage to the devices. At the same time, wide-core, low-impedance cables are used for power transmission to reduce transmission loss and ensure the stability of power supply at the remote end of the subarray. The reference clock circuit of the signal processing unit generates a high-precision reference clock, which is converted into a differential clock signal by the second interface integrated circuit and transmitted to the subarray through the signal core wire of the coaxial cable. After demodulation by the first interface integrated circuit, it is sent to the clock circuit of the subarray as the timing reference of the PLL and control processor.

[0050] The above description is merely a few embodiments of this application and is not intended to limit this application in any way. Although this application discloses preferred embodiments as described above, it is not intended to limit this application. Any changes or modifications made by those skilled in the art without departing from the scope of the technical solution of this application using the disclosed technical content are equivalent to equivalent implementation cases and fall within the scope of the technical solution.

Claims

1. A Ka-band active phased array antenna system, characterized in that, include: An active phased array subarray (1) and a separately configured signal processing unit (2); The active phased array subarray (1) adopts a tiled flat integrated structure and integrates an antenna array (18), a TR component and a beamforming device (17). The signal processing unit (2) includes a baseband processing circuit (13); The active phased array subarray (1) is connected to the signal processing unit (2) via a coaxial connector (19) and a coaxial cable (15) for transmitting radio frequency signals, control signals and DC power.

2. The Ka-band active phased array antenna system according to claim 1, characterized in that, The active phased array subarray (1) also includes integrated control and interface circuits; The control and interface circuit includes a control processor (14). The control processor (14) is electrically connected to the TR component and the beamforming device (17) and is used to send beam control commands to the TR component and the beamforming device (17) and receive their status information.

3. The Ka-band active phased array antenna system according to claim 1, characterized in that, The control and interface circuit also includes the following coupled components: The first interface integrated circuit (4) is connected to the signal processing unit (2) via the coaxial cable (15) and is used to receive control signals from the signal processing unit (2); The first control circuit (6) is electrically connected to the first interface integrated circuit (4) and the control processor (14) and is used to convert and distribute control signals; The first intermediate frequency circuit (8) is electrically connected to the TR component and the beamforming device (17) and is used to process the transmission and reception of intermediate frequency signals between the TR component and the beamforming device (17). Clock circuit (10) is used to provide a reference clock signal for the control and interface circuit; PLL (16) is electrically connected to the clock circuit (10) and the TR component and beamforming device (17) for generating a local oscillator signal according to the reference clock signal and providing it to the TR component and beamforming device (17). The first control circuit (6) is also electrically connected to the first intermediate frequency circuit (8), the clock circuit (10) and the PLL (16) respectively, for coordinating and controlling the working timing of each circuit.

4. The Ka-band active phased array antenna system according to claim 3, characterized in that, The first control circuit (6) integrates a modem; The modem is electrically connected to the first interface integrated circuit (4) and the control processor (14) for performing OOK modulation and demodulation on the control signals transmitted through the first interface integrated circuit (4).

5. The Ka-band active phased array antenna system according to claim 3, characterized in that, The first control circuit (6) is connected to the control processor (14) via an SPI interface, and the control processor (14) configures the first control circuit (6) into a bidirectional synchronous data signal interface mode via the SPI interface. The control processor (14) is an FPGA or a microcontroller; The SPI interface includes four signal lines: data input, data output, clock, and chip select. The first control circuit (6) contains a set of data registers that can be read and written through the SPI interface, used to configure the working mode, read status information, and digital RSSI value.

6. The Ka-band active phased array antenna system according to claim 3, characterized in that, The signal processing unit (2) further includes a coupled component: Second interface integrated circuit (3); The second control circuit (5) is electrically connected to the baseband processing circuit (13) and the second interface integrated circuit (3) for forwarding control commands and status information; The second intermediate frequency circuit (7) is electrically connected to the baseband processing circuit (13) and the second interface integrated circuit (3) for converting between baseband signals and intermediate frequency signals; The reference clock circuit (9) is electrically connected to the baseband processing circuit (13) and the second intermediate frequency circuit (7) to provide a reference clock for signal processing; The second interface integrated circuit (3) is electrically connected to the second intermediate frequency circuit (7) and the second control circuit (5), and is connected to the first interface integrated circuit (4) through a coaxial cable (15) for aggregating and transmitting radio frequency intermediate frequency signals, control signals and DC power.

7. The Ka-band active phased array antenna system according to claim 1, characterized in that, The antenna array (18) is an integrated multilayer dielectric printed circuit board structure; The integrated multilayer dielectric printed circuit board structure includes, from top to bottom, a passive antenna array (18.1), a multifunctional integrated motherboard (18.2), and components disposed on the multifunctional integrated motherboard; The multi-functional integrated motherboard integrates control wiring, power supply network and beamforming network; The TR component, beamforming device (17), and control and interface circuitry are integrated on the multi-functional integrated motherboard.

8. The Ka-band active phased array antenna system according to claim 7, characterized in that, The system also includes a heat dissipation plate (20), which is disposed at the bottom of the antenna array (18).

9. The Ka-band active phased array antenna system according to claim 1, characterized in that, The TR component and beamforming device (17) include multiple TR channels arranged in parallel, each of which integrates an amplifier, a digitally controlled phase shifter and a digitally controlled attenuator connected in sequence; In the transmission operation state, the intermediate frequency signal input to the TR channel is amplified by the amplifier, and the phase and amplitude are adjusted by the digitally controlled phase shifter before being synthesized by the power combiner and radiated through the antenna array (18). In the receiving state, the signal received by the antenna array (18) is decomposed into each TR channel by the power combiner, and then the amplitude and phase are adjusted and amplified with low noise by the digitally controlled attenuator, digitally controlled phase shifter and amplifier in sequence, and then the intermediate frequency signal is output.

10. The Ka-band active phased array antenna system according to claim 1, characterized in that, The signal processing unit (2) provides a reference clock signal and DC power to the active phased array subarray (1) via the coaxial cable (15).

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