Unified carrier reverse lamination modulation method based on three-level converter

Abstract

The invention provides a unified carrier reverse lamination modulation method based on a three-level converter. The method comprises the following steps: acquiring the current three-phase reference voltage of the three-level converter; calculating a zero-sequence component of a current modulation strategy according to the three-phase reference voltage and the current modulation strategy; determining a three-phase modulation wave according to the three-phase reference voltage and the zero-sequence component; and generating a switching tube driving signal of each bridge arm in the three-level converter according to the three-phase modulation wave. According to the invention, through a unified zero-sequence component calculation mode, on the basis of carrier reverse-phase laminated modulation, compatibility with different modulation strategies is realized, a zero-sequence vector calculation process is omitted, a space vector region does not need to be judged, occupation of calculation resources when the modulation strategies are realized is effectively reduced, and the implementation efficiency of the modulation strategies is improved. And transient oscillation during strategy switching is suppressed.

Description

Technical Field

[0001] This disclosure relates to the field of inverter modulation technology, and in particular to a unified carrier reverse cascade modulation method, apparatus, storage medium, electronic device and three-level converter based on a three-level converter. Background Technology

[0002] With the rapid development of new energy industries such as photovoltaics, wind power, and energy storage, three-level converters are widely used in these industries due to their advantages, including high output current and voltage quality, low device losses, and low cost. The modulation methods for three-level converters can be divided into carrier in-phase cascade modulation and carrier out-of-phase cascade modulation. Compared to carrier in-phase cascade modulation, carrier out-of-phase cascade modulation reduces the operating time of small vectors in the three-level converter, suppresses fluctuations in zero-sequence voltage during switching between different sectors, and improves system stability, thus gaining widespread application in industry.

[0003] In the carrier inversion layered modulation method of a three-level converter, different modulation strategies have different characteristics. Traditional continuous pulse width modulation (SVPWM) strategies, such as Space Vector Pulse Width Modulation (SVPWM) and Zero Neutral-point Voltage (ZNV-SVPWM), exhibit low bus midpoint voltage ripple. However, SVPWM strategies increase device turn-on and turn-off losses, thus reducing system efficiency. Furthermore, SVPWM is susceptible to power factor fluctuations; a low power factor exacerbates bus midpoint voltage ripple in three-level converters, reducing the power quality of output voltage and current. In contrast, strategies such as Zero-Clamped Discontinuous Pulse Width Modulation (ZC-DPWM) and Discontinuous Pulse Width Modulation (DPWM3) effectively reduce device turn-on and turn-off losses in three-level converters by clamping the output state of the three-level converter to [P], [O], or [N] states, thereby improving system efficiency. Meanwhile, due to the use of small vectors, the DPWM modulation strategy keeps the bus midpoint voltage fluctuation essentially constant when the power value changes. Currently, some literature describes switching the modulation strategy of a three-level converter under different power factors and modulation ratios to meet the system's requirements under different operating conditions.

[0004] In traditional modulation strategies, differences in the method of generating zero-sequence components increase the computational load on the controller, and sudden changes in zero-sequence flow during strategy switching trigger LCL resonant current. Under certain operating conditions, modulation strategies struggle to balance bus midpoint voltage, efficiency, and power quality. Summary of the Invention

[0005] The purpose of this disclosure is to provide a unified carrier reverse stacking modulation method, apparatus, storage medium, electronic device, and three-level converter based on a three-level converter, so as to solve the problem that the difference in the zero-sequence component generation method in the prior art leads to an increase in the controller's computational load.

[0006] The embodiments of this disclosure adopt the following technical solution: a unified carrier reverse stacked modulation method based on a three-level converter, comprising: obtaining the current three-phase reference voltage of the three-level converter; calculating the zero-sequence component of the current modulation strategy according to the three-phase reference voltage and the current modulation strategy; determining the three-phase modulation wave according to the three-phase reference voltage and the zero-sequence component; and generating the switching transistor drive signal of each bridge arm in the three-level converter according to the three-phase modulation wave.

[0007] This disclosure also provides a unified carrier reverse-stacking modulation device based on a three-level converter, comprising: an acquisition module for acquiring the current three-phase reference voltage of the three-level converter; a zero-sequence component calculation module for calculating the zero-sequence component of the current modulation strategy based on the three-phase reference voltage and the current modulation strategy; a modulation wave calculation module for determining the three-phase modulation wave based on the three-phase reference voltage and the zero-sequence component; and a driving module for generating switching transistor driving signals for each bridge arm of the three-level converter based on the three-phase modulation wave.

[0008] This disclosure also provides a storage medium storing a computer program, which, when executed by a processor, implements the steps of the above-described unified carrier reverse cascade modulation method based on a three-level converter.

[0009] This disclosure also provides an electronic device, including at least a memory and a processor. The memory stores a computer program, and the processor, when executing the computer program in the memory, implements the steps of the above-described unified carrier reverse cascade modulation method based on a three-level converter.

[0010] This disclosure also provides a three-level converter, which includes at least the electronic equipment described above.

[0011] The beneficial effects of the embodiments of this disclosure are as follows: by using a unified method for calculating the zero-sequence component, compatibility with different modulation strategies is achieved on the basis of carrier anti-phase stacked modulation, the calculation process of the zero-sequence vector is omitted, there is no need to judge the region of the spatial vector, the occupation of computing resources during the implementation of the modulation strategy is effectively reduced, and transient oscillations during strategy switching are suppressed. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in one or more embodiments of this specification or in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a schematic diagram of the topology of an I-NPC three-level converter;

[0014] Figure 2 This is a flowchart of the unified carrier reverse stacking modulation method based on a three-level converter in the first embodiment of this disclosure;

[0015] Figure 3 This is a block diagram of the constant power control of the three-level converter in the first embodiment of this disclosure;

[0016] Figure 4 This is a schematic diagram of the control vector of the three-level converter in the first embodiment of this disclosure;

[0017] Figure 5 This is a schematic diagram of the third harmonic zero-sequence component constructed in the first embodiment of this disclosure;

[0018] Figure 6 T is the first embodiment of this disclosure mag Three-phase modulated waves with different values ​​and their zero-sequence component diagrams;

[0019] Figure 7 This is a schematic diagram of the structure of the unified carrier inverse stacked modulation device based on a three-level converter in the second embodiment of this disclosure. Detailed Implementation

[0020] To enable those skilled in the art to better understand the technical solutions in one or more embodiments of this specification, the technical solutions in one or more embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this specification, and not all of the embodiments. Based on one or more embodiments of this specification, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of this document.

[0021] With the rapid development of new energy industries such as photovoltaics, wind power, and energy storage, three-level converters are widely used in these industries due to their advantages, including high output current and voltage quality, low device losses, and low cost. The modulation methods for three-level converters can be divided into carrier in-phase cascade modulation and carrier out-of-phase cascade modulation. Compared to carrier in-phase cascade modulation, carrier out-of-phase cascade modulation reduces the operating time of small vectors in the three-level converter, suppresses fluctuations in zero-sequence voltage during switching between different sectors, and improves system stability, thus gaining widespread application in industry.

[0022] In the carrier-inverting cascaded modulation method of three-level converters, different modulation strategies have different characteristics. Traditional continuous pulse width modulation strategies such as SVPWM and ZNV-SVPWM have low bus midpoint voltage fluctuations. However, SVPWM strategies increase the turn-on and turn-off losses of devices, thus reducing system efficiency. Furthermore, SVPWM is easily affected by the power factor. When the power factor is low, it leads to aggravated bus midpoint voltage fluctuations in the three-level converter, thereby reducing the power quality of the output voltage and current. On the other hand, modulation strategies such as ZC-DPWM and DPWM3 effectively reduce the turn-on and turn-off losses of devices in the three-level converter by clamping the output state of the three-level converter to [P], [O], or [N] states, thus improving system efficiency. At the same time, the DPWM modulation strategy, due to the use of small vectors, keeps the bus midpoint voltage fluctuation value basically unchanged when the power value changes. Currently, some literature discusses switching the modulation strategy of three-level converters under different power factors and modulation ratios to meet the needs of the system under different operating conditions.

[0023] In traditional modulation strategies, differences in the method of generating zero-sequence components increase the computational load on the controller, and sudden changes in zero-sequence flow during strategy switching trigger LCL resonant current. Under certain operating conditions, modulation strategies struggle to balance bus midpoint voltage, efficiency, and power quality.

[0024] To address the aforementioned issues, the first embodiment of this disclosure provides a unified carrier inverse cascade modulation method based on a three-level converter. The execution entity can be the host controller of the three-level converter, primarily used to control the on / off switching of the bridge arm switches of the three-level converter according to different modulation strategies, ultimately outputting a three-phase sinusoidal signal. The method provided in this embodiment can generate the zero-sequence components of common modulation strategies in carrier inverse cascade modulation, such as Space Vector Pulse Width Modulation (SVPWM), Sinusoidal Pulse Width Modulation (SPWM), Zero-Crossing Clamping Discontinuous Pulse Width Modulation (ZC-DPWM), and Discontinuous Pulse Width Modulation (DPWM3), without vector calculation or region judgment. This effectively reduces the computational load on the controller and enables smooth switching between the aforementioned modulation strategies, improving system stability and providing a solution for the different modulation strategies required by the three-level converter under various operating conditions.

[0025] Figure 1 A schematic diagram of the topology of an I-NPC three-level converter is shown in this embodiment. Figure 1 The unified carrier inverse cascade modulation method is explained using the three-level converter shown as an example. Figure 1 As shown, each phase of the three-level converter consists of four switching transistors and two freewheeling diodes. Cap1 and Cap2 are the DC-side bus capacitors. dc S is the DC side voltage. xi Let S be the drive signal for the i-th switch in phase x, i.e., x = a, b, c; i = 1, 2, 3, 4. Let S be the drive signal for the i-th switch in phase x. xi When S is 1, the corresponding switch is turned on, and when S... xi When the value is 0, the corresponding switch is turned off. Therefore, analysis shows that each phase of the I-NPC three-phase three-level converter can output three levels: U... dc / 2, 0 and -U dc / 2, corresponding to states [P], [O], and [N] respectively. The I-NPC three-phase three-level converter is followed by an LCL filter system, which consists of three parts: inverter-side inductor L1, filter capacitor C, and grid-side inductor L2. The converter is connected to the grid through the LCL filter system.

[0026] Figure 2 The flowchart of the unified carrier reverse cascade modulation method based on a three-level converter in this embodiment is shown, which mainly includes steps S10 to S40:

[0027] S10: Obtain the current three-phase reference voltage of the three-level converter.

[0028] The core function of a three-level converter is to convert the DC-side voltage into a three-phase AC voltage that meets the requirements of the load or power grid. In practical applications, the converter needs to cope with disturbances such as load fluctuations and changes in DC-side voltage. Therefore, it is necessary to dynamically adjust the three-phase reference voltage through closed-loop control (such as voltage closed-loop and current closed-loop) to ensure stable output.

[0029] Figure 3 The constant power control block diagram of the converter in this embodiment is shown. This embodiment obtains the current loop output and the grid voltage feedforward output, performs summation, inverse Park and inverse Clark transformations, and then standardizes the transformation results to obtain the three-phase reference voltage u. a ,u b ,u c Specifically, since a PI loop can follow a DC current without steady-state error, the current loop in this embodiment uses a PI loop to calculate the current command I along the dq axis based on the current grid voltage. d and I q The grid-connected current is transformed by dq and then used as the feedback value input into the current loop. At the same time, since the grid voltage fluctuates, the output of the PI loop is superimposed with the grid voltage feedforward and then normalized to obtain the three-phase reference voltage.

[0030] S20, calculate the zero-sequence component of the current modulation strategy based on the three-phase reference voltage and the current modulation strategy.

[0031] In the modulation strategy of a three-level converter, the zero-sequence component is a "flexible adjustment tool." Its core function is to improve the converter's performance by optimizing the three-phase reference voltage without changing the line voltage output. The calculation method for the zero-sequence component differs for different modulation strategies. As the actual usage of the power grid changes, the modulation strategy also changes continuously. Therefore, the change in the corresponding zero-sequence component when switching between different modulation strategies is crucial for the stable operation of the power grid. However, in practice, the calculation of the zero-sequence component under various different strategies increases the computational load on the controller and makes it impossible to smoothly and timely adjust to the strategy switching, easily leading to sudden changes in zero-sequence and triggering LCL resonant current.

[0032] This embodiment constructs a general method for calculating zero-sequence components, which divides zero-sequence components into fixed zero-sequence components and uniformly modulated zero-sequence components. The fixed zero-sequence components are only related to the current three-phase reference voltage value and will not change with different modulation strategies, while the uniformly modulated zero-sequence components will be adjusted according to different modulation strategies. Therefore, different modulation strategies can be implemented by superimposing the uniformly modulated zero-sequence components on the fixed zero-sequence components.

[0033] Specifically, the control vector diagram of the three-level converter is as follows: Figure 4As shown, it mainly includes 27 voltage vectors, comprising 6 long vectors, 6 medium vectors, 12 small vectors, and 3 zero vectors. In the inverted cascaded modulation method, three-phase SVPWM only uses long and medium vectors. Other modulation strategies, such as SPWM and ZC-DPWM, can be considered as adding small vectors to SVPWM. Therefore, the fixed zero-sequence component in this embodiment can be calculated using the zero-sequence component calculation method of the SVPWM strategy. In actual calculation, firstly, based on the three-phase reference voltage u... a ,u b ,u c Determine the maximum value u. max and minimum value u min Then, the fixed zero-sequence component u0 is calculated according to the following formula (1):

[0034] u0 = -(u max +u min ) / twenty one)

[0035] Furthermore, the unified modulation zero-sequence component u m Then based on the fixed zero-order component u0 and the maximum value u max Minimum value u min And the three-phase reference voltage is calculated, for example, the uniform modulation zero-sequence component u is calculated according to the following formula (2). m :

[0036] u m =k×(1-u max0 (2)

[0037] in,

[0038]

[0039] u max0 =MAX((u a +u0),(u b +u0),(u c +u0)); (4)

[0040] Where k represents the proportion of the small vector within one switching cycle, and T mag T represents different current modulation strategies. mag = [-p, p], where p is a non-zero rational number, u a ,u b ,u c This is the three-phase reference voltage. In this embodiment, the zero-sequence component u is uniformly modulated. m It is the small vector that needs to be added based on the current modulation strategy, where k represents the proportion of the small vector within a switching cycle. Figure 4It can be seen that the small vectors required for the action are distributed within large sectors. In the three-level modulation algorithm, there are six large sectors. Therefore, the value of k needs to be a third harmonic component to complete the construction of the third harmonic zero-sequence component. In formula (3), (u max +u min ) / (1-0.5(u max -u min The third harmonic component is shown in the diagram below. Figure 5 As shown, T mag This determines the amplitude of the third harmonic component, T. mag When T is zero, it is equivalent to not adding a small vector, and the modulation strategy is SVPWM; when T mag Taking a positive or negative value means that different small vectors are applied, in order to Figure 4 Taking sector I as an example, when T mag A positive value indicates the application of the POO small vector, while T mag Taking a negative value signifies the application of the OON small vector; when T mag When the absolute value is large enough, the modulation strategy will exhibit states of clamping to [P] and [N], which can realize discontinuous modulation strategies such as ZC-DPWM or DPWM3.

[0041] In some embodiments, the main modulation strategies of the three-level converter include Space Vector Pulse Width Modulation (SVPWM), Sinusoidal Pulse Width Modulation (SPWM), Zero-Crossing Clamping Discontinuous Pulse Width Modulation (ZC-DPWM), and Discontinuous Pulse Width Modulation (DPWM); then T mag The correspondence between the value of and the above modulation strategy is as follows:

[0042] In T mag When = 0, it indicates that the current modulation strategy is SVPWM;

[0043] In T mag When q = 0, it indicates that the current modulation strategy is SPWM. <q<p;

[0044] In T mag When =p, it indicates that the current modulation strategy is ZC-DPWM;

[0045] In T mag When the value is -p, it indicates that the current modulation strategy is DPWM3.

[0046] It is important to note that the values ​​of p and q can be configured based on the actual application scenario of the three-level converter, the device model, the load conditions, and the application of small vectors between different modulation strategies. For example, the value of p can be 1.5, and the value of q can be 0.5. In different application scenarios of the three-level converter, T can be adjusted according to actual needs. magAdjustments are made to achieve different modulation strategies to reach a balance between bus midpoint voltage fluctuation control and efficiency improvement.

[0047] Under most operating conditions, SVPWM offers better power quality and lower bus midpoint voltage ripple, but its efficiency is lower, while ZC-DPWM and DPWM3 offer larger bus midpoint voltage ripple and higher efficiency. When the system requires better bus midpoint voltage balance and higher power quality, T... mag This can be achieved by taking a value close to 0.5; however, when the system needs to improve its efficiency, then T... mag The value can be close to -1.5 or 1.5. When the system needs to achieve a balance between bus midpoint voltage balance, efficiency and power quality, the value can be taken in the range of [0.5, 1.5] or [-1.5, 0.5] to achieve the above requirements. Specifically, the balance between bus midpoint voltage balance, efficiency and power quality can be achieved by determining the optimal solution under different weights in the above two continuous intervals.

[0048] S30 determines the three-phase modulation wave based on the three-phase reference voltage and the zero-sequence component.

[0049] The three-phase modulation wave is the instantaneous waveform of the three-phase phase voltages expected to be output by the converter. It directly determines the amplitude, frequency, phase, and waveform of the output voltage and serves as the reference signal for the modulation strategy, determining the on / off timing of the switching transistors. In this embodiment, after calculating both the fixed zero-sequence component and the unified modulation zero-sequence component, the two are superimposed to obtain the zero-sequence component under the current modulation strategy. The three-phase modulation wave can be determined based on the currently acquired and calculated three-phase reference voltage and zero-sequence component, specifically including:

[0050] u a,UCB =u a +u0+u m ;

[0051] u b,UCB =u b +u0+u m ;

[0052] u c,UCB =u c +u0+u m ;

[0053] Among them, u a,UCB ,u b,UCB ,u c,UCB Represents a three-phase modulated wave, u0+u m This represents the zero-order component.

[0054] S40 generates the switching transistor drive signals for each bridge arm in the three-level converter based on the three-phase modulation wave.

[0055] After obtaining the three-phase modulated wave, the drive signals for the switching transistors of each bridge arm in the three-level converter can be generated based on the carrier anti-phase cascade modulation. This enables the control of the switching transistors of each phase bridge arm in the three-level converter to turn on and off based on the drive signals, generating U. dc / 2, 0 and -U dc The system employs three output levels ( / 2) to ultimately generate an output voltage containing a fundamental frequency and a high-frequency voltage signal. After the high-frequency signal is filtered out by an LCL filter, a three-phase sinusoidal signal is generated. It should be noted that the specific generation method of the drive signal for the switching transistor can be directly referenced from existing drive signal generation methods; this embodiment will not provide specific details.

[0056] Figure 6 This illustrates the method provided in this embodiment in T mag Three-phase modulated waves and their zero-sequence component diagrams with different values, wherein:

[0057] like Figure 6 As shown in (a), when T mag When the value is 1.5, it can implement ZC-DPWM. ZC-DPWM implements three clamping methods: [P], [O], and [N], which can effectively reduce system losses and improve system efficiency. However, it has a larger bus midpoint voltage fluctuation value, and the THD is larger than that of SVPWM.

[0058] like Figure 6 As shown in (b), when T mag When the value is 0.5, it can implement SPWM.

[0059] like Figure 6 As shown in (c), when T mag When = 0, it can realize SVPWM. SVPWM can improve the bus voltage utilization rate. Among the carrier inversion layered modulation method, SVPWM has the highest bus voltage utilization rate and can reduce bus midpoint voltage fluctuation and improve the quality of output voltage and current.

[0060] like Figure 6 As shown in (d), when T mag When the power factor is -1.5, it can implement DPWM3, which is similar to ZC-DPWM. Although this modulation strategy only uses the [P] and [N] clamping methods, it uses a small vector, so the power factor changes have little impact on the bus midpoint voltage fluctuation. When the power factor is low, this modulation strategy can maintain both low bus midpoint voltage fluctuation and high efficiency.

[0061] This embodiment achieves compatibility with different modulation strategies by using a unified method for calculating the zero-sequence component, based on carrier-inverting cascaded modulation. It omits the calculation process of the zero-sequence vector, eliminates the need to determine the region of the spatial vector, effectively reduces the computational resource consumption during modulation strategy implementation, and suppresses transient oscillations during strategy switching. Simultaneously, by adjusting T... mag Dynamically balancing bus voltage fluctuations, THD, and switching losses provides a solution for the application of modulation strategies for three-level converters under different operating conditions.

[0062] Based on the same inventive concept, the second embodiment of this disclosure provides a unified carrier reverse stacking modulation device based on a three-level converter. This device can be installed in the upper controller of the three-level converter and, by acquiring the voltage and current status of the three-level converter in real time, completes the on / off control of the bridge arm switching tubes of the three-level converter under different modulation strategies, so as to enable it to complete the output of the corresponding three-phase sinusoidal signals.

[0063] Figure 7 The diagram illustrates the structure of the unified carrier inverse stacked modulation device based on a three-level converter in this embodiment. It mainly includes: an acquisition module 10 for acquiring the current three-phase reference voltage of the three-level converter; a zero-sequence component calculation module 20 for calculating the zero-sequence component of the current modulation strategy based on the three-phase reference voltage and the current modulation strategy; a modulation wave calculation module 30 for determining the three-phase modulation wave based on the three-phase reference voltage and the zero-sequence component; and a driving module 40 for generating the switching transistor driving signals for each bridge arm of the three-level converter based on the three-phase modulation wave.

[0064] In some embodiments, the acquisition module 10 is specifically used to: acquire the current loop output and voltage feedforward output of the three-level converter; calculate the sum of the current loop output and voltage feedforward output; perform inverse Park transformation and inverse Clark transformation on the sum, and after standardizing the transformation results, obtain the three-phase reference voltage.

[0065] In some embodiments, the zero-sequence component calculation module 20 is specifically used to: obtain the maximum value u in the three-phase reference voltage. max and minimum value u min According to the maximum value u max and minimum value u min Calculate the fixed zero-sequence component u0, where u0 = -(u max +u min ) / 2; based on the fixed zero-sequence component u0 and the maximum value u max Minimum value u min And the three-phase reference voltage calculation of the unified modulation zero-sequence component u m ; Calculate the uniform modulation zero-sequence component u mThe sum with the fixed zero-sequence component u0 is used as the zero-sequence component of the current modulation strategy.

[0066] In some embodiments, the zero-sequence component calculation module 20 is specifically configured to: calculate the unified modulation zero-sequence component u according to the following formula m :

[0067] u m = k×(1 - u max0 );

[0068]

[0069] u <( max0 = MAX((u <( a + u0), (u <( b + u0), (u <( c + u0)); [[ID=二十八]]

[0070] Where, k represents the ratio of the small vector within one switching period, T mag represents different current modulation strategies, T <00(00093>= [-p, p], p is a non-zero rational number, u a , u b , u c are the three-phase reference voltages

[0071] In some embodiments, the current modulation strategy at least includes: space vector pulse width modulation, sine pulse width modulation, zero-sequence component injection type discontinuous pulse width modulation, discontinuous pulse width modulation; the zero-sequence component calculation module 20 is specifically configured to: when T mag = 0, it indicates that the current modulation strategy is space vector pulse width modulation; when T mag = q, it indicates that the current modulation strategy is sine pulse width modulation, 0 < q < p; when T mag = p, it indicates that the current modulation strategy is zero-sequence component injection type discontinuous pulse width modulation; when T mag = -p, it indicates that the current modulation strategy is discontinuous pulse width modulation [[ID=五十二]]

[0072] In some embodiments, the modulation wave calculation module 30 is specifically configured to: determine the three-phase modulation waves according to the following formula group:

[0073] u a,UCB = u a + u0 + u m ;

[0074] u b,UCB = u b + u0 + u​​​​​​​​​m ;

[0076] Among them, u a,UCB ,u b,UCB ,u c,UCB Represents a three-phase modulated wave, u0+u m This represents the zero-order component.

[0077] This embodiment achieves compatibility with different modulation strategies by using a unified method for calculating the zero-sequence component, based on carrier-inverting cascaded modulation. It omits the calculation process of the zero-sequence vector, eliminates the need to determine the region of the spatial vector, effectively reduces the computational resource consumption during modulation strategy implementation, and suppresses transient oscillations during strategy switching. Simultaneously, by adjusting T... mag Dynamically balancing bus voltage fluctuations, THD, and switching losses provides a solution for the application of modulation strategies for three-level converters under different operating conditions.

[0078] Based on the same inventive concept, a third embodiment of this disclosure provides a storage medium storing a computer program. When executed by a processor, the computer program implements the steps of the unified carrier reverse-stacking modulation method based on a three-level converter described in the first embodiment of this disclosure. This storage medium can be installed in the host controller of the three-level converter, so that the host controller executes the computer program stored in the storage medium when driving the three-level converter.

[0079] Based on the same inventive concept, the fourth embodiment of this disclosure provides an electronic device, including at least a memory and a processor. The memory stores a computer program, and when the processor executes the computer program in the memory, it implements the steps of the unified carrier reverse-stacking modulation method based on a three-level converter described in the first embodiment of this disclosure. This electronic device can be a host controller for a three-level converter. When driving the three-level converter, the electronic device executes the computer program stored in the memory to implement the corresponding modulation strategy.

[0080] Based on the same inventive concept, the fifth embodiment of this disclosure provides a three-level converter, which includes at least the electronic equipment provided in the fourth embodiment of this disclosure. In conjunction with the conventional topology of the converter, the electronic equipment is used as a driving device to control the switching transistors of each bridge arm of the converter, thereby realizing the three-phase sinusoidal signal output of the three-level converter under different modulation strategies.

[0081] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A unified carrier reverse-stacking modulation method based on a three-level converter, characterized in that, include: Obtain the current three-phase reference voltage of the three-level converter; Based on the three-phase reference voltage and the current modulation strategy, calculate the zero-sequence component of the current modulation strategy; The three-phase modulation wave is determined based on the three-phase reference voltage and the zero-sequence component; The switching transistor drive signals for each bridge arm in the three-level converter are generated based on the three-phase modulation wave.

2. The unified carrier reverse stacked modulation method according to claim 1, characterized in that, The process of obtaining the current three-phase reference voltage of the three-level converter includes: Obtain the current loop output and voltage feedforward output of the three-level converter; Calculate the sum of the current loop output and the voltage feedforward output; The sum is subjected to inverse Park and inverse Clark transformations, and the transformation results are then normalized to per-unit values ​​to obtain the three-phase reference voltage.

3. The unified carrier reverse stacked modulation method according to claim 1, characterized in that, The step of calculating the zero-sequence component of the current modulation strategy based on the three-phase reference voltage and the current modulation strategy includes: Obtain the maximum value u among the three-phase reference voltages. max and minimum value u min ; According to the maximum value u max and the minimum value u min Calculate the fixed zero-sequence component u0, where u0 = -(u max +u min ) / 2; Based on the fixed zero-sequence component u0 and the maximum value u max The minimum value u min And the three-phase reference voltage calculation unified modulation zero-sequence component u m ; Calculate the unified modulation zero-sequence component u m The sum of the sum and the fixed zero-sequence component u0 is used as the zero-sequence component of the current modulation strategy.

4. The unified carrier reverse stacked modulation method according to claim 3, characterized in that, The fixed zero-order component u0 and the maximum value u are... max The minimum value u min And the three-phase reference voltage calculation unified modulation zero-sequence component u m ,include: The unified modulation zero-sequence component u is calculated according to the following formula. m : in m =k×(1-u max0 ); u max0 =MAX((u a +u0),(u b +u0),(u c +u0)); Where k represents the proportion of the small vector within one switching cycle, and T mag T represents different current modulation strategies. mag = [-p, p], where p is a non-zero rational number, u a ,u b ,u c This is the three-phase reference voltage.

5. The unified carrier inverse stacked modulation method according to claim 4, characterized in that, The current modulation strategy includes at least: space vector pulse width modulation, sinusoidal pulse width modulation, zero-crossing clamping discontinuous pulse width modulation, and discontinuous pulse width modulation. In T mag When = 0, it indicates that the current modulation strategy is space vector pulse width modulation; In T mag When = q, it indicates that the current modulation strategy is sinusoidal pulse width modulation; 0 <q<p; In T mag When =p, it indicates that the current modulation strategy is zero-sequence component injection type discontinuous pulse width modulation; In T mag When the value is -p, it indicates that the current modulation strategy is discontinuous pulse width modulation.

6. The unified carrier inverse stacked modulation method according to claim 4, characterized in that, The step of determining the three-phase modulation wave based on the three-phase reference voltage and the zero-sequence component includes: The three-phase modulation wave is determined according to the following set of formulas: u a,UCB =u a +u0+u m ; u b,UCB =u b +u0+u m ; u c,UCB =u c +u0+u m ; Among them, u a,UCB ,u b,UCB ,u c,UCB This represents the three-phase modulated wave, u0+u m This represents the zero-order component.

7. A unified carrier inverse cascade modulation device based on a three-level converter, characterized in that, include: The acquisition module is used to acquire the current three-phase reference voltage of the three-level converter; The zero-sequence component calculation module is used to calculate the zero-sequence component of the current modulation strategy based on the three-phase reference voltage and the current modulation strategy. The modulation wave calculation module is used to determine the three-phase modulation wave based on the three-phase reference voltage and the zero-sequence component; The drive module is used to generate drive signals for the switching transistors of each bridge arm in the three-level converter based on the three-phase modulation wave.

8. A storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the unified carrier reverse stacked modulation method based on a three-level converter as described in any one of claims 1 to 6.

9. An electronic device, comprising at least a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program on the memory, it implements the steps of the unified carrier reverse stacked modulation method based on a three-level converter as described in any one of claims 1 to 6.

10. A three-level converter, characterized in that, It includes at least the electronic device as described in claim 9.

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