Power chip packaging detection method and device

Abstract

The invention provides a power chip packaging detection method and device, and the method comprises the steps: obtaining a structure image, an infrared thermal imaging frame sequence and a working electrical parameter data set of a target power chip after packaging, and carrying out the layering and regional peak analysis, so as to construct a morphology feature parameter set and a thermal anomaly feature set; inputting the morphology feature parameter set, the thermal anomaly feature set and the working electrical parameter data set into a preset defect identification model to obtain a chip packaging anomaly identification map; and performing hierarchical division and node aggregation on the chip packaging abnormity identification map to obtain a packaging defect type result. By constructing a multi-modal packaging detection system taking a structural image, an infrared thermal imaging frame sequence and a working electrical parameter data set as input, accurate identification of the power chip is realized, the accuracy of packaging defect detection is effectively improved, and the problems of low identification precision and information isolation of an existing detection method are improved.

Description

Technical Field

[0001] This application relates to the field of chips, and in particular to a packaging and testing method and apparatus for power chips. Background Technology

[0002] With the widespread application of power devices in new energy, electric vehicles, high-speed communications, and industrial control, the packaging quality of power chips has become a crucial factor affecting the reliability and stability of the entire system. Power chips typically have high voltage and high current carrying capacity, placing higher demands on their heat dissipation performance and structural integrity. Minor defects during the packaging process, such as broken leads, poor solder joints, bubbles in the encapsulant, or interface delamination, can all lead to thermal runaway, breakdown, or premature failure of the chip.

[0003] Existing power chip packaging inspection methods mainly include X-ray imaging, ultrasonic scanning, infrared thermal imaging, and electrical parameter sampling. X-ray imaging can identify solder joint voids and abnormalities in the internal structure of the package; ultrasonic scanning can be used to detect interlayer delamination and bubble distribution; infrared thermal imaging is used to observe chip heating and hot spot distribution; and electrical parameter sampling assesses the quality of the chip package by measuring indicators such as on-resistance and leakage current.

[0004] Although the above detection methods can achieve macroscopic detection of defects in power chip packaging, when faced with complex defects involving multiple factors, X-ray imaging cannot accurately determine abnormal heat conduction paths, infrared thermal imaging is difficult to analyze in conjunction with structural level data, and outlier changes in electrical parameters are difficult to establish a direct mapping relationship with specific packaging structure defects. Therefore, existing methods lack a unified multi-dimensional feature fusion mechanism, which easily leads to information silos and low chip identification accuracy. Summary of the Invention

[0005] The technical problem to be solved by the present invention is that the identification accuracy is low in the prior art, so as to provide a packaging inspection method and device for power chips to improve the accuracy of packaging defect identification.

[0006] In view of this, a first aspect of the present invention provides a method for packaging inspection of a power chip, comprising: acquiring a structural image of the target power chip after packaging, an infrared thermal imaging frame sequence, and a working electrical parameter dataset; performing layered recognition on the structural image, extracting morphological feature parameters of the chip body layer, lead interconnect layer, and encapsulating colloid layer obtained from the layered recognition, to construct a set of morphological feature parameters; performing transient difference and regional peak analysis on the infrared thermal imaging frame sequence to construct thermal field offset and temperature rise response anomaly regions, and constructing a thermal anomaly feature set based on the thermal field offset and the temperature rise response; inputting the set of morphological feature parameters, the set of thermal anomaly features, and the working electrical parameter dataset into a preset defect identification model to obtain a chip packaging anomaly identification map; and performing hierarchical division and node aggregation on the chip packaging anomaly identification map to obtain packaging defect type results.

[0007] Preferably, the acquisition of the structural image, infrared thermal imaging frame sequence, and operating electrical parameter dataset of the target power chip after packaging specifically includes: capturing multi-angle images of the target power chip; performing grayscale equalization and noise reduction preprocessing on the multi-angle images to obtain a structural image; acquiring infrared radiation field strength data and a time-series thermal diffusion distribution map of the target power chip under rated voltage conditions; extracting the maximum temperature curve of the region based on the infrared radiation field strength data to construct a transient temperature change trajectory; identifying the heat diffusion path based on the time-series thermal diffusion distribution map to obtain a thermal diffusion region response map; performing time and spatial registration between the transient temperature change trajectory and the thermal diffusion region response map to obtain an infrared thermal imaging frame sequence; and acquiring an operating electrical parameter dataset of the target power chip under multiple operating states, wherein the operating electrical parameter dataset includes on-resistance, breakdown voltage, leakage current, and thermal resistance data.

[0008] Preferably, the step of performing layered recognition on the structural image and extracting morphological feature parameters of the chip body layer, interconnect layer, and encapsulating colloid layer obtained from the layered recognition to construct a set of morphological feature parameters specifically includes: performing image segmentation and region reconstruction on the structural image to obtain region layer boundaries; extracting gray-level gradient abrupt change regions, geometric arrangement information, and edge connectivity based on the region layer boundaries; identifying pad contours and body mean intensity regions based on the gray-level gradient abrupt change regions to determine the chip body layer; extracting uniformity indicators, edge continuity, and pad symmetry in the chip body layer to construct a body layer morphological sub-feature set; and based on the... The geometric arrangement information is used to identify the lead trace trajectory and metal reflective strip, determine the lead interconnect layer, and extract the metal trajectory connectivity, pin distribution density, and pin twist degree in the lead interconnect layer to construct an interconnect layer morphology sub-feature set; based on the edge connectivity, the package edge contour and texture uniformity distribution are identified to determine the package colloid layer, and the bubble texture density, colloid distribution gradient, and edge shrinkage rate are extracted in the package colloid layer to construct a colloid layer morphology sub-feature set; the body layer morphology sub-feature set, the interconnect layer morphology sub-feature set, and the colloid layer morphology sub-feature set are fused to construct a multi-level morphology feature parameter set.

[0009] Preferably, the step of performing transient difference and regional peak analysis on the infrared thermal imaging frame sequence to construct thermal field offset and temperature rise response anomaly regions, and constructing a thermal anomaly feature set based on the thermal field offset and the temperature rise response specifically includes: performing multi-frame averaging and transient difference analysis on the infrared thermal imaging frame sequence to extract the time-temperature evolution curves of each layer region of the chip; mapping the time-temperature evolution curves to the chip body layer, the lead interconnect layer, and the encapsulation colloid layer using the region layer boundaries to obtain a layered thermal response map; performing gradient analysis and anomaly point marking on the layered thermal response map to identify regions of abrupt thermal diffusion changes and hysteresis rise. In the temperature region, with the geometric center of the target power chip as a reference, the thermal diffusion offset vector of the thermal diffusion abrupt change region and the maximum thermal center deviation of the hysteresis heating region are calculated; a thermal field offset is constructed based on the thermal diffusion offset vector and the maximum thermal center deviation; time window segmentation and regional peak analysis are performed on the infrared thermal imaging frame sequence to obtain the temperature rise curve change rate and the duration of abnormal frames; the temperature rise response abnormal region is identified by combining the temperature rise curve change rate and the duration of abnormal frames; cross-analysis is performed on the thermal field offset and the temperature rise response abnormal region, and a thermal anomaly feature set is generated based on the analysis results.

[0010] Preferably, the step of inputting the set of morphological feature parameters, the set of thermal anomaly features, and the set of working electrical parameters into a preset defect identification model to obtain a chip packaging anomaly identification map specifically includes: vectorizing and encoding the set of morphological feature parameters to generate a subset of morphological feature map structures; constructing a subset of thermal feature map structures based on the set of thermal anomaly features; performing multidimensional normalization processing on the set of working electrical parameters; and combining the normalized set of working electrical parameters with anomaly weight distribution information to construct a subset of electrical parameter map structures; wherein, the anomaly weight distribution information refers to information based on historical data... The chip test samples are used to construct a set of electrical parameter deviation confidence scores. The morphological feature map structure subset, the thermal feature map structure subset, and the electrical parameter map structure subset are input into a preset defect identification model. In the defect identification model, a structural anomaly feature sub-map is established based on the morphological feature map structure subset, a thermal response anomaly sub-map is established based on the thermal feature map structure subset, and an electrical parameter deviation sub-map is established based on the electrical parameter map structure subset. The structural anomaly feature sub-map, thermal response anomaly sub-map, and electrical parameter deviation sub-map are subjected to graph embedding cross-fusion to output a chip packaging anomaly identification map.

[0011] Preferably, the step of performing hierarchical division and node aggregation on the chip packaging anomaly identification map to obtain packaging defect type results specifically includes: performing hierarchical division and node aggregation on the chip packaging anomaly identification map to construct a multi-scale graph structure index set; performing pattern matching on the graph structure index set to obtain a set of package anomaly aggregated fragments; extracting packaging structure defect regions, thermal diffusion anomaly paths, and high-risk electrical parameters based on the set of package anomaly aggregated fragments; and generating packaging defect type results based on the packaging structure defect regions, the thermal diffusion anomaly paths, and the high-risk electrical parameters.

[0012] Preferably, after performing hierarchical division and node aggregation on the chip packaging anomaly identification map to obtain packaging defect type results, the method further includes: extracting the corresponding defect cause node set based on the packaging defect type results; performing causal attribute clustering on the defect cause node set to obtain a causal feature set; and generating a packaging process causal path diagram based on the causal feature set. Using the packaging process causal path diagram, key process deviation factors leading to defect formation are identified; the key process deviation factors are mapped to process logs and process condition tables to obtain matching process events; the timing information, frequency of occurrence, and equipment number of the process events are extracted based on the matching process events; cross-analysis is performed on the timing of the process events, the frequency of occurrence, and the equipment number to obtain a defect cause path set; and key nodes in the defect cause path set are used as process traceability anchor points.

[0013] A second aspect of this invention provides a power chip packaging inspection device, comprising: a data acquisition module for acquiring a structural image, an infrared thermal imaging frame sequence, and a working electrical parameter dataset of a target power chip after packaging; an image processing module for performing layer-by-layer recognition on the structural image and extracting morphological feature parameters of the chip body layer, lead interconnect layer, and encapsulating colloid layer obtained from the layer-by-layer recognition to construct a morphological feature parameter set; a data analysis module for performing transient difference and regional peak analysis on the infrared thermal imaging frame sequence to construct thermal field offset and temperature rise response anomaly regions, and constructing a thermal anomaly feature set based on the thermal field offset and the temperature rise response; a data recognition module for inputting the morphological feature parameter set, the thermal anomaly feature set, and the working electrical parameter dataset into a preset defect recognition model to obtain a chip packaging anomaly recognition map; and a node aggregation module for performing hierarchical division and node aggregation on the chip packaging anomaly recognition map to obtain packaging defect type results.

[0014] The technical solution of this invention has the following advantages: high recognition accuracy. By constructing a multimodal packaging detection system with structural images, infrared thermal imaging frame sequences, and working electrical parameter datasets as inputs, it achieves comprehensive extraction and correlation modeling of chip structural hierarchical information, thermal behavior characteristics, and electrical performance status; through image layer processing and structural feature parameter extraction, it accurately identifies microstructural anomalies in the chip body layer, lead interconnect layer, and packaging colloid layer; furthermore, through transient difference and peak region analysis of infrared thermal imaging frame sequences, it establishes an abnormal feature model of thermal diffusion behavior, and constructs a thermal anomaly feature set by combining the temperature rise curve change rate and thermal center offset; by uniformly encoding the above morphology, thermal anomalies, and electrical parameter information into the defect recognition model, it achieves semantic mapping and embedding fusion between different feature dimensions, constructing a chip packaging anomaly recognition map with structural, thermal, and electrical parameter linkage attributes; through the hierarchical division and node aggregation of the graph structure, it identifies defect types, completing a closed-loop detection process from defect perception, correlation recognition to pattern determination, effectively improving the accuracy of packaging defect detection, and significantly improving the problems of low recognition accuracy and information isolation in existing detection methods. Attached Figure Description

[0015] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0016] Figure 1 A schematic flowchart of a power chip packaging and testing method provided in an embodiment of the present invention; Figure 2 This is a schematic block diagram of a power chip packaging and testing device provided in an embodiment of the present invention. Detailed Implementation

[0017] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] In the description of this invention, it should be noted that the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0019] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0020] like Figure 1 As shown, this embodiment provides a packaging inspection method for power chips. This packaging inspection method achieves unified fusion identification of structural features, thermal diffusion behavior, and electrical parameters, thereby improving the detection accuracy of power chip packaging defects. The packaging inspection method includes the following steps: Step S10: Obtain the structural image, infrared thermal imaging frame sequence, and working electrical parameter dataset of the target power chip after packaging.

[0021] In practical applications, multi-angle images of the target power chip are acquired using industrial-grade imaging equipment (such as an area array camera with a pixel resolution higher than 5 million). During the acquisition process, a servo rotation platform is used to adjust the shooting angle to ensure that the image covers the entire surface structure of the chip. Subsequently, grayscale equalization and spatial domain filtering are performed on the multi-angle images to enhance image contrast and remove high-frequency noise, ultimately generating a clear structural image. Simultaneously, under constant rated voltage input conditions (such as 650V / 10A), a miniature infrared thermal imager is used to record the infrared radiation field strength data and dynamic images of thermal diffusion after the chip is powered on. The thermal images at different time points are synchronously processed and stored as a frame sequence to obtain an infrared thermal imaging frame sequence with temporal continuity. In addition, key electrical parameters such as on-resistance, breakdown voltage, leakage current, and thermal resistance of the chip under different operating states (such as low load, medium load, and high load) are acquired through on-chip test interfaces or electrical parameter measuring instruments (such as Keysight B150) to form a structured working electrical parameter dataset.

[0022] Furthermore, the grayscale equalization process employs a local histogram equalization algorithm (CLAHE) to enhance the contrast of the chip contour region; the denoising process uses a joint strategy of median filtering and bilateral filtering to retain edge information while removing texture interference; the frame rate of the infrared thermal imaging frame sequence acquisition is set to ≥60fps to ensure the recording of transient thermal changes; inter-frame alignment is calibrated using an image registration algorithm (such as a registration method based on mutual information); the measurement accuracy of the on-resistance is controlled within ±0.5mΩ; the thermal resistance test is obtained using a steady-state method combined with a variable power thermal excitation method; all electrical parameter data are standardized and stored in the working electrical parameter dataset for subsequent fusion analysis.

[0023] Step S20: Perform layer recognition on the structural image, extract the morphological feature parameters of the chip body layer, lead interconnect layer and encapsulation colloid layer, and construct a set of morphological feature parameters.

[0024] In practical applications, the preprocessed structural image is input into an image segmentation network (such as U-Net or the edge detection-based Canny-Sobel hybrid algorithm). First, the boundary information of the structural layers is extracted to complete the regional division of the chip body layer, the lead interconnect layer, and the encapsulation colloid layer. In the chip body layer, morphological features such as pad contours, mean intensity, and edge continuity are extracted through region connectivity analysis and pad symmetry recognition algorithms. In the lead interconnect layer, the metal trajectory connectivity graph is identified, and structural indicators such as the curvature of the pin trace trajectory, the density of the metal reflective area, and the pin twist angle are extracted. In the encapsulation colloid layer, the colloid density distribution, edge shrinkage rate, and internal bubble texture features are extracted through texture analysis to form a multidimensional structural feature subset.

[0025] Furthermore, the image segmentation process employs a U-Net-based convolutional neural network model with a training dataset containing over 100 labeled sample images, achieving an accuracy exceeding 95%. Pad symmetry recognition utilizes a centroidal symmetry axis detection and contour mapping algorithm. Pin twist is measured by fitting line segments and then measuring the angle of deviation from the initial path. Bubble density extraction in the encapsulation colloid layer employs wavelet texture feature analysis (such as the Haralick texture matrix) combined with local variance thresholding to divide bubble regions, ultimately forming a unified set of morphological feature parameters.

[0026] Step S30, Step 3: Perform transient difference and regional peak analysis on the infrared thermal imaging frame sequence to construct the thermal field offset and temperature rise response anomaly region, and construct a thermal anomaly feature set based on the thermal field offset and temperature rise response.

[0027] In practical applications, the inter-frame temperature difference analysis of the infrared thermal imaging frame sequence is first performed to extract the thermal change trend between frames. The temperature rise rate and hysteresis response of different regions are calculated by using a sliding time window to generate temperature evolution curves in the time dimension. Then, high-temperature anomaly regions are identified by spatial peak localization algorithms (such as local extremum detection and K-means region clustering), and vector modeling of the heat diffusion trajectory of each region is performed. The offset vector is calculated by combining the chip geometric center and the heat diffusion center to obtain the thermal field offset. Finally, the peak thermal hysteresis region is identified and the temperature rise response anomaly region is constructed by combining the duration, area and response rate and other indicators, and fused into a thermal anomaly feature set.

[0028] Furthermore, the temperature evolution curve uses a time sliding window width of 1.5s, a frame sampling interval of 16.7ms (corresponding to 60fps), and a region division granularity controlled at the 5×5 pixel block level. In peak identification, the temperature threshold of local extreme points is set to the average temperature + 2.5 times the standard deviation. When the duration of an abnormal region is greater than 20ms and the maximum temperature rise in the region exceeds 12℃, it is judged as a hysteresis anomaly. The offset vector is represented by a vector from the geometric center to the thermal center. When the length is greater than 15% of the total diagonal length, it is marked as an abnormal offset. Finally, a thermal anomaly feature set is formed for spectral analysis.

[0029] Step S40: Input the set of morphological feature parameters, the set of thermal anomaly features, and the set of working electrical parameters into the preset defect identification model to obtain the chip packaging anomaly identification map.

[0030] In practical applications, the extracted morphological feature parameters of the chip body layer, lead interconnect layer, and encapsulation colloid layer are vectorized and encoded to construct the node and edge relationships in the structure graph. Simultaneously, the spatial location and thermal features of the thermal field offset, temperature rise response anomaly area, and other parameters are mapped to region nodes and anomaly path edges in the thermal response graph. The various indicators in the working electrical parameter dataset are Z-score normalized and combined with the deviation weight scoring mechanism built based on historical defect data to form electrical parameter graph nodes with risk weight attributes. Finally, the three subgraphs are fused and input into the defect identification model for graph embedding analysis and correlation reasoning to output a chip packaging anomaly identification map.

[0031] Furthermore, the defect recognition model adopts a graph neural network (GAT) architecture, performs graph embedding at the subgraph level, aggregates multi-dimensional feature information through an attention mechanism, and finally outputs node anomaly scores through a graph classifier. The structural graph has 45-60 nodes, the heat map has 20-30 nodes, and the electrical parameter graph has 10 index nodes. The overall graph structure contains more than 10 directed edges. The final generated chip packaging anomaly recognition map simultaneously includes structural anomaly nodes, thermal response anomaly paths, and electrical parameter deviation correlation edges, which are used for deep defect pattern recognition.

[0032] Step S50: Perform hierarchical division and node aggregation on the chip packaging anomaly identification map to obtain the packaging defect type results.

[0033] In practical applications, based on the semantic labels and attribute weights of nodes in the graph structure, a hierarchical partitioning algorithm (such as the Louvain method) is used to divide the recognition graph into structural domains, resulting in multiple defect sub-graph units. Subsequently, nodes with similar structural anomalies, thermal anomalies, and electrical parameter deviations are aggregated to form multi-scale feature blocks. By matching and comparing the blocks with historically known encapsulation defect templates, the encapsulation defect types are identified, including encapsulation bubbles, high thermal resistance channels, and solder pad cold solder joints, and the defect type identifier and its corresponding graph node information are output.

[0034] Furthermore, the node aggregation strategy sets the aggregation threshold to 0.85 based on feature cosine similarity, matches 50 typical defect patterns, and achieves an accuracy rate of over 94%. The final output includes the node index of the defect name, defect level (low, medium, high), and affected area, which is used for subsequent process tracing and defect classification processing.

[0035] In this embodiment, the structural image, infrared thermal imaging frame sequence, and working electrical parameter dataset of the target power chip after packaging are acquired as the input basis for multi-source detection information. Then, the structural image is processed in layers to identify the chip body layer, lead interconnect layer, and encapsulation colloid layer in sequence, and the corresponding morphological feature parameters of each layer are extracted to construct a morphological feature parameter set. Next, the infrared thermal imaging frame sequence is processed by transient differential processing and regional peak analysis to extract spatial offset and temporal anomalies in thermal diffusion changes, thereby constructing thermal field offset and temperature rise response anomaly regions, and generating a thermal anomaly feature set. Subsequently, the morphological feature parameter set, thermal anomaly feature set, and working electrical parameter dataset are input into a preset defect identification model, and a chip packaging anomaly identification map is output based on graph structure modeling and feature association. Finally, the chip packaging anomaly identification map is hierarchically divided and node aggregated to form a clear multi-scale defect characterization, thereby obtaining the packaging defect type result.

[0036] By constructing a multi-source feature input mechanism that includes structural images, infrared thermal imaging frame sequences, and working electrical parameter datasets, the simultaneous acquisition and fusion processing of structural information, thermal diffusion behavior, and electrical performance indicators in packaging inspection is achieved, improving the comprehensiveness of defect identification. Layered analysis of structural images and extraction of morphological feature parameters from the chip body layer, lead interconnect layer, and encapsulation colloid layer effectively enhances the sensitivity to microstructural defects. Transient difference and regional peak analysis in the infrared thermal imaging frame sequences are used to construct thermal field offset and temperature rise response anomaly zones, strengthening the modeling capability for dynamic thermal mismatch problems. A defect identification model is introduced, achieving a unified graph structure representation of morphology, thermal anomalies, and electrical parameter data. Through hierarchical partitioning and node aggregation of the graph structure, the identification accuracy for complex defect patterns is improved. This effectively overcomes the problems of low identification accuracy, fragmented feature analysis, and poor result correlation in existing technologies, improving the low identification accuracy and information isolation issues of existing detection methods.

[0037] As a preferred embodiment, step S10 can preferably be: Multi-angle images of the target power chip are captured, and grayscale equalization and noise reduction preprocessing are performed on the multi-angle images to obtain structural images.

[0038] In this step, multi-angle image acquisition of the target power chip is performed using an industrial-grade camera. A programmable mechanical rotation platform is used to sequentially adjust the shooting angle (e.g., from 0° to 180° around the vertical axis, taking a picture every 15°) to ensure that the entire chip structure is fully covered. Each image acquisition is completed under constant lighting conditions to avoid grayscale deviations introduced by changes in light intensity. After shooting, grayscale equalization processing is performed on each frame of the acquired image to enhance detail contrast, and spatial filtering is used for noise reduction to eliminate artifacts caused by reflections or optical distortions at the device edges. The processed images are reconstructed through an image fusion module to improve the overall image clarity and structural recognizability, ultimately forming a structural image with micron-level precision.

[0039] Specifically, gray-level equalization employs an adaptive histogram equalization algorithm (CLAHE), which improves the uniformity of gray-level distribution in each local region, enhancing the visibility of weakly structured edge areas. Denoising processing utilizes a joint median filtering and bilateral filtering algorithm: median filtering suppresses high-frequency noise, while bilateral filtering smooths unstructured areas while maintaining edge sharpness. During image reconstruction, a pyramid image fusion strategy is used to fuse multi-angle image information into a single main view. An edge-preserving factor is introduced during the fusion process to ensure that detailed structures are not blurred. The final output structural image has a pixel accuracy controlled within 1 μm / pixel, meeting the needs of subsequent structural image layering and morphological feature extraction.

[0040] The infrared radiation field strength data and time-series thermal diffusion distribution map of the target power chip under rated voltage conditions are obtained. The maximum temperature curve of the region is extracted based on the infrared radiation field strength data to construct the transient temperature change trajectory.

[0041] In this step, the target power chip is powered on a temperature-controlled experimental platform, applying its rated voltage and current conditions (e.g., 650V, 10A). Simultaneously, a miniature high-sensitivity infrared thermal imager (response band 8–14μm, thermal sensitivity ≤40mK) is used to perform real-time infrared monitoring of the chip surface. Infrared image acquisition is performed at a fixed frame rate (e.g., 60fps) to ensure the temporal continuity of the dynamic thermal diffusion process. From the acquired infrared radiation field strength data, peak values ​​are extracted based on the temperature field of each frame, constructing a temperature change curve with time as the horizontal axis and the maximum area temperature as the vertical axis. This describes the thermal response process of a local area of ​​the chip and forms a preliminary transient temperature change trajectory.

[0042] Specifically, the infrared acquisition process was controlled at a constant ambient temperature (25±1℃), and testing began after calibration with a blackbody reference source. In each frame of the thermal image, a region of interest (ROI) was defined, and a local maximum (LMR) localization algorithm was applied to extract the peak thermal intensity. To filter out local noise, a moving average filter (window size 5 frames) was used to smooth the maximum value curve. A temperature rise rate exceeding 3℃ / s and lasting for more than 0.5s was defined as the thermal activation stage. Temperature peaks, troughs, and waveform slopes were recorded to ultimately form a complete sequence of transient temperature change trajectory data.

[0043] The heat diffusion path is identified based on the time-series heat diffusion distribution map, and the response map of the heat diffusion region is obtained. The transient temperature change trajectory is time-space registered with the response map of the heat diffusion region to obtain an infrared thermal imaging frame sequence.

[0044] In this step, inter-frame differencing is performed on the thermal imaging frame sequence to identify the positional changes of the heat diffusion front at different time points, thereby drawing a time-series heat diffusion distribution map. Using the temperature gradient information in each frame, a heat diffusion profile is constructed using region growing and boundary tracing methods to generate a heat diffusion path map. Subsequently, the time labels in the transient temperature change trajectory are aligned with the frame times in the heat diffusion region response map, and the spatial centers are aligned through geometric coordinate mapping to achieve time-space registration, ultimately forming a structurally sound and inter-frame synchronized infrared thermal imaging frame sequence.

[0045] Specifically, the time registration process uses a timestamp index matching method to ensure a one-to-one correspondence between thermal data and structural data at each moment. Spatial registration employs an affine transformation matching algorithm based on the maximum overlap area, using feature point extraction and rigid rotation registration to achieve coordinate alignment within an error range of ≤2 pixels. In the constructed thermal diffusion region response map, the thermal diffusion radius is calculated every 0.2s time step, and regions with radius changes greater than 5% are identified as thermal diffusion abrupt change zones to assist in verifying registration accuracy. After registration, each frame in the infrared thermal imaging frame sequence contains complete time, temperature, region label, and coordinate mapping information, serving as the basic data structure for subsequent thermal anomaly identification.

[0046] Acquire the operating electrical parameter dataset of the target power chip under multiple operating states, including on-resistance, breakdown voltage, leakage current, and thermal resistance data.

[0047] In this step, a multi-functional semiconductor parameter analyzer is used to measure the electrical parameters of the target power chip under multiple operating conditions. Low load (10% of rated value), medium load (50% of rated value), and high load (100% of rated value) operating current conditions are applied respectively, and key indicators such as on-resistance, breakdown voltage, leakage current, and thermal resistance are collected. Each parameter test is conducted in an environment with controlled temperature and EMI shielding to ensure test accuracy. The collected raw electrical parameter data undergoes unified dimension conversion and normalization to construct a structured operating electrical parameter dataset for subsequent spectrum modeling and feature fusion.

[0048] Specifically, the continuity resistance test uses a constant current source method. With the current set to 1A, the voltage value is collected and the resistance is calculated. The measurement is repeated five times, and the average value is taken, with a measurement error not exceeding ±1%. The breakdown voltage test applies voltage in stages at a boost rate of 5V / ms, and the first sudden current change is recorded as the breakdown point. The leakage current test records the steady-state current value under a bias voltage of 90% of the rated voltage, with accuracy controlled within the picoampere range. The thermal resistance measurement uses a steady-state method, based on the temperature rise to power dissipation ratio formula: ; in For the junction temperature, Shell temperature, The measured thermal resistance value is used to evaluate thermal management capability, representing power. All electrical parameter data are organized and stored in a ternary structure of "state-parameter name-value", with a unified normalization interval of 0, 10, 10, 1, ultimately forming a standardized working electrical parameter dataset that can be directly used in graph structure encoding and model inference.

[0049] As a preferred embodiment, step S20 can preferably be: Image segmentation and region reconstruction are performed on the structural image to obtain the region layer boundaries. Based on the region layer boundaries, gray-level gradient abrupt change areas, geometric arrangement information and edge connectivity are extracted.

[0050] In this step, image segmentation is performed on the structural image to separate multiple structural regions of the power chip according to physical layers. Image segmentation employs a method based on pixel-level grayscale difference and edge information fusion to preserve chip structural details. Next, a region reconstruction algorithm, combined with a geometric template of the known packaging structure, is used to fit contours and restore boundaries of the segmented regions, thus forming clear regional layer boundaries. Subsequently, based on these regional layer boundaries, grayscale gradient extraction is performed on each layer to identify regions with significant grayscale abrupt changes. Then, the geometric arrangement information of the structures within these regions is extracted, including structural central symmetry, arrangement direction, and unit spacing. Simultaneously, the connectivity of the edge contours of each region is analyzed as a basis for subsequent layer identification and feature extraction.

[0051] Specifically, image segmentation employs a hybrid approach combining the Canny edge detection algorithm and a region growing algorithm. The former detects edge locations, while the latter ensures boundary continuity and region integrity. During reconstruction, edge lines are fitted using an Active Contour Model and aligned with standard chip-level templates (such as GDSII file fragments provided by the packaging manufacturer). Gray-level abrupt change regions are extracted using a first-order gradient threshold (e.g., gradient values ​​greater than 20% of the global maximum gradient). Geometric arrangement information is primarily assessed using the minimum enclosing matrix rotation angle and uniform spacing; edge connectivity is identified and encoded using Connected Component Labeling (CCP) technology.

[0052] Based on the gray-scale gradient abrupt change region, the pad outline and the body mean intensity region are identified to determine the chip body layer. Uniformity index, edge continuity and pad symmetry are extracted from the chip body layer to construct the body layer morphology sub-feature set.

[0053] In this step, the chip body layer region is identified based on the contrast between the pad outlines in the grayscale abrupt change area and the body brightness region. The chip body layer appears in the image as a rectangular region with clear boundaries and stable brightness distribution, containing multiple uniformly distributed pads. After identifying this region, the uniformity of its image intensity distribution (i.e., image brightness variance), edge continuity (degree of integrity of the outline lines), and the symmetry of the pads in the horizontal and vertical directions are extracted to reflect the manufacturing consistency and structural integrity of the body layer.

[0054] Specifically, the uniformity index is calculated using the standard deviation of gray values ​​per unit area; edge continuity is evaluated based on the percentage of edge pixel connectivity (e.g., the proportion of continuous boundary length to theoretical boundary length); pad symmetry is calculated by comparing the center mirror image, with a symmetry threshold set such as 95% or higher as ideal symmetry. The ontology layer morphology sub-feature set output by this process is organized in the form of structural labels + index values, including fields such as "uniformity index", "edge continuity coefficient", and "symmetry deviation", which are used as input for subsequent models.

[0055] Based on the geometric arrangement information, the lead trace trajectory and metal reflective strip are identified to determine the lead interconnect layer. The metal trajectory connectivity, pin distribution density and pin twist degree are extracted in the lead interconnect layer to construct the interconnect layer morphology sub-feature set.

[0056] In this step, the geometric arrangement information of the structural region is used to identify the metal interconnect traces and their reflective band features in the image, thereby locating the lead interconnect layer. The lead interconnect layer appears in the image as bright, slender line segments extending from pads; its shape should maintain high connectivity, moderate density, and directional regularity. Further analysis of the metal trace connectivity index, pin distribution density per unit area, and pin bending degree (torsion) is performed on this layer structure to evaluate its interconnect quality and processing deviations.

[0057] Specifically, the connectivity of the metal trajectory is evaluated using skeleton extraction combined with connected component algorithms (such as Zhang-Suen thinning and FloodFill connectivity checks) to assess its integrity; pin distribution density is assessed using pin counting per unit area; and the distortion is calculated based on the trajectory curvature change, i.e., the frequency of curvature change per unit length. The extracted interconnect layer morphology sub-feature set includes structural features such as "connectivity integrity rate," "unit pin density value," and "maximum curvature fluctuation value," which are adapted for subsequent defect pattern recognition.

[0058] Based on edge connectivity, the contour and texture uniformity distribution of the encapsulation edge are identified, the encapsulation colloid layer is determined, and the bubble texture density, colloid distribution gradient and edge shrinkage rate are extracted from the encapsulation colloid layer to construct a morphological sub-feature set of the colloid layer.

[0059] In this step, based on the connectivity analysis results of the image edge region, the encapsulation edge lines are identified, and local texture statistics are extracted within the region to locate the encapsulation colloid layer region. Image features of the encapsulation colloid layer include contour smoothness, texture distribution uniformity, and microbubble texture density. It is necessary to combine boundary closure and internal grayscale texture distribution to identify edge contraction and material distribution anomalies. Finally, indicators reflecting encapsulation integrity are extracted, including bubble texture density, distribution gradient (referring to the rate of change of texture between inner and outer regions), and edge contraction rate.

[0060] Specifically, the bubble texture density is quantified using the number of high-frequency noise points in the local texture energy map (such as the energy channels of the gray-level co-occurrence matrix); the colloid distribution gradient is represented by the slope of a linear fit of the region's average gray value from the center to the edge; and the edge shrinkage rate is calculated by the ratio of the actual area of ​​the encapsulation boundary to the area of ​​the standard template. The final output colloid layer morphology sub-feature set includes "high-frequency texture point density value", "colloid brightness gradient slope", and "encapsulation edge shrinkage ratio", etc.

[0061] The morphology sub-feature sets of the bulk layer, interconnect layer, and colloidal layer are fused to construct a multi-level set of morphology feature parameters.

[0062] In this step, the extracted morphological sub-feature sets of the body layer, the lead interconnect layer, and the encapsulation colloid layer are merged according to a unified hierarchical labeling system to construct a set of morphological feature parameters under a multi-level structure. The fusion process preserves the independence of each layer and is organized according to a three-level mapping structure of "structural level → feature category → index value," which enables the subsequent model to have distinguishability and categorizability when processing features from different layers.

[0063] Specifically, the fusion method employs a structural feature vector concatenation strategy, supplemented with hierarchical encoding information, such as "Layer1:Symmetry_Index=0.97" and "Layer3:Edge_Shrinkage=0.12". The fused set structure is a standard JSON or matrix structure, which can be directly passed into the defect recognition model for node construction and feature assignment. The entire set possesses good scalability and semantic clarity, laying a structural foundation for multimodal feature fusion and classification recognition.

[0064] As a preferred embodiment, step S30 can preferably be: Multi-frame averaging and transient differential analysis were performed on the infrared thermal imaging frame sequence to extract the time thermal evolution curves of each layer region of the chip. The time thermal evolution curves were then mapped to the chip body layer, lead interconnect layer and encapsulation colloid layer using the region layer boundaries to obtain the layered thermal response map.

[0065] In this step, the infrared thermal imaging frame sequence is preprocessed, including multi-frame averaging and inter-frame transient difference analysis. Multi-frame averaging is used to improve the image signal-to-noise ratio and reduce the impact of occasional thermal noise; transient difference analysis is used to extract the temperature change trend between consecutive frames in the thermal imaging frame sequence. Subsequently, combined with the regional layer boundaries extracted in the previous steps, the extracted thermal field temperature data of each frame is projected onto the boundary range of the chip body layer, lead interconnect layer, and encapsulation colloid layer, and the temperature change of each region over time is formed into a continuous curve, constructing a time-temperature thermal evolution curve. Layered thermal response maps of each structural layer are generated through space-time mapping for subsequent thermal anomaly analysis.

[0066] Specifically, multi-frame averaging employs a windowed moving average algorithm with a sliding window width of 5 frames; transient differencing uses inter-frame pixel-level subtraction followed by normalization. The construction of the time-varying thermal evolution curve uses the regional average temperature change curve over time, with each layer of the region modeled independently. The layered thermal response map uses structural layer labels as indexes and a temperature-time two-dimensional matrix as its core content, forming formatted thermal response data blocks for direct processing by downstream analysis modules.

[0067] Gradient analysis and outlier marking are performed on the layered thermal response map to identify regions of abrupt thermal diffusion change and regions of delayed heating. Using the geometric center of the target power chip as a reference, the thermal diffusion offset vector of the region of abrupt thermal diffusion change and the maximum thermal center deviation of the region of delayed heating are calculated.

[0068] In this step, gradient analysis and outlier marking are performed on the heat propagation path and time response characteristics in the layered thermal response map to identify two key regions: one is the region of abrupt thermal diffusion change, i.e., the location where the temperature gradient changes drastically in a short period of time; the other is the region of delayed heating, i.e., the region where the thermal response speed is significantly slower than that of the overall chip area. Based on the geometric center position reconstructed from the chip contour map, the spatial offset direction and distance of the region of abrupt thermal diffusion change (i.e., the thermal diffusion offset vector) and the maximum deviation distance of local hot spots relative to the center in the region of delayed heating (i.e., the maximum thermal center deviation) are calculated.

[0069] Specifically, gradient analysis uses the Sobel operator to process the temperature field in the thermal response map and detects the rate of temperature change. Outlier markers are selected based on a dual-threshold strategy (e.g., a local gradient greater than twice the global mean or a heating delay greater than 5 frames). The thermal diffusion offset vector is calculated using the coordinate difference between the hotspot centroid and the chip's geometric center; the maximum thermal center deviation is the Euclidean distance from the maximum temperature point in all hysteresis regions to the chip center. These parameters are used to subsequently construct the thermal field offset.

[0070] The thermal field offset is constructed based on the thermal diffusion offset vector and the maximum thermal center deviation.

[0071] In this step, the extracted thermal diffusion offset vector is fused with the maximum thermal center deviation to construct a thermal field offset, which comprehensively reflects the spatial anomaly degree and temporal response delay degree of the internal heat conduction path of the chip. The thermal field offset, as one of the core indicators of thermal characteristics, is used to reveal the location of structural or material defects causing thermal anomalies.

[0072] Specifically, the thermal field offset is represented as a ternary structure containing direction, magnitude, and hysteresis. The direction is the unit direction vector of the thermal diffusion offset vector, the magnitude is the modulus of this vector (i.e., the offset distance), and the hysteresis is the ratio of the maximum thermal center deviation value to the global average temperature rise rate. This structure is ultimately encoded as the edge attributes and thermal anomaly labels of the region nodes in the model.

[0073] By performing time window segmentation and regional peak analysis on the infrared thermal imaging frame sequence, the rate of change of the temperature rise curve and the duration of abnormal frames are obtained. By combining the rate of change of the temperature rise curve and the duration of abnormal frames, the abnormal temperature rise response area is identified.

[0074] In this step, the infrared thermal imaging frame sequence is segmented into fixed time windows (e.g., every 10 frames). Peak value analysis is performed on the temperature change curves of each region within each time window to calculate the rate of change of the temperature rise curves in each region and identify the frames with abnormal temperature rise changes. At the same time, the duration of abnormal frames is counted to filter out regions with sudden increases in high temperature or abnormal continuous heating within a specific time window, and finally, the abnormal temperature rise response areas are identified.

[0075] Specifically, the rate of temperature change is measured in units of the average temperature difference per frame, and a threshold (e.g., greater than 1.5 times the global average temperature rise rate) is set as the criterion for anomaly detection. The duration of abnormal frames is marked by the number of consecutive frames exceeding the threshold (e.g., greater than 6 consecutive frames). The final result is a set of regional coordinates and corresponding anomaly type labels, labeled as "rate anomaly," "persistent anomaly," or "both combined."

[0076] Cross-analysis is performed on the thermal field offset and the temperature rise response anomaly zone, and a set of thermal anomaly features is generated based on the analysis results.

[0077] In this step, the constructed thermal field offset and the identified temperature rise response anomaly areas are cross-analyzed in both spatial and temporal dimensions to determine their spatial overlap and temporal coupling relationship. If a region exhibits both significant thermal diffusion offset and persistent temperature rise anomalies, it can be identified as having a high defect risk. Based on this analysis, a thermal anomaly feature set is formed, containing specific index parameters and corresponding labels for each anomaly region.

[0078] Specifically, the cross-analysis employs spatial intersection comparison (e.g., regional IoU intersection greater than 0.3) and temporal window overlap determination (e.g., duration overlap greater than 0.5), ultimately encapsulating regions satisfying the overlap relationship into a structured set of thermal anomaly nodes. Each node includes attributes such as coordinates, offset vector, heating rate, hysteresis, and anomaly level, ultimately constructing a thermal anomaly feature set for input into the defect identification model.

[0079] As a preferred embodiment, step S40 can preferably be: The features of each layer in the morphological feature parameter set are vectorized and encoded to generate a subset of morphological feature map structures. Based on the thermal offset and abnormal region in the thermal anomaly feature set, the thermal offset and abnormal region are transformed into region nodes and edge attributes to construct a subset of thermal feature map structures. The working electrical parameter dataset is subjected to multidimensional normalization. The normalized working electrical parameter dataset is combined with the anomaly weight distribution information to construct a subset of electrical parameter map structures. The anomaly weight distribution information refers to the electrical parameter deviation confidence score set constructed based on historical chip test samples, which is used to measure the deviation weight distribution of electrical parameter features under a specific defect type.

[0080] In this step, the morphological sub-feature sets of the bulk layer, interconnection layer, and colloidal layer in the morphological feature parameter set are first vectorized and encoded to extract the key descriptive indicators of each structural layer. Then, structural graph nodes are constructed using node representation methods, and edge information is constructed using spatial connection relationships, thereby generating a structural subset of morphological feature graph with a clear structure and distinct hierarchy.

[0081] Secondly, information such as thermal diffusion offset vector, maximum thermal center deviation, temperature rise curve change rate and anomalous frame duration in the thermal anomaly feature set is transformed into node features and edge weight attributes to form a subset of thermal feature map structure representing the correlation between spatial anomaly intensity and temporal thermal evolution.

[0082] Meanwhile, the obtained working electrical parameters (including on-resistance, breakdown voltage, leakage current, and thermal resistance) are processed by Min-Max normalization to distribute them in the range of 0 to 1. Then, they are weighted and fused with the abnormal weight distribution information established in the training of historical chip samples to construct the electrical parameter deviation confidence score, which is used to generate node confidence and abnormal category edge attributes, and finally form a subset of electrical parameter graph structure.

[0083] Specifically, in the morphological feature map structure subset, each node represents a sub-structural unit, such as a pad in the body layer, a pin in the lead layer, or a package boundary in the colloid layer. Each node contains feature vectors such as "connectivity, symmetry, and texture density," and edge information records spatial adjacency and inter-layer coupling.

[0084] In the thermal feature map structure subset, nodes represent regional thermal anomaly units, such as offset hotspot regions and lagging heating regions. The additional features of nodes are "offset direction, amplitude, lag score", etc., and the edge attributes record the directionality of the heat diffusion path and the temperature difference gradient.

[0085] In the electrical parameter graph structure subset, nodes represent a single electrical parameter index, the feature dimension is a normalized value, and the edge attributes are set by a confidence score after matching with the abnormal weight distribution, indicating the sensitivity of the electrical parameter to a specific packaging defect.

[0086] The morphological feature map structure subset, thermal feature map structure subset, and electrical parameter map structure subset are input into the preset defect identification model. In the defect identification model, a structural anomaly feature sub-map is established based on the morphological feature map structure subset, a thermal response anomaly sub-map is established based on the thermal feature map structure subset, and an electrical parameter deviation sub-map is established based on the electrical parameter map structure subset.

[0087] In this step, the three graph structure subsets mentioned above are input into a preset defect identification model according to the node-edge construction form. This model adopts a multi-subgraph joint reasoning mechanism to construct structural anomaly feature subgraphs, thermal response anomaly subgraphs, and electrical parameter deviation subgraphs, respectively. Each subgraph consists of its own nodes and edges and has an independent graph embedding module and aggregation mechanism to extract anomaly discrimination features at the graph level, subgraph level, and node level.

[0088] Specifically, the defect identification model adopts a Graph Neural Network (GNN) architecture, comprising several subgraph embedding models. Each subgraph embedding model is a feature extraction module independently constructed for each type of subgraph, used to model its internal structural relationships and semantic distribution features. The subgraph embedding models can use either a Graph Convolutional Network (GCN) or a Graph Attention Network (GAT) as their basic structure. GCN is suitable for subgraphs with relatively balanced node structure distribution and clear local topological relationships, such as subgraphs with structural anomaly characteristics. GAT is suitable for subgraphs with strong semantic dependencies between nodes and significant differences in edge attributes, such as subgraphs with abnormal thermal response or subgraphs with deviating electrical parameters.

[0089] In the structural anomaly feature subgraph, the model extracts the topological geometric consistency index of each structural node through GCN, and combines it with the topological connectivity between adjacent nodes to output a structural stability score, which is used to determine whether there are structural anomalies such as missing pads or lead offsets.

[0090] In the thermal response anomaly subplot, the model uses GAT to focus on features such as directional shifts in the thermal diffusion path and hot spot node location distribution to calculate thermal response deviation scores, thereby identifying encapsulation thermal anomalies such as thermal diffusion asymmetry and local overheating.

[0091] In the electrical parameter deviation subgraph, the model combines the confidence weight matching results of each electrical parameter node with the historical samples to establish a coupling strength mapping between node features and expected reference standards, and outputs an electrical performance stability score to measure whether there are electrical parameter problems such as voltage breakdown and leakage current anomalies.

[0092] It is important to note that the graph neural network in this scheme does not aim for traditional "node classification" or "graph classification" as its final output. Instead, it outputs a structured encapsulated anomaly graph structure through subgraph embedding and cross-domain fusion mechanisms, serving as the basis for subsequent anomaly aggregation, causal reasoning, and process tracing. This structured output format has stronger hierarchical expressiveness, information correlation, and visualization analysis capabilities compared to traditional GNN models.

[0093] The structural anomaly feature subgraph, thermal response anomaly subgraph, and electrical parameter deviation subgraph are cross-fused by graph embedding to output a chip packaging anomaly identification map. This map simultaneously includes structural anomaly nodes, thermal response anomaly paths, and electrical parameter deviation related edges.

[0094] In this step, after performing unified graph embedding processing on the three subgraphs, a cross-fusion mechanism at the graph level is used to achieve the linkage mapping of multi-dimensional anomaly information. Cross-fusion includes node-level alignment, edge attribute collaborative modeling, and semantic projection between subgraphs, which associates structural anomalies, thermal response anomalies, and electrical parameter anomalies in the same graph, forming an encapsulated anomaly identification graph.

[0095] Specifically, a multi-head graph attention fusion mechanism is employed to embed the three subgraphs in parallel. Attention weighting is applied to the common adjacency regions between nodes and the similarity of edge attributes to achieve cross-domain fusion of structural, thermal, and electrical parameter features. The resulting recognition map output after fusion includes: The node label marks the type of structural anomaly (such as missing pads, warped pins, etc.). The path structure records the path of abnormal thermal response (such as thermal diffusion imbalance). The deviation of electrical parameters from the reference value is marked in the edge attributes (e.g., the breakdown voltage is more than 20% lower than the reference value).

[0096] This map serves as the foundation for representing the overall encapsulation defect results, possessing multiple capabilities such as layering, visualization, and source tracing, and providing a basic structure for subsequent steps.

[0097] As a preferred embodiment, step S50 can preferably be: The chip packaging anomaly identification map is hierarchically divided and node aggregated to construct a multi-scale graph structure index set. Pattern matching is performed on the graph structure index set to obtain a set of aggregated packaging anomaly fragments.

[0098] In this step, based on the aforementioned chip packaging anomaly identification map, a hierarchical partitioning operation is first performed, dividing structural anomaly nodes, thermal response anomaly paths, and electrical parameter deviation edges in the map into different layers. A node hierarchy is established based on the packaging physical structure, heat conduction region, and electrical performance indicators. Subsequently, a node aggregation strategy is employed to merge features of nodes with high semantic similarity or strong spatial proximity, generating region-level node representations. Finally, a multi-scale graph structure index set with local details and global contours is constructed. This index set supports feature recognition at different scales.

[0099] Next, a graph matching algorithm (such as the VF2 subgraph isomorphic matching algorithm) is used to search for sub-image segments that highly match the existing encapsulation defect template in the multi-scale graph structure index set, thereby obtaining a set of multiple encapsulation anomaly aggregate fragments, which are used to summarize and extract typical encapsulation defect patterns.

[0100] Specifically, in the hierarchical partitioning stage, the type attributes (structural nodes / hot path nodes / electrical parameter edges) and position attributes (coordinate position, hierarchical index) of graph nodes are used as grouping criteria to form a three-layer graph structure; in the node aggregation stage, the cosine similarity of graph embedding vectors is used as a criterion to aggregate nodes with a similarity higher than 0.85, generate new aggregated nodes, and update edge attributes.

[0101] Subsequently, by setting a graph structure matching threshold (such as node attribute differences less than 0.1 and topological structure similarity of more than 90%), the potential local subgraphs in the graph are compared with typical defect pattern templates, and a set of encapsulated abnormal aggregate fragments is output.

[0102] Based on the set of aggregated fragments of packaging anomalies, the packaging structure defect region, thermal diffusion anomaly path, and high-risk electrical parameter indicators are extracted, and the packaging defect type results are generated based on the packaging structure defect region, thermal diffusion anomaly path, and high-risk electrical parameter indicators.

[0103] In this step, the core foundation is the set of anomalous encapsulation fragments. The node and edge information contained within these fragments is further analyzed to identify areas with abnormally dense structural distribution as encapsulation structural defect areas, and heat accumulation offset paths as abnormal heat diffusion paths. Edge nodes with prominent confidence weights in the electrical parameter graph are used as high-risk indicators of electrical parameters. Finally, through feature fusion across three dimensions—encapsulation structure, thermal response, and electrical performance—defect type labels are generated, outputting encapsulation defect type results such as "lead bridging," "encapsulation bulge," "uneven heat dissipation," and "electrical parameter drift."

[0104] Specifically, in the structural layer, areas with asymmetrical pad distribution and uneven shrinkage at the package edge are identified as defect areas; in the thermal response layer, thermal flow paths that deviate from the geometric center of the chip are traced and confirmed as abnormal paths; in the electrical parameters layer, parameters with high confidence scores (such as breakdown voltage deviation > 20%) are extracted as high-risk indicators.

[0105] The three types of anomalies are combined and matched with a decision tree model (based on a trained defect label rule base) to generate specific packaging defect types, such as "pin open-circuit thermal stress failure" caused by hot spot accumulation or "packaging delamination defect" caused by structural degradation.

[0106] As a preferred embodiment, after step S50, the following is also included: Based on the packaging defect type results, the corresponding defect cause node set is extracted, and the defect cause node set is clustered by causal attributes to obtain the causal feature set. Based on the association pattern in the causal feature set, the packaging process causal path diagram is derived and generated.

[0107] In this step, using the identified packaging defect type results, the graph nodes in the packaging anomaly identification map that have a direct or indirect impact on the defect result are traced back and extracted into a set of defect cause nodes. The attribute values, deviation levels, and dependencies on the defect label are labeled for each node. After causal attribute encoding of the nodes in this set, cluster analysis (such as DBSCAN density clustering) is performed to form multiple subsets of causal factors, constituting a causal feature set. Furthermore, based on the correlation strength and logical deduction relationships between causal features, influence paths are constructed, ultimately deriving a complete causal path diagram of the packaging process.

[0108] Specifically, the defect causal node set includes elements such as electrical parameter mutation nodes, structural connectivity breakpoints, and thermal anomaly nodes. Their attributes, such as offset magnitude and correlation strength, are standardized to form causal feature vectors. A density clustering algorithm is then used to aggregate similar causal nodes into multiple sub-causal sets.

[0109] Subsequently, using Bayesian causal graph modeling or Markov causal chain reasoning, a causal path graph is established, where each path represents a causal chain from a process deviation factor to a defect type, forming a complete process causal evolution map.

[0110] By using the causal path diagram of the packaging process, the key process deviation factors that lead to the formation of defects are identified. The key process deviation factors are mapped to the process log and the process condition table to obtain matching process events. Based on the matching process events, the timing information, occurrence frequency and equipment number of the process events are extracted.

[0111] In this step, based on nodes with higher positions and path weights in the process causal path diagram, several key process deviation factors that have the greatest impact on defect type formation are selected, such as "colloidal filling deviation," "insufficient curing time," and "pad humidity contamination." This set of factors is then mapped item by item to historical process logs and process condition tables. Related matching process events are identified through field matching (such as process parameter name, process segment number, and equipment identification code). These events are further processed by extracting time sequence information (timestamp), occurrence frequency (work order count), and equipment number (machine number) for subsequent traceability and correction.

[0112] Specifically, for example, if the critical deviation factor is "insufficient curing time," then the process log will search for records with curing time less than the preset standard in the process log for the record with process number "CURE_05." If the problem occurs in three consecutive production cycles under a certain machine number "EQ101," then its timestamp and frequency will be extracted as process event data. This type of matching is accomplished through SQL condition filtering or ElasticSearch keyword aggregation.

[0113] Cross-analysis of the timing, frequency, and equipment number of process events yields a set of defect cause paths, and key nodes in the defect cause path set are used as process traceability anchors.

[0114] In this step, based on process event data, a ternary vector matrix is ​​constructed that includes time sequence information (event order), frequency information (abnormal repetition degree), and equipment association information (fault concentration). Cross-analysis is performed to construct a set of defect cause paths. From this set, the critical path nodes that contribute the most to defect type identification are selected. These critical nodes are used as process traceability anchors that can be located, controlled, and re-inspected for feedback control and defect closed-loop correction.

[0115] Specifically, the cross-analysis employs event aggregation analysis and path weight backtracking algorithm. By calculating the frequency threshold (e.g., ≥3 times) of a device repeatedly associating with the same deviation factor within a certain time period, and the node whose deviation factor has a weight exceeding 0.75 in the causal path graph, it is included in the candidate traceability anchor point. Finally, a complete closed-loop path graph of defect type - process causal path - traceability anchor point is formed, which can be output to the MES system as alarm rules or production process optimization suggestions.

[0116] like Figure 2 As shown, this application also provides a power chip packaging inspection device 10, which specifically includes the following modules: The data acquisition module 11 is used to acquire the structural image, infrared thermal imaging frame sequence, and working electrical parameter dataset of the target power chip after packaging.

[0117] High-precision optical imaging equipment is used to acquire structural images of the target power chip under multi-angle and multi-focal length conditions. At the same time, infrared imaging equipment is used to acquire continuous infrared thermal imaging frame sequences under the chip's rated operating voltage and different operating conditions. Electrical parameter testing instruments are used to collect electrical parameter data such as the chip's on-resistance, breakdown voltage, leakage current, and thermal resistance, ensuring multi-dimensional data coverage and high-quality acquisition.

[0118] Image processing module 12 is used to perform layer recognition on structural images and extract morphological feature parameters of chip body layer, lead interconnect layer and encapsulation colloid layer to construct a set of morphological feature parameters.

[0119] A multi-scale image segmentation algorithm was used to segment the structural image hierarchically, identifying the chip body layer, lead interconnect layer, and encapsulating colloid layer. Based on gradient detection and texture analysis methods, morphological feature parameters of each layer were extracted, including uniformity, edge continuity, metal trajectory connectivity, and bubble texture density, constructing a complete set of morphological feature parameters for subsequent analysis.

[0120] The data analysis module 13 is used to perform transient difference and regional peak analysis on the infrared thermal imaging frame sequence to construct the thermal field offset and temperature rise response anomaly region, and to construct a thermal anomaly feature set based on the thermal field offset and temperature rise response.

[0121] The transient difference algorithm is used to calculate the thermal field changes at each moment in the infrared thermal imaging frame sequence. Hot spots and abnormal heating areas are identified through regional peak detection. Furthermore, time series analysis methods are combined to construct thermal field offset and abnormal temperature rise response areas. Based on the above results, a set of thermal anomaly features is generated to characterize the location of thermal conduction anomalies and potential defects in the chip.

[0122] The data recognition module 14 is used to input the set of morphological feature parameters, the set of thermal anomaly features, and the set of working electrical parameters into a preset defect recognition model to obtain a chip packaging anomaly recognition map.

[0123] After vectorizing and encoding the set of morphological feature parameters, the set of thermal anomaly features, and the set of working electrical parameters, the data is input into the preset defect identification model. The model is based on graph structure construction and graph embedding algorithm to achieve cross-fusion of multi-source features and outputs a chip packaging anomaly identification map, which comprehensively reflects multi-dimensional defect information of structure, thermal response and electrical parameter deviation.

[0124] The node aggregation module 15 is used to perform hierarchical division and node aggregation of the chip packaging anomaly identification map to obtain the packaging defect type results.

[0125] The anomaly identification map is hierarchically divided and nodes are aggregated. A multi-scale graph pattern matching algorithm is used to extract the aggregated fragments of packaging anomalies. Finally, by combining structural defects, abnormal thermal diffusion paths, and abnormal electrical parameters, the packaging defect type results are generated, providing an accurate basis for subsequent process optimization and quality control.

[0126] It should be noted that those skilled in the art will understand that, for the sake of convenience and brevity, the specific working process of the device and each module described above can be referred to the corresponding process in the aforementioned Embodiment 1, and will not be repeated here.

[0127] The above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A method for packaging and testing power chips, characterized in that, The method comprises the following steps: obtaining the structure image, the infrared thermal imaging frame sequence and the working electrical parameter data set of the target power chip after packaging; performing layered identification on the structure image, and extracting the morphological feature parameters of the chip body layer, the lead interconnection layer and the packaging adhesive layer obtained through layered identification to construct a morphological feature parameter set; performing transient differential and regional peak value analysis on the infrared thermal imaging frame sequence to construct a thermal field offset and a temperature rise response abnormal area, and constructing a thermal anomaly feature set based on the thermal field offset and the temperature rise response; inputting the morphological feature parameter set, the thermal anomaly feature set and the working electrical parameter data set into a preset defect identification model to obtain a chip packaging abnormality identification atlas; performing hierarchical division and node aggregation on the chip packaging abnormality identification atlas to obtain a packaging defect type result.

2. The method of claim 1, wherein, The method comprises the following steps: photographing the target power chip from multiple angles, performing gray scale equalization and denoising preprocessing on the multi-angle images to obtain the structure image; obtaining the infrared radiation field intensity data and the time sequence thermal diffusion distribution map of the target power chip under the rated voltage condition, extracting the regional temperature maximum value curve according to the infrared radiation field intensity data to construct a transient temperature change trajectory; identifying the heat diffusion path according to the time sequence thermal diffusion distribution map to obtain a heat diffusion area response map, and performing time and space registration on the transient temperature change trajectory and the heat diffusion area response map to obtain the infrared thermal imaging frame sequence; obtaining the working electrical parameter data set of the target power chip under multiple working conditions, wherein the working electrical parameter data set includes on-resistance, breakdown voltage, leakage current and thermal resistance data.

3. The method of claim 1, wherein the power chip package detection method is characterized by, The method comprises the following steps: performing image segmentation and region reconstruction on the structure image to obtain a region layered boundary, and extracting a gray scale gradient mutation area, geometric arrangement information and edge connectivity based on the region layered boundary; identifying the pad contour and the body average intensity region according to the gray scale gradient mutation area to determine the chip body layer, and extracting uniformity index, edge continuity and pad symmetry in the chip body layer to construct a body layer morphological sub-feature set; identifying the lead trace trajectory and the metal reflection band according to the geometric arrangement information to determine the lead interconnection layer, and extracting metal trace connectivity, pin distribution density and pin twist degree in the lead interconnection layer to construct an interconnection layer morphological sub-feature set; identifying the packaging edge contour and the texture uniformity distribution according to the edge connectivity to determine the packaging adhesive layer, and extracting bubble texture density, adhesive distribution gradient and edge shrinkage rate in the packaging adhesive layer to construct an adhesive layer morphological sub-feature set; fusing the body layer morphological sub-feature set, the interconnection layer morphological sub-feature set and the adhesive layer morphological sub-feature set to construct a multi-level morphological feature parameter set.

4. The method of claim 3, wherein the power chip package detection method is characterized by, The transient differential and regional peak value analysis are performed on the infrared thermal imaging frame sequence to construct a thermal field offset and a temperature rise response abnormal area, and a thermal anomaly feature set is constructed based on the thermal field offset and the temperature rise response. The multi-frame average and transient differential analysis are performed on the infrared thermal imaging frame sequence to extract a time thermal evolution curve of each layer area of the chip, the time thermal evolution curve is mapped to the chip body layer, the lead interconnection layer and the encapsulation glue layer by using the area layered boundary, and a layered thermal response graph is obtained; The gradient analysis and abnormal point marking are performed on the layered thermal response graph to identify a thermal diffusion mutation area and a lagging temperature rise area, and a thermal diffusion offset vector of the thermal diffusion mutation area and a maximum thermal center deviation of the lagging temperature rise area are calculated based on the geometric center of the target power chip as a reference; The thermal field offset is constructed based on the thermal diffusion offset vector and the maximum thermal center deviation; The time window segmentation and regional peak value analysis are performed on the infrared thermal imaging frame sequence to obtain a temperature rise curve change rate and an abnormal frame duration, and the temperature rise curve change rate and the abnormal frame duration are combined to identify a temperature rise response abnormal area; The thermal field offset and the temperature rise response abnormal area are cross-analyzed, and a thermal anomaly feature set is generated based on the analysis result.

5. The method of claim 1, wherein, The morphology feature parameter set, the thermal anomaly feature set and the working electrical parameter data set are input into a preset defect recognition model to obtain a chip packaging abnormality recognition graph, and the chip packaging abnormality recognition graph is obtained. The morphology feature parameter set is vectorized and encoded to generate a morphology feature graph structure subset, a thermal feature graph structure subset is constructed based on the thermal anomaly feature set, a multi-dimensional normalization processing is performed on the working electrical parameter data set, the normalized working electrical parameter data set is combined with abnormal weight distribution information to construct an electrical parameter graph structure subset, and the abnormal weight distribution information refers to an electrical parameter deviation confidence score set constructed based on historical chip test samples; The morphology feature graph structure subset, the thermal feature graph structure subset and the electrical parameter graph structure subset are input into a preset defect recognition model, in the defect recognition model, a structure abnormal feature subgraph is established based on the morphology feature graph structure subset, a thermal response abnormal subgraph is established based on the thermal feature graph structure subset, and an electrical parameter deviation subgraph is established based on the electrical parameter graph structure subset; The structure abnormal feature subgraph, the thermal response abnormal subgraph and the electrical parameter deviation subgraph are cross-fused by graph embedding to output a chip packaging abnormality recognition graph.

6. The method of claim 1, wherein, The chip packaging abnormality recognition graph is hierarchically divided and node-aggregated to obtain a packaging defect type result, and the packaging defect type result is obtained. The chip packaging abnormality recognition graph is hierarchically divided and node-aggregated to construct a multi-scale graph structure index set, and a packaging abnormality aggregation segment set is obtained by performing pattern matching on the graph structure index set. Based on the encapsulation abnormal aggregation fragment set, encapsulation structure defect area, thermal diffusion abnormal path and high risk index of electrical parameters are extracted, and a packaging defect type result is generated based on the encapsulation structure defect area, the thermal diffusion abnormal path and the high risk index of electrical parameters.

7. The method of claim 1, wherein After the chip packaging anomaly recognition graph is hierarchically divided and the nodes are aggregated to obtain the packaging defect type result, the method further includes: According to the packaging defect type result, a corresponding defect cause node set is extracted, the defect cause node set is subjected to causal attribute clustering to obtain a causal feature set, and a packaging process causal path graph is generated based on the causal feature set; Using the packaging process causal path graph, a key process deviation factor causing the defect formation is identified, the key process deviation factor is mapped to a process log and a process condition table to obtain a matching process event, and time sequence information, occurrence frequency and equipment number of the process event are extracted according to the matching process event; The time sequence, the occurrence frequency and the equipment number of the process event are cross-analyzed to obtain a defect cause path set, and a key node in the defect cause path set is taken as a process trace anchor point.

8. A package detection apparatus of a power chip, characterized by comprising: It includes: A data acquisition module is configured to acquire a structural image, an infrared thermal imaging frame sequence and a working electrical parameter data set of a target power chip after packaging is completed; An image processing module is configured to perform hierarchical identification on the structural image, and extract morphological feature parameters of a chip body layer, a lead interconnection layer and a packaging adhesive layer obtained through hierarchical identification to construct a morphological feature parameter set; A data analysis module is configured to perform transient differential and regional peak value analysis on the infrared thermal imaging frame sequence to construct a thermal field offset and a temperature rise response abnormal area, and construct a thermal anomaly feature set based on the thermal field offset and the temperature rise response; A data recognition module is configured to input the morphological feature parameter set, the thermal anomaly feature set and the working electrical parameter data set into a preset defect recognition model to obtain a chip packaging anomaly recognition graph; A node aggregation module is configured to hierarchically divide the chip packaging anomaly recognition graph and aggregate the nodes to obtain a packaging defect type result.

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