Interface circuit board detection system method based on Netlist

Abstract

The invention relates to the technical field of fault detection, and particularly discloses a Netlist-based interface circuit board detection system and method, and the method comprises the following steps: analyzing a Netlist, and generating the test path information of an interface circuit board; according to the test path information, a Channel-map is generated; generating a diagnosis program according to the test path information and a diagnosis code library; when the terminal of the test path information contains the DUT pin, determining a test machine channel corresponding to the DUT pin by referring to Channel-map, and performing test control according to the test machine channel; running the diagnosis program, controlling a test machine to apply a test signal to the interface circuit board, and obtaining a response signal; and according to the response signal, determining whether the electrical characteristics of the device in the interface circuit board conform to expectation. According to the invention, the Netlist is introduced to realize the automatic test of the interface circuit board.

Description

Technical Field

[0001] This invention relates to the field of fault detection technology, and more specifically to a method for detecting interface circuit boards based on Netlist. Background Technology

[0002] Semiconductor testing is a crucial part of the integrated circuit industry, and interface circuit boards play a vital role in the testing process. Ensuring the interface circuit boards are functioning correctly before testing is paramount. Traditional circuit board testing relies on manually locating test paths and writing test code, which suffers from low efficiency, insufficient coverage, and an inability to dynamically adapt to complex circuit structures.

[0003] While some patent applications have improved detection accuracy through hardware optimization, existing technologies still lack intelligent support for test code generation. Furthermore, Netlist, a core component of circuit design, has not been fully utilized in automated testing processes. Summary of the Invention

[0004] The purpose of this invention is to provide a Netlist-based interface circuit board testing system and method to solve the above-mentioned technical problems.

[0005] The objective of this invention can be achieved through the following technical solutions: A Netlist-based method for testing interface circuit boards includes the following steps: The receiving interface circuit board has a Netlist, which includes network names and corresponding node connection relationships. The Netlist is parsed to extract the circuit topology and generate the test path information of the interface circuit board. The test path information includes a connection path that starts from a device pin and ends at a test instrument channel, DUT pin, power supply or ground. Based on the test path information, a channel-map is generated, which contains the mapping relationship between DUT pins and test equipment channels; Based on the test path information and the diagnostic code library, a diagnostic program is generated. The diagnostic code library stores detection code modules corresponding to device types. When the terminal of the test path information includes a DUT pin, the test machine channel corresponding to the DUT pin is determined by referring to the Channel-map and test control is performed accordingly. The diagnostic program is run to control the test machine to apply test signals to the interface circuit board and acquire response signals. Based on the response signal, it is determined whether the electrical characteristics of the devices in the interface circuit board meet expectations.

[0006] As a further aspect of the present invention, the process of generating test path information includes: Identify the node names in the Netlist, the node names having a prefix indicating the node type; Based on the network names and node connection relationships, construct the circuit connection diagram; From the circuit connection diagram, all connection paths are searched and listed to form the test path information.

[0007] As a further aspect of the present invention: the process of generating the Channel-map specifically includes: From the test path information, select the connection path that starts from the DUT pin and ends at the test machine channel; From the selected connection paths, extract the DUT pin identifiers, network names, and test machine channel identifiers, and combine them to generate the Channel-map.

[0008] As a further aspect of the present invention: the process of generating the diagnostic program includes: The type of the device is determined based on the device name contained in the test path information; Depending on the type of the device, the corresponding detection code module is called from the diagnostic code library; Configure the test parameters of the called detection code module based on the connection relationship described in the test path information; The diagnostic program is formed by integrating multiple configured detection code modules.

[0009] As a further aspect of the present invention: the diagnostic code library includes detection code modules such as a resistance detection module, a capacitance detection module, an inductance detection module, and a relay detection module.

[0010] As a further aspect of the present invention: before running the diagnostic program, it further includes: A dummy chip is installed on the DUT socket of the interface circuit board. The dummy chip is used to short multiple pins of the DUT to ground.

[0011] A Netlist-based interface circuit board testing system includes: The parsing module receives the Netlist from the interface circuit board, which contains network names and corresponding node connection relationships. The Netlist is parsed to extract the circuit topology and generate the test path information of the interface circuit board. The test path information includes a connection path that starts from a device pin and ends at a test instrument channel, DUT pin, power supply or ground. Generation module: Based on the test path information, generate a channel-map, which contains the mapping relationship between DUT pins and test equipment channels; Based on the test path information and the diagnostic code library, a diagnostic program is generated. The diagnostic code library stores detection code modules corresponding to device types. When the terminal of the test path information includes a DUT pin, the test machine channel corresponding to the DUT pin is determined by referring to the Channel-map and test control is performed accordingly. Test module: Runs the diagnostic program, controls the test machine to apply test signals to the interface circuit board, and acquires response signals; Based on the response signal, it is determined whether the electrical characteristics of the devices in the interface circuit board meet expectations.

[0012] The beneficial effects of this invention compared to the prior art are as follows: 1) Dynamically generate test paths using Netlist files. By parsing the Netlist file of the interface circuit board, extract the circuit topology, key nodes, and signal path information as the basic input for the test logic. Based on the netlist features, automatically generate test cases covering all critical paths.

[0013] 2) Utilize AI-supported test optimization to build a learning model. Train the model using historical test data to identify common fault modes (such as short circuits, open circuits, signal crosstalk, etc.) and predict potential defect areas. Empowerment learning is used to dynamically adjust test parameters (such as voltage, current, etc.) and optimize the test process based on real-time feedback, reducing redundant steps and improving coverage.

[0014] 3) The design incorporates a dummy chip to improve test coverage. By shorting the chip pins with a dummy chip, the number of test paths can be increased, thereby improving test coverage. Attached Figure Description

[0015] The invention will now be further described with reference to the accompanying drawings.

[0016] Figure 1 This is a system application block diagram of the Netlist-based interface circuit board testing method of the present invention; Figure 2 This is a schematic diagram of the connection path when generating test cases for resistors in this invention; Figure 3 This is a schematic diagram of the optimized connection path when generating test cases for resistors in this invention; Figure 4 This is a schematic diagram of the connection path when generating test cases for capacitors in this invention; Figure 5This is a schematic diagram of the connection path when generating test cases for relays in this invention; Figure 6 This is a schematic diagram of the optimized connection path when generating test cases for relays in this invention; Figure 7 This is a schematic diagram of another method for testing relays in this invention. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] Please see Figures 1-7 As shown, this invention is a method for testing interface circuit boards based on Netlist, comprising the following steps: The Netlist analysis toolset takes Netlist files as input. By parsing the Netlist files, the tools can extract channel-map information that can be used by the test program, extract SingleNets, and check for potential problems in the Netlist. It can also generate a device list and test paths. Step 1: Left-click "Select Netlist File" to select the Netlist file of the target circuit board, and parse it to generate the circuit topology diagram. The Netlist file is the output file of the EDA drawing software, which contains Net (NetName) and Node (NetPins) information and connection relationships. Its basic content is shown in the table below:

[0019] Step 2: Left-click "Generate Channel-map" to generate a Channel-map (also called a socket file). The Channel-map searches starting from the pins of the chip under test (DUT), as shown in the table above. The DUT will be named with "U", with U1 referring to the first DUT under test. It's a mapping table with the instrument channel as the terminal (instrument terminal node names start with "J"). The generated ChannelMap can be used for chip testing. The generated Channel-map information is shown in the table below:

[0020] Step 3: Left-click "Generate Test Path" to generate the test path. The test path is a mapping table that searches from the device pins on the DIB board, ending at the instrument channel, the pin of the chip under test (DUT), power supply, or GND. The generated test path is as follows: R1.1->HSU.DR01; R1.2->U1.D1; Based on the information above, we know that one pin of resistor R1 is connected to the equipment resource, and the other pin is connected to the chip pin. Therefore, we can find the complete test path for resistor R1.

[0021] Step 4: Left-click "Check Netlist" to help users check the schematic, such as generating SingleNets and checking Naming Rules. The presence of SingleNets in the Netlist indicates that the user may have missed connecting some circuitry. Additionally, it checks against the customer's naming rules; any violations of Net and Node naming conventions will be statistically analyzed and output. This helps users check their schematic design.

[0022] The DIBChecker toolkit takes the output of the Netlist analysis toolkit as input and generates a test project based on the generated test path and the DIB diagnostic code library for interface circuit board diagnostics.

[0023] Step 1: Left-click "Select Netlist Results" to select the result file generated by the Netlist toolset.

[0024] Step 2: Left-click the "Generate Test Program" button. The tool will generate a test project based on the Netlist result file and the DIB diagnostic code library for interface circuit board diagnostics. Two platforms are available: "T800" and "TM8000". Other platforms can be added gradually.

[0025] The DIB diagnostic code library contains device inspection methods based on test equipment, including but not limited to testing methods and code for devices such as resistors, capacitors, inductors, and relays. The code library is stored in a modular fashion, creating corresponding test cases for different types of test paths. When the test path information matches the corresponding test case, the corresponding test case is invoked to generate test code. An example is provided below; Example 1, Resistance: like Figure 2 The DUT pin Pin1 is connected to the instrument channel of the machine via R1. The following path can be generated using the NetList analysis toolset: Path 1: R1.1 to HSU.PD5; Path 2: From R1.2 to DUT1.1; Because the characteristics of DUT1Pin1 are variable, to achieve a complete test path, we introduce a DummyDUT to short DUT1Pin1 and GND together. This simplifies the test path to... Figure 3 : Therefore, we can apply two different currents I1 and I2 through PD5, measure V1 and V2 respectively, and then obtain the resistance value R1 = (V2-V1) / (I2-I1). Once the resistance value is obtained, it can be compared with the expected resistance value to determine whether it meets the expectation. The other examples follow the same comparison approach. The code corresponding to the above process is automatically generated by combining the test path and code library. The applied current value (test parameter) will also be automatically selected based on the resistance value to be measured. The selection method is determined by looking up a table.

[0026] Example 2, Capacitor: like Figure 4 As shown, one end of C1 is connected to the instrument channel of the machine, and the other end is grounded. The following path can be generated using the NetList analysis toolset: Path 1: C1.1 to HSU.PD6; Path 2: C1.2 to GND; Therefore, we can charge the capacitor by applying a current I through PD6, calculate the capacitance in the linear region, and determine the calculation result based on the capacitor charging formula: The tool automatically selects I, dV, and dt based on the capacitance value using a lookup table method, with the table pre-stored. Users can gradually optimize the tool's accuracy based on the test results. Example 3, Relay: like Figure 5 As shown, one end of K1 is connected to the instrument channel of the testing equipment, and the other end is connected to the pin of the chip under test (DUT). The following path can be generated using the NetList analysis toolset: Path 1: K1.1 to HSU.PD7; Path 2: From K1.2 to DUT1.3; In this case, we have two ways to test the relay. One is to test it with a dummy chip. Since the dummy chip grounds all its pins, the test schematic can be simplified as follows: Figure 6 .

[0027] When the relay is closed, a current I is applied through PD7. If the measured voltage is close to 0V, it means that the relay is closed successfully; otherwise, the relay fails to close.

[0028] When the relay is disconnected, a current I is applied through PD7. If the measured voltage is the clamping voltage, it means that the relay has successfully disconnected; otherwise, the relay has failed to disconnect.

[0029] Another testing method is to use TDR (Time Domain Reflectometry) without the dummy chip, such as... Figure 7 As shown: We can apply a step signal to the relay when it is closed and open using PD7, and simultaneously capture the waveform. By utilizing the characteristic that signals reflect when impedance is discontinuous, we can determine whether the relay can close normally. The judgment conditions are as follows: 1. If the timing of the reflected signals captured under both open and closed relay conditions is the same or the difference is small, it indicates that the relay operation has failed.

[0030] 2. If the time difference between the reflected signals captured under the conditions of relay opening and closing is large, it indicates that the relay has operated successfully.

[0031] It should be noted that the test signal refers to the electrical excitation applied by the test equipment to the determined test path during detection. It can take the form of constant current, constant voltage, pulse or step, etc. The application position corresponds to the excitation end in the channel mapping relationship. The purpose is to drive the device in the path into an observable state under controlled conditions. The response signal refers to the electrical quantity record collected by the measuring end under the same time reference, which corresponds one-to-one with the test signal. It is usually expressed as a voltage-time sequence, a current-time sequence, or a time sequence of reflected waveforms, used to characterize the behavior of the path under the applied excitation conditions. For example, when detecting a resistor, the test signal is a constant current, and the response signal is a continuous record of the potentials at both ends of the device; when detecting a capacitor, the test signal is a constant current charging, and the response signal is a curve of potential rising over time; when detecting a relay with a dummy chip installed, the test signal is a stable excitation applied to different switching states, and the response signal is the distribution of the terminal potential in the two states; when no dummy chip is installed, the test signal is a step excitation, and the response signal is the reflected waveform generated at the contact.

[0032] Understandably, other components are handled in a similar manner. Component types are named according to predefined naming rules when the schematic is drawn. The tool determines the component type based on the name and generates test code using the searched path information and the DIB diagnostic code library. This significantly reduces code development time. Simultaneously, the code library continuously optimizes test conditions based on user feedback, resulting in more accurate test results. Users can then quickly diagnose interface circuit board issues using the generated test project and the DummyDUT, saving more time for debugging the chip under test. It's important to note that when the endpoint of a test path is a pin of the chip under test (DUT), the test equipment cannot be activated directly based solely on the pin name. This is because the equipment only recognizes its own channel number. Therefore, the "Channel-map" must be consulted first to map the pin to the specific channel number on the equipment. With this mapping, the channel can be included in the current test path on the equipment, specifying whether it is responsible for outputting test signals or acquiring response signals. This allows for channel access and switching, and subsequent output and acquisition actions can then be performed along the path. This is possible because the Channel-map is a one-to-one correspondence list of "DUT pins - equipment channels" compiled based on the previously generated test path information. It converts the logical node names from the Netlist into physical channels that the equipment can control, thus clearly defining "which equipment channel will output and which will acquire" the "pin endpoint" in the path, ensuring that there is no ambiguity when the path is actually connected to the equipment. It should be noted that deep learning technology can be introduced to use AI-supported test optimization to build a learning model. This model can be trained using historical test data to identify common fault modes (such as short circuits, open circuits, signal crosstalk, etc.) and predict potential defect areas. At the same time, reinforcement learning can be used to dynamically adjust test parameters (such as voltage, current, etc.) and optimize the test process based on real-time feedback, reducing redundant steps and improving coverage.

[0033] A Netlist-based interface circuit board testing system includes: The parsing module receives the Netlist from the interface circuit board, which contains network names and corresponding node connection relationships. The Netlist is parsed to extract the circuit topology and generate the test path information of the interface circuit board. The test path information includes a connection path that starts from a device pin and ends at a test instrument channel, DUT pin, power supply or ground. Generation module: Based on the test path information, generate a channel-map, which contains the mapping relationship between DUT pins and test equipment channels; Based on the test path information and the diagnostic code library, a diagnostic program is generated. The diagnostic code library stores detection code modules corresponding to device types. When the terminal of the test path information includes a DUT pin, the test machine channel corresponding to the DUT pin is determined by referring to the Channel-map and test control is performed accordingly. Test module: Runs the diagnostic program, controls the test machine to apply test signals to the interface circuit board, and acquires response signals; Based on the response signal, it is determined whether the electrical characteristics of the devices in the interface circuit board meet expectations.

[0034] The foregoing has provided a detailed description of one embodiment of the present invention, but this description is merely a preferred embodiment and should not be construed as limiting the scope of the invention. All equivalent variations and modifications made within the scope of the present invention should still fall within the scope of the present invention.

Claims

1. A method for detecting a Netlist-based interface circuit board, characterized by, The method comprises the following steps: receiving a Netlist of an interface circuit board, the Netlist comprising network names and corresponding node connection relationships; parsing the Netlist, extracting a circuit topology, and generating test path information of the interface circuit board, the test path information comprising connection paths starting from device pins and ending at test machine channels, DUT pins, power supplies, or grounds; generating a Channel-map according to the test path information, the Channel-map comprising mapping relationships between DUT pins and test machine channels; generating a diagnostic program according to the test path information and a diagnostic code library, the diagnostic code library storing detection code modules corresponding to device types; when the terminal of the test path information comprises a DUT pin, referring to the Channel-map to determine the test machine channel corresponding to the DUT pin and performing test control accordingly; running the diagnostic program to control a test machine to apply test signals to the interface circuit board and acquire response signals; determining whether the electrical characteristics of devices in the interface circuit board meet expectations according to the response signals.

2. The method of claim 1, wherein the interface circuit board is a Netlist-based interface circuit board. The process of generating the test path information comprises: identifying node names in the Netlist, the node names having prefixes indicating node types; constructing a circuit connection graph according to the network names and node connection relationships; searching and listing all connection paths from the circuit connection graph to form the test path information.

3. The method of claim 2, wherein the interface board is a Netlist-based interface board. The process of generating the Channel-map specifically comprises: filtering, from the test path information, connection paths starting from DUT pins and ending at test machine channels; extracting DUT pin identifiers, network names, and test machine channel identifiers from the filtered connection paths to generate the Channel-map.

4. The method of claim 1, wherein the interface circuit board is a Netlist-based interface circuit board. The process of generating the diagnostic program comprises: determining the type of a device according to the device name contained in the test path information; calling a corresponding detection code module from the diagnostic code library according to the type of the device; configuring test parameters of the called detection code module according to the connection relationship described in the test path information; integrating multiple configured detection code modules to form the diagnostic program.

5. The method of claim 1, wherein the interface circuit board is a Netlist-based interface circuit board. The detection code modules contained in the diagnostic code library comprise resistance detection modules, capacitance detection modules, inductance detection modules, and relay detection modules.

6. The method of claim 1, wherein the interface board is a Netlist-based interface board. Before running the diagnostic program, the method further comprises: installing a dummy chip on a DUT socket of the interface circuit board, the dummy chip being used to short multiple pins of a DUT to ground.

7. A Netlist-based interface board detection system, characterized by, The method comprises: a parsing module: receiving a Netlist of an interface circuit board, the Netlist comprising network names and corresponding node connection relationships; parsing the Netlist, extracting a circuit topology, and generating test path information of the interface circuit board, the test path information comprising connection paths starting from device pins and ending at test machine channels, DUT pins, power supplies, or grounds; generating a Channel-map according to the test path information, the Channel-map containing mapping relationship between DUT pins and test bench channels; generating a diagnostic program according to the test path information and a diagnostic code library, the diagnostic code library storing detection code modules corresponding to device types; when the terminal of the test path information contains a DUT pin, determining the test bench channel corresponding to the DUT pin according to the Channel-map and performing test control accordingly; a test module: running the diagnostic program, controlling the test bench to apply test signals to the interface circuit board, and acquiring response signals; determining whether the electrical characteristics of the device in the interface circuit board meet expectations according to the response signals.

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