Array substrate and touch display device

Abstract

The invention relates to the technical field of display, and discloses an array substrate and a touch display device. The array substrate comprises a first substrate body and a second substrate body, the first conductive layer is arranged on one side of the first substrate, and the first conductive layer comprises a touch signal line extending in the first direction; the insulating layer group is arranged on the side, away from the first substrate, of the first conducting layer, the insulating layer group comprises a first insulating layer group and a second insulating layer which are arranged in a stacked mode, a plurality of first via holes and a plurality of second via holes are formed in the first insulating layer group, and a plurality of third via holes are formed in the second insulating layer; the second conductive layer is arranged on at least one layer in the first insulating layer group and one side, deviating from the first substrate, of the second insulating layer, the second conductive layer comprises a touch electrode, and the touch electrode is connected to a touch signal line through a first via hole and a third via hole which are communicated and a second via hole and a third via hole which are communicated; the at least one first via hole and the at least one second via hole are communicated to the same touch signal line, the third via hole is provided with a first hole wall and a second hole wall which are oppositely arranged in the first direction, the first via hole is arranged close to the first hole wall, and the second via hole is arranged close to the second hole wall. According to the array substrate, low-frequency flicker can be avoided.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, in particular, to an array substrate and a touch display device. BACKGROUND

[0002] The existing touch and display driver integration (TDDI) product is a touch display device in which touch electrodes are arranged inside a display panel, also known as an in-cell touch display device. The touch display device has high integration, is more lightweight, and thus has a wide application prospect.

[0003] However, some touch display devices currently have a low-frequency flicker defect.

[0004] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and thus can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0005] The purpose of the present disclosure is to overcome the deficiencies of the prior art, and to provide an array substrate and a touch display device.

[0006] According to one aspect of the present disclosure, an array substrate is provided, comprising:

[0007] a first substrate substrate;

[0008] a first conductive layer arranged on one side of the first substrate substrate, the first conductive layer comprising a touch signal line, the touch signal line extending in a first direction;

[0009] an insulating layer group arranged on a side of the first conductive layer away from the first substrate substrate, the insulating layer group comprising a first insulating layer group and a second insulating layer arranged in a stack, the first insulating layer group being provided with a plurality of first vias and a plurality of second vias, the second insulating layer being provided with a plurality of third vias;

[0010] a second conductive layer arranged on a side of at least one layer of the first insulating layer group and the second insulating layer away from the first substrate substrate, the second conductive layer comprising a touch electrode, the touch electrode being connected to the touch signal line through the first via and the third via in communication and the second via and the third via in communication;

[0011] The first via and the second via are communicated to the same touch signal line, the third via has a first hole wall and a second hole wall oppositely arranged in the first direction, the first via is arranged closer to the first hole wall relative to the second hole wall in the first direction, and the second via is arranged closer to the second hole wall relative to the first hole wall in the first direction.

[0012] In an example embodiment of the present disclosure, the first insulating layer group comprises:

[0013] The first insulating layer is arranged on a side of the first conductive layer away from the first substrate, and a plurality of first sub-vias and a plurality of second sub-vias are arranged on the first insulating layer, and the second insulating layer is arranged on a side of the first insulating layer away from the first substrate;

[0014] And / or, the third insulating layer is arranged on a side of the second insulating layer away from the first substrate, and a plurality of third sub-vias and a plurality of fourth sub-vias are arranged on the third insulating layer;

[0015] The first via comprises the first sub-via and / or the third sub-via, and the first sub-via and the third sub-via are communicated to each other; and the second via comprises the second sub-via and / or the fourth sub-via, and the second sub-via and the fourth sub-via are communicated to each other.

[0016] In an example embodiment of the present disclosure, the first sub-via is arranged on the first substrate, and the third sub-via is arranged on the first substrate.

[0017] In an example embodiment of the present disclosure, the third insulating layer covers the hole wall of the third via at the first via and the third via; or the third insulating layer does not cover the first hole wall, and the third insulating layer covers the second hole wall; or the third insulating layer does not cover the first hole wall and does not cover a part of a side of the second insulating layer away from the first substrate close to the first hole wall, and the third insulating layer covers the second hole wall.

[0018] In an example embodiment of the present disclosure, the first sub-via is arranged on the first substrate, and the third sub-via is arranged on the first substrate.

[0019] In an example embodiment of the present disclosure, at the second via and the third via, the third insulating layer covers the hole wall of the third via; or, the third insulating layer does not cover the second hole wall, and the third insulating layer covers the first hole wall; or, the third insulating layer does not cover the second hole wall and does not cover a part of the second insulating layer, which is close to the second hole wall and faces away from the first substrate, and the third insulating layer covers the first hole wall.

[0020] In an example embodiment of the present disclosure, the material of the first insulating layer and the third insulating layer comprises inorganic material; and the material of the second insulating layer comprises organic material.

[0021] In an example embodiment of the present disclosure, the second conductive layer is arranged between the second insulating layer and the third insulating layer, the touch control electrode extends to one end of the second direction in the third via, the second direction intersects the first direction and is parallel to the side of the first substrate on which the first conductive layer is arranged; and the array substrate further comprises:

[0022] a third conductive layer arranged on the side of the third insulating layer facing away from the first substrate, the third conductive layer comprises a pixel electrode, a first connecting part and a second connecting part, the pixel electrode is arranged separately from the first connecting part and the second connecting part, the first connecting part connects the touch control electrode and the touch control signal line through the third via and the first via, and the second connecting part connects the touch control electrode and the touch control signal line through the third via and the second via;

[0023] Alternatively, the second conductive layer is arranged on the side of the third insulating layer facing away from the first substrate; and the array substrate further comprises:

[0024] a third conductive layer arranged between the second insulating layer and the third insulating layer, the third conductive layer comprising a pixel electrode.

[0025] In an example embodiment of the present disclosure, the array substrate further comprises:

[0026] a gate layer arranged on the side of the first substrate, the gate layer comprising a gate and a gate line, the gate being connected to the gate line;

[0027] a gate insulating layer arranged on the side of the gate layer facing away from the first substrate;

[0028] an active layer arranged on the side of the gate insulating layer facing away from the first substrate, the active layer comprising a channel part and a source connecting part and a drain connecting part arranged at both ends of the channel part;

[0029] The first conductive layer is arranged on a side of the active layer away from the first substrate, and the first conductive layer further comprises a data line, a source electrode and a drain electrode. The data line extends along the first direction and is arranged in a spaced manner with the touch signal line. The source electrode is connected to the data line and the source connection part. The drain electrode is connected to the pixel electrode and the drain connection part.

[0030] In an exemplary embodiment of the present disclosure, the first conductive layer further comprises a gate electrode and a gate line. The gate electrode is connected to the gate line. The gate line extends along the first direction and is arranged in a spaced manner with the touch signal line. The first insulating layer group further comprises:

[0031] A gate insulating layer is arranged on a side of the first conductive layer away from the first substrate. The gate insulating layer is provided with a plurality of fifth sub-vias and a plurality of sixth sub-vias.

[0032] The first via comprises the first sub-via, the third sub-via and the fifth sub-via which are in communication with each other. The second via comprises the second sub-via, the fourth sub-via and the sixth sub-via which are in communication with each other.

[0033] In an exemplary embodiment of the present disclosure, in the second direction, the distance between the edge line of the orthographic projection of the third sub-via on the first substrate and the edge line of the orthographic projection of the third via on the first substrate is greater than or equal to 1 micrometer and less than or equal to 2.5 micrometers.

[0034] In the second direction, the distance between the edge line of the orthographic projection of the fourth sub-via on the first substrate and the edge line of the orthographic projection of the third via on the first substrate is greater than or equal to 1 micrometer and less than or equal to 2.5 micrometers. The second direction intersects the first direction and is parallel to the side of the first substrate on which the first conductive layer is arranged.

[0035] In an exemplary embodiment of the present disclosure, in the first direction, the distance between the orthographic projection of the hole wall of the first via close to the first hole wall on the first substrate and the orthographic projection of the first hole wall on the first substrate is less than or equal to 0.5 micrometers. The distance between the orthographic projection of the hole wall of the first via close to the second hole wall on the first substrate and the orthographic projection of the second hole wall on the first substrate is greater than or equal to 1 micrometer and less than or equal to 2.5 micrometers.

[0036] In an example embodiment of the present disclosure, in the first direction, the distance between the second via hole and the orthographic projection of the second hole wall on the first substrate is less than or equal to 0.5 microns; the distance between the second via hole and the orthographic projection of the first hole wall on the first substrate is greater than or equal to 1 micron and less than or equal to 2.5 microns.

[0037] In an example embodiment of the present disclosure, the touch electrodes are multiplexed as common electrodes.

[0038] In an example embodiment of the present disclosure, the array substrate comprises:

[0039] The first connection structure comprises the first via hole and the third via hole.

[0040] The second connection structure comprises the second via hole and the third via hole.

[0041] In an example embodiment of the present disclosure, one of the touch electrodes is connected to one of the touch signal lines through the alternately arranged first connection structure and second connection structure.

[0042] Alternatively, at least two of the first connection structures are included in a first connection group, at least two of the second connection structures are included in a second connection group, and one of the touch electrodes is connected to one of the touch signal lines through the alternately arranged first connection group and second connection group.

[0043] In an example embodiment of the present disclosure, one of the touch electrodes is connected to at least two of the touch signal lines, and each of the touch signal lines is connected to the touch electrode through the alternately arranged first connection structure and second connection structure.

[0044] Alternatively, at least two of the first connection structures are included in a first connection group, at least two of the second connection structures are included in a second connection group, and one of the touch electrodes is connected to at least two of the touch signal lines, and each of the touch signal lines is connected to the touch electrode through the alternately arranged first connection group and second connection group.

[0045] In an example embodiment of the present disclosure, the first connection structure and the second connection structure connected to two adjacent touch signal lines are arranged in a staggered manner.

[0046] In an example embodiment of the present disclosure, the first insulating layer group further has a fourth via hole, and a projection of the fourth via hole on the first substrate is located in a middle region of a projection of the third via hole on the first substrate; the third via hole and the fourth via hole are included in a third connection structure.

[0047] In an example embodiment of the present disclosure, the first connection structure, the second connection structure and the third connection structure are included in a third connection group; one touch electrode is connected to one touch signal line through the third connection group; or, one touch electrode is connected to at least two touch signal lines, and each touch signal line is connected to the touch electrode through the third connection structure.

[0048] In an example embodiment of the present disclosure, one touch electrode is connected to one touch signal line through a plurality of connection structures; the third connection structure is located at both ends of the plurality of connection structures, and the rest of the connection structures include the first connection structure and the second connection structure; or, the third connection structure is located in the middle of the plurality of connection structures, and the rest of the connection structures include the first connection structure and the second connection structure.

[0049] In an example embodiment of the present disclosure, one touch electrode is connected to at least two touch signal lines, and each touch signal line is connected to the touch electrode through a plurality of connection structures; the third connection structure is located at both ends of the plurality of connection structures, and the rest of the connection structures include the first connection structure and the second connection structure; or, the third connection structure is located in the middle of the plurality of connection structures, and the rest of the connection structures include the first connection structure and the second connection structure.

[0050] In an example embodiment of the present disclosure, one touch electrode is connected to at least two touch signal lines, and at least two touch signal lines connected to the same touch electrode form a group of touch signal line groups, and the array substrate further includes:

[0051] A touch lead wire is connected to one end of at least two touch signal lines to make at least two touch signal lines in parallel, and a data line is arranged between adjacent two touch signal lines belonging to the same group, and a data line is also arranged between adjacent two groups of touch signal line groups.

[0052] According to another aspect of the present disclosure, a touch display device is provided, which includes the array substrate of any one of the above.

[0053] The array substrate of the present disclosure, the plurality of first vias and the plurality of second vias disposed on the first insulating layer group and the plurality of third vias disposed on the second insulating layer need to be formed by different patterning processes, the first via is disposed close to the first hole wall, the second via is disposed close to the second hole wall, and at least one first via and at least one second via are communicated to the same touch signal line. On the one hand, for the first via, the overlapping margin of the first via on the side close to the first hole wall and the third via can not be considered, so that the first via and the third via can be disposed smaller; for the second via, the overlapping margin of the second via on the side close to the second hole wall and the third via can not be considered, so that the second via and the third via can be disposed smaller, that is, the occupied area of the first via, the second via and the third via can be reduced, thereby increasing the setting space of the capacitance of the sub-pixel to ensure the voltage holding capability of the sub-pixel and avoid the occurrence of low-frequency flicker. On the other hand, even if there is a deviation in the alignment process of the mask plate during the patterning process, when the first hole wall is offset, although the first via and the third via may be connected poorly, the second via is offset to the center position of the third via, thereby ensuring the communication between the second via and the third via, thereby ensuring the connection between the touch electrode and the touch signal line; similarly, when the second hole wall is offset, although the second via and the third via may be connected poorly, the first via is offset to the center position of the third via, thereby ensuring the communication between the first via and the third via, thereby ensuring the connection between the touch electrode and the touch signal line; moreover, the offset is in the first direction, and the touch signal line extends along the first direction, so that no matter how the offset is, it will not deviate from the touch signal line.

[0054] It should be understood that the general description above and the detailed description below are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0055] The drawings herein are incorporated into the specification and form part of the specification, show embodiments consistent with the present disclosure, and together with the specification serve to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can also be obtained from these drawings without creative labor for those skilled in the art.

[0056] Figure 1 It is a schematic diagram of the structure of the in-cell touch display device.

[0057] Figure 2 It is Figure 1 It is a schematic diagram of the position relationship between the touch signal line and the sub-pixel area in the in-cell touch display device shown.

[0058] Figure 3 It is Figure 1The diagram shows the structure of a sub-pixel in the embedded touch display device.

[0059] Figure 4 This is a schematic diagram of the structure of the touch electrode and touch signal line in the array substrate of this disclosure.

[0060] Figure 5 This is a top view of an example embodiment of the array substrate disclosed herein.

[0061] Figure 6 for Figure 5 A schematic diagram of the structure of the touch electrode.

[0062] Figure 7 for Figure 5 A schematic diagram of the structure of the middle pixel electrode.

[0063] Figure 8 for Figure 5 A magnified view of the portion indicated by H in the middle.

[0064] Figure 9 In accordance with Figure 8 A schematic diagram of a cross-section cut by section AA.

[0065] Figure 10 In accordance with Figure 8 A sectional view diagram of the BB section.

[0066] Figure 11 In accordance with Figure 8 A schematic diagram of a cross-section cut by CC.

[0067] Figure 12 In accordance with Figure 8 A cross-sectional schematic diagram of another example implementation of CC sectioning.

[0068] Figure 13 In accordance with Figure 8 A cross-sectional schematic diagram of another example implementation of CC sectioning in the diagram.

[0069] Figure 14 This is a top view of the second and third vias in the array substrate of this disclosure.

[0070] Figure 15 In accordance with Figure 13 A schematic diagram of the DD section in the diagram.

[0071] Figure 16 In accordance with Figure 13 A schematic diagram of the EE section in the diagram.

[0072] Figure 17 This is a cross-sectional schematic diagram of another example embodiment of the array substrate disclosed herein.

[0073] Figure 18 A cross-sectional view of the array substrate according to a first example embodiment of the present disclosure.

[0074] Figure 19 A cross-sectional view of the array substrate according to a second example embodiment of the present disclosure.

[0075] Figure 20 A structure view of a connection structure between a touch electrode and a touch signal line according to a first example embodiment.

[0076] Figure 21 A structure view of a connection structure between a touch electrode and a touch signal line according to a second example embodiment.

[0077] Figure 22 A structure view of a connection structure between a touch electrode and a touch signal line according to a third example embodiment.

[0078] Figure 23 A structure view of a connection structure between a touch electrode and a touch signal line according to a fourth example embodiment.

[0079] Figure 24 A structure view of a connection structure between a touch electrode and a touch signal line according to a fifth example embodiment.

[0080] Figure 25 A top view of the array substrate according to a fourth example embodiment of the present disclosure.

[0081] Figure 26 A cross-sectional view according to a cut along F-F in FIG. 10. Figure 25

[0082] A cross-sectional view according to a cut along G-G in FIG. 11. Figure 27 Figure 25 A structure view of a connection structure between a touch electrode and a touch signal line according to a sixth example embodiment.

[0083] Figure 28 A structure view of a connection structure between a touch electrode and a touch signal line according to a seventh example embodiment.

[0084] Figure 29 A structure view of a connection structure between a touch electrode and a touch signal line according to an eighth example embodiment.

[0085] Figure 30 A structure view of a connection structure between a touch electrode and a touch signal line according to a ninth example embodiment.

[0086] Figure 31 A structure view of a connection structure between a touch electrode and a touch signal line according to a tenth example embodiment.

[0087] ​Figure 32 Structure diagram of a tenth example embodiment of a connection structure between a touch electrode and a touch signal line.

[0088] Figure 33 Structure diagram of an eleventh example embodiment of a connection structure between a touch electrode and a touch signal line.

[0089] Figure 34 Structure diagram of a twelfth example embodiment of a connection structure between a touch electrode and a touch signal line.

[0090] Figure 35 Structure diagram of an array of the present disclosure, in which a touch signal line and a data line are matched in a non-display area.

[0091] Figure 36 Structure diagram of an example embodiment of a touch display device of the present disclosure.

[0092] Explanation of reference numerals:

[0093] 100, array substrate; 200, color film substrate; 300, liquid crystal layer; 400, frame;

[0094] 1, first substrate;

[0095] 2, gate layer; 21, gate; 22, gate line; 23, data lead;

[0096] 3, gate insulating layer; 31, fifth sub-via; 32, sixth sub-via; 33, data via;

[0097] 4, active layer; 41, channel portion; 42, source connection portion; 43, drain connection portion;

[0098] 5, first conductive layer; 51, touch signal line; 51a, touch signal line group; 52, data line; 53, source; 54, drain; 55, touch lead;

[0099] 6, insulating layer group; 601, via; 6a, first insulating layer group; 6a1, first via; 6a2, second via; 6a3, fourth via;

[0100] 61, first insulating layer; 611, first sub-via; 612, second sub-via; 613, seventh sub-via; 62, second insulating layer; 621, third via; 6211, first hole wall; 6212, second hole wall; 63, third insulating layer; 631, third sub-via; 632, fourth sub-via; 633, eighth sub-via;

[0101] 7, second conductive layer; 71, touch electrode;

[0102] 8, third conductive layer; 81, first connection portion; 82, second connection portion; 83, third connection portion; 84, pixel electrode;

[0103] 9, touch control circuit;

[0104] 11, first connection structure; 12, second connection structure; 13, third connection structure; 14, first connection group; 15, second connection group; 16, third connection group;

[0105] X, first direction; Y, second direction. DETAILED DESCRIPTION

[0106] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings. Example embodiments, may, however, be implemented in many different forms and should not be construed as limited to the implementations set forth herein; rather, these implementations are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the specification. It will be understood that, although the terms first, second, third etc. can be used herein to describe various elements / regions, these elements / regions should not be limited by these terms since such elements / regions can be labeled in another suitable manner.

[0107] Although relative terms such as "on", "under", etc. are used herein to describe one component's relationship to another component, these terms are used herein for convenience only and only in the relative sense intended in the examples described in the drawings. It will be understood that if the apparatus of the icon is turned upside down, the component recited as "on" will become the component recited as "under". When a certain structure is "on" another structure, it can mean that the certain structure is formed directly on the other structure, or that the certain structure is "directly" on the other structure, or that the certain structure is "indirectly" on the other structure via another structure.

[0108] The terms "one", "a", "an", "the", and "at least one" are used to indicate that there is one or more of the elements / components / etc.; the term "includes" and the term "including" are used as open-ended terms and do not exclude the presence of additional elements / components / etc.; the term "first", "second", and "third" are used only as labels, and do not limit the quantities or the order of the elements they refer to.

[0109] In the present application, unless specifically defined and limited otherwise, the term "connected" shall be construed broadly, for example, "connected" can be fixed connection, or detachable connection, or integral; can be directly connected, or indirectly connected through intermediate medium. "And / or", is only a description of the relationship between the associated objects, indicating that there can be three kinds of relationships, for example, A and / or B, can represent: A alone, A and B exist at the same time, B alone, these three cases. In addition, the character " / " in this paper generally represents that the front and rear associated objects are a "or" relationship.

[0110] The inventors found that the main cause of the low-frequency flicker is that the reference Figure 1 and Figure 2 As shown in the array substrate 100, a part of the sub-pixels need to be provided with a via hole 601, and the touch electrode 71 and the touch signal line 51 are connected through the via hole 601. The via hole 601 needs to occupy a certain space. For products with high PPI (Pixels Per Inch, pixel density) and small sub-pixels, the sub-pixels provided with the via hole 601 are different from the normal sub-pixels in design, and the common electrode and the pixel electrode 84 need to be cut to a certain extent to place the via hole 601 or the connecting part, thereby causing the Cst (storage capacitance) of the sub-pixel provided with the via hole 601 to be smaller than that of the normal sub-pixel, and causing the voltage holding capacity of the sub-pixel provided with the via hole 601 to be worse than that of the normal sub-pixel, especially in the low-frequency case, low-frequency flicker is prone to occur.

[0111] The example embodiments of the present disclosure provide an array substrate 100, referring to Figures 1-35As shown, the array substrate 100 can include a first substrate substrate 1, a first conductive layer 5, an insulating layer group 6, and a second conductive layer 7; the first conductive layer 5 is arranged on one side of the first substrate substrate 1, and the first conductive layer 5 includes a touch signal line 51 extending along a first direction X; the insulating layer group 6 is arranged on the side of the first conductive layer 5 away from the first substrate substrate 1, and the insulating layer group 6 includes a first insulating layer group 6a and a second insulating layer 62 arranged in a stack, a plurality of first vias 6a1 and a plurality of second vias 6a2 are arranged on the first insulating layer group 6a, and a plurality of third vias 621 are arranged on the second insulating layer 62; the second conductive layer 7 is arranged on the side of at least one layer of the first insulating layer group 6a and the second insulating layer 62 away from the first substrate substrate 1, and the second conductive layer 7 includes a touch electrode 71 connected to the touch signal line 51 through the first via 6a1 and the third via 621 in communication and the second via 6a2 and the third via 621 in communication; wherein the at least one first via 6a1 and the at least one second via 6a2 are in communication with the same touch signal line 51, and the third via 621 has a first hole wall 6211 and a second hole wall 6212 arranged opposite in the first direction X, and in the first direction X, the first via 6a1 is arranged closer to the first hole wall 6211 relative to the second hole wall 6212, and the second via 6a2 is arranged closer to the second hole wall 6212 relative to the first hole wall 6211.

[0112] The array substrate 100 of the present disclosure, on the one hand, for the first via 6a1, the overlapping edge margin of the side of the first via 6a1 close to the first hole wall 6211 with the third via 621 can not be considered, so that the first via 6a1 and the third via 621 can be arranged smaller; for the second via 6a2, the overlapping edge margin of the side of the second via 6a2 close to the second hole wall 6212 with the third via 621 can not be considered, so that the second via 6a2 and the third via 621 can be arranged smaller, that is, the occupied area of the first via 6a1, the second via 6a2 and the third via 621 can be reduced, so as to increase the setting space of the capacitance of the sub-pixel, so as to ensure the voltage holding ability of the sub-pixel and avoid the occurrence of low-frequency flicker.

[0113] In another aspect, even if the alignment process of the mask plate deviates during the patterning process, when offsetting towards the first hole wall 6211, although the first via hole 6a1 and the third via hole 621 can be connected poorly, the second via hole 6a2 is offset towards the center of the third via hole 621, thereby ensuring the connection between the second via hole 6a2 and the third via hole 621, and ensuring the connection between the touch electrode 71 and the touch signal line 51; similarly, when offsetting towards the second hole wall 6212, although the second via hole 6a2 and the third via hole 621 can be connected poorly, the first via hole 6a1 is offset towards the center of the third via hole 621, thereby ensuring the connection between the first via hole 6a1 and the third via hole 621, and ensuring the connection between the touch electrode 71 and the touch signal line 51; moreover, the offset is in the first direction X, and the touch signal line 51 extends along the first direction X, so that no matter how the offset is, it will not deviate from the touch signal line 51.

[0114] Referring to Figure 1 , Figure 5 and Figure 6 , the multi-layer stack cannot see the structure of each layer, Figure 5 In Figure 5 , the touch electrode 71 is not shown, and the touch electrode 71 is basically arranged in an entire layer. The array substrate 100 can include a plurality of touch electrodes 71 arranged in an array and a plurality of touch signal lines 51. Each touch electrode 71 is electrically connected to a corresponding touch signal line 51 through a via hole 601, thereby being electrically connected to the touch control circuit 9 through the touch signal line 51.

[0115] Referring to Figure 2 , the array substrate 100 can include a plurality of pixel regions P Figure 2 , four pixel regions P1, P2, P3 and P4 are shown for example), each pixel region P includes three sub-pixel regions (see SP1, SP2, SP3), and each sub-pixel region is defined by adjacent gate lines 22 Figure 2 , two gate lines 22 are shown for example) and adjacent data lines 52 Figure 2 , 521 to 526 are shown for example) intersecting each other.

[0116] The array substrate 100 further includes a plurality of touch signal lines 51 Figure 2The plurality of touch signal lines 51 extend along the first direction X and are arranged in sequence along the second direction Y (as shown in 511-512), and each touch signal line 51 passes through an opening region of the sub-pixel area SP which is not shielded by a black matrix layer in the display device. A via hole 601 is arranged at the sub-pixel area SP3 of the pixel area P1, and the touch electrode 71 and the touch signal line 51 are connected through the via hole 601, which causes the Cst (storage capacitance) of the sub-pixel area SP3 to be smaller than the Cst (storage capacitance) of the normal sub-pixel areas SP1 and SP2, and causes the voltage retention capability of the sub-pixel area SP3 to be poorer than that of the normal sub-pixel, which is prone to low-frequency flicker, especially in the case of low frequency.

[0117] In the example embodiment, the first substrate 1 can be a glass substrate; of course, in some other example embodiments of the present disclosure, the first substrate 1 can also be quartz or the like; the first substrate 1 can further include an insulating material layer, which can be arranged on one side of the glass substrate, and the insulating material layer can be a resin material such as polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and polyethylene naphthalate.

[0118] In the example embodiment, referring to Figure 3 , a gate layer 2 can be arranged on one side of the first substrate 1, and the gate layer 2 can include a plurality of gate lines 22 and a plurality of gates 21. The gate lines 22 can extend along the second direction Y, and the plurality of gates 21 arranged along the second direction Y can be connected to the same gate line 22, or a part of the gate line 22 can serve as a gate 21.

[0119] In the example embodiment, referring to Figure 3 , a gate insulating layer 3 is arranged on the side of the gate layer 2 away from the first substrate 1. An active layer 4 is arranged on the side of the gate insulating layer 3 away from the first substrate 1, and the active layer 4 can include a channel portion 41 and conductor portions arranged at both ends of the channel portion 41, one of the two conductor portions being a source connection portion 42 and the other being a drain connection portion 43. The channel portion 41 is arranged on the side of the gate line 22 away from the first substrate 1, i.e., a part of the gate line 22 opposite the channel portion 41 serves as a gate 21.

[0120] In the example embodiment, referring to Figure 3 , a first conductive layer 5 is arranged on the side of the active layer 4 away from the first substrate 1, and the first conductive layer 5 can include a source 53, a drain 54, a data line 52, and a touch signal line 51. The touch signal line 51 extends along the first direction X, and the data line 52 extends along the first direction X, and the first direction X intersects the second direction Y, e.g., the first direction X can be perpendicular to the second direction Y.

[0121] The source 53 is connected to the data line 52 and to the source connection portion 42, thereby connecting the source connection portion 42 and the data line 52 through the source 53; the drain 54 is connected to the subsequently formed pixel electrode and to the drain connection portion 43, thereby connecting the drain connection portion 43 and the pixel electrode through the drain 54. The gate 21, the channel portion 41, the source 53, the drain 54, and the source connection portion 42 and the drain connection portion 43 form a switching unit, which is a thin-film transistor.

[0122] It should be noted that the thin-film transistor described in this specification is a bottom-gate thin-film transistor. In other exemplary embodiments of this disclosure, the thin-film transistor may also be a top-gate or dual-gate type, and its specific structure will not be described in detail here. Moreover, in cases where thin-film transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source 53" and "drain 54" are sometimes interchanged. Therefore, in this specification, the "source 53" and "drain 54" can be interchanged.

[0123] In this example implementation, refer to Figure 3 As shown, an insulating layer group 6 is disposed on the side of the first conductive layer 5 away from the first substrate 1. The insulating layer group 6 may include a first insulating layer group 6a and a second insulating layer 62. The material of the first insulating layer group 6a may include inorganic materials, such as silicon nitride, silicon oxide, etc. The material of the second insulating layer 62 may include organic materials, such as polyimide, polycarbonate, polyacrylate, etc. The material of the second insulating layer 62 may be photoresist. When forming the second sub-via 612 on the second insulating layer 62, only exposure and development are required, saving process steps; while when forming the second sub-via 612 on other film layers, after exposure and development, it is necessary to etch the other film layers using photoresist as a mask.

[0124] Of course, in some other exemplary embodiments of this disclosure, the first insulating layer group 6a may also include organic materials, and the second insulating layer 62 may also include inorganic materials.

[0125] Reference Figure 4As shown, the first insulating layer group 6a and the second insulating layer 62 are not shown, only the first via hole 6a1, the second via hole 6a2 and the third via hole 621 are shown; the first insulating layer group 6a is provided with a plurality of first via holes 6a1 and a plurality of second via holes 6a2, at least one first via hole 6a1 and at least one second via hole 6a2 are communicated to the same touch signal line 51, that is, the orthographic projection of at least one first via hole 6a1 and at least one second via hole 6a2 on the substrate is overlapped with the orthographic projection of the same touch signal line 51 on the substrate; it can also be said that the same touch signal line 51 has at least two parts not covered by the first insulating layer group 6a; for example, one first via hole 6a1 and one second via hole 6a2 can be communicated to the same touch signal line 51, or two or more first via holes 6a1 and two or more second via holes 6a2 can be communicated to the same touch signal line 51.

[0126] Specifically, referring to Figure 3 As shown, the first insulating layer group 6a can include a first insulating layer 61, which is arranged on the side of the first conductive layer 5 away from the first substrate 1. The material of the first insulating layer 61 can be an inorganic material, for example, it can be silicon nitride, silicon oxide, etc. The first insulating layer 61 is provided with a plurality of first sub-via holes 611 and a plurality of second sub-via holes 612.

[0127] In the present example embodiment, referring to Figure 3 As shown, the second insulating layer 62 is arranged on the side of the first insulating layer 61 away from the first substrate 1, and the second insulating layer 62 is provided with a plurality of third via holes 621, the third via holes 621 have a first hole wall 6211 and a second hole wall 6212 arranged opposite in the first direction X.

[0128] The second conductive layer 7 is arranged on the side of at least one layer of the first insulating layer group 6a and the second insulating layer 62 away from the first substrate 1, specifically, the second conductive layer 7 is arranged on the side of the second insulating layer 62 away from the first substrate 1, and the second conductive layer 7 can include a touch electrode 71, referring to Figure 4 As shown, the touch electrode 71 is connected to the touch signal line 51 through the communicated first via hole 6a1 and the third via hole 621, and the communicated second via hole 6a2 and the third via hole 621.

[0129] The material of the second conductive layer 7 can be a transparent conductive material, specifically, the material of the first conductive layer 5 can be ITO (indium tin oxide), IZO (indium zinc oxide), etc.

[0130] Referring to Figure 8 , Figure 9 and Figure 14As shown, the touch electrode 71 extends to one end of the second direction Y within the third via hole 621, that is, the touch electrode 71 does not occupy the whole of the third via hole 621, but only occupies one end of the second direction Y of the third via hole 621, and the other part of the second direction Y of the third via hole 621 is for exposing the touch signal line 51. While the first via hole 6a1 and the second via hole 6a2 are offset in the first direction X, as long as the first via hole 6a1 is in communication with the third via hole 621 or the second via hole 6a2 is in communication with the third via hole 621, the connection of the touch electrode 71 and the touch signal line 51 can be ensured.

[0131] The touch electrode 71 can be multiplexed as a common electrode. Specifically, the touch electrode 71 can be time-multiplexed as a common electrode, that is, in a first time period, the touch signal line 51 is loaded with a touch signal, and the touch electrode 71 is used as a touch electrode 71 to realize a touch function; in a second time period, the touch signal line 51 is loaded with a common voltage, and the touch electrode 71 is used as a common electrode to realize a display function.

[0132] Referring to Figure 3 As shown, the first insulating layer group 6a can further include a third insulating layer 63. Specifically, the third insulating layer 63 is arranged on the side of the second conductive layer 7 away from the first substrate 1, that is, the second conductive layer 7 is arranged between the second insulating layer 62 and the third insulating layer 63. The material of the third insulating layer 63 can be an inorganic material, for example, silicon nitride, silicon oxide, etc. A plurality of third sub-via holes 631 and a plurality of fourth sub-via holes 632 are arranged on the third insulating layer 63.

[0133] The first via hole 6a1 can include a first sub-via hole 611 and a third sub-via hole 631, and the first sub-via hole 611 and the third sub-via hole 631 are in communication with each other, that is, the third sub-via hole 631 is communicated to the first sub-via hole 611. The second via hole 6a2 can include a second sub-via hole 612 and a fourth sub-via hole 632, and the second sub-via hole 612 and the fourth sub-via hole 632 are in communication with each other, that is, the fourth sub-via hole 632 is communicated to the second sub-via hole 612, so that at least one third sub-via hole 631 and at least one fourth sub-via hole 632 are communicated to the same touch signal line 51. Moreover, at least one third sub-via hole 631 and at least one fourth sub-via hole 632 are communicated to the same touch electrode 71, that is, the same touch electrode 71 is exposed at the position of at least one third sub-via hole 631 and at least one fourth sub-via hole 632 without being covered by the third insulating layer 63.

[0134] Of course, in some other example embodiments of the present disclosure, the first insulating layer group 6a can only include the first insulating layer 61, in which case the second conductive layer 7 is arranged on the side of the second insulating layer 62 facing away from the first substrate 1, the first via hole 6a1 can only include the first sub-via hole 611, and the second via hole 6a2 can only include the second sub-via hole 612; the first insulating layer group 6a can only include the third insulating layer 63, in which case the first via hole 6a1 can only include the third sub-via hole 631, and the second via hole 6a2 can only include the fourth sub-via hole 632.

[0135] Since the first via hole 6a1 and the second via hole 6a2 on the first insulating layer group 6a and the third via hole 621 on the second insulating layer 62 are formed by two different patterning processes respectively, due to the deviation of the alignment process of the mask plate during the two patterning processes, the deviation range is between -2 microns and +2 microns (positive and negative represent the direction), the third via hole 621 needs to be set larger, so that the periphery of the third via hole 621 and the periphery of the first via hole 6a1 and the periphery of the second via hole 6a2 form an overlay margin, so as to ensure that the first via hole 6a1 and the second via hole 6a2 formed later can be connected to the third via hole 621, so as to realize the electrical connection of the touch electrode 71 and the touch signal line 51.

[0136] In the present example embodiment, in the first direction, the first via hole 6a1 is arranged closer to the first hole wall 6211 than the second hole wall 6212, so that the first via hole 6a1 is located on one side of the third via hole 621 in the first direction X; the second via hole 6a2 is arranged closer to the second hole wall 6212 than the first hole wall 6211, so that the second via hole 6a2 is located on the other side of the third via hole 621 in the first direction X; that is, the first via hole 6a1 and the second via hole 6a2 are arranged offset from the center of the third via hole 621.

[0137] In this way, for the first via hole 6a1, the overlay margin of the first via hole 6a1 on the side close to the first hole wall 6211 and the third via hole 621 can not be considered, so that the first via hole 6a1 and the third via hole 621 can be arranged smaller; for the second via hole 6a2, the overlay margin of the second via hole 6a2 on the side close to the second hole wall 6212 and the third via hole 621 can not be considered, so that the second via hole 6a2 and the third via hole 621 can be arranged smaller, thereby increasing the setting space of the capacitance of the sub-pixel, to ensure the voltage holding capability of the sub-pixel and avoid the occurrence of low-frequency flicker defects.

[0138] Furthermore, since the first via 6a1 and the second via 6a2 are located at opposite ends of the third via 621, even if the alignment process of the mask plate deviates during the patterning process, and the second via 6a2 shifts towards the center of the third via 6211 when it shifts towards the first hole wall 6211, although the first via 6a1 and the third via 621 may have poor communication, this causes the second via 6a2 to shift towards the center of the third via 621, thereby ensuring the communication between the second via 6a2 and the third via 621, and thus ensuring the connection between the touch electrode 71 and the touch signal line 51. Similarly, when shifting towards the second hole wall 6212, although the second via 6a2 and the third via 621 may have poor communication, this causes the first via 6a1 to shift towards the center of the third via 621, thereby ensuring the communication between the first via 6a1 and the third via 621, and thus ensuring the connection between the touch electrode 71 and the touch signal line 51.

[0139] In this example embodiment, a third conductive layer 8 is provided on the side of the third insulating layer 63 facing away from the first substrate 1. The material of the third conductive layer 8 can be a transparent conductive material. Specifically, the material of the first conductive layer 5 can be ITO (indium tin oxide), IZO (indium zinc oxide), etc. (Refer to...) Figure 7 , Figure 8 and Figure 14 As shown, the third conductive layer 8 may include a pixel electrode 84, a first connecting portion 81 and a second connecting portion 82, and the pixel electrode 84, the first connecting portion 81 and the second connecting portion 82 are spaced apart, that is, there is no connection between the pixel electrode 84, the first connecting portion 81 and the second connecting portion 82.

[0140] The first connecting part 81 connects the touch control electrode 71 and the touch signal line 51 through the third via 621 and the first via 6a1, and the second connecting part 82 connects the touch control electrode 71 and the touch signal line 51 through the third via 621 and the second via 6a2. Thus, the touch control electrode 71 and the touch signal line 51 are connected as a single unit through the first connecting part 81 and the second connecting part 82, and touch signals can be transmitted to the touch electrode 71 through the touch signal line 51.

[0141] This configuration reduces the opening area of ​​the first via 6a1, the second via 6a2, and the third via 621, thereby reducing the area of ​​the first connecting portion 81 and the second connecting portion 82. This increases the area of ​​the pixel electrode 84 and the Cst of the sub-pixel with the via, ensuring the voltage retention capability of the sub-pixel with the via and preventing low-frequency flicker.

[0142] Reference Figures 8-13As shown, due to the shielding of the first insulating layer 61 by the second insulating layer 62 and the touch electrode 71 when the first sub-via hole 611 is formed, the orthographic projection of the first sub-via hole 611 on the first substrate 1 is located within the orthographic projection of the third via hole 621 on the first substrate 1, specifically, the area of the orthographic projection of the first sub-via hole 611 on the first substrate 1 is smaller than the area of the orthographic projection of the third via hole 621 on the first substrate 1, and the orthographic projection of the third via hole 621 on the first substrate 1 completely covers the orthographic projection of the first sub-via hole 611 on the first substrate 1.

[0143] The orthographic projection of the third sub-via hole 631 on the first substrate 1 at least partially overlaps the orthographic projection of the third via hole 621 on the first substrate 1.

[0144] For example, referring to Figs. 6a and 6b, the orthographic projection of the third sub-via hole 631 on the first substrate 1 can be located within the orthographic projection of the third via hole 621 on the first substrate 1, and one side edge of the orthographic projection of the third sub-via hole 631 on the first substrate 1 coincides with the orthographic projection of the first hole wall 6211 of the third via hole 621 on the first substrate 1, so that at the first via hole 6a1 and the third via hole 621, the third insulating layer 63 does not cover the first hole wall 6211, and the third insulating layer 63 covers the second hole wall 6212. Figure 10 Figure 11 For example, referring to Figs. 6a and 6b, the orthographic projection of the third sub-via hole 631 on the first substrate 1 can be located within the orthographic projection of the third via hole 621 on the first substrate 1, and one side edge of the orthographic projection of the third sub-via hole 631 on the first substrate 1 coincides with the orthographic projection of the first hole wall 6211 of the third via hole 621 on the first substrate 1, so that at the first via hole 6a1 and the third via hole 621, the third insulating layer 63 does not cover the first hole wall 6211, and the third insulating layer 63 covers the second hole wall 6212.

[0145] For example, referring to Figs. 6a and 6b, the orthographic projection of the third sub-via hole 631 on the first substrate 1 can be located within the orthographic projection of the third via hole 621 on the first substrate 1, and one side edge of the orthographic projection of the third sub-via hole 631 on the first substrate 1 coincides with the orthographic projection of the first hole wall 6211 of the third via hole 621 on the first substrate 1, so that at the first via hole 6a1 and the third via hole 621, the third insulating layer 63 does not cover the first hole wall 6211, and the third insulating layer 63 covers the second hole wall 6212. Figure 12 For example, referring to Figs. 6a and 6b, the orthographic projection of the third sub-via hole 631 on the first substrate 1 can be located within the orthographic projection of the third via hole 621 on the first substrate 1, and one side edge of the orthographic projection of the third sub-via hole 631 on the first substrate 1 coincides with the orthographic projection of the first hole wall 6211 of the third via hole 621 on the first substrate 1, so that at the first via hole 6a1 and the third via hole 621, the third insulating layer 63 does not cover the first hole wall 6211, and the third insulating layer 63 covers the second hole wall 6212.

[0146] Figure 13 For example, referring to Figs. 6a and 6b, the orthographic projection of the third sub-via hole 631 on the first substrate 1 can be located within the orthographic projection of the third via hole 621 on the first substrate 1, and one side edge of the orthographic projection of the third sub-via hole 631 on the first substrate 1 coincides with the orthographic projection of the first hole wall 6211 of the third via hole 621 on the first substrate 1, so that at the first via hole 6a1 and the third via hole 621, the third insulating layer 63 does not cover the first hole wall 6211, and the third insulating layer 63 covers the second hole wall 6212.

[0147] In addition, referring to Figs. 6a and 6b, the orthographic projection of the third sub-via hole 631 on the first substrate 1 can be located within the orthographic projection of the third via hole 621 on the first substrate 1, so that at the first via hole 6a1 and the third via hole 621, the third insulating layer 63 covers the hole wall of the third via hole 621, that is, the third insulating layer 63 almost completely covers the hole wall of the third via hole 621. Figure 9 ​​As shown, in the above example embodiment, at the first via 6a1 and the third via 621, the third insulating layer 63 covers the two sidewalls of the third via 621 that are disposed opposite each other in the second direction Y.

[0148] Reference Figure 9 , Figures 14-16 As shown, since the second insulating layer 62 and the touch electrode 71 can block the first insulating layer 61 when the second sub-via 612 is formed, the orthogonal projection of the second sub-via 612 on the first substrate 1 is located within the orthogonal projection of the third via 621 on the first substrate 1. Specifically, the area of ​​the orthogonal projection of the second sub-via 612 on the first substrate 1 is smaller than the area of ​​the orthogonal projection of the third via 621 on the first substrate 1, and the orthogonal projection of the third via 621 on the first substrate 1 completely covers the orthogonal projection of the second sub-via 612 on the first substrate 1.

[0149] The orthographic projection of the fourth sub-via 632 on the first substrate 1 at least partially overlaps with the orthographic projection of the third via 621 on the first substrate 1.

[0150] For example, refer to Figure 15 and Figure 16 As shown, the orthographic projection of the fourth sub-via 632 on the first substrate 1 may be located within the orthographic projection of the third via 621 on the first substrate 1, and one side edge of the orthographic projection of the fourth sub-via 632 on the first substrate 1 may coincide with the orthographic projection of the second hole wall 6212 of the third via 621 on the first substrate 1, such that at the second via 6a12 and the third via 621, the third insulating layer 63 does not cover the second hole wall 6212, and the third insulating layer 63 covers the first hole wall 6211.

[0151] When forming the second via 6a2, if the mask plate is offset more towards the first hole wall 6211, the orthogonal projection of the fourth sub-via 632 on the first substrate 1 may be located within the orthogonal projection of the third via 621 on the first substrate 1, so that at the second via 6a12 and the third via 621, the third insulating layer 63 covers the hole wall of the third via 621, that is, the third insulating layer 63 almost completely covers the surrounding hole walls of the third via 621.

[0152] When forming the second via 6a2, if the mask plate is offset more towards the second hole wall 6212, a portion of the orthographic projection of the fourth sub-via 632 on the first substrate 1 may overlap with a portion of the orthographic projection of the third via 621 on the first substrate 1. This results in the third insulating layer 63 not covering the second hole wall 6212 and not covering a portion of the side of the second insulating layer facing away from the first substrate 1 near the second hole wall 6212 at the second via 6a12 and the third via 621, and the third insulating layer 63 covering the first hole wall 6211.

[0153] Additionally, refer to Figure 9 As shown, in the above example embodiment, at the second via 6a12 and the third via 621, the third insulating layer 63 covers the two sidewalls of the third via 621 that are disposed opposite each other in the second direction Y.

[0154] In addition, in some other exemplary embodiments of this disclosure, reference is made to... Figure 17 As shown, the second conductive layer 7 is disposed on the side of the third insulating layer 63 facing away from the first substrate 1; the touch electrode 71 can be directly connected to the touch signal line 51 through the connected first via 6a1 and third via 621 and the connected second via 6a2 and third via 621, without the need for the first connecting portion 81 and the second connecting portion 82. In this case, the array substrate may also include a third conductive layer 8, which is disposed between the second insulating layer 62 and the third insulating layer 63, and includes a pixel electrode 84. Since the connection between the touch electrode 71 and the touch signal line 51 also requires the connection through the connected first via 6a1 and third via 621 and the connected second via 6a2 and third via 621, the above-mentioned arrangement of the first via 6a1, second via 6a2 and third via 621 is also applicable to this example embodiment, and the specific structure will not be described here.

[0155] In other exemplary embodiments of this disclosure, reference is made to Figure 18 and Figure 19 As shown, the first conductive layer 5 may further include a gate 21 and a gate line 22, meaning the first conductive layer 5 is the gate layer 2. The touch signal line 51 and the gate line 22 are disposed on the same layer to avoid the touch signal line 51 and the gate line 22 crossing. The gate line 22 also extends along the first direction X and is spaced apart from the touch signal line 51. The gate 21 is connected to the gate line 22, and its specific structure will not be described in detail here.

[0156] In this case, the first insulating layer group 6a can further include a gate insulating layer 3 disposed on a side of the first conductive layer 5 facing away from the first substrate 1, and a plurality of fifth sub-vias 31 and a plurality of sixth sub-vias 32 are disposed on the gate insulating layer 3; the plurality of fifth sub-vias 31 and the plurality of sixth sub-vias 32 are formed by the same patterning process as the first sub-via 611 and the second sub-via 612 on the first insulating layer 61 and the third sub-via 631 and the fourth sub-via 632 on the third insulating layer 63, so that the first via 6a1 can include the first sub-via 611, the third sub-via 631, and the fifth sub-via 31 that are in communication with each other, and the second via 6a2 can include the second sub-via 612, the fourth sub-via 632, and the sixth sub-via 32 that are in communication with each other.

[0157] The fifth sub-via 31 has a projection on the first substrate 1 that is located within a projection of the third via 621 on the first substrate 1, and specifically, an area of the projection of the fifth sub-via 31 on the first substrate 1 is less than an area of the projection of the third via 621 on the first substrate 1, and the projection of the third via 621 on the first substrate 1 completely covers the projection of the fifth sub-via 31 on the first substrate 1.

[0158] The sixth sub-via 32 has a projection on the first substrate 1 that is located within a projection of the third via 621 on the first substrate 1, and specifically, an area of the projection of the sixth sub-via 32 on the first substrate 1 is less than an area of the projection of the third via 621 on the first substrate 1, and the projection of the third via 621 on the first substrate 1 completely covers the projection of the sixth sub-via 32 on the first substrate 1.

[0159] In addition, it should be noted that the present example embodiment limits the touch signal line 51 to be located in the gate layer 2, and therefore, other structures in the above example embodiments can be combined as long as they do not conflict with the present example embodiment, which will not be described one by one here.

[0160] In the present example embodiment, in the second direction Y, a distance between an edge line of the projection of the third sub-via 631 on the first substrate 1 and an edge line of the projection of the third via 621 on the first substrate 1 is greater than or equal to 1 micrometer and less than or equal to 2.5 micrometers, for example, the distance between the edge line of the projection of the third sub-via 631 on the first substrate 1 and the edge line of the projection of the third via 621 on the first substrate 1 can be 1.2 micrometers, 1.5 micrometers, 1.7 micrometers, 2 micrometers, 2.3 micrometers, and the like.

[0161] If the distance between the edge of the orthographic projection of the third sub-via 631 on the first substrate 1 and the edge of the orthographic projection of the third via 621 on the first substrate 1 is too small, it will increase the difficulty of the alignment process and thus increase the manufacturing cost.

[0162] If the distance between the edge of the orthographic projection of the third sub-via 631 on the first substrate 1 and the edge of the orthographic projection of the third via 621 on the first substrate 1 is too large, the third via 621 needs to be enlarged, which is not conducive to the layout of other structures on the array substrate 100. Alternatively, the third sub-via 631 needs to be reduced, which may easily lead to the third sub-via 631 and the third via 621 being unable to communicate.

[0163] The above-mentioned numerical range will not increase the difficulty of the alignment process or the manufacturing cost; moreover, it can meet the alignment deviation requirements of the two patterning processes and ensure that the third sub-via 631 and the third via 621 are connected.

[0164] It should be noted that, referring to Figure 9 As shown, since the first sub-via 611 and the third sub-via 631 are formed through the same patterning process, and one end of the first sub-via 611 in the second direction Y is blocked by the touch electrode 71 while the other end is not blocked; therefore, in the second direction Y, the distance between the corresponding edge lines of the orthographic projection of the hole wall of the first sub-via 611 near the touch electrode 71 on the first substrate 1 and the orthographic projection of the third sub-via 621 on the first substrate 1 is the length of the touch electrode 71 extending into the third sub-via 621. The distance between the corresponding edge lines of the orthographic projection of the hole wall of the first sub-via 611 away from the touch electrode 71 on the first substrate 1 and the orthographic projection of the third sub-via 621 on the first substrate 1 is also greater than or equal to 1 micrometer and less than or equal to 2.5 micrometers.

[0165] In this example embodiment, in the second direction Y, the distance between the edge of the orthographic projection of the fourth sub-via 632 on the first substrate 1 and the edge of the orthographic projection of the third via 621 on the first substrate 1 is greater than or equal to 1 micrometer and less than or equal to 2.5 micrometers. For example, the distance between the edge of the orthographic projection of the fourth sub-via 632 on the first substrate 1 and the edge of the orthographic projection of the third via 621 on the first substrate 1 can be 1.2 micrometers, 1.5 micrometers, 1.7 micrometers, 2 micrometers, 2.3 micrometers, etc.

[0166] If the distance between the edge of the orthographic projection of the fourth sub-via 632 on the first substrate 1 and the edge of the orthographic projection of the third via 621 on the first substrate 1 is too small, it will increase the difficulty of the alignment process and thus increase the manufacturing cost.

[0167] If the distance between the edge of the orthographic projection of the fourth sub-via 632 on the first substrate 1 and the edge of the orthographic projection of the third via 621 on the first substrate 1 is too large, the third via 621 needs to be enlarged, which is not conducive to the layout of other structures on the array substrate 100. Alternatively, the fourth sub-via 632 needs to be reduced, which may result in the fourth sub-via 632 and the third via 621 being unable to communicate.

[0168] The above-mentioned numerical range will not increase the difficulty of the alignment process or the manufacturing cost; moreover, it can meet the alignment deviation requirements of the two patterning processes and ensure that the fourth sub-via 632 and the third via 621 are connected.

[0169] It should be noted that, referring to Figure 9 As shown, since the second sub-via 612 and the third sub-via 631 are formed through the same patterning process, and one end of the second sub-via 612 in the second direction Y is blocked by the touch electrode 71 while the other end is not blocked; therefore, in the second direction Y, the distance between the corresponding edge lines of the orthographic projection of the second sub-via 612 near the touch electrode 71 on the first substrate 1 and the orthographic projection of the third sub-via 621 on the first substrate 1 is the length of the touch electrode 71 extending into the third sub-via 621. The distance between the corresponding edge lines of the orthographic projection of the second sub-via 612 away from the touch electrode 71 on the first substrate 1 and the orthographic projection of the third sub-via 621 on the first substrate 1 is also greater than or equal to 1 micrometer and less than or equal to 2.5 micrometers.

[0170] In this example embodiment, in the first direction X, the distance between the orthographic projection of the first via 6a1 near the first hole wall 6211 on the first substrate 1 and the orthographic projection of the first hole wall 6211 on the first substrate 1 is less than or equal to 0.5 micrometers. For example, the distance between the orthographic projection of the first via 6a1 near the first hole wall 6211 on the first substrate 1 and the orthographic projection of the first hole wall 6211 on the first substrate 1 can be 0.05 micrometers, 0.1 micrometers, 0.15 micrometers, 0.2 micrometers, 0.25 micrometers, 0.3 micrometers, 0.35 micrometers, 0.4 micrometers, 0.45 micrometers, etc.

[0171] If the distance between the orthographic projection of the first via 6a1 near the first hole wall 6211 on the first substrate 1 and the orthographic projection of the first hole wall 6211 on the first substrate 1 is too large, the first via 6a1 will deviate too far from the center of the third via 621, or the first via 6a1 will not deviate much from the center of the third via 621. This will result in the first via 6a1 being set too large, failing to achieve the purpose of reducing the first via 6a1 to reduce the first connection portion 81 and increase the pixel electrode 84, and low-frequency flickering will still occur.

[0172] It should be noted that, with reference to Figure 12 It should be noted that, with reference to

[0173] The distance between the orthographic projection of the hole wall of the first via 6a1 close to the second hole wall 6212 on the first substrate substrate 1 and the orthographic projection of the second hole wall 6212 on the first substrate substrate 1 is greater than or equal to 1 microns and less than or equal to 2.5 microns, for example, the distance between the orthographic projection of the hole wall of the first via 6a1 close to the second hole wall 6212 on the first substrate substrate 1 and the orthographic projection of the second hole wall 6212 on the first substrate substrate 1 can be 1.2 microns, 1.5 microns, 1.7 microns, 2 microns, 2.3 microns, etc.

[0174] The first via 6a1 and the second via 6a2 on the first insulating layer group 6a and the third via 621 on the second insulating layer 62 are respectively formed by two different patterning processes; due to the deviation of the alignment process of the mask plate during the two patterning processes, the deviation range is between -2 microns and +2 microns (positive and negative represent the direction), the third via 621 formed first needs to be set larger, so that the first via 6a1 and the second via 6a2 formed later can be connected to the third via 621.

[0175] If the distance between the orthographic projection of the hole wall of the first via 6a1 close to the second hole wall 6212 on the first substrate substrate 1 and the orthographic projection of the second hole wall 6212 on the first substrate substrate 1 is too small, it will increase the difficulty of the alignment process, thereby increasing the preparation cost.

[0176] If the distance between the orthographic projection of the hole wall of the first via 6a1 close to the second hole wall 6212 on the first substrate substrate 1 and the orthographic projection of the second hole wall 6212 on the first substrate substrate 1 is too large, the third via 621 needs to be increased, which is not conducive to the layout of other structures on the array substrate 100, or the first via 6a1 needs to be reduced, which is easy to cause the first via 6a1 and the third via 621 cannot be connected.

[0177] The above numerical range does not increase the difficulty of the alignment process and does not increase the preparation cost, and can meet the requirements of the alignment deviation of the two patterning processes, and can ensure the communication of the first via hole 6a1 and the third via hole 621.

[0178] It should be noted that since the hole wall of the first sub-via hole 611, the hole wall of the third sub-via hole 631, the first hole wall 6211 and the second hole wall 6212 are generally all inclined, the orthogonal projection of the hole wall of the third sub-via hole 631, the first hole wall 6211 and the second hole wall 6212 on the first substrate 1 has a certain width; therefore, the hole wall of the third sub-via hole 631 close to the first hole wall 6211 and the first hole wall 6211 need to be in the corresponding position, and the hole wall of the third sub-via hole 631 close to the second hole wall 6212 and the second hole wall 6212 also need to be in the corresponding position; for example, they can all be away from the edge of the first substrate 1, or they can all be close to the edge of the first substrate 1.

[0179] In the present example embodiment, in the first direction X, the distance between the orthogonal projection of the hole wall of the second via hole 6a2 close to the second hole wall 6212 on the first substrate 1 and the orthogonal projection of the second hole wall 6212 on the first substrate 1 is less than or equal to 0.5 microns, for example, the distance between the orthogonal projection of the hole wall of the second via hole 6a2 close to the second hole wall 6212 on the first substrate 1 and the orthogonal projection of the second hole wall 6212 on the first substrate 1 can be 0.05 microns, 0.1 microns, 0.15 microns, 0.2 microns, 0.25 microns, 0.3 microns, 0.35 microns, 0.4 microns, 0.45 microns, etc.

[0180] If the distance between the orthogonal projection of the hole wall of the second via hole 6a2 close to the second hole wall 6212 on the first substrate 1 and the orthogonal projection of the second hole wall 6212 on the first substrate 1 is too large, the second via hole 6a2 will deviate too far from the center of the third via hole 621 or the second via hole 6a2 will not deviate from the center of the third via hole 621, resulting in a larger second via hole 6a2, which cannot achieve the purpose of reducing the second via hole 6a2 to reduce the second connecting portion 82 while increasing the pixel electrode 84, and low-frequency flicker will still occur.

[0181] It should be noted that, since the second via hole 6a2 can include the second sub-via hole 612 and the fourth sub-via hole 632, in the case where a part of the second via hole 6a2 is offset to the outside of the third via hole 621, the second sub-via hole 612 will not be offset to the outside of the third via hole 621 due to the shielding of the second insulating layer 62, in which case, the hole wall of the second sub-via hole 612 close to the second hole wall 6212 is substantially flush with the second hole wall 6212, and the above numerical range can refer to the distance between the orthographic projection of the hole wall of the fourth sub-via hole 632 close to the second hole wall 6212 on the first substrate 1 and the orthographic projection of the second hole wall 6212 on the first substrate 1.

[0182] The distance between the orthographic projection of the hole wall of the second via hole 6a2 close to the first hole wall 6211 on the first substrate 1 and the orthographic projection of the first hole wall 6211 on the first substrate 1 is greater than or equal to 1 microns and less than or equal to 2.5 microns, for example, the distance between the orthographic projection of the hole wall of the second via hole 6a2 close to the first hole wall 6211 on the first substrate 1 and the orthographic projection of the first hole wall 6211 on the first substrate 1 can be 1.2 microns, 1.5 microns, 1.7 microns, 2 microns, 2.3 microns, etc.

[0183] If the distance between the orthographic projection of the hole wall of the second via hole 6a2 close to the first hole wall 6211 on the first substrate 1 and the orthographic projection of the first hole wall 6211 on the first substrate 1 is too small, the difficulty of the alignment process will be increased, thereby increasing the preparation cost.

[0184] If the distance between the orthographic projection of the hole wall of the second via hole 6a2 close to the first hole wall 6211 on the first substrate 1 and the orthographic projection of the first hole wall 6211 on the first substrate 1 is too large, the third via hole 621 needs to be increased, which is not conducive to the layout of other structures on the array substrate 100, or the second via hole 6a2 needs to be reduced, which is easy to cause the second via hole 6a2 and the third via hole 621 to be unable to communicate.

[0185] The above numerical range not only will not increase the difficulty of the alignment process and the preparation cost, but also can meet the requirement of the alignment deviation of the two times of patterning process and ensure the communication between the second via hole 6a2 and the third via hole 621.

[0186] It should be noted that, since the hole wall of the second sub-via hole 612, the hole wall of the fourth sub-via hole 632, the first hole wall 6211 and the second hole wall 6212 are generally all inclined, the orthographic projection of the hole wall of the fourth sub-via hole 632, the first hole wall 6211 and the second hole wall 6212 on the first substrate 1 has a certain width; therefore, the hole wall of the fourth sub-via hole 632 close to the first hole wall 6211 and the first hole wall 6211 need to be in the corresponding position, and the hole wall of the fourth sub-via hole 632 close to the second hole wall 6212 and the second hole wall 6212 also need to be in the corresponding position; for example, they can all be away from the edge of the first substrate 1, or they can all be close to the edge of the first substrate 1.

[0187] Specifically, the size of the first sub-via hole 611 in the first direction X is greater than or equal to 2 microns and less than or equal to 15 microns, for example, the size of the first sub-via hole 611 in the first direction X can be 5 microns, 7 microns, 10 microns, 13 microns, etc. The size of the second sub-via hole 612 in the first direction X is greater than or equal to 2 microns and less than or equal to 15 microns, for example, the size of the second sub-via hole 612 in the first direction X can be 5 microns, 7 microns, 10 microns, 13 microns, etc.; reduced by 15%-35% relative to the structure in the prior art.

[0188] The size of the third via hole 621 in the first direction X is greater than or equal to 2 microns and less than or equal to 20 microns, for example, the size of the third via hole 621 in the first direction X can be 5 microns, 7 microns, 10 microns, 13 microns, 15 microns, 18 microns, etc.; reduced by 15%-35% relative to the structure in the prior art.

[0189] The size of the third sub-via hole 631 in the first direction X is greater than or equal to 2 microns and less than or equal to 20 microns, for example, the size of the third sub-via hole 631 in the first direction X can be 5 microns, 7 microns, 10 microns, 13 microns, 15 microns, 18 microns, etc. The size of the fourth sub-via hole 632 in the first direction X is greater than or equal to 2 microns and less than or equal to 20 microns, for example, the size of the fourth sub-via hole 632 in the first direction X can be 5 microns, 7 microns, 10 microns, 13 microns, 15 microns, 18 microns, etc. Reduced by 15%-35% relative to the structure in the prior art.

[0190] The array substrate can include a first connection structure 11 and a second connection structure 12; the first connection structure can include a first via 6a1 and a third via 621; the second connection structure can include a second via 6a2 and a third via 621. In the example embodiment, the first connection part 81, the third via 621 and the first via 6a1 are included in the first connection structure 11, that is, the first connection structure 11 can include the first connection part 81 and the third via 621 and the first via 6a1 which are in communication with each other; the second connection part 82, the third via 621 and the second via 6a2 are included in the second connection structure 12, that is, the second connection structure 12 can include the second connection part 82, the third via 621 and the second via 6a2 which are in communication with each other.

[0191] Referring to Figure 20 and Figure 21 , one touch electrode 71 is connected to one touch signal line 51 through the first connection structure 11 and the second connection structure 12 arranged alternately, so that one second connection structure 12 is arranged between two adjacent first connection structures 11, and one first connection structure 11 is arranged between two adjacent second connection structures 12; for example, the first connection structure 11 and the second connection structure 12 can each be arranged as ten; referring to Figure 20 , the starting one can be the first connection structure 11; referring to Figure 21 , the starting one can be the second connection structure 12.

[0192] In some example embodiments of the present disclosure, referring to Figure 22 , at least two first connection structures 11 are included in the first connection group 14, that is, the first connection group 14 can include at least two first connection structures 11, for example, the first connection group 14 can include two first connection structures 11, and the first connection group 14 can also include three or more first connection structures 11. At least two second connection structures 12 are included in the second connection group 15, that is, the second connection group 15 can include at least two second connection structures 12, for example, the second connection group 15 can include two second connection structures 12, and the second connection group 15 can also include three or more second connection structures 12.

[0193] One touch electrode 71 is connected to one touch signal line 51 through the first connection group 14 and the second connection group 15 arranged alternately, so that one second connection group 15 is arranged between two adjacent first connection groups 14, and one first connection group 14 is arranged between two adjacent second connection groups 15; the starting group can be the first connection group 14; the starting group can also be the second connection group 15.

[0194] In some example embodiments of the present disclosure, referring to Figure 23As shown, one touch electrode 71 is connected with at least two touch signal lines 51, and the at least two touch signal lines 51 can be connected in parallel, for example, one touch electrode 71 can be connected with two touch signal lines 51, and one touch electrode 71 can also be connected with three or more touch signal lines 51.

[0195] Each touch signal line 51 is connected to the touch electrode 71 through the alternately arranged first connection structure 11 and the second connection structure 12. For example, in the case where one touch electrode 71 is connected with two touch signal lines 51, the two touch signal lines 51 include a first touch signal line 511 and a second touch signal line 512, the first touch signal line 511 is connected to the touch electrode 71 through the alternately arranged first connection structure 11 and the second connection structure 12, and the second touch signal line 512 is also connected to the touch electrode 71 through the alternately arranged first connection structure 11 and the second connection structure 12. So that one second connection structure 12 is arranged between two adjacent first connection structures 11, and one first connection structure 11 is arranged between two adjacent second connection structures 12; the first connection structure 11 and the second connection structure 12 connected to each touch signal line 51 can be arranged as ten; the starting one can be the first connection structure 11; the starting one can be the second connection structure 12. Moreover, the starting connection structure of the adjacent two touch signal lines 51 can be the same or different.

[0196] In some example embodiments of the present disclosure, with reference to Figure 24 As shown, at least two first connection structures 11 are included in the first connection group 14, that is, the first connection group 14 can include at least two first connection structures 11, for example, the first connection group 14 can include two first connection structures 11, and the first connection group 14 can also include three or more first connection structures 11. At least two second connection structures 12 are included in the second connection group 15, that is, the second connection group 15 can include at least two second connection structures 12, for example, the second connection group 15 can include two second connection structures 12, and the second connection group 15 can also include three or more second connection structures 12.

[0197] One touch electrode 71 is connected with at least two touch signal lines 51, and the at least two touch signal lines 51 can be connected in parallel, for example, one touch electrode 71 can be connected with two touch signal lines 51, and one touch electrode 71 can also be connected with three or more touch signal lines 51.

[0198] Each touch signal line 51 is connected to the touch electrode 71 through the first connection group 14 and the second connection group 15 arranged alternately. For example, in the case that one touch electrode 71 is connected with two touch signal lines 51, the two touch signal lines 51 include a first touch signal line 511 and a second touch signal line 512, the first touch signal line 511 is connected to the touch electrode 71 through the first connection group 14 and the second connection group 15 arranged alternately, and the second touch signal line 512 is also connected to the touch electrode 71 through the first connection group 14 and the second connection group 15 arranged alternately. One second connection group 15 is arranged between two adjacent first connection groups 14, and one first connection group 14 is arranged between two adjacent second connection groups 15; the first connection group 14 and the second connection group 15 connected to each touch signal line 51 can be arranged as ten; the starting one can be the first connection group 14; the starting one can be the second connection group 15. Moreover, the starting connection structure of the adjacent two touch signal lines 51 can be the same or different.

[0199] Alternatively, the first connection structure 11 and the second connection structure 12 connected to the adjacent two touch signal lines 51 are arranged staggeredly, that is, the first connection structure 11 and the second connection structure 12 connected to the adjacent two touch signal lines 51 are not arranged oppositely, so as to avoid the mutual influence between the first connection structure 11 and the second connection structure 12.

[0200] In some example embodiments of the present disclosure, referring to FIG. 1, Figures 25-27 As shown in FIG. 1, the fourth via hole 6a3 can include a seventh sub-via hole 613 arranged on the first insulating layer 61 and an eighth sub-via hole 633 arranged on the third insulating layer 63. The orthographic projection of the fourth via hole 6a3 on the first substrate 1 is located in the middle region of the orthographic projection of the third via hole 621 on the first substrate 1, that is, the orthographic projection of the fourth via hole 6a3 on the first substrate 1 entirely overlaps with the middle region of the orthographic projection of the third via hole 621 on the first substrate 1, or in other words, the distance between each hole wall of the fourth via hole 6a3 and each hole wall of the third via hole 621 is substantially the same.

[0201] In this case, the third conductive layer 8 can further include a third connection part 83, the third connection part 83 is arranged spaced apart from the pixel electrode 84, the first connection part 81 and the second connection part 82, that is, the third connection part 83 is not connected with the pixel electrode 84, the first connection part 81 and the second connection part 82; the third connection part 83 is connected to the touch electrode 71 and the touch signal line 51 through the fourth via hole 6a3 and the third via hole 621, and the touch signal line 51 can transmit the touch signal to the touch electrode 71.

[0202] The third via hole 621 and the fourth via hole 6a3 are included in the third connection structure 13, specifically, the third connection part 83, the fourth via hole 6a3 and the third via hole 621 are included in the third connection structure 13, that is, the third connection structure 13 can include the third connection part 83, the fourth via hole 6a3 and the third via hole 621.

[0203] Referring to Figure 28 It is shown that the first connection structure 11, the second connection structure 12 and the third connection structure 13 are included in the third connection group 16, that is, the third connection group 16 can include one first connection structure 11, one second connection structure 12 and one third connection structure 13, which can be arranged in the order of the first connection structure 11, the third connection structure 13 and the second connection structure 12, or in the order of the first connection structure 11, the second connection structure 12 and the third connection structure 13. Of course, other arrangements are also possible, which will not be described one by one here.

[0204] Referring to Figure 28 It is shown that one touch electrode 71 is connected to one touch signal line 51 through the third connection group 16, for example, one touch electrode 71 is connected to one touch signal line 51 through one third connection group 16, and one touch electrode 71 is connected to one touch signal line 51 through two or more third connection groups 16.

[0205] Alternatively, referring to Figure 29 It is shown that one touch electrode 71 is connected to at least two touch signal lines 51, for example, one touch electrode 71 can be connected to two touch signal lines 51, and one touch electrode 71 can also be connected to three or more touch signal lines 51.

[0206] Each touch signal line 51 is connected to a touch electrode 71 through a third connection structure 13; for example, in the case where one touch electrode 71 is connected to two touch signal lines 51, the two touch signal lines 51 include a first touch signal line 511 and a second touch signal line 512, the first touch signal line 511 is connected to the touch electrode 71 through the third connection structure 13; the second touch signal line 512 is also connected to the touch electrode 71 through the third connection structure 13.

[0207] In some example embodiments of the present disclosure, referring to Figure 30 It is shown that one touch electrode 71 is connected to one touch signal line 51 through a plurality of connection structures; the two ends of the plurality of connection structures are third connection structures 13, and the remaining connection structures include first connection structures 11 and second connection structures 12; the first connection structures 11 and the second connection structures 12 can be arranged in an overlapping manner.

[0208] Alternatively, referring to Figure 31As shown in FIG. 1, the middle of the plurality of connection structures is the third connection structure 13, and the remaining connection structures include the first connection structure 11 and the second connection structure 12. The first connection structure 11 and the second connection structure 12 can be arranged alternately.

[0209] In some example embodiments of the present disclosure, referring to FIG. 1, the first connection structure 11 and the second connection structure 12 can be arranged alternately. Figure 32 and Figure 33 As shown in FIG. 1, one touch electrode 71 is connected to at least two touch signal lines 51, for example, one touch electrode 71 can be connected to two touch signal lines 51, and one touch electrode 71 can also be connected to three or more touch signal lines 51.

[0210] Each touch signal line 51 is connected to the touch electrode 71 through a plurality of connection structures. For example, in the case where one touch electrode 71 is connected to two touch signal lines 51, the two touch signal lines 51 include the first touch signal line 511 and the second touch signal line 512, the first touch signal line 511 is connected to the touch electrode 71 through a plurality of connection structures, and the second touch signal line 512 is also connected to the touch electrode 71 through a plurality of connection structures.

[0211] Referring to FIG. 1, the middle of the plurality of connection structures is the third connection structure 13, and the remaining connection structures can include the first connection structure 11 or the second connection structure 12. The first connection structure 11 and the second connection structure 12 can be arranged alternately. Figure 32 Alternatively, referring to FIG. 1, the two ends of the plurality of connection structures are the third connection structure 13, and the remaining connection structures can include the first connection structure 11 and the second connection structure 12. The first connection structure 11 and the second connection structure 12 can be arranged alternately.

[0212] Figure 33 It should be noted that the middle of the plurality of connection structures is not only the one in the middle, for example, the middle of nine connection structures can be the fifth one, that is, the fifth one of the nine connection structures is the third connection structure 13. The middle of the plurality of connection structures can also be a region in the middle, for example, the middle of nine connection structures can be the fourth, fifth and sixth ones, and the middle of ten connection structures can be the fourth, fifth, sixth and seventh ones.

[0213] In addition, in some other example embodiments of the present disclosure, referring to FIG. 1, it can also be that one first connection structure 11 or second connection structure 12 is arranged between two adjacent third connection structures 13, and the first connection structure 11 and the second connection structure 12 are arranged alternately between the two adjacent third connection structures 13.

[0214] Referring to FIG. 1, the middle of the plurality of connection structures is the third connection structure 13, and the remaining connection structures can include the first connection structure 11 or the second connection structure 12. The first connection structure 11 and the second connection structure 12 can be arranged alternately. Figure 34 Referring to FIG. 1, the two ends of the plurality of connection structures are the third connection structure 13, and the remaining connection structures can include the first connection structure 11 and the second connection structure 12. The first connection structure 11 and the second connection structure 12 can be arranged alternately.

[0215] Referring to FIG. 1, the middle of the plurality of connection structures is the third connection structure 13, and the remaining connection structures can include the first connection structure 11 or the second connection structure 12. The first connection structure 11 and the second connection structure 12 can be arranged alternately.​Figure 35 As shown, one touch control electrode 71 is connected with at least two touch signal lines 51, and the at least two touch signal lines 51 connected with the same touch control electrode 71 form a group of touch signal line groups 51a. The array substrate can further include a touch lead 55, which can be located in a non-display area where the touch control circuit 9 is arranged, and the touch lead 55 is connected to one end of the at least two touch signal lines 51 to make the at least two touch signal lines 51 in parallel. A data line 52 is arranged between adjacent two touch signal lines 51 belonging to the same group, specifically, one data line 52 is arranged between adjacent two touch signal lines 51 belonging to the same group. A data line 52 is arranged between adjacent two groups of touch signal line groups 51a, specifically, one data line 52 is arranged between adjacent two groups of touch signal line groups 51a. The touch signal line 51, the data line 52 and the touch lead 55 can be arranged in the same layer, that is, the touch signal line 51, the data line 52 and the touch lead 55 can be arranged in the first conductive layer 5.

[0216] The array substrate can further include a data lead 23, which can also be located in a non-display area where the touch control circuit 9 is arranged. The data lead 23 can be arranged in the gate layer 2, and the data lead 23 can be connected with the data line 52 through a data via hole 33 arranged on the gate insulating layer 3, so as to avoid the intersection of the data lead 23 and the touch lead 55 in the same layer.

[0217] Based on the same inventive concept, the example embodiments of the present disclosure provide a touch display device, which refers to Figure 36 As shown, the touch display device can include the array substrate 100 according to any one of the above embodiments, and the specific structure of the array substrate 100 has been described in detail above, so it will not be repeated here.

[0218] The touch display device can be a liquid crystal touch display device, specifically, the touch display device can further include a color filter substrate 200, a seal frame 400 and a liquid crystal layer 300; the color filter substrate 200 is arranged on the side of the array substrate 100 away from the first substrate 1; the seal frame 400 is arranged between the array substrate 100 and the color filter substrate 200; and the liquid crystal layer 300 is arranged between the array substrate 100 and the color filter substrate 200 and located in the seal frame 400.

[0219] The specific type of the touch display device is not particularly limited, and any type of touch display device commonly used in the art can be used, such as mobile devices such as mobile phones, wearable devices such as watches, and the like. The specific type of the touch display device can be selected by a person skilled in the art according to the specific use of the display device, and will not be repeated here.

[0220] It should be noted that the touch display device further comprises other necessary components and compositions besides the array substrate 100, for example, a housing, a circuit board, a power line, etc. for a display, and the like, and the skilled in the art can make corresponding supplements according to the specific use requirements of the touch display device, which will not be described here.

[0221] Compared with the prior art, the touch display device provided by the example embodiments of the present application has the same beneficial effects as the array substrate 100 provided by the example embodiments described above, which will not be described here.

[0222] Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses or adaptations of the disclosure that are deemed to fall within the general principles of the disclosure and include examples of the known art or technical means in the field which are not disclosed in the present disclosure. The specification and examples are considered to be exemplary only, and the true scope and spirit of the disclosure are indicated by the appended claims.

Claims

1. An array substrate, characterized in that, include: First substrate; A first conductive layer is disposed on one side of the first substrate, and the first conductive layer includes a touch signal line extending along a first direction; An insulating layer group is disposed on the side of the first conductive layer away from the first substrate. The insulating layer group includes a first insulating layer group and a second insulating layer stacked together. The first insulating layer group has a plurality of first vias and a plurality of second vias, and the second insulating layer has a plurality of third vias. A second conductive layer is disposed on at least one layer of the first insulating layer group and on the side of the second insulating layer opposite to the first substrate. The second conductive layer includes a touch electrode, which is connected to the touch signal line through a first via and a third via, as well as a second via and a third via. Wherein, at least one first via and at least one second via are connected to the same touch signal line, and the third via has a first hole wall and a second hole wall disposed opposite to each other in the first direction. In the first direction, the first via is disposed closer to the first hole wall than the second hole wall, and the second via is disposed closer to the second hole wall than the first hole wall.

2. The array substrate according to claim 1, characterized in that, The first insulating layer group includes: A first insulating layer is disposed on the side of the first conductive layer away from the first substrate. The first insulating layer has a plurality of first sub-vias and a plurality of second sub-vias. The second insulating layer is disposed on the side of the first insulating layer away from the first substrate. And / or, a third insulating layer is disposed on the side of the second insulating layer opposite to the first substrate, and the third insulating layer is provided with a plurality of third sub-vias and a plurality of fourth sub-vias; Wherein, the first via includes the first sub-via and / or the third sub-via, and the first sub-via and the third sub-via are interconnected; the second via includes the second sub-via and / or the fourth sub-via, and the second sub-via and the fourth sub-via are interconnected.

3. The array substrate according to claim 2, characterized in that, The orthographic projection of the first sub-via on the first substrate is located within the orthographic projection of the third via on the first substrate, and the orthographic projection of the third sub-via on the first substrate at least partially overlaps with the orthographic projection of the third via on the first substrate.

4. The array substrate according to claim 3, characterized in that, At the first via and the third via, the third insulating layer covers the wall of the third via; or, the third insulating layer does not cover the first via wall and covers the second via wall; or, the third insulating layer does not cover the first via wall and does not cover a portion of the side of the second insulating layer facing away from the first substrate near the first via wall, and the third insulating layer covers the second via wall.

5. The array substrate according to claim 2, characterized in that, The orthographic projection of the second sub-via on the first substrate is located within the orthographic projection of the third via on the first substrate, and the orthographic projection of the fourth sub-via on the first substrate at least partially overlaps with the orthographic projection of the third via on the first substrate.

6. The array substrate according to claim 5, characterized in that, At the second via and the third via, the third insulating layer covers the wall of the third via; or, the third insulating layer does not cover the second via wall, and the third insulating layer covers the first via wall; or, the third insulating layer does not cover the second via wall and does not cover a portion of the side of the second insulating layer facing away from the first substrate near the second via wall, and the third insulating layer covers the first via wall.

7. The array substrate according to claim 2, characterized in that, The first insulating layer and the third insulating layer are made of inorganic materials; the second insulating layer is made of organic materials.

8. The array substrate according to claim 2, characterized in that, The second conductive layer is disposed between the second insulating layer and the third insulating layer. The touch electrode extends to one end of the third via in a second direction, the second direction intersecting the first direction and being parallel to the side of the first substrate where the first conductive layer is disposed. The array substrate further includes: A third conductive layer is disposed on the side of the third insulating layer opposite to the first substrate. The third conductive layer includes a pixel electrode, a first connection portion, and a second connection portion. The pixel electrode, the first connection portion, and the second connection portion are spaced apart. The first connection portion connects the touch electrode and the touch signal line through the third via and the first via. The second connection portion connects the touch electrode and the touch signal line through the third via and the second via. Alternatively, the second conductive layer is disposed on the side of the third insulating layer opposite to the first substrate; the array substrate further includes: A third conductive layer is disposed between the second insulating layer and the third insulating layer, and the third conductive layer includes a pixel electrode.

9. The array substrate according to claim 8, characterized in that, The array substrate further includes: A gate layer is disposed on one side of the first substrate, the gate layer including a gate and a gate line, the gate being connected to the gate line; A gate insulating layer is disposed on the side of the gate layer opposite to the first substrate. An active layer is disposed on the side of the gate insulating layer away from the first substrate. The active layer includes a channel portion and a source connection portion and a drain connection portion disposed at both ends of the channel portion. The first conductive layer is disposed on the side of the active layer away from the first substrate. The first conductive layer also includes a data line, a source electrode, and a drain electrode. The data line extends along the first direction and is spaced apart from the touch signal line. The source electrode is connected to the data line and to the source electrode connection portion. The drain electrode is connected to the pixel electrode and to the drain electrode connection portion.

10. The array substrate according to claim 8, characterized in that, The first conductive layer further includes a gate and a gate line, the gate being connected to the gate line, the gate line extending along the first direction and spaced apart from the touch signal line; the first insulating layer group further includes: A gate insulating layer is disposed on the side of the first conductive layer opposite to the first substrate, and a plurality of fifth sub-vias and a plurality of sixth sub-vias are disposed on the gate insulating layer; The first via includes a first sub-via, a third sub-via, and a fifth sub-via that are interconnected, and the second via includes a second sub-via, a fourth sub-via, and a sixth sub-via that are interconnected.

11. The array substrate according to claim 8, characterized in that, In the second direction, the distance between the edge of the orthographic projection of the third sub-via on the first substrate and the edge of the orthographic projection of the third via on the first substrate is greater than or equal to 1 micrometer and less than or equal to 2.5 micrometers. In the second direction, the distance between the edge of the orthographic projection of the fourth sub-via on the first substrate and the edge of the orthographic projection of the third via on the first substrate is greater than or equal to 1 micrometer and less than or equal to 2.5 micrometers. The second direction intersects the first direction and is parallel to the side of the first substrate on which the first conductive layer is disposed.

12. The array substrate according to claim 1, characterized in that, In the first direction, the distance between the orthographic projection of the first via wall near the first via wall on the first substrate and the orthographic projection of the first via wall on the first substrate is less than or equal to 0.5 micrometers; The distance between the orthographic projection of the first via wall near the second via wall on the first substrate and the orthographic projection of the second via wall on the first substrate is greater than or equal to 1 micrometer and less than or equal to 2.5 micrometers.

13. The array substrate according to claim 1, characterized in that, In the first direction, the distance between the orthographic projection of the second via wall near the second via wall on the first substrate and the orthographic projection of the second via wall on the first substrate is less than or equal to 0.5 micrometers; The distance between the orthographic projection of the second via wall near the first via wall on the first substrate and the orthographic projection of the first via wall on the first substrate is greater than or equal to 1 micrometer and less than or equal to 2.5 micrometers.

14. The array substrate according to claim 1, characterized in that, The touch electrodes are reused as common electrodes.

15. The array substrate according to any one of claims 1 to 14, characterized in that, The array substrate includes: The first connection structure includes the first via and the third via; The second connection structure includes the second via and the third via.

16. The array substrate according to claim 15, characterized in that, One of the touch electrodes is connected to a touch signal line via alternating first and second connection structures; Alternatively, at least two of the first connection structures are included in a first connection group, at least two of the second connection structures are included in a second connection group, and one of the touch electrodes is connected to a touch signal line through alternating first and second connection groups.

17. The array substrate according to claim 15, characterized in that, Each of the touch electrodes is connected to at least two touch signal lines, and each touch signal line is connected to the touch electrode through an alternately arranged first connection structure and a second connection structure; Alternatively, at least two of the first connection structures are included in a first connection group, at least two of the second connection structures are included in a second connection group, and one of the touch electrodes is connected to at least two of the touch signal lines, with each of the touch signal lines connected to the touch electrode via alternating first and second connection groups.

18. The array substrate according to claim 17, characterized in that, The first connection structure and the second connection structure connected to the two adjacent touch signal lines are staggered.

19. The array substrate according to claim 15, characterized in that, The first insulating layer group is further provided with a fourth via, and the orthographic projection of the fourth via on the first substrate is located in the middle region of the orthographic projection of the third via on the first substrate. The third via and the fourth via are included in the third connection structure.

20. The array substrate according to claim 19, characterized in that, The first connection structure, the second connection structure, and the third connection structure are included in a third connection group; one of the touch electrodes is connected to one of the touch signal lines through the third connection group; or, one touch electrode is connected to at least two of the touch signal lines, and each of the touch signal lines is connected to the touch electrode through the third connection structure.

21. The array substrate according to claim 19, characterized in that, One of the touch electrodes is connected to a touch signal line through multiple connection structures; among the multiple connection structures, the third connection structure is located at both ends, and the remaining connection structures include the first connection structure and the second connection structure; or, among the multiple connection structures, the third connection structure is located in the middle, and the remaining connection structures include the first connection structure and the second connection structure.

22. The array substrate according to claim 19, characterized in that, One of the touch electrodes is connected to at least two touch signal lines, and each touch signal line is connected to the touch electrode through multiple connection structures; among the multiple connection structures, the third connection structure is located at both ends, and the remaining connection structures include the first connection structure and the second connection structure; or, among the multiple connection structures, the third connection structure is located in the middle, and the remaining connection structures include the first connection structure and the second connection structure.

23. The array substrate according to any one of claims 1 to 14, characterized in that, One of the touch electrodes is connected to at least two touch signal lines, and the at least two touch signal lines connected to the same touch electrode form a group of touch signal lines. The array substrate further includes: A touch lead is connected to one end of at least two touch signal lines to make at least two touch signal lines connected in parallel. A data line is provided between two adjacent touch signal lines belonging to the same group, and a data line is also provided between two adjacent groups of touch signal lines.

24. A touch display device, characterized in that, include: The array substrate according to any one of claims 1 to 23.

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