A semiconductor chip, a method for manufacturing a metal interconnection layer, and a metal interconnection layer

Abstract

The application discloses a semiconductor chip, a preparation method of a metal interconnection layer and the metal interconnection layer. The semiconductor chip comprises a semiconductor substrate, and a plurality of device structures are formed on the semiconductor substrate. The metal interconnection layer is located above the semiconductor substrate and is used for connecting the plurality of device structures. The metal interconnection layer at least comprises a first titanium layer located above the semiconductor substrate, a first titanium nitride layer located above the first titanium layer, a metal layer located above the first titanium nitride layer, and at least two groups of composite barrier layers located above the metal layer. Each group of composite barrier layers comprises a second titanium layer and a second titanium nitride layer located above the second titanium layer. The thickness of the second titanium nitride layer in each group of composite barrier layers is less than a first preset thickness. The sum of the thicknesses of the second titanium nitride layers in each group of composite barrier layers is equal to or greater than a second preset thickness. The semiconductor chip meets the thickness requirement and reduces metal residual defects on the surface of the semiconductor substrate.

Description

Technical Field

[0001] This application relates to the field of semiconductor device fabrication technology, specifically to a semiconductor chip, a method for fabricating a metal interconnect layer, and the metal interconnect layer itself. Background Technology

[0002] In integrated circuit manufacturing processes, aluminum interconnect metal is typically used as the conductive layer of semiconductor chips, and this aluminum interconnect metal mainly has a "sandwich" structure, namely a Ti / TiN-AL-Ti / TiN structure. A thick titanium nitride layer is deposited on top of the aluminum metal layer to reduce light reflection during exposure, thereby improving the accuracy of pattern transfer.

[0003] However, existing processes leave excessive metal residues on the periphery and center of the semiconductor substrate surface, which poses a risk of semiconductor device failure. Summary of the Invention

[0004] This application provides a semiconductor chip, a method for fabricating a metal interconnect layer, and the metal interconnect layer itself, which can reduce metal residues formed at the periphery and center of the semiconductor substrate surface of the semiconductor chip. The specific solution is as follows:

[0005] In a first aspect, this application provides a semiconductor chip, the semiconductor chip comprising:

[0006] A semiconductor substrate on which several device structures are formed;

[0007] A metal interconnect layer is located above a semiconductor substrate and is used to connect several device structures. The metal interconnect layer includes at least a first titanium layer located above the semiconductor substrate.

[0008] The first titanium nitride layer is located above the first titanium layer;

[0009] A metal layer located above the first titanium nitride layer; and,

[0010] At least two sets of composite barrier layers are located above the metal layer; each set of composite barrier layers includes a second titanium layer and a second titanium nitride layer located above the second titanium layer; the thickness of the second titanium nitride layer in each set of composite barrier layers is less than a first preset thickness; the sum of the thicknesses of the second titanium nitride layers in each set of composite barrier layers is equal to or greater than the second preset thickness.

[0011] Secondly, this application also provides a method for fabricating a metal interconnect layer, the method comprising:

[0012] A first titanium layer is deposited on a semiconductor substrate, and a first titanium nitride layer is deposited on top of the first titanium layer;

[0013] A metal layer is deposited over the first titanium nitride layer;

[0014] At least two sets of composite barrier layers are deposited on top of the metal layer; each set of composite barrier layers includes a second titanium layer and a second titanium nitride layer; the thickness of the second titanium nitride layer in each set of composite barrier layers is less than a first preset thickness; the sum of the thicknesses of the second titanium nitride layers in each set of composite barrier layers is equal to or greater than the second preset thickness.

[0015] Thirdly, this application also provides a metal interconnect layer, the metal interconnect layer comprising:

[0016] First titanium layer;

[0017] The first titanium nitride layer is located above the first titanium layer;

[0018] A metal layer located above the first titanium nitride layer;

[0019] At least two sets of composite barrier layers are located above the metal layer; each set of composite barrier layers includes a second titanium layer and a second titanium nitride layer located above the second titanium layer; the thickness of the second titanium nitride layer in each set of composite barrier layers is less than a first preset thickness; the sum of the thicknesses of the second titanium nitride layers in each set of composite barrier layers is equal to or greater than the second preset thickness.

[0020] As described above, the semiconductor chip, the method for fabricating the metal interconnect layer, and the metal interconnect layer of this application have the following beneficial effects:

[0021] In this application, the metal interconnect layer of the semiconductor chip has multiple sets of composite barrier layers deposited above the metal layer. Each set of composite barrier layers includes a second titanium layer and a second titanium nitride layer above the second titanium layer. The thickness of the second titanium nitride layer in each set of composite barrier layers is limited and is less than a first preset thickness. That is, in each set of composite barrier layers, a thinner second titanium nitride layer is deposited above the second titanium layer to interrupt the formation characteristics of titanium nitride along the C-axis in the second titanium nitride layer, change the crystal orientation of the titanium nitride, and ensure that the gaps in the second titanium nitride layer in the composite barrier layer are small. This prevents photoresist and developer from forming byproducts at the titanium nitride grain boundaries, thereby avoiding the formation of tooth-like defects and reducing metal residue on the surface of the semiconductor substrate.

[0022] Simultaneously, the total thickness of the second titanium nitride layer in each composite barrier layer is equal to or greater than the second preset thickness, ensuring that the total thickness of the titanium nitride layer in the composite barrier layer above the metal layer meets the thickness requirements of the barrier layer during exposure, reducing light reflection by the metal layer during exposure and ensuring pattern transfer accuracy. In other words, this metal interconnect layer can reduce metal residue on the semiconductor substrate surface while ensuring pattern transfer accuracy. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of an example structure of a metal interconnect layer fabricated using existing processes.

[0024] Figure 2 This is a schematic diagram of the metal residue in a metal interconnect layer prepared by existing processes.

[0025] Figure 3 This is a schematic diagram of an example structure of the metal interconnect layer in a semiconductor chip provided in this application embodiment.

[0026] Figure 4 This is another example of a structural schematic diagram of a metal interconnect layer in a semiconductor chip provided in this application embodiment.

[0027] Figure 5 This is a schematic diagram comparing the distribution of residual metal defects in the metal interconnect layer of the semiconductor chip provided in this application embodiment with that in the metal interconnect layer prepared by existing processes.

[0028] Figure 6 This is a flowchart of an example of a method for fabricating a metal interconnect layer provided in an embodiment of this application.

[0029] Figure 7 This is a comparative schematic diagram showing the distribution of metal residues before and after the application of a cleaning step during the preparation of the metal interconnect layer provided in the embodiments of this application.

[0030] Figure 8 This is a comparative schematic diagram showing the distribution of metal residues on the surface of a semiconductor substrate when different cleaning times are used for the second deposition chamber during the fabrication of the metal interconnect layer provided in this application. Detailed Implementation

[0031] To enable those skilled in the art to better understand the technical solutions of this application, the application will be clearly and completely described below with reference to the accompanying drawings of the embodiments. However, this application can be implemented in many other ways different from those described below. Therefore, based on the embodiments provided in this application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this application.

[0032] It should be noted that the terms "first," "second," "third," etc., in the claims, specification, and drawings of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. Such data are interchangeable where appropriate so that the embodiments of this application described herein can be implemented in a sequence other than that shown or described in this application. Furthermore, the terms "comprising," "having," and their variations are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or apparatuses.

[0033] It should be understood that in the embodiments of this application, "at least one" means one or more, and "more than one" means two or more. "And / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. The character " / " generally indicates that the related objects before and after it are in an "or" relationship. "Contains A, B and / or C" means containing any one, two, or three of A, B, and C.

[0034] It should be understood that in the embodiments of this application, "B corresponding to A", "B corresponding to A", "A corresponds to B" or "B corresponds to A" means that B is associated with A, and B can be determined based on A. Determining B based on A does not mean that B is determined solely based on A; B can also be determined based on A and / or other information.

[0035] Before introducing the semiconductor chip provided in this application, let's first combine... Figure 1 and Figure 2 This paper introduces semiconductor chips manufactured using existing processes and their defects. Among them, Figure 1 A schematic diagram of the structure of the metal interconnect layer in a semiconductor chip using existing processes is provided; Figure 2 A schematic diagram of metal residue in a semiconductor chip manufactured using existing processes is provided, in which... Figure 2 (a) is a microscope image of a semiconductor substrate wafer manufactured using existing processes. Figure 2 (b) is an EDX image of the semiconductor substrate of a semiconductor chip manufactured using existing processes. Figure 2 (c) is a schematic diagram of residual metal defects in semiconductor chips manufactured using existing processes.

[0036] like Figure 1 As shown, the metal interconnect layer 100 in a semiconductor chip manufactured using existing processes includes titanium (Ti) located above the semiconductor substrate. TiTitanium layer 110, titanium nitride layer above titanium layer 110 TiN ) layer 120, aluminum ( ) located above the titanium nitride layer 120 AL The aluminum layer 130 and the composite barrier layer 140 located above the aluminum layer 130; wherein the composite barrier layer 140 includes a titanium layer 141 located above the aluminum layer 130 and a titanium nitride layer 142 located above the titanium layer 141.

[0037] In existing processes, the titanium nitride layer 142 is typically deposited to a relatively thick thickness, for example, Figure 1 The thickness of the titanium nitride layer 142 shown can be 1400 Å, and the thickness of the titanium layer 141 can be 100 Å, so that the reflectivity of the aluminum layer to light can be reduced through the titanium nitride layer 142 during exposure, thereby improving the accuracy of pattern transfer.

[0038] However, if the thickness of the titanium nitride layer 142 increases, it will cause the grain boundaries between the columnar titanium nitride grains in the layer to become larger, such as... Figure 2 As shown in (a), Figure 2 Microscopic images of semiconductor substrates manufactured using existing processes show obvious gaps in the titanium nitride layer (i.e., the gaps within the white boxes). When this gap exists in the titanium nitride layer, during the exposure and development stages of the existing process, both photoresist and developer penetrate downwards along these grain boundary gaps, remaining within them and reacting to form organic byproducts. During metal etching, fluorine-containing gases cannot corrode these organic byproducts, ultimately resulting in metal residue defects. Figure 2 As shown in (b), excessive metal residues form on the periphery and center of the semiconductor substrate surface. This ultimately leads to defects in the semiconductor chip, such as... Figure 2 The tooth-like defect shown in (c) ultimately leads to chip failure.

[0039] To address the aforementioned technical deficiencies, this application provides a semiconductor chip, a method for fabricating a metal interconnect layer, and the metal interconnect layer itself. The aim is to solve or partially solve the above-mentioned technical problems, thereby reducing metal residue defects in semiconductor chips.

[0040] The technical solution of this application will be described in detail below through specific embodiments. It should be noted that the following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0041] The following is combined with Figure 3 This application provides an introduction to the semiconductor chip. Figure 3 This is a schematic diagram of the structure of the metal interconnect layer provided in this application.

[0042] The semiconductor chip provided in this application includes: a semiconductor substrate and a metal interconnect layer formed on the semiconductor substrate. Several device structures, such as CMOS devices and logic devices, are formed on the semiconductor substrate. The metal interconnect layer is used to electrically connect the several device structures; the metal interconnect layer includes at least: a first titanium layer located on the semiconductor substrate; a first titanium nitride layer located above the first titanium layer; a metal layer located above the first titanium nitride layer; and at least two sets of composite barrier layers located above the metal layer; each set of composite barrier layers includes a second titanium layer and a second titanium nitride layer located above the second titanium layer; the thickness of the second titanium nitride layer in each set of composite barrier layers is less than a first preset thickness; the sum of the thicknesses of the second titanium nitride layers in each set of composite barrier layers is equal to or greater than a second preset thickness.

[0043] The specific metal in the aforementioned metal layer may include, but is not limited to, aluminum, copper, tungsten, etc., but this embodiment does not impose any specific restrictions.

[0044] The metal interconnect layer may include two, three, or more sets of composite barrier layers, with each set of composite barrier layers overlapping. In an optional specific embodiment, when the metal interconnect layer includes two sets of composite barrier layers (i.e., a first composite barrier layer and a second composite barrier layer), the first composite barrier layer is located above the metal layer, and the second composite barrier layer is located above the first composite barrier layer.

[0045] Reference Figure 3 , Figure 3 A schematic diagram of a metal interconnect layer including two sets of composite barrier layers is provided. Figure 3 The metal interconnect layer 200 shown includes at least: a first titanium layer 210 above the semiconductor substrate, a first titanium nitride layer 220 above the first titanium layer 210, an aluminum layer 230 above the first titanium nitride layer 220, and a composite barrier layer 240 and a composite barrier layer 250 above the aluminum layer 230; wherein the composite barrier layer 240 includes a second titanium layer 241 above the aluminum layer 230 and a second titanium nitride layer 242 above the second titanium layer 241; the composite barrier layer 250 includes a second titanium layer 251 above the second titanium nitride layer 242 and a second titanium nitride layer 252 above the second titanium layer 251.

[0046] Or, refer to Figure 4 , Figure 4 A schematic diagram of a metal interconnect layer including multiple sets of composite barrier layers is provided. Figure 4The metal interconnect layer 300 shown includes at least: a first titanium layer 210 above the semiconductor substrate, a first titanium nitride layer 220 above the first titanium layer 210, an aluminum layer 230 above the first titanium nitride layer 220, and N sets of composite barrier layers (composite barrier layer 240, composite barrier layer 250, ..., composite barrier layer N) above the aluminum layer 230.

[0047] Optionally, the first thickness of the second titanium layer in the first composite barrier layer includes 100 Å to 200 Å, the second thickness of the second titanium nitride layer in the first composite barrier layer includes 900 Å to 1000 Å, the third thickness of the second titanium layer in the second composite barrier layer is 2 to 3 times the first thickness, and the fourth thickness of the second titanium nitride layer in the second composite barrier layer is 0.2 to 0.3 times the second thickness.

[0048] For example, Figure 3 The thickness of the first titanium layer 210 is 100 Å, the thickness of the first titanium nitride layer 220 is 200 Å, the thickness of the composite barrier layer 240 is 1100 Å, and the thickness of the composite barrier layer 250 is 400 Å. Specifically, the thickness of the second titanium layer 241 in the composite barrier layer 240 is 100 Å, and the thickness of the second titanium nitride layer 242 in the composite barrier layer 240 is 1000 Å. The thickness of the second titanium layer 251 in the composite barrier layer 250 is twice the thickness of the second titanium layer 241 in the composite barrier layer 240, specifically 200 Å, and the thickness of the second titanium nitride layer 252 in the composite barrier layer 250 is 0.2 times the thickness of the second titanium nitride layer 242 in the composite barrier layer 240, specifically 200 Å.

[0049] The aforementioned first preset thickness refers to the maximum critical thickness of the second titanium nitride layer in each group of composite barrier layers. That is, the thickness of the second titanium nitride layer in each group of composite barrier layers can be the same or different; this embodiment does not specifically limit this, as long as it is less than the first preset thickness. Specifically, when the second titanium nitride layer in the composite barrier layer is less than the first preset thickness, it indicates that the second titanium nitride layer is relatively thin. In this way, the growth characteristics of the titanium nitride layer along the C-axis can be interrupted by the titanium layer deposited below it, changing the crystal orientation of the titanium nitride and ensuring that the gaps in the second titanium nitride layer in the composite barrier layer are small. This prevents the formation of byproducts by photoresist and developer at the titanium nitride grain boundaries, thereby avoiding the formation of tooth-like defects and reducing metal residue on the semiconductor substrate surface. If the thickness of the second titanium nitride layer in the composite barrier layer is greater than the first preset thickness, it is likely to result in larger gaps in the second titanium nitride layer, leading to significant metal residue.

[0050] Optionally, the first preset thickness may specifically include any thickness from 900A to 1000A, including boundary values ​​such as 900A and 1000A. All parameter ranges described in this embodiment include the corresponding boundary values.

[0051] The aforementioned second preset thickness refers to the minimum critical value of the total thickness of the second titanium nitride layers in each group of composite barrier layers in the metal interconnect layer. As described above, depositing a thicker titanium nitride layer above the aluminum metal layer is to reduce light reflection during exposure, thereby improving the accuracy of pattern transfer. If the total thickness of the second titanium nitride layers in each group of composite barrier layers is less than the second preset thickness, the pattern transfer accuracy will be reduced. Therefore, in this embodiment, even if the thickness of the second titanium nitride layers in each group of composite barrier layers is relatively thin, the total thickness of the second titanium nitride layers in each group of composite barrier layers needs to be equal to or greater than the aforementioned second preset thickness to ensure pattern transfer accuracy while reducing metal residual defects.

[0052] Optionally, the second preset thickness may specifically include: 1100A~1300A.

[0053] Optionally, the sum of the thicknesses of all composite barrier layers is less than a third preset thickness; the third preset thickness is between 1400 Å and 1600 Å, including the boundary value between 1400 Å and 1600 Å. This third preset thickness is the critical value of the total thickness of all composite barrier layers. When the total thickness of all composite barrier layers is less than the third preset thickness, it can be ensured that the total thickness of the metal interconnect layer meets the requirements of existing semiconductor chips.

[0054] contrast Figure 1 and Figure 3 The structure of the metal interconnect layer shown is as follows: Figure 1 The titanium nitride layer in the provided metal interconnect layer is relatively thick (e.g., titanium nitride layer 142 is 1400 Å), while Figure 3 In the metal interconnect layer shown, the titanium nitride layers in each group of composite barrier layers above the aluminum layer are relatively thin (e.g., the thickness of the second titanium nitride layer 142 is 1000 Å, and the thickness of the second titanium nitride layer 152 is 200 Å), but the total thickness of the two metal interconnect layers remains the same. Thus, while ensuring that the thickness of the semiconductor chip provided in this application meets existing thickness requirements, the thickness of the second titanium nitride layer in each group of composite barrier layers in the semiconductor chip provided in this application is thinner than the titanium nitride layer in existing processes, and a corresponding titanium layer is deposited in each group of composite barrier layers. The deposited titanium layer interrupts the growth characteristics of titanium nitride along the C-axis, changes the crystal orientation of titanium nitride, and ensures that the gaps in the second titanium nitride layer in the composite barrier layer are small, reducing metal residue defects. At the same time, the total thickness of each titanium nitride layer is relatively thick, which can ensure reduced light reflection efficiency and ensure pattern transfer accuracy.

[0055] To further verify the characteristics of the metal interconnect layer formed by the method described in this embodiment, EDX (Energy Dispersive X-ray Spectroscopy) tests were performed on the metal interconnect layer in the semiconductor chip provided in this application and the metal interconnect layer prepared by existing processes. The test results are as follows: Figure 5 As shown, where, Figure 5 (a) is a schematic diagram of the distribution of residual metal defects in a metal interconnect layer prepared by existing processes. Figure 5 Image (b) shows the distribution of residual metal defects in the metal interconnect layer of the semiconductor chip provided in this application; according to the comparison results, the residual metal defects in the metal interconnect layer of the semiconductor chip provided in this application are significantly reduced.

[0056] Corresponding to the semiconductor chip provided in this application, embodiments of this application also provide a method for fabricating a metal interconnect layer, such as... Figure 6 As shown, Figure 6 This is a flowchart illustrating an example of a method for fabricating a metal interconnect layer according to an embodiment of this application. It should be noted that the same method is used sequentially to fabricate the metal interconnect layer for different semiconductor substrates. Therefore, this embodiment will subsequently describe the fabrication of a metal interconnect layer for a single semiconductor substrate. The method may include the following steps S310 to S330.

[0057] Step S310: Deposit a first titanium layer on a semiconductor substrate, and deposit a first titanium nitride layer on top of the first titanium layer;

[0058] In an optional embodiment, the above may be a semiconductor substrate, such as a semiconductor substrate with various device structures formed thereon or a bare semiconductor substrate.

[0059] In an optional embodiment, the first titanium layer and the first titanium nitride layer can be deposited using a physical vapor deposition (PVD) method. Specifically, the first titanium layer and the first titanium nitride layer are formed using a magnetron sputtering process. In an optional embodiment, the deposition can be carried out in a third deposition chamber, such as... Figure 3 As shown, a first titanium layer 210 is deposited on a semiconductor substrate, and a first titanium nitride layer 220 is deposited on top of the first titanium layer 210.

[0060] Optionally, the aforementioned third deposition chamber is a high-vacuum titanium process chamber. In the high-vacuum titanium process chamber, under the conditions of sputtering power of 2000~4000W and argon flow rate of 20~40 (standard cubic centimeters per minute), a first titanium layer 210 with a thickness of 100 Å~200 Å is deposited on the semiconductor substrate by magnetron sputtering. Preferably, the thickness of the deposited first titanium layer 210 is 100 Å.

[0061] After forming the first titanium layer 210, a first titanium nitride layer 220 is formed in the third deposition chamber. The pressure range of the third deposition chamber is set to 0.004-0.005 Torr, and the temperature is set to 25-35°C. First, the sputtering power of the third deposition chamber is set to 10000-15000 W, the argon flow rate is set to 20-40 standard cubic centimeters per minute (sccm), and the nitrogen flow rate is set to 60-100 sccm, depositing a first titanium nitride layer 220 with a thickness of 200 Å-300 Å. Preferably, the sputtering power of the third deposition chamber is set to 11000 W, the argon flow rate is set to 28 sccm, and the nitrogen flow rate is set to 80 sccm, depositing a first titanium nitride layer 220 with a thickness of 200 Å above the first titanium layer 210. When the relevant sputtering parameters are selected reasonably, a first titanium layer and a first titanium nitride layer with high uniformity, low resistance, high density and strong adhesion can be sputtered. However, if the sputtering parameters are not reasonable (such as excessive pressure, excessive power, improper nitrogen ratio, etc.), the first titanium layer and the first titanium nitride layer will have corresponding defects, such as poor density, high resistivity and decreased adhesion.

[0062] Step S320: Deposit a metal layer over the first titanium nitride layer.

[0063] In this embodiment, aluminum layer is used as an example for description.

[0064] After the first titanium nitride layer is deposited, the semiconductor substrate with the first titanium layer and the first titanium nitride layer deposited is transferred from the third deposition chamber to the fourth deposition chamber, for example, by a robotic arm. This fourth deposition chamber is a process chamber for depositing metals (such as aluminum). The sputtering power of this fourth deposition chamber is set to 38000~55000W, the temperature to 250~290℃, and the argon flow rate to 150~180sccm, depositing an aluminum layer of 10000Å~13000Å. In a preferred embodiment, the process temperature of the fourth deposition chamber is set to 270℃, the sputtering power to 55000W, and the argon flow rate to 160sccm, depositing an aluminum layer of 230Å.

[0065] Step S330: Deposit at least two sets of composite barrier layers on top of the metal layer; each set of composite barrier layers includes a second titanium layer and a second titanium nitride layer; the thickness of the second titanium nitride layer in each set of composite barrier layers is less than a first preset thickness; the sum of the thicknesses of the second titanium nitride layers in each set of composite barrier layers is equal to or greater than the second preset thickness.

[0066] In an optional implementation, at least two sets of composite barrier layers can be deposited on top of the metal layer after a preset time has elapsed since the completion of metal layer deposition. That is, the preset time elapsed after metal layer deposition allows the deposited metal layer structure to stabilize, the metal grain size distribution to become more uniform, and the semiconductor substrate product to remain stable. Here, the preset time can be understood as the preset time interval between the completion of metal layer deposition and the start of composite barrier layer deposition, i.e., the evolution time reserved for the metal layer corresponding to a semiconductor substrate.

[0067] Optionally, the sum of the thicknesses of each composite barrier layer is less than a third preset thickness, and this third preset thickness is between 1400 Å and 1600 Å. Other similar details can be found in the preceding description and will not be repeated here.

[0068] Optionally, the composite barrier layer includes at least a first composite barrier layer and a second composite barrier layer. Based on this, in the preparation method, after the metal layer is deposited, a first composite barrier layer is deposited on top of the metal layer; and a second composite barrier layer is deposited on top of the first composite barrier layer.

[0069] Specifically, after the aluminum layer 230 is deposited in the fourth deposition chamber, the semiconductor substrate with the aluminum layer 230 deposited can be transferred to the first deposition chamber, where a first composite barrier layer 240 is deposited on top of the aluminum layer 230. After the first composite barrier layer 240 is deposited in the first deposition chamber, the semiconductor substrate can be transferred to the second deposition chamber, where a second composite barrier layer 250 is deposited on top of the first composite barrier layer 240. Although both involve the deposition of composite barrier layers, the first and second deposition chambers are two independent chambers.

[0070] In an optional embodiment, the sputtering power of the first deposition chamber can be set to 2000~4000W and the argon flow rate to 20~40 sccm to deposit the second titanium layer 241 in the first composite barrier layer 240 of a first thickness; the first thickness includes 100 Å~200 Å; in a preferred embodiment, the sputtering power of the first deposition chamber can be set to 3000W and the argon flow rate to 31 sccm to deposit the second titanium layer 241 in the first composite barrier layer 240 of 100 Å.

[0071] Then, the sputtering power of the first deposition chamber can be set to 10000~15000W, the argon flow rate to 20~40sccm, and the nitrogen flow rate to 60~100sccm to deposit a second titanium nitride layer 242 in the first composite barrier layer 240 of a second thickness; optionally, the second thickness includes 900Å~1100Å. In a preferred embodiment, the sputtering power of the first deposition chamber can be set to 11000W, the argon flow rate to 28sccm, and the nitrogen flow rate to 80sccm to deposit a second titanium nitride layer 242 in the first composite barrier layer 240 of 1000Å.

[0072] Furthermore, after the first composite barrier layer 240 is deposited in the first deposition chamber, the semiconductor substrate can be transferred to the second deposition chamber. The sputtering power of the second deposition chamber is set to 2000~4000W, and the argon flow rate is set to 20~40sccm. The second titanium layer 251 in the second composite barrier layer 250 with a third thickness is deposited. The third thickness is 2~3 times the first thickness, specifically 200Å~300Å. In a preferred embodiment, the sputtering power of the second deposition chamber can be set to 3000W, and the argon flow rate can be set to 31sccm. The second titanium layer 251 in the second composite barrier layer 250 with a thickness of 200Å is deposited.

[0073] Then, the sputtering power of the second deposition chamber is set to 10000~15000W, the argon flow rate is 20~40sccm, and the nitrogen flow rate is 60~100sccm, to deposit the second titanium nitride layer 252 of the second composite barrier layer 250 with a fourth thickness. The fourth thickness is 0.2~0.3 times the second thickness; following the above example, the fourth thickness can specifically include 200Å~300Å. In a preferred embodiment, the sputtering power in the second deposition chamber can be set to 11000W, the argon flow rate to 28sccm, and the nitrogen flow rate to 80sccm, to deposit the second titanium nitride layer 252 in the second composite barrier layer 250 with a thickness of 200Å. In an optional embodiment, after the first composite barrier layer is deposited in the first deposition chamber, the fabrication step further includes a cleaning step: before the semiconductor substrate is transferred to the second deposition chamber, the second deposition chamber is cleaned to remove the titanium nitride deposited on the titanium target in the second deposition chamber. This makes the second titanium layer 251 in the second composite barrier layer 250 formed in the next deposition cycle purer. For example, the cleaning power of the second deposition chamber is set to 10000-15000W, the argon flow rate is 80-160 sccm, and the cleaning time is 10-15s. Then, the waste gas is removed to remove the titanium nitride film deposited on the surface of the titanium target, making the target surface pure titanium. This improves the formation effect of titanium nitride, reduces the grain boundary density of titanium nitride, and thus improves the barrier effect of titanium nitride on photoresist and developer.

[0074] In a preferred embodiment, the cleaning power of the second deposition chamber can be set to 12000W, the argon flow rate to 100sccm, and the cleaning time to 10s.

[0075] In an optional implementation, when depositing three or more composite barrier layers on top of the metal layer, each composite barrier layer can be deposited in a different deposition chamber. Before each composite barrier layer is deposited, its corresponding deposition chamber is cleaned. The cleaning steps are as described above and will not be repeated here.

[0076] To further verify the impact of the cleaning steps in this optional embodiment on the characteristics of the metal interconnect layer formed by the method of this embodiment, EDX tests were performed on the metal interconnect layers formed with and without the above cleaning steps, respectively. The test results are as follows: Figure 7 As shown, where, Figure 7 (a1) ~ Figure 7 Image (a4) shows the defect distribution images for the four semiconductor substrates in the continuous process without the aforementioned cleaning steps. Correspondingly, Figure 7 (b1) Figure 7 Image (b4) shows the defect distribution images of the four semiconductor substrates in the subsequent process after the above cleaning steps were applied; it can be seen that, without the above cleaning steps, except for the first semiconductor substrate (b4), the defect distribution is significantly lower. Figure 7 The metal residual defects corresponding to (a1) are relatively few, and the remaining semiconductor substrates (i.e. Figure 7 The metal residues corresponding to (a2) to (a4) are abnormally high. After applying the above cleaning steps, four semiconductor substrates were processed in succession. Figure 7 (b1) Figure 7 In (b4), the metal residue around and in the center of the semiconductor substrate formed by the four semiconductor substrates is greatly reduced.

[0077] Furthermore, the cleaning time for the titanium target in the second deposition chamber needs to be adjusted according to the actual situation. The cleaning time is generally 10-15 seconds, preferably 10 seconds. After the semiconductor substrate completes the process in the first deposition chamber, it awaits the cleaning process for the titanium target in the second deposition chamber. If the cleaning process is too long, it will result in an excessively long residence time after aluminum deposition, leading to inconsistent aluminum grain sizes between the first semiconductor substrate and subsequent semiconductor substrates, affecting the results of subsequent metal etching. If the cleaning process is too short, the titanium nitride on the surface of the titanium target cannot be completely removed, resulting in non-pure titanium deposits. This can easily lead to dense titanium nitride grain boundaries, failing to effectively block the photoresist and developer.

[0078] like Figure 8 As shown, Figure 8The image provides defect distribution images at different cleaning times, where... Figure 8 (a1) ~ Figure 8 Image (a4) shows the defect distribution images corresponding to cleaning times of 5s, 100s, 150s, and 200s, respectively. It can be seen that after appropriately reducing the above cleaning times, the metal residue on the periphery and center of the semiconductor substrate is significantly reduced.

[0079] in addition, Figure 8 (b1) Figure 8 Image (b4) shows the distribution of residual metal defects on the four semiconductor substrates in the continuous process when the cleaning time is 10s. It can be seen that the residual metal defects on the semiconductor substrates with a cleaning time of 10s are significantly reduced compared to those with cleaning times of 5s, 100s, 150s, and 200s.

[0080] This concludes the description of the method for fabricating the metal interconnect layer provided in this application.

[0081] Next, the metal interconnect layer prepared by the method provided in this application will be described. Please refer to... Figure 3 or Figure 4 .by Figure 3 For example, the metal interconnect layer 200 includes: a first titanium layer 210; a first titanium nitride layer 220 located above the first titanium layer 210; a metal layer 230 located above the first titanium nitride layer 220; a composite barrier layer 240 located above the metal layer 230; and a composite barrier layer 250 located above the composite barrier layer 240.

[0082] Alternatively, three or more composite barrier layers can be sputtered above the metal layer 230, such as... Figure 4 As shown, above the metal layer 230 are composite barrier layers 240, 250, ..., N, where N is an integer equal to or greater than 3.

[0083] Each composite barrier layer comprises a second titanium layer and a second titanium nitride layer above the second titanium layer; such as Figure 3 and Figure 4 As shown, the composite barrier layer 240 includes a second titanium layer 241 and a second titanium nitride layer 242; the composite barrier layer 250 includes a second titanium layer 251 and a second titanium nitride layer 252; the composite barrier layer N includes a second titanium layer n and a second titanium nitride layer n+1; furthermore, the thickness of the second titanium nitride layer in each group of composite barrier layers is less than a first preset thickness; the sum of the thicknesses of the second titanium nitride layers in each group of composite barrier layers is equal to or greater than the second preset thickness.

[0084] The specific characteristics of this metal interconnect layer can be described in the previous text, and will not be repeated here.

[0085] While this application discloses preferred embodiments as described above, it is not intended to limit the scope of this application. Any possible variations and modifications can be made by those skilled in the art without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A semiconductor chip, characterized in that, include: A semiconductor substrate on which a plurality of device structures are formed; A metal interconnect layer, located above the semiconductor substrate, is used to connect a plurality of the device structures, wherein the metal interconnect layer includes at least: a first titanium layer located above the semiconductor substrate; A first titanium nitride layer located above the first titanium layer; A metal layer located above the first titanium nitride layer; and, At least two sets of composite barrier layers are located above the metal layer; each set of composite barrier layers includes a second titanium layer and a second titanium nitride layer located above the second titanium layer; the thickness of the second titanium nitride layer in each set of composite barrier layers is less than a first preset thickness; the sum of the thicknesses of the second titanium nitride layers in each set of composite barrier layers is equal to or greater than a second preset thickness; the first preset thickness includes 900 Å to 1000 Å; the second preset thickness includes 1100 Å to 1300 Å.

2. The semiconductor chip according to claim 1, characterized in that, The sum of the thicknesses of the composite barrier layers in each group is less than the third preset thickness; the third preset thickness is between 1400 Å and 1600 Å.

3. The semiconductor chip according to claim 1, characterized in that, The composite barrier layer includes at least a first composite barrier layer and a second composite barrier layer; the first composite barrier layer is located above the metal layer; and the second composite barrier layer is located above the first composite barrier layer.

4. The semiconductor chip according to claim 3, characterized in that, The first thickness of the second titanium layer in the first composite barrier layer includes 100 Å to 200 Å, the second thickness of the second titanium nitride layer in the first composite barrier layer includes 900 Å to 1000 Å, the third thickness of the second titanium layer in the second composite barrier layer is 2 to 3 times the first thickness, and the fourth thickness of the second titanium nitride layer in the second composite barrier layer is 0.2 to 0.3 times the second thickness.

5. A method for fabricating a metal interconnect layer, characterized in that, The method includes: A first titanium layer is deposited on a semiconductor substrate, and a first titanium nitride layer is deposited on top of the first titanium layer; A metal layer is deposited over the first titanium nitride layer; At least two sets of composite barrier layers are deposited on top of the metal layer; each set of composite barrier layers includes a second titanium layer and a second titanium nitride layer; the thickness of the second titanium nitride layer in each set of composite barrier layers is less than a first preset thickness; the sum of the thicknesses of the second titanium nitride layers in each set of composite barrier layers is equal to or greater than a second preset thickness; the first preset thickness includes 900 Å to 1000 Å; the second preset thickness includes 1100 Å to 1300 Å.

6. The method according to claim 5, characterized in that, The sum of the thicknesses of the composite barrier layers in each group is less than the third preset thickness; the third preset thickness is between 1400 Å and 1600 Å.

7. The method according to claim 5, characterized in that, The deposition of at least two sets of composite barrier layers on top of the metal layer includes: When the time elapsed after the metal layer deposition is completed meets a preset time elapsed, at least two sets of composite barrier layers are deposited on top of the metal layer.

8. The method according to any one of claims 5 to 7, characterized in that, The composite barrier layer includes at least a first composite barrier layer and a second composite barrier layer; the deposition of at least two sets of composite barrier layers on the metal layer includes: The first composite barrier layer is deposited over the metal layer; A second composite barrier layer is deposited on top of the first composite barrier layer.

9. The method according to claim 8, characterized in that, The deposition of the first composite barrier layer over the metal layer includes: The first composite barrier layer is deposited over the metal layer through the first deposition chamber; The deposition of the second composite barrier layer over the first composite barrier layer includes: The second composite barrier layer is deposited over the first composite barrier layer through the second deposition chamber.

10. The method according to claim 9, characterized in that, The deposition of the first composite barrier layer over the metal layer through the first deposition chamber includes: The sputtering power of the first deposition chamber is set to 2000~4000W, and the argon flow rate is 20~40 standard cubic centimeters per minute, to deposit the second titanium layer in the first composite barrier layer of the first thickness; The sputtering power of the first deposition chamber is set to 10000~15000W, the argon flow rate is 20~40 standard cubic centimeters per minute, and the nitrogen flow rate is 60~100 standard cubic centimeters per minute, to deposit the second titanium nitride layer in the first composite barrier layer of the second thickness. The first thickness includes 100A to 200A; the second thickness includes 900A to 1100A.

11. The method according to claim 10, characterized in that, The deposition of the second composite barrier layer over the first composite barrier layer through the second deposition chamber includes: The sputtering power of the second deposition chamber is set to 2000~4000W, and the argon flow rate is 20~40 standard cubic centimeters per minute to deposit the second titanium layer in the second composite barrier layer of the third thickness. The sputtering power of the second deposition chamber is set to 10000~15000W, the argon flow rate is 20~40 standard cubic centimeters per minute, and the nitrogen flow rate is 60~100 standard cubic centimeters per minute, and the second titanium nitride layer of the second composite barrier layer with a fourth thickness is deposited. The third thickness is 2 to 3 times the first thickness; the fourth thickness is 0.2 to 0.3 times the second thickness.

12. The method according to claim 9, characterized in that, Before depositing the second composite barrier layer over the first composite barrier layer through the second deposition chamber, the method further includes: The second deposition chamber is cleaned to remove titanium nitride deposited on the titanium target within the second deposition chamber.

13. The method according to claim 12, characterized in that, The cleaning of the second deposition chamber includes: The cleaning time for the second deposition chamber is set to be in the range of 50~200A; During the cleaning period, the second deposition chamber is cleaned.

14. The method according to any one of claims 5 to 7, characterized in that, The step of depositing a first titanium layer on a semiconductor substrate and depositing a first titanium nitride layer on top of the first titanium layer includes: The sputtering power of the third deposition chamber is set to 2000~4000W, the argon flow rate is 20~40 standard cubic centimeters per minute, and the first titanium layer of 100A~200A is deposited. The sputtering power of the third deposition chamber is set to 10000~15000W, the argon flow rate is 20~40 standard cubic centimeters per minute, and the nitrogen flow rate is 60~100 standard cubic centimeters per minute, to deposit the first titanium nitride layer of 200A~300A.

15. The method according to any one of claims 5 to 7, characterized in that, The deposition of a metal layer over the first titanium nitride layer includes: The sputtering power of the fourth deposition chamber is set to 38000~55000W, the temperature to 250~290℃, and the argon flow rate to 150~180 standard cubic centimeters per minute, to deposit the metal layer of 10000A~13000A.

16. A metal interconnect layer, characterized in that, The metal interconnect layer includes: First titanium layer; A first titanium nitride layer located above the first titanium layer; A metal layer located above the first titanium nitride layer; At least two sets of composite barrier layers are located above the metal layer; each set of composite barrier layers includes a second titanium layer and a second titanium nitride layer located above the second titanium layer; the thickness of the second titanium nitride layer in each set of composite barrier layers is less than a first preset thickness; the sum of the thicknesses of the second titanium nitride layers in each set of composite barrier layers is equal to or greater than a second preset thickness; the first preset thickness includes 900 Å to 1000 Å; the second preset thickness includes 1100 Å to 1300 Å.

Images