Overcurrent protection frequency control method, processor, storage medium and program product

Abstract

The application discloses an over-current protection frequency control method, a processor, a storage medium and a program product, and the method comprises the following steps: determining frequency values of each stage of over-current protection according to a target working frequency, and configuring the frequency values of each stage of over-current protection to a first register; when the target working frequency is configured through a second register, transmitting the frequency values of each stage in the first register to a third register; wherein the second register is a frequency configuration register used for indicating a post-divider, and the third register is a frequency configuration register used for indicating frequency values used by a state machine in each stage. The application can realize dynamic configuration of OCP frequency, the frequency configuration of OCP does not need to be placed in the same register as the frequency configuration of the post-divider, and the flexibility of OCP frequency configuration is improved, and the cost of the register is saved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of artificial intelligence chips, and in particular to a frequency control method for overcurrent protection, a processor, a storage medium and a program product. BACKGROUND

[0002] At present, for the execution frequency configuration of OCP (Over Current Protection) of high computing power chips such as GPGPU (General-purpose computing on graphics processing units), the following two methods are commonly used: one is to fix the execution frequency of OCP. In the case of a large working frequency range, the fixed execution frequency of OCP is easy to cause large power noise. This is because the frequency of OCP is lower than the frequency configured during normal work, so the frequency of OCP is lower than the minimum value of the working frequency range. This causes the first frequency reduction amplitude to be too large when the OCP interrupt is triggered, resulting in large power noise. The other is that the frequency configuration register of the OCP execution frequency and the post divider (post divider) frequency configuration register of the PLL FOUT (Phase-Locked Loop output frequency) are placed together to share a set (32 bits). In this way, the configuration of the working frequency of the PLL and the execution frequency of the OCP can be updated synchronously, but the FOUT that needs to place the post divider register and the frequency configuration register of the OCP together can only support OCP, resulting in a lack of flexibility. If all FOUTD (the final output frequency after post divider frequency division) can be supported, all post divider registers of all FOUT need to be added a set of registers for OCP configuration. This requires more cost, and the execution of OCP also needs to determine which set of configuration registers should be used, resulting in a lack of flexibility.

[0003] Therefore, how to improve the flexibility of OCP frequency configuration and reduce the cost of registers is a technical problem that needs to be solved in the field. SUMMARY

[0004] In view of the problems in the prior art, the embodiments of the present application provide an overcurrent protection frequency control method, a processor, a storage medium and a program product, which can realize dynamic configuration of OCP frequency, improve the flexibility of OCP frequency configuration and save the cost of registers.

[0005] In a first aspect, the embodiments of the present application provide an overcurrent protection frequency control method, comprising:

[0006] Determine the frequency values of the stages of the over-current protection according to the target working frequency, and configure the frequency values of the stages of the over-current protection to a first register;

[0007] When the target working frequency is configured through a second register, transmit the frequency values of the stages in the first register to a third register; wherein the second register is a frequency configuration register for indicating a post-divider, and the third register is a frequency configuration register for indicating the frequency values used by a state machine in the stages.

[0008] As an improvement of the above-mentioned scheme, when the target working frequency is configured through the second register, transmitting the frequency values of the stages in the first register to the third register comprises:

[0009] When the target working frequency is configured through the second register, reset an update enable signal of a set bit in the second register; wherein the update enable signal comprises clock pulse signals of a plurality of flip-flops of the third register;

[0010] When the update enable signal is reset, the first register transmits the frequency values of the stages to the second register.

[0011] As an improvement of the above-mentioned scheme, the first register transmits the frequency values of the stages to the second register comprises:

[0012] The frequency values of the stages stored in a plurality of flip-flops in the first register are transmitted in parallel and synchronously to a plurality of flip-flops in the second register;

[0013] Wherein, the plurality of flip-flops in the first register are transmitted one by one to the plurality of flip-flops in the second register; one or more flip-flops in the first register are used to store the frequency value of one stage.

[0014] As an improvement of the above-mentioned scheme, configuring the frequency values of the stages of the over-current protection to the first register comprises:

[0015] Transmit the frequency values of the stages to the plurality of flip-flops in the first register in a serial manner;

[0016] Wherein, the plurality of flip-flops in the first register are triggered by a system clock signal to transmit and store data.

[0017] As an improvement of the above-mentioned scheme, determining the frequency values of the stages of the over-current protection according to the target working frequency comprises:

[0018] Determine the target multiples of the stages of the over-current protection according to the multiples of the post-divider;

[0019] According to the target working frequency, the target frequency multiples of each stage, and the frequency multiplication of the phase-locked loop, frequency values of each stage are calculated.

[0020] As an improvement of the above-mentioned solution, the method further comprises:

[0021] When detecting the over-current protection interruption, the state machine reads the frequency values of each stage of the over-current protection stored in the third register;

[0022] The state machine adjusts the output frequency of the phase-locked loop according to the read frequency values of each stage.

[0023] As an improvement of the above-mentioned solution, the state machine adjusts the output frequency of the phase-locked loop according to the read frequency values of each stage, comprising:

[0024] In the response stage of the over-current protection interruption, the output frequency of the phase-locked loop is stepwise down-regulated according to the frequency values of each stage of the over-current protection until the over-current protection interruption is detected to be recovered;

[0025] When detecting the over-current protection interruption recovery, the output frequency of the phase-locked loop is stepwise up-regulated according to the frequency values of each stage of the over-current protection until the output frequency of the phase-locked loop recovers to the target working frequency.

[0026] In the second aspect, an embodiment of the present application provides a processor, comprising: a first register, a second register and a third register;

[0027] The first register is configured to store frequency values of each stage of over-current protection; wherein the frequency values of each stage are determined according to a target working frequency;

[0028] The second register is configured to configure the target working frequency; wherein the second register is a frequency configuration register for indicating a post-divider;

[0029] The third register is configured to: when the target working frequency is configured through the second register, the frequency values of each stage in the first register are transmitted to the third register; wherein the third register is a frequency configuration register for indicating frequency values used by a state machine in each stage.

[0030] In the third aspect, an embodiment of the present application provides a computer readable storage medium, which stores a computer program, wherein when the computer program runs, the computer readable storage medium controls a device where the computer readable storage medium is located to execute the over-current protection frequency control method in any one of the first aspect.

[0031] In a fourth aspect, an embodiment of the present application provides a computer program product, comprising computer programs or instructions, which, when executed by a processor, implement the overcurrent protection frequency control method according to any one of the first aspect.

[0032] Compared with the prior art, the overcurrent protection frequency control method, the processor, the storage medium and the program product provided by the embodiment of the present application can determine the frequency values of each stage of overcurrent protection according to the target working frequency when the frequency conversion mechanism is ready to configure a new target working frequency, and configure the frequency values of each stage of overcurrent protection to a first register; after the first register is configured, the frequency values of each stage in the first register are transmitted to a third register when the target working frequency is configured through a second register; wherein the second register is used to indicate the frequency configuration register of the post-divider, and the third register is used to indicate the frequency configuration register of the frequency value used by the state machine in each stage. The present application can realize dynamic configuration of OCP frequency, and the frequency configuration of OCP does not need to be placed in the same register as the frequency configuration of the post-divider, thereby improving the flexibility of OCP frequency configuration and saving the cost of registers. BRIEF DESCRIPTION OF DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the present application, the drawings used in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0034] Figure 1 is a flow chart of the overcurrent protection frequency control method provided by the embodiment of the present application;

[0035] Figure 2 is a schematic diagram of the framework of DVFS and OCP provided by the embodiment of the present application;

[0036] Figure 3 is a schematic diagram of the frequency output waveform of OCP control provided by the embodiment of the present application;

[0037] Figure 4 is a schematic diagram of the frequency value example of each stage of OCP provided by the embodiment of the present application;

[0038] Figure 5 is a data transmission schematic diagram of the first register and the second register provided by the embodiment of the present application;

[0039] Figure 6 is another data transmission schematic diagram of the first register and the second register provided by the embodiment of the present application;

[0040] Figure 7 is a structural block diagram of a processor provided by an embodiment of the present application. DETAILED DESCRIPTION

[0041] The technical solutions in the embodiments of the present application will be clearly and completely described with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative effort fall within the protection scope of the present application.

[0042] It can be understood that various numbers involved in the embodiments of the present application are only distinguished for convenience of description, and are not used to limit the scope of the present application. The size of the serial numbers of the processes does not mean the execution order, and the execution order of the processes should be determined according to their functions and inherent logic.

[0043] In the embodiments of the present application, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. The terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. The element defined by the phrase "comprises" without more limitation does not exclude the presence of additional identical elements in the process, method, article or device including the element. The term "a plurality of or several" means two or more.

[0044] Please refer to Figure 1 , Figure 1 is a flowchart of a frequency control method for overcurrent protection provided by an embodiment of the present application. The frequency control method for overcurrent protection is applied to a processor, and specifically includes:

[0045] S11: determining frequency values of each stage of overcurrent protection according to a target working frequency, and configuring the frequency values of each stage of overcurrent protection to a first register;

[0046] The target working frequency is used to indicate that the processor is based on a variable frequency mechanism to prepare a new clock frequency configuration. The clock frequency of the processor is locked on the target working frequency by a phase-locked loop.

[0047] A phase-locked loop (PLL) is a circuit or system that is a negative feedback control system for keeping the phase of its output signal stable with the phase of an input reference signal. A PLL can also be combined with a post-divider to get an arbitrary frequency point. The post-divider can divide the output frequency of the PLL to get a lower frequency that is phase-synchronized with the target operating frequency and output, achieving the functions of frequency locking and phase synchronization.

[0048] In the embodiment of the present application, after the target operating frequency is determined, the target operating frequency is not configured first, but the frequency values of each stage of the over-current protection OCP are calculated according to the target operating frequency, and the frequency values of each stage of the over-current protection OCP are configured to the first register OCP_REG_A.

[0049] S12: When the target operating frequency is configured through the second register, the frequency values of each stage in the first register are transmitted to the third register; wherein the second register is a frequency configuration register for indicating the post-divider, and the third register is a frequency configuration register for indicating the frequency values used by the state machine in each stage.

[0050] After the first register is configured, when the target operating frequency is configured through the second register (also referred to as the fout post divider register or the post divider register of FOUT), the frequency values of each stage of the over-current protection OCP stored in the first register OCP_REG_A are transmitted to the third register OCP_REG_B through firmware logic (FW logic). Subsequently, when the OCP interrupt is triggered, the state machine always executes the frequency configuration of the third register OCP_REG_B.

[0051] In the embodiment of the present application, since the action of data transmission from the first register OCP_REG_A to the third register OCP_REG_B is a hardware behavior, the transmission speed is very fast, and the update of the third register OCP_REG_B falling behind the update of the working frequency of the fout post divider register can be basically ignored, so that the change of the OCP frequency and the change of the working frequency are synchronous, thereby the dynamic configuration of the OCP frequency can be realized, meanwhile, the frequency configuration of the OCP does not need to be placed in the fout post divider register together with the frequency configuration of the fout post divider, so that the flexibility of the OCP frequency configuration is improved; in addition, since the frequency configuration of the OCP does not need to be placed in the fout post divider register together with the frequency configuration of the fout post divider in the embodiment of the present application, so that the OCP frequency register does not need to be added to each fout post divider register, and the bit number of the OCP frequency register does not need to be sacrificed, thereby the register cost is saved.

[0052] In an optional embodiment, the frequency value of each stage of the overcurrent protection is determined according to the target working frequency, including:

[0053] According to the multiple of the post divider, the target multiple of each stage of the overcurrent protection is determined;

[0054] According to the target working frequency, the target multiple of each stage and the frequency multiplication of the phase-locked loop, the frequency value of each stage is calculated.

[0055] Before the frequency value of each stage of the overcurrent protection OCP is calculated, the execution of the overcurrent protection OCP is described as follows.

[0056] As Figure 2The shown framework of DVFS (Dynamic Voltage and Frequency Scaling) and OCP. When the processor is working normally, the MPU (Microprocessor Unit) controls the output frequency Fout of the phase-locked loop PLL to realize the DVFS function. When the state machine (Finite State Machine, FSM) receives an OCP interrupt, such as receiving a GPIO OCP interrupt, that is, an overcurrent protection interrupt signal sent to the processor through the GPIO (General-purpose input / output) pin, the state machine reads the state information Status of the corresponding register. If the state information Status indicates that OCP_Int=1 represents an overcurrent protection interrupt, the OCP function is controlled, such as the MPU writing new configuration parameters (such as the working frequency) into the register Register unit corresponding to the voltage-controlled oscillator feedback divider (VCO_FB - divider) and the post divider, and increasing their frequency division ratios. The target working frequency is processed by the voltage-controlled oscillator feedback divider VCO_FB - divider and the post divider, so that the clock frequency finally output to each module of the system is reduced.

[0057] The waveform of the frequency output controlled by the OCP is as shown in Figure 3 Specifically, when the state machine FSM receives an OCP interrupt, the OCP function is controlled, and the response stage response stage is first, and the frequency is gradually reduced to cause overcurrent protection. When the OCP interrupt is detected to recover, the frequency is gradually increased back to the original working frequency.

[0058] It can be understood that the frequency adjustment of the OCP can be divided into multiple stages (also described as frequency adjustment intervals, steps, stages), each stage corresponding to a frequency adjustment operation, such as increasing the frequency or decreasing the frequency, so that in the response stage response stage of the OCP interrupt, the frequency is gradually decreased, and after the OCP interrupt recovers, the frequency is gradually increased. The frequency values adjusted by each stage of the OCP can be the same or different, and the present application does not make specific limitations.

[0059] In the embodiment of the present application, based on the principle of reducing the frequency by changing the post divider to achieve the effect of overcurrent protection OCP, the frequency values of each stage stage of overcurrent protection are calculated based on the multiple of the post divider. Among them, the clock frequency is calculated as follows:

[0060] Output = Refer_clock PLL_FBDIV / post-divider (1) ;

[0061] Wherein, Refer_clock represents the reference clock frequency input to the phase-locked loop PLL, such as the target working frequency, PLL_FBDIV (feedback divider) represents the frequency multiplication setting of the feedback divider inside the phase-locked loop PLL, such as the feedback division ratio; post divider represents the frequency division setting of the post divider inside the phase-locked loop PLL, such as the multiple N; Output represents the clock frequency output by the system.

[0062] Based on the above formula (1), it can be known that the OCP effect is realized by increasing the value of the post divider, that is, reducing the frequency. In the embodiment of the present application, the multiple of the post divider is increased or decreased according to a preset step, and the response stage of the OCP interruption and the target multiple required in each stage after the OCP interruption is recovered are determined. For example, the frequency division ratio of the post divider is 6, and the step is 1. For the response stage of the OCP interruption, the target multiple of the first stage stage0 of the OCP is N+1=6+1, the target multiple of the second stage stage1 of the OCP is N+2=6+2, the target multiple of the third stage stage2 of the OCP is N+3=6+3, and the target multiple of the fourth stage stage0 of the OCP is N+4=6+4, and so on. Correspondingly, after the OCP interruption is recovered, the target multiple of the first stage stage5 of the OCP is 6+4, the target multiple of the second stage stage6 of the OCP is 6+3, the target multiple of the third stage stage7 of the OCP is 6+2, and the target multiple of the fourth stage stage8 of the OCP is 6+1, and so on. It can be understood that the frequency control of the response stage of the OCP interruption and the frequency control after the OCP interruption is recovered are symmetrical.

[0063] According to the target working frequency, the feedback division ratio of the phase-locked loop, and the target multiple required in each stage of the OCP, the frequency values in each stage are calculated, so that the control frequency of the OCP can be gradually reduced to realize overcurrent protection, and when the OCP interruption disappears, the working frequency can be gradually recovered to the original working frequency. For example, the frequency values in each stage = Refer_clock PLL_FBDIV / target multiple (such as N+1, N+2, N+3, N+4, etc.). One example of the frequency values in each stage of the OCP is shown in the table. Figure 4

[0064] ​The embodiment of the present application prepares the target working frequency based on the frequency conversion mechanism, calculates the frequency values of each stage of the OCP by changing the multiple of the post frequency divider, can make the frequency adjustment of the OCP more accurate, avoid over-protection or insufficient protection, and at the same time, through the stepwise descending or rising mode for the OCP frequency control, can make the frequency transition more stable, reduce the impact of the frequency mutation on the system when the OCP interrupt trigger or recovery.

[0065] In an optional embodiment, when the target working frequency is configured by the second register, the frequency values of each stage in the first register are transmitted to the third register, comprising:

[0066] When the second register configures the target working frequency, the update enable signal of the set bit in the second register is reset; wherein the update enable signal includes the clock pulse signal of the plurality of flip-flops of the third register;

[0067] When the update enable signal is reset, the first register transmits the frequency values of each stage to the second register.

[0068] In the embodiment of the present application, when the first register OCP_REG_A is configured, the target working frequency is configured by the second register (i.e. the fout post divider register), the set bit bit of the second register is used to store the update enable signal (i.e. the update_OCP_REG_B signal), the update_OCP_REG_B signal includes the clock pulse signal (i.e. the CP signal) of the plurality of flip-flops of the third register OCP_REG_B, and each time the second register (the fout post divider register) is configured, the above set bit bit is reset to trigger the data (such as the frequency values of each stage of the OCP) of the first register OCP_REG_A to be transmitted to the third register OCP_REG_B. Since the action of transmitting the data of the first register OCP_REG_A to the third register OCP_REG_B is a hardware behavior, i.e. the frequency configuration of the OCP is refreshed by the FW, the speed will be very fast, and the update of the third register OCP_REG_B falling behind the frequency update of the fout post divider register can be basically ignored, which ensures that the change of the OCP frequency and the change of the working frequency are synchronous, so as to realize the dynamic configuration of the OCP frequency.

[0069] Consider the following two scenarios: (1) The operating frequency is changed, and then the OCP interrupt is triggered, but the new OCP frequency configuration has not yet been successfully configured; (2) If the OCP frequency configuration is changed before the operating frequency is configured, but the OCP interrupt is triggered before the operating frequency is configured. In this embodiment of the invention, the problem of mismatch between the frequency configuration of OCP execution and the operating frequency when releasing OCP is caused by the above two scenarios. For example, either the OCP frequency is higher than the operating frequency, which not only fails to perform the function of OCP but may also cause a larger overcurrent and a large power supply noise, or the frequency of OCP is reduced too much, causing a large power supply noise. In order to reduce the power supply noise caused by frequency change when executing OCP, the frequency value of each stage of OCP is configured according to the target operating frequency to be configured, so that the operating frequency adjustment range can be large and there is no need to worry that the OCP frequency cannot match the new operating frequency, so as not to meet the overcurrent protection. At the same time, by using the step-down or rise method to control the OCP frequency, the frequency adjustment when executing OCP can be more accurate, the frequency transition can be more stable, and the power supply noise when the frequency changes during OCP interruption triggering or recovery can be reduced.

[0070] Specifically, the first register transfers the frequency values ​​of each stage to the second register, including:

[0071] The frequency values ​​of each stage stored in the multiple flip-flops in the first register are transmitted in parallel and synchronously to the multiple flip-flops in the second register;

[0072] In this configuration, multiple flip-flops in the first register correspond one-to-one with multiple flip-flops in the second register for data transmission; one or more flip-flops in the first register are used to store the frequency value of a stage.

[0073] like Figure 5 As shown, when the second register OCP_REG_B receives the update enable signal Update_EN, it requests the frequency values ​​of each stage of OCP from the first register OCP_REG_A. The first register OCP_REG_A updates the frequency values ​​(i.e., frequency configuration) of each stage of OCP to the second register OCP_REG_B through the FW method.

[0074] It can be understood that the first register OCP_REG_A or the second register OCP_REG_B can store the frequency values of one stage through a group of flip-flops (including one or more flip-flops), for example, 3 flip-flops as a group, the first 3 flip-flops store the frequency values of the first stage, the 4-6 flip-flops store the frequency values of the second stage, and so on. When refreshing the frequency configuration of the second register OCP_REG_B through the FW, the data of each flip-flop in the first register OCP_REG_A is transmitted to the corresponding flip-flop in the second register OCP_REG_B in a synchronous and parallel manner. For example, the flip-flop D numbered FF0 in the first register OCP_REG_A synchronously transmits data to the flip-flop D numbered FF0 in the second register OCP_REG_B, the flip-flop D numbered FF1 in the first register OCP_REG_A synchronously transmits data to the flip-flop D numbered FF1 in the second register OCP_REG_B, and so on.

[0075] The embodiment of the application can basically ignore that the update of the third register OCP_REG_B lags behind the frequency update of the fout post divider register through the FW to refresh the frequency configuration of the OCP, ensures the synchronous update of the OCP frequency and the working frequency, and further realizes the dynamic configuration of the OCP frequency.

[0076] Specifically, the method comprises:

[0077] transmitting the frequency values of each stage to the plurality of flip-flops of the first register in a serial manner;

[0078] The plurality of flip-flops of the first register are triggered by the system clock signal to transmit and store data.

[0079] In the embodiment of the application, the system clock signal clk based on the system clock clock triggers the update of the frequency configuration of the first register, and the data of each flip-flop of the first register is updated in a serial manner. As shown in Figure 5 The first register OCP_REG_A sequentially transmits the frequency values of each stage according to the order of the flip-flop D numbers FF0-FF31. It is considered that the first register OCP_REG_A is not the state machine corresponding to the register executed at the time of the OCP interrupt, and the plurality of flip-flops of the first register OCP_REG_A are updated in a serial manner, which can reduce the wiring complexity, and the use of the system clock signal to coordinate the data update of the flip-flop can improve the system stability.

[0080] Further, the method further comprises:

[0081] When an overcurrent protection interruption is detected, the state machine reads the frequency values ​​of each stage of the overcurrent protection stored in the third register.

[0082] The state machine adjusts the output frequency of the phase-locked loop based on the frequency values ​​read from each stage.

[0083] Specifically, the state machine adjusts the output frequency of the phase-locked loop based on the frequency values ​​read from each stage, including:

[0084] During the response phase of overcurrent protection interruption, the output frequency of the phase-locked loop is adjusted down stepwise according to the frequency values ​​of each stage of overcurrent protection until the overcurrent protection interruption recovery is detected.

[0085] When an overcurrent protection interruption recovery is detected, the output frequency of the phase-locked loop is adjusted stepwise according to the frequency values ​​of each stage of the overcurrent protection until the output frequency of the phase-locked loop is restored to the target operating frequency.

[0086] In this embodiment of the invention, when the state machine receives an OCP interrupt, it uses the frequency configuration of the second register OCP_REG_B to perform OCP frequency control, such as... Figure 6 As shown. Specifically, firstly, in the response stage, the frequency is reduced according to the frequency values ​​of each stage to achieve overcurrent protection, for example... Figure 4 When PLL_FBDIV=240 and N=6, N+1, N+2, N+3, and N+4 correspond to frequency values ​​of 857MHz, 750MHz, 667MHz, and 600MHz, respectively. The operating frequency of OCP is gradually reduced in the order of 857MHz, 750MHz, 667MHz, and 600MHz to achieve overcurrent protection.

[0087] When an OCP interrupt is detected and recovered, the frequency is gradually increased back to the original operating frequency according to the frequency value of the corresponding stage. For example, in the response stage, if the frequency is reduced to the frequency value of 600MHz corresponding to N+4 and the OCP interrupt is detected and recovered, the OCP operating frequency is gradually increased in the order of 600MHz, 667MHz, 750MHz, and 857MHz. Or, in the response stage, if the frequency is reduced to the frequency value of 750MHz corresponding to N+2 and the OCP interrupt is detected and recovered, the OCP operating frequency is gradually increased in the order of 750MHz and 857MHz.

[0088] The embodiment of the present application configures the frequency values of each stage of OCP according to the target working frequency to be configured, so that the working frequency range can be large and the frequency of OCP does not need to be worried about matching the new working frequency, so as to meet the over-current protection, realize the dynamic configuration of the frequency of each stage of OCP, save the register; at the same time, the OCP frequency control is performed in the way of stepwise decline or rise, so that the frequency adjustment during the execution of OCP is more accurate, the frequency transition is more stable, and the power supply noise during the frequency change when the OCP interrupt trigger or recovery is reduced. Secondly, compared with the traditional scheme of configuring the frequency of OCP in the post divider register of Fout, the embodiment of the present application realizes the synchronous update of the OCP frequency and the working frequency, does not need to add the frequency register of OCP to each post-divider register of Fout, does not need to sacrifice the bit number of the frequency register of OCP, reduces the influence on the number of controllable steps of CP (Clock Pulse, clock pulse), and improves the flexibility of the frequency configuration of OCP.

[0089] Referring to Figure 7 , Figure 7 is a structural block diagram of a processor provided by the embodiment of the present application, the processor comprises a first register 11, a second register 12 and a third register 13.

[0090] The first register 11 is used for storing the frequency values of each stage of over-current protection; wherein the frequency values of each stage are determined according to the target working frequency.

[0091] The second register 12 is used for configuring the target working frequency; wherein the second register 12 is a frequency configuration register used for indicating the post-divider.

[0092] The third register 13 is configured to: when the target working frequency is configured through the second register 12, the frequency values of each stage in the first register 11 are transmitted to the third register 13; wherein the third register 13 is a frequency configuration register used for indicating the frequency values used by the state machine in each stage.

[0093] The processor can be any one of a GPGPU (General-purpose computing on graphics processing units), a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), a NPU (Neural network Processing Unit), a DPU (Deep learning Processing Unit), an APU (Accelerated Processing Unit), and a GPGPU (General-Purpose Graphics Processing Unit), and the application does not make specific limitations.

[0094] It should be noted that the working processes of the first register, the second register and the third register of the processor according to the embodiments of the application can refer to the working processes of the receiving side in the frequency control method for overcurrent protection described in the above embodiments, and the technical effects achieved are the same as those of the frequency control method for overcurrent protection described in the above embodiments, and thus will not be described herein again.

[0095] The embodiments of the application further provide a non-volatile computer readable storage medium storing a computer program, wherein the computer program controls a device where the non-volatile computer readable storage medium is located to perform the frequency control method for overcurrent protection according to the above embodiments when the computer program is running.

[0096] The embodiments of the application further provide a computer program product including a computer program or instructions, which, when executed by a processor, implement the frequency control method for overcurrent protection according to the above embodiments.

[0097] Exemplarily, the non-volatile computer readable storage medium can be used to store the computer program and / or modules, the processor executes the overcurrent protection frequency control method by running or executing the computer program and / or modules stored in the non-volatile computer readable storage medium and calling the data stored in the non-volatile computer readable storage medium. The non-volatile computer readable storage medium can mainly include a program storage area and a data storage area, wherein the program storage area can store an operating system, at least one application program required by a function (such as a sound playing function, an image playing function, etc.), etc.; and the data storage area can store data created according to the use of the mobile phone (such as audio data, a phone book, etc.), etc. In addition, the non-volatile computer readable storage medium can include a high-speed random access memory, and can also include a non-volatile memory, for example, a hard disk, a memory, a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, at least one disk storage device, a flash memory device, or other volatile solid-state storage devices.

[0098] It should be noted that the apparatus embodiments described above are merely illustrative, wherein the units described as separate components can or can not be physically separated, and the components displayed as units can or can not be physical units, i.e., can be located in one place, or can be distributed to multiple network units. Part or all of the modules can be selected to achieve the purpose of the embodiment according to actual needs. In addition, the connection relationship between the modules in the apparatus embodiments provided by the present application indicates that there is a communication connection between them, which can be implemented as one or more communication buses or signal lines. Those skilled in the art can understand and implement it without creative labor.

[0099] The above is the preferred embodiment of the present application, and it should be noted that those skilled in the art can make various improvements and refinements without departing from the principles of the present application, and these improvements and refinements are also considered within the protection scope of the present application.

Claims

1. A method of frequency control with overcurrent protection, characterized in that, The method comprises: determining frequency values of each stage of the over-current protection according to a target working frequency, and configuring the frequency values of each stage of the over-current protection to a first register; when the target working frequency is configured through a second register, transmitting the frequency values of each stage in the first register to a third register; wherein the second register is a frequency configuration register for indicating a post-divider, and the third register is a frequency configuration register for indicating frequency values used by a state machine in each stage.

2. The overcurrent-protected frequency control method of claim 1, wherein, The transmitting the frequency values of each stage in the first register to the third register when the target working frequency is configured through the second register comprises: when the target working frequency is configured through the second register, resetting an update enable signal of a set bit in the second register; wherein the update enable signal comprises clock pulse signals of a plurality of flip-flops of the third register; when the update enable signal is reset, the first register transmits the frequency values of each stage to the second register.

3. The overcurrent-protected frequency control method of claim 2, wherein, The transmitting the frequency values of each stage in the first register to the second register comprises: the frequency values of each stage stored in the plurality of flip-flops in the first register are transmitted in parallel and synchronously to the plurality of flip-flops in the second register; wherein the plurality of flip-flops in the first register are transmitted one by one to the plurality of flip-flops in the second register; one or more flip-flops in the first register are used to store the frequency value of one stage.

4. The overcurrent-protected frequency control method of claim 1, wherein, The configuring the frequency values of each stage of the over-current protection to the first register comprises: the frequency values of each stage are transmitted to the plurality of flip-flops in the first register in a serial manner; wherein the plurality of flip-flops in the first register are triggered by a system clock signal to transmit and store data.

5. The overcurrent-protected frequency control method of claim 1, wherein, The determining the frequency values of each stage of the over-current protection according to the target working frequency comprises: determining target multiples of each stage of the over-current protection according to a multiple of the post-divider; calculating the frequency values of each stage according to the target working frequency, the target multiples of each stage, and a frequency multiplication of a phase-locked loop.

6. The overcurrent-protected frequency control method of claim 1, wherein, The method further comprises: when an over-current protection interruption is detected, the state machine reads the frequency values of each stage of the over-current protection stored in the third register; the state machine adjusts an output frequency of the phase-locked loop according to the read frequency values of each stage.

7. The overcurrent-protected frequency control method of claim 6, wherein, The adjusting the output frequency of the phase-locked loop according to the read frequency values of each stage by the state machine comprises: in a response stage of the over-current protection interruption, performing a stepwise down operation on the output frequency of the phase-locked loop according to the frequency values of each stage of the over-current protection, until it is detected that the over-current protection interruption is recovered; when the over-current protection interruption recovery is detected, performing a stepwise up operation on the output frequency of the phase-locked loop according to the frequency values of each stage of the over-current protection, until the output frequency of the phase-locked loop recovers to the target working frequency.

8. A processor, characterized in that, The method comprises: a first register, a second register, and a third register; the first register is used to store frequency values of each stage of the over-current protection; wherein the frequency values of each stage are determined according to a target working frequency. The second register is configured to configure the target operating frequency; wherein the second register is a frequency configuration register for indicating a post-divider; The third register is configured to, when the target operating frequency is configured through the second register, transmit the frequency values of each stage in the first register to the third register; wherein the third register is a frequency configuration register for indicating the frequency values used by a state machine in each stage.

9. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program, wherein the computer program controls a device where the computer readable storage medium is located to execute the over-current protection frequency control method of any one of claims 1 to 7 when the computer program is running.

10. A computer program product comprising computer programs or instructions, characterized in that, The computer program or the instructions are executed by the processor to implement the over-current protection frequency control method of any one of claims 1 to 7.

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