Charge pump circuit and operation method of charge pump circuit

Abstract

The invention provides a charge pump circuit and an operation method of the charge pump circuit. The charge pump circuit includes a voltage converter and a pre-charge circuit. The voltage converter is configured to receive a first voltage and convert the first voltage to a second voltage. The first voltage is greater than the second voltage. The pre-charge circuit is coupled to the voltage converter. The pre-charge circuit is configured to charge a specified node of the voltage converter from a third voltage to a fourth voltage during the first charge. The voltage converter charges the designated node from the fourth voltage to the first voltage during the second charging. The fourth voltage is greater than the third voltage, and the third voltage and the fourth voltage are between the first voltage and the second voltage.

Description

TECHNICAL FIELD

[0001] The present invention relates to an electronic circuit and an operating method thereof, and more particularly, to a charge pump circuit and an operating method thereof. BACKGROUND

[0002] The control structure of charge pump circuits, such as negative voltage charge pumps, can be mainly divided into two categories. The first category is pulse frequency modulation (PFM), which has the advantage of high light load efficiency, but is accompanied by the disadvantage of excessive output voltage ripple. The second category is pulse amplitude modulation (PAM), which has the characteristics of low output voltage ripple and high light load power consumption due to power loss of power transistors, but results in low light load efficiency. SUMMARY

[0003] The present invention relates to a charge pump circuit and an operating method thereof, which can reduce power loss of power transistors through a pre-charge operation.

[0004] An embodiment of the present invention provides a charge pump circuit including a voltage converter and a pre-charge circuit. The voltage converter is configured to receive a first voltage and convert the first voltage to a second voltage. The first voltage is greater than the second voltage. The pre-charge circuit is coupled to the voltage converter. The pre-charge circuit is configured to charge a particular node of the voltage converter from a third voltage to a fourth voltage during a first charging period. The voltage converter charges the particular node from the fourth voltage to the first voltage during a second charging period. The fourth voltage is greater than the third voltage, and the third voltage and the fourth voltage are between the first voltage and the second voltage.

[0005] An embodiment of the present invention provides an operating method of a charge pump circuit. The charge pump circuit is configured to convert a first voltage to a second voltage. The operating method includes charging a particular node of the voltage converter from a third voltage to a fourth voltage during a first charging period, wherein the fourth voltage is greater than the third voltage, and the third voltage and the fourth voltage are between the first voltage and the second voltage; charging the particular node from the fourth voltage to the first voltage during a second charging period; discharging the particular node from the first voltage to the third voltage during a discharging period; and converting the third voltage on the particular node to the second voltage, wherein the first voltage is greater than the second voltage.

[0006] In order to make the foregoing more readily understood, the several embodiments will be described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0007] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain principles of the present disclosure.

[0008] Figure 1 is a block diagram of a charge pump circuit according to an embodiment of the present invention.

[0009] Figure 2 is a circuit diagram of a voltage converter according to an embodiment of the present invention. Figure 1

[0010] Figure 3 is a waveform diagram of a control signal and a drain end voltage according to an embodiment of the present invention. Figure 2

[0011] Figure 4 is a circuit diagram of a charge pump circuit according to an embodiment of the present invention. Figure 1

[0012] Figure 5 is a flowchart of steps of an operation method of a charge pump circuit according to an embodiment of the present invention.

[0013] Figure 6 is a graph showing a reduction in operating current at different operating frequencies according to an embodiment of the present invention.

[0014] Figure 7 is a graph showing a reduction in operating current at different pre-charge voltages according to an embodiment of the present invention.

[0015] BRIEF DESCRIPTION OF DRAWINGS

[0016] 100: charge pump circuit

[0017] 110: voltage converter

[0018] 112: amplifier

[0019] 120: pre-charge circuit

[0020] 122: first switching circuit

[0021] 124: first control circuit

[0022] 130: voltage boosting circuit

[0023] 140: second control circuit

[0024] AVDD: first voltage

[0025] AVEE: second voltage

[0026] C1: capacitor ​​​

[0027] CHG: second control signal

[0028] CLK: frequency signal

[0029] DSG: third control signal

[0030] DT1: dead time

[0031] DT2: dead time

[0032] GND: third voltage

[0033] MN1, MN2, MN3, MP1: power transistor

[0034] ND: designated node\drain end

[0035] PCHG: first control signal

[0036] S100, S110, S120, S130: method steps

[0037] T1: first charging period

[0038] T2: second charging period

[0039] T3: discharging period

[0040] VD: voltage of drain end

[0041] VIN: pre-charge voltage DETAILED DESCRIPTION

[0042] The term "coupled (or connected)" used in the present specification (including the claims) can refer to any direct or indirect connection. For example, "a first device coupled to a second device" should be interpreted as "a first device directly connected to a second device" or "a first device indirectly connected to a second device through other devices or connection means". The terms "first" and "second" mentioned in the present specification (including the claims) are used for naming elements or distinguishing different embodiments or ranges, and are not used to limit the upper or lower number of elements, nor to limit the order of elements. In addition, in the drawings and embodiments, the same reference numbers of elements / devices / steps are used as much as possible to represent the same or similar parts. The elements / elements / steps using the same numbers or the same terms in different embodiments can be used as cross-references to each other.

[0043] Figure 1 is a block diagram of a charge pump circuit according to an embodiment of the present application. Figure 2 is a circuit diagram of a voltage converter according to an embodiment of the present application. Figure 1 Figure 3 is a circuit diagram of a voltage converter according to an embodiment of the present application. Figure 2 ​a waveform diagram of the control signal and the drain terminal voltage.

[0044] Referring to Figures 1 to 3 The charge pump circuit 100 includes a voltage converter 110 and a pre-charge circuit 120. The pre-charge circuit 120 includes a first switch circuit 122 and a first control circuit 124. The charge pump circuit 100 further includes a boost circuit 130 and a second control circuit 140. The charge pump circuit 100 can be implemented in a power management integrated circuit (PMIC), but the present application is not limited thereto.

[0045] The voltage converter 110 is configured to receive a first voltage AVDD from the boost circuit 130 and convert the first voltage AVDD into a second voltage AVEE. The boost circuit is configured to receive a pre-charge voltage VIN, boost the pre-charge voltage VIN into the first voltage AVDD, and output the first voltage AVDD to the voltage converter 110.

[0046] Referring to Figure 2 The voltage converter 110 includes a plurality of power transistors MP1, MN1, MN2, and MN3, and a capacitor C1. The power transistor MP1 is a p-type metal-oxide-semiconductor (PMOS) transistor, and the power transistors MN1, MN2, and MN3 are n-type metal-oxide-semiconductor (NMOS) transistors.

[0047] Taking the power transistor MP1 as an example, a first terminal of the power transistor MP1 (the second switch circuit) is coupled to the first voltage AVDD, a second terminal of the power transistor MP1 is a drain terminal ND and serves as a designated node of the voltage converter 110, and a control terminal of the power transistor MP1 is coupled to a second control signal CHG. In the embodiment of the present application, the designated node of the voltage converter 110 is the drain terminal ND of the power transistor MP1. The first control circuit 124 outputs the second control signal CHG to the power transistor MP1 to control a conduction state of the power transistor MP1. When the power transistor MP1 is turned on according to the second control signal CHG, the voltage converter 110 charges the drain terminal ND of the power transistor MP1 to the first voltage AVDD during a second charging period T2. Therefore, the capacitor C1 is charged to the first voltage AVDD and stores energy during the second charging period T2.

[0048] On the other hand, a first terminal of a power transistor MN1 (third switch circuit) is coupled to the drain terminal ND of the power transistor MP1, a second terminal of the power transistor MN1 is coupled to a third voltage GND, and a control terminal of the power transistor MN1 is coupled to a third control signal DSG. The second control circuit 140 outputs the third control signal DSG to the power transistor MN1 to control the on state of the power transistor MN1. When the power transistor MN1 is turned on according to the third control signal DSG, the voltage converter 110 discharges the drain terminal ND of the power transistor MP1 from the first voltage AVDD to the third voltage GND during a discharge period T3. The discharge period T3 is after the second charge period T2. The operations of the power transistors MN2 and MN3 can be similarly performed, and thus are not described herein. Thus, the energy stored in the capacitor C1 can be discharged in a charge sharing manner to generate the second voltage AVEE at the output terminal of the voltage converter 110.

[0049] By switching the power transistors MP1, MN1, MN2, and MN3, the capacitor C1 is charged with the first voltage AVDD and discharged with the third voltage GND, so that the voltage converter 110 can provide the second voltage AVEE. The voltage converter 110 can be a negative charge pump converter, and thus the first voltage AVDD is greater than the second voltage AVEE.

[0050] Since the carrier mobility of the PMOS transistor is worse than that of the NMOS transistor, in order to maintain the same on resistance, the power transistor MP1 must be designed to be large. However, a large size of the power transistor has a large drain parasitic capacitance. At the beginning of each charge period, if the voltage VD of the drain terminal ND of the power transistor MP1 is directly charged from the third voltage GND to the first voltage AVDD, a large power loss can be caused by the drain parasitic capacitance of the power transistor MP1 during each charge and discharge period, so that the basic operating power consumption of the voltage converter 110 cannot be reduced, thereby affecting the overall conversion efficiency.

[0051] At least to overcome the above problems, the pre-charge circuit 120 is configured to perform a pre-charge operation on the drain terminal ND of the power transistor MP1 during the first charge period T1, so that the voltage VD of the drain terminal ND of the power transistor MP1 can be pre-charged from the third voltage GND to a pre-charge voltage VIN (fourth voltage). In this way, the power loss of the power transistor MP1 can be reduced by the pre-charge operation.

[0052] Specifically, the pre-charge circuit 120 charges the drain end ND of the power transistor MP1 from the third voltage GND to the pre-charge voltage VIN during the first charging period T1. Then, the voltage converter 110 charges the drain end ND of the power transistor MP1 from the pre-charge voltage VIN to the first voltage AVDD during the second charging period T2. Thus, the drain end ND of the power transistor MP1 is pre-charged from the third voltage GND to the pre-charge voltage VIN, and the voltage VD of the drain end ND of the power transistor MP1 is not directly charged from the third voltage GND to the first voltage AVDD. By the pre-charge operation, the power loss caused by the drain parasitic capacitance of the power transistor MP1 during each charge-discharge period can be reduced.

[0053] In the embodiment, as shown in Figure 3 , the first charging period T1 is a charging period, which is prior to the second charging period T2, and the first charging period T1 and the second charging period T2 are consecutive periods. In addition, there is a dead time DT1 between the first charging period T1 and the previous discharging period T3, and there is a dead time DT2 between the second charging period T2 and the next discharging period T3.

[0054] In the embodiment, the fourth voltage is the pre-charge voltage VIN, as shown in Figure 3 , the pre-charge voltage VIN is greater than the third voltage GND, and the third voltage GND and the pre-charge voltage VIN are between the first voltage AVDD and the second voltage AVEE. The difference between the pre-charge voltage VIN and the third voltage GND is greater than the difference between the first voltage AVDD and the pre-charge voltage VIN. In the embodiment, the third voltage GND is a ground voltage.

[0055] In the embodiment, the first control circuit 124 and the second control circuit 140 can be designed by a hardware description language (HDL) or any other digital circuit design method familiar to those skilled in the art, and can be implemented by a field programmable gate array (FPGA), a complex programmable logic device (CPLD), or a specific application integrated circuit (ASIC). In addition, regarding the hardware structure of the first switch circuit 122 and the boost circuit 130, sufficient teaching, suggestion, and implementation instructions can be obtained from the known common sense in the related art.

[0056] Figure 4 is a circuit diagram of a charge pump circuit according to the embodiment of the present application Figure 1 . Please refer to Figure 3 and Figure 4 , the boost circuit 130 boosts the pre-charge voltage VIN to the first voltage AVDD and outputs the first voltage AVDD to the voltage converter 110. The first voltage AVDD is input to the voltage converter 110 as a voltage source for voltage conversion.

[0057] The first switch circuit 122 has a back-to-back NMOS structure and is controlled by the first control signal PCHG. The first end of the first switch circuit 122 is coupled to the pre-charge voltage VIN, the second end of the first switch circuit 122 is coupled to the drain end ND of the power transistor MP1, and the control end of the first switch circuit 122 is coupled to the first control signal PCHG. When the first switch circuit 122 is turned on according to the first control signal PCHG, the pre-charge circuit 120 can charge the drain end ND of the power transistor MP1 during the first charging period T1. The first switch circuit 122 with a back-to-back NMOS structure can avoid the current flowing from the drain end ND of the power transistor MP1 to the first end of the first switch circuit 122 in the first charging period T1. The structure of the first switch circuit 122 is not limited in the present application.

[0058] On the other hand, the second control circuit 140 is configured to receive the frequency signal CLK and generate the second control signal CHG and the third control signal DSG. The second control circuit 140 outputs the second control signal CHG to the first control circuit 124. The first control circuit 124 receives the second control signal CHG and generates the first control signal PCHG according to the second control signal CHG. The first control circuit 124 outputs the first control signal PCHG to the first switch circuit 122 to control the on-off state of the first switch circuit 122. The second control circuit 140 outputs the third control signal DSG to the power transistors MN1 and MN3 to control the on-off state of the power transistors MN1 and MN3.

[0059] The first control circuit 124 and the second control circuit 140 can be integrated into a single control circuit and serve as a non-overlap circuit, but the present application is not limited thereto. The first control signal PCHG, the second control signal CHG, and the third control signal DSG are configured to control the operations of pre-charging / charging and discharging so that these operations are not overlapped in time sequence.

[0060] Then, the voltage converter 110 can operate in a pulse amplitude modulation (PAM) mode. The charging period T2 and the discharging period T3 are continuously interleaved, and the power transistors MP1 and MN1 are frequently switched. After the end of the discharging period T3, the pre-charge period T1 is added to charge the drain end ND of the power transistor MP1 to the pre-charge voltage VIN, and then the charging period T2 is started by turning on the power transistors MP1 and MN2 to charge the voltage across the capacitor to the first voltage AVDD, and the charging period T2 is completed. As shown, the addition of pre-charge can reduce the overall power consumption of the first voltage AVDD by converting the power loss of the power transistors into the pre-charge voltage VIN. Figure 3 As shown, the addition of pre-charge can reduce the overall power consumption of the first voltage AVDD by converting the power loss of the power transistors into the pre-charge voltage VIN.

[0061] In addition, the voltage converter 110 further comprises a plurality of amplifiers 112 coupled to the corresponding power transistors. The amplifiers can process the corresponding control signals as buffers or inverters.

[0062] Figure 5 is a step flowchart of an operation method of the charge pump circuit according to an embodiment of the present application. Please refer to Figures 1 to 3 and Figure 5 The operation method of the present embodiment is applicable to at least the charge pump circuit 100 shown in Figure 1 , but the present application is not limited thereto.

[0063] Taking the charge pump circuit 100 as an example, in step S100, the pre-charge circuit 120 charges a designated node ND of the voltage converter 110 from a third voltage GND to a fourth voltage VIN during a first charging period T1. In step S110, the voltage converter 110 charges the designated node ND of the voltage converter 110 from the fourth voltage VIN to a first voltage AVDD during a second charging period T2. In step S120, the voltage converter 110 discharges the designated node ND of the voltage converter 110 from the first voltage AVDD to the third voltage GND during a discharging period T3. In step S130, the voltage converter 110 converts the third voltage GND on the designated node ND of the voltage converter 110 to a second voltage AVEE. For example, the energy stored in the capacitor C1 can be released in a charge sharing manner to generate the second voltage AVEE at the output of the voltage converter 110.

[0064] The operation method of the charge pump circuit according to the embodiments of the present application can obtain sufficient teaching, suggestion and implementation description in Figures 1 to 4 , and thus will not be described in detail.

[0065] Figure 6 is a curve diagram showing the reduction of operating current at different operating frequencies according to an embodiment of the present application. Please refer to Figure 6 The charge pump circuit 100 can operate at a frequency between 600 to 1200 kilohertz (kHz) and apply a designated fixed pre-charge voltage. Compared with the charge pump circuit without pre-charge operation, the operating current of the present embodiment is reduced by 17% to 20%. The reduction of operating current indicates that the power loss can be reduced by the pre-charge operation.

[0066] Figure 7 is a curve diagram showing the reduction of operating current at different pre-charge voltages according to an embodiment of the present application. Please refer to Figure 7, the charge pump circuit 100 can operate at a specified frequency and a pre-charge voltage between 2.5 to 4.5 volts is applied to the charge pump circuit 100. The operating current of the embodiment of the present application is reduced by between 10% to 30% compared to a charge pump circuit without pre-charge operation. The reduction in operating current indicates that power dissipation can be reduced by the pre-charge operation.

[0067] From Figure 6 and Figure 7 it can be seen that by different operating frequencies and pre-charge voltages, the basic operating power dissipation of the voltage converter 110 can be reduced by 10-30% to achieve energy saving effects.

[0068] In summary, in the embodiment of the present application, the pre-charge circuit pre-charges the drain terminal of the power transistor to a pre-charge voltage before the drain terminal of the power transistor is charged to the first voltage. The voltage of the drain terminal of the power transistor is not directly charged from the third voltage to the first voltage. Therefore, by the pre-charge operation, the power dissipation due to the drain parasitic capacitance of the power transistor during each charge and discharge period can be reduced.

[0069] It will be understood by those skilled in the art that various modifications and changes can be made without departing from the scope or spirit of the present disclosure. In view of the foregoing, it is the intent of the present disclosure to cover modifications and variations of the present disclosure provided they come within the scope of the appended claims and their equivalents.

Claims

1. A charge pump circuit, comprising: a voltage converter configured to receive a first voltage and convert the first voltage to a second voltage, wherein the first voltage is greater than the second voltage; and a pre-charge circuit coupled to the voltage converter and configured to charge a designated node of the voltage converter from a third voltage to a fourth voltage during a first charging period, wherein the voltage converter charges the designated node from the fourth voltage to the first voltage during a second charging period, wherein the fourth voltage is greater than the third voltage, and the third voltage and the fourth voltage are between the first voltage and the second voltage. 2.The charge pump circuit of claim 1, wherein the first charging period is prior to the second charging period. 3.The charge pump circuit of claim 1, wherein the first charging period and the second charging period are consecutive periods. 4.The charge pump circuit of claim 1, wherein the voltage converter discharges the designated node from the first voltage to the third voltage during a discharging period. 5.The charge pump circuit of claim 4, wherein the discharging period is after the second charging period. 6.The charge pump circuit of claim 1, wherein a difference between the fourth voltage and the third voltage is greater than a difference between the first voltage and the fourth voltage. 7.The charge pump circuit of claim 1, further comprising: a boost circuit coupled to the voltage converter and configured to receive the fourth voltage, boost the fourth voltage to the first voltage, and output the first voltage to the voltage converter. 8.The charge pump circuit of claim 1, wherein the pre-charge circuit comprises: a first switch circuit comprising a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first switch circuit is coupled to the fourth voltage, the second terminal of the first switch circuit is coupled to the designated node, and the control terminal of the first switch circuit is coupled to a first control signal, wherein the pre-charge circuit charges the designated node during the first charging period when the first switch circuit is turned on according to the first control signal. 9.The charge pump circuit of claim 8, wherein the pre-charge circuit further comprises: a first control circuit coupled to the first switch circuit and configured to output the first control signal to the first switch circuit. 10.The charge pump circuit of claim 9, further comprising: a second control circuit coupled to the first control circuit and configured to receive a frequency signal and generate and output a second control signal to the first control circuit according to the frequency signal, wherein the first control circuit receives the second control signal and generates the first control signal according to the second control signal. 11.The charge pump circuit of claim 10, wherein the voltage converter comprises: ​ a second switch circuit including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the second switch circuit is coupled to the first voltage, the second terminal of the second switch circuit is the designated node, and the control terminal of the second switch circuit is coupled to a second control signal, wherein the first control circuit further outputs the second control signal to the second switch circuit, and when the second switch circuit is turned on according to the second control signal, the voltage converter charges the designated node during a second charging period.

12. The charge pump circuit of claim 10, wherein the voltage converter comprises: a third switch circuit including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the third switch circuit is coupled to the designated node, the second terminal of the third switch circuit is coupled to a third voltage, and the control terminal of the third switch circuit is coupled to a third control signal, wherein the second control circuit further generates and outputs the third control signal to the third switch circuit according to the frequency signal, and when the third switch circuit is turned on according to the third control signal, the voltage converter discharges the designated node during a discharging period.

13. A method of operating a charge pump circuit, wherein the charge pump circuit is configured to convert a first voltage to a second voltage, the method comprising: charging a designated node of the voltage converter from a third voltage to a fourth voltage during a first charging period, wherein the fourth voltage is greater than the third voltage, and the third voltage and the fourth voltage are between the first voltage and the second voltage; charging the designated node from the fourth voltage to the first voltage during a second charging period; discharging the designated node from the first voltage to the third voltage during a discharging period; and converting the third voltage of the designated node to the second voltage, wherein the first voltage is greater than the second voltage.

14. The method of operating a charge pump circuit of claim 13, wherein the first charging period precedes the second charging period.

15. The method of operating a charge pump circuit of claim 13, wherein the first charging period and the second charging period are consecutive periods.

16. The method of operating a charge pump circuit of claim 13, wherein the discharging period follows the second charging period.

17. The method of operating a charge pump circuit of claim 13, wherein a difference between the fourth voltage and the third voltage is greater than a difference between the first voltage and the fourth voltage.

18. The method of operating a charge pump circuit of claim 13, further comprising: receiving the fourth voltage for charging during the first charging period; and boosting the fourth voltage to the first voltage for charging during the second charging period.

19. The method of operating a charge pump circuit of claim 13, wherein the designated node is charged in accordance with the first control signal during the first charging period, the designated node is charged in accordance with the second control signal during the second charging period, and the method further comprises: generating the first control signal in accordance with the second control signal; and generating the second control signal in accordance with a frequency signal.

20. The method of operating a charge pump circuit of claim 19, wherein the designated node is discharged in accordance with the third control signal during the discharging period, and the method further comprises: generating the third control signal in accordance with the frequency signal.

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