Voltage converter and circuitry using the same

Abstract

This invention provides a voltage converter and a circuit system using the same, the voltage converter having a switch, a latch, and a voltage clamping circuit. The switch receives an input signal and opens or closes according to the input signal. The latch receives a power supply voltage. The voltage clamping circuit has a first node, a second node, and a third node, the first node being electrically connected to an output terminal of the latch for outputting an output signal, the second node being electrically connected to another output terminal of the latch along with the switch, and the third node being a voltage follower node of the second node. Compared to the prior art, the voltage converter of this invention requires only a single power supply to operate, and the output signal is not unknown when the power supply is first turned on.

Description

Technical Field

[0001] This invention relates to a voltage converter, and more particularly to a single-supply voltage converter and a circuit system using the same. Background Technology

[0002] A voltage converter is a device that converts the voltage of an input signal to an output signal with the converted voltage. Traditional voltage converters use dual power supplies, which has some shortcomings that need improvement. Specifically, voltage converters are logic circuits designed using common standard cells. Therefore, the design requires both an analog high-voltage power supply (AVDD) and a digital low-voltage power supply (VDDL) to operate normally. However, the digital low-voltage power supply (VDDL) is generated by the analog high-voltage power supply (AVDD). During power-on, before the analog high-voltage power supply (AVDD) is ready, the digital low-voltage power supply (VDDL) needs to have the correct logic signals to ensure that the digital low-voltage power supply signal is not mistakenly transmitted, thus preventing malfunctions in the downstream digital circuitry and avoiding technical problems such as incorrect signal transmission or incorrect output voltage.

[0003] The following describes several conventional voltage converters as background technology for this case. First, please refer to... Figure 1 , Figure 1 This is a circuit diagram of another conventional voltage converter. Voltage converter 2 is designed as a single-supply voltage converter, which includes inverters 200 and 201, a PMOS transistor 203, and an NMOS transistor. Inverters 200 and 201 are high-voltage inverters. The supply voltage (VDD, i.e., the voltage at node VL) of inverter 200 is stepped down from voltage VDDH to voltage VDDL by the diode-connected NMOS transistor 204, and then the output feedback switch composed of PMOS transistor 203 is used to switch the voltage at node VL to voltage VDDH. In this way, the voltage conversion circuit realizes single-supply power conversion. However, since the voltage VDDL is provided by the NMOS transistor 204 which is diode connected (i.e., VDDL = VDDH - VTH, where VTH is the threshold voltage of the NMOS transistor 204), the process, operating voltage and operating temperature range of the NMOS transistor 204 need to be considered to obtain the corresponding voltage VDDL. In other words, it is not easy to obtain a voltage VDDL with a large voltage range due to the limitations of the process, operating voltage and operating temperature range of the NMOS transistor 204.

[0004] Next, please refer to Figure 2 , Figure 2This is another circuit diagram of a conventional voltage converter. Voltage converter 3 includes PMOS transistors 301, 303, 304, and 305, and NMOS transistors 302, 306, and 307. PMOS transistors 301, 303, and NMOS transistor 302 can form a discharge path to switch the high-voltage latch (composed of PMOS transistors 304 and 305). When the input signal VIN is logic high, NMOS transistor 307 is turned on and the gate of PMOS transistor 301 is logic low, so the input signal VIN can be temporarily stored at node VC. At this time, the voltage of node VC is essentially equal to the voltage of the input signal VIN, and NMOS transistor 302 is turned off. When the input signal VIN is logic low, NMOS transistor 307 and PMOS transistor 301 are turned off, making the voltage of the output signal VOUT 0. Voltage converter 3 uses a bootstrap method to raise the input signal VIN, which serves as the control signal (the voltage of node VC) used when voltage converter 3 switches states. However, during power-on, because the voltage of the input signal VIN is 0, the voltage of node VC is also 0, resulting in the voltages of both the output signal VOUT and the inverted output signal VOUTB being unknown. Summary of the Invention

[0005] An embodiment of the present invention provides a voltage converter, the voltage converter comprising: a switch for receiving an input signal and opening or closing according to the input signal; a latch for receiving a power supply voltage; and a voltage clamping circuit having a first node, a second node, and a third node, the first node being electrically connected to the output terminal of the latch, the second node being electrically connected to another output terminal of the latch, and the third node being a voltage follower node of the second node; wherein when the input signal is a logic low level, the switch is closed, causing the voltage of the second node to be pulled high, the voltage of the third node being pulled high as a result of the voltage of the second node being pulled high, and the voltage of the first node being equal to the logic low level voltage, and the latch entering a switching state, the output voltage of the output signal of the output terminal of the latch being the logic low level; wherein when the input signal is a logic high level, the switch is opened, causing the voltage of the second node to be the logic low level voltage, the latch switching state, the voltage of the third node decreasing to a threshold voltage, the voltage of the first node being connected to the power supply voltage, and the output voltage of the output signal of the output terminal of the latch being the logic high level.

[0006] In one embodiment, the voltage converter further includes: an input buffer circuit electrically connected to the input signal, the input buffer circuit having a buffer node electrically connected to the voltage clamping circuit, the buffer node being used to buffer the input signal when the input signal is at the logic high level.

[0007] In one embodiment, the voltage clamping circuit includes: a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, and a second PMOS transistor; wherein the source of the second PMOS transistor receives the power supply voltage, the gate and drain of the second PMOS transistor are electrically connected to each other, the source of the first NMOS transistor receives the input signal, the drain of the first NMOS transistor is electrically connected to the first node, the gates of the first NMOS transistor and the second NMOS transistor are electrically connected to each other, the gates of the first NMOS transistor and the second NMOS transistor are electrically connected to the third node, the third node is electrically connected to the drain of the second PMOS transistor and the source of the first PMOS transistor, the drains of the first PMOS transistor and the second NMOS transistor are electrically connected to each other, the gate of the first PMOS transistor is electrically connected to the second node, the gate of the first PMOS transistor is electrically connected to the switch, and the source of the second NMOS transistor is electrically connected to the temporary storage node of the input temporary storage circuit.

[0008] In one embodiment, the input temporary storage circuit includes a third PMOS transistor and a charge storage capacitor; wherein one end of the charge storage capacitor is electrically connected to ground, the other end of the charge storage capacitor is electrically connected to the temporary storage node and the drain of the third PMOS transistor, the source of the third PMOS transistor receives the input signal, and the gate of the third PMOS transistor is electrically connected to the switch.

[0009] In one embodiment, the input temporary storage circuit includes a diode and a third NMOS transistor; wherein the two ends of the diode are respectively connected to the input signal and the temporary storage node, the gate of the third NMOS transistor is connected to the temporary storage node, and the source and drain of the third NMOS transistor are connected to ground.

[0010] In one embodiment, the voltage drop between the first node and the input signal is absorbed by the first NMOS transistor of the voltage clamping circuit.

[0011] In one embodiment, the voltage clamping circuit includes: a first NMOS transistor, a first PMOS transistor, and a second PMOS transistor; wherein the source of the first PMOS transistor receives the power supply voltage, the gate and drain of the first PMOS transistor are electrically connected to each other and connected to the third node, the source of the first NMOS transistor receives the input signal, the gate of the first NMOS transistor is electrically connected to the third node, the drain of the first NMOS transistor is electrically connected to the first node, the source of the second PMOS transistor is connected to the third node, the gate of the second PMOS transistor is connected to the second node, and the drain of the second PMOS transistor is connected to ground.

[0012] In one embodiment, the latch includes: two PMOS transistors, the sources of the two PMOS transistors being connected to the power supply voltage, the drains of each of the two PMOS transistors being electrically connected to the gate of the other PMOS transistor, and the drains of the two PMOS transistors serving as the two output terminals of the latch.

[0013] In one embodiment, the voltage converter further includes: a buffer composed of an even number of inverters, the input of the buffer being electrically connected to the first node of the voltage clamping circuit, and the output of the buffer being used to output the output signal.

[0014] An embodiment of the present invention provides a circuit system comprising: an input circuit, a load, and any one of the aforementioned voltage converters; wherein the voltage converter is electrically connected to the input circuit and the load, the input circuit is used to provide the input signal, and the load is used to receive the output signal.

[0015] In summary, compared with the prior art, the voltage converter of the present invention only requires a single power supply to operate, and the output signal is not unknown when the power supply is first turned on.

[0016] To further understand the technology, means, and effects of the present invention, reference can be made to the following detailed description and accompanying drawings, which will provide a thorough and concrete understanding of the purpose, features, and concepts of the present invention. However, the following detailed description and accompanying drawings are for reference and illustration only and are not intended to limit the present invention. Attached Figure Description

[0017] The present invention can be more fully understood through the following detailed description of the embodiments in conjunction with the accompanying drawings, in which:

[0018] Figure 1 This is a circuit diagram of a traditional voltage converter;

[0019] Figure 2This is a circuit diagram for another type of conventional voltage converter;

[0020] Figure 3 This is a circuit diagram of a voltage converter according to an embodiment of the present invention;

[0021] Figure 4 This is a circuit diagram of a voltage converter according to another embodiment of the present invention;

[0022] Figure 5 This is a circuit diagram of a voltage converter according to another embodiment of the present invention.

[0023] The symbols shown in the diagram are explained as follows:

[0024] 2-6 voltage converter;

[0025] 41, 61 latches;

[0026] 203, 301, 303-305, 411, 412, 443, 444, 421, 522, 611, 612, 642, 644 PMOS transistors;

[0027] 42 and 52 input temporary storage circuits;

[0028] 422 charge storage capacitor;

[0029] VL, VC, VR, O, P nodes;

[0030] Switches 43 and 63;

[0031] 204, 302, 306, 307, 431, 441, 442, 631, 641 NMOS transistors;

[0032] 44 and 64 voltage clamping circuits;

[0033] 45, 65 buffers;

[0034] Inverters 200, 201, 451, 452, 651, and 652;

[0035] 521 diode;

[0036] VDDH and VDDL voltages;

[0037] VIN input signal;

[0038] VOUT output signal;

[0039] VOUTB inverted output signal;

[0040] GND ground. Detailed Implementation

[0041] Reference will now be made in detail to exemplary embodiments of the invention, which are illustrated in the accompanying drawings. Where possible, the same component reference numerals are used in the drawings and description to refer to the same or similar parts. Furthermore, the exemplary embodiments are merely one way of implementing the design concept of the invention, and the following examples are not intended to limit the invention.

[0042] This invention provides a single-supply voltage converter that requires only a low-voltage logic signal and a high-voltage power supply to convert a low-voltage input signal into a high-voltage output signal. Simultaneously, the output signal can serve as a ready signal for the low-voltage power supply. When the high-voltage power supply is first turned on, the voltage converter's switching mechanism will not experience signal mistransmission or incorrect voltage levels due to insufficient power supply readiness. In short, one objective of this invention is to address the drawback of traditional voltage converters requiring dual power supplies.

[0043] First, please refer to Figure 3 , Figure 3 This is a circuit diagram of a voltage converter according to an embodiment of the present invention. The voltage converter 4 includes a latch 41, an input buffer circuit 42, a switch 43, a power clamping circuit 44, and a buffer 45. The latch 41 is composed of PMOS transistors 411 and 412. The sources of PMOS transistors 411 and 412 are electrically connected to voltage VDDH (power supply voltage), respectively. The gate of PMOS transistor 411 is electrically connected to the drain of PMOS transistor 412, and the gate of PMOS transistor 412 is electrically connected to the drain of PMOS transistor 411. The drain of PMOS transistor 411 of the latch 41 (i.e., the output terminal of the latch 41) is electrically connected to node O of the power clamping circuit 44 and connected to the input terminal of the buffer 45. The drain of PMOS transistor 412 of the latch 41 (i.e., the other output terminal of the latch 41) is electrically connected to node P of the power clamping circuit 44.

[0044] The buffer 45 is composed of two inverters 451 and 452 connected in series. Specifically, the output of inverter 451 is electrically connected to the input of inverter 452, and the input of inverter 451 (i.e., the input of buffer 45) is electrically connected to node O of the power clamping circuit 44 and the PMOS transistor 411 of the latch 41. The output of inverter 452 is used to generate the output signal VOUT. The power supply terminals and ground terminals of inverters 451 and 452 are electrically connected to voltage VDDH and ground GND, respectively. Note that buffer 45 is not a necessary component of this invention, and it can be implemented by, for example, four or six inverters connected in series (i.e., buffer 45 is implemented with an even number of inverters), or even replaced by an inverting buffer (implemented with an odd number of inverters).

[0045] The voltage clamping circuit 44 is composed of NMOS transistors 441 and 442 and PMOS transistors 443 and 444, and has nodes O, P, and VR. The source of PMOS transistor 444 receives voltage VDDH, and the gate and drain of PMOS transistor 444 are electrically connected to each other. The source of NMOS transistor 441 receives input signal VIN, and the drain of NMOS transistor 441 is electrically connected to node O. The gates of NMOS transistors 441 and 442 are electrically connected to each other, and the gates of NMOS transistors 441 and 442 are also electrically connected to node VR. Node VR is electrically connected to the drain of PMOS transistor 444 and the source of PMOS transistor 443. The drains of PMOS transistor 443 and NMOS transistor 442 are electrically connected to each other. The gate of PMOS transistor 443 is electrically connected to node P, and node P is electrically connected to switch 43, that is, the gate of PMOS transistor 443 is electrically connected to switch 43. The source of NMOS transistor 442 is electrically connected to node VC of input temporary storage circuit 42, that is, the source of NMOS transistor 442 is electrically connected to input temporary storage circuit 42.

[0046] Switch 43 is composed of NMOS transistor 431. The source of NMOS transistor 431 is electrically connected to ground GND, the gate of NMOS transistor 431 receives the input signal VIN, and the drain of NMOS transistor 431 is electrically connected to node P and input temporary storage circuit 42.

[0047] The input temporary storage circuit 42 is composed of a PMOS transistor 421 and a charge storage capacitor 422, and has a node VC. One end of the charge storage capacitor 422 is electrically connected to ground GND, and the other end of the charge storage capacitor 422 is electrically connected to node VC and the drain of the PMOS transistor 421. The source of the PMOS transistor 421 receives the input signal VIN, and the gate of the PMOS transistor 421 is electrically connected to the drain of the NMOS transistor 431.

[0048] Through the architecture of the voltage converter 4 described above, the voltage converter 4 can adjust the lower-level (voltage VDDL, lower than voltage VDDH) input signal VIN to the same high level as voltage VDDH when only the voltage VDDH is provided, thereby providing power to the load electrically connected to the back end of the voltage converter 4. Figure 3 (Not shown) In use. Further, switch 43 is controlled by the input signal VIN to make the voltage at node P 0 or a raised non-zero voltage divider. When the input signal VIN is logic low (i.e., 0), NMOS transistor 431 is turned off; when the input signal VIN is logic high (voltage VDDL), NMOS transistor 431 is turned on.

[0049] When NMOS transistor 431 is turned off (input signal VIN is logic low), latch 41 is in an unknown state, and the voltage at node P is raised due to the voltage divider between PMOS transistor 412 and NMOS transistor 431. Then, the raised voltage at node P causes PMOS transistor 443 to turn off, so the voltage at node VR is pulled high due to the drain of PMOS transistor 444, which is connected to a diode (i.e., the voltage at node VR equals the voltage at node P (non-zero voltage divider) plus the threshold voltage of PMOS transistor 443; or, node VR is a voltage following node P). The raised voltage at node VR causes NMOS transistor 441 to turn on, forcing the voltage at node O to be substantially equal to the logic low level voltage (0) of input signal VIN. Thus, latch 41 enters a transition state, and buffer 45 outputs a low voltage (0 or logic low level voltage) output signal VOUT based on the voltage at node O (a low voltage of 0 or a logic low level voltage).

[0050] When NMOS transistor 431 is turned on (input signal VIN is at logic high), the voltage at node P is low (0 or logic low), causing latch 41 to switch states. PMOS transistor 421 in temporary storage circuit 42 then turns on, and charge storage capacitor 422 can store the input signal VIN, making the voltage at node VC essentially equal to the voltage of the input signal VIN. PMOS transistor 443 in voltage clamping circuit 44 is turned on, and voltage clamping circuit 44 enters normal operating mode. This causes PMOS transistor 444, which is diode-connected, to provide a momentary bias current to node VR, making the voltage at node VR follow the voltage at node P (i.e., the voltage at node VR equals the voltage at node P (0 or logic low) plus the threshold voltage of PMOS transistor 443; or, node VR is a voltage-following node of node P). NMOS transistors 441 and 442 achieve the voltage clamping effect, forcing the voltage at input signal VIN to equal the voltage at node VC. At this time, node O is connected to voltage VDDH due to the state change of latch 41. Simultaneously, the excessively high voltage level drops across NMOS transistor 441, protecting the input circuitry used to generate the input signal VIN for voltage VDDL. Finally, buffer 45 outputs an output signal VOUT with voltage VDDH based on the voltage VDDH at node O.

[0051] As can be seen from the above, the voltage converter 4 can operate with only a single power supply (voltage VDDH), and the output signal VOUT will not be unknown when the power supply is first turned on. Furthermore, the voltage clamping circuit 44 can protect the input circuit used to form the input signal VIN of the voltage VDDL. For example, the voltage drop between node O and the input signal VIN is borne by the voltage clamping circuit 44 (as mentioned above, it is achieved by dropping the voltage across the NMOS transistor 441 at an excessively high level).

[0052] Next, please refer to Figure 4 , Figure 4 This is a circuit diagram of a voltage converter according to another embodiment of the present invention. The voltage converter 5 also includes a latch 41, an input temporary storage circuit 52, a switch 43, a voltage clamping circuit 44, and a buffer 45, compared to... Figure 3 In this embodiment, the input buffer circuit 52 of voltage converter 5 differs slightly from the input buffer circuit 42 of voltage converter 4. In this embodiment, the input buffer circuit 52 is composed of a diode 521 and an NMOS transistor 522, wherein the two ends of diode 521 are respectively connected to the input signal VIN and node VC. The function of diode 521 is... Figure 3 Similar to the PMOS transistor 421, the gate of the NMOS transistor 522 is connected to node VC, and the source and drain of the NMOS transistor 522 are connected to ground GND, so that the function of the NMOS transistor 522 is the same. Figure 3 The charge storage capacitance is the same as that of 422.

[0053] Next, please refer to Figure 5 , Figure 5 This is a circuit diagram of a voltage converter according to another embodiment of the present invention. Unlike... Figure 3 and Figure 4 In this embodiment, the voltage converter 6 includes a latch 61, a switch 63, a voltage clamping circuit 64, and a buffer 65, but does not have an input temporary storage circuit. The latch 61 is composed of PMOS transistors 611 and 612, and the buffer 65 is composed of two inverters 651 and 652. The functions of the latch 61 and the buffer 65 are respectively related to... Figure 3 and Figure 4 The latch 41 is the same as the buffer 45.

[0054] The voltage clamping circuit 64 is composed of NMOS transistor 641 and PMOS transistors 642 and 644, and has nodes O, VR, and P. The source of PMOS transistor 644 receives voltage VDDH, and its gate and drain are electrically connected to each other and connected to node VR. The source of NMOS transistor 641 receives input signal VIN, its gate is electrically connected to node VR, and its drain is electrically connected to node O. The source of PMOS transistor 642 is connected to node VR, its gate is connected to node P, and its drain is connected to ground GND.

[0055] Switch 63 is composed of an NMOS transistor 631. The source of NMOS transistor 631 is electrically connected to ground GND, the gate of NMOS transistor 631 receives the input signal VIN, and the drain of NMOS transistor 631 is electrically connected to node P.

[0056] Switch 63 is controlled by the input signal VIN to make the voltage at node P either 0 or a raised non-zero voltage divider. When the input signal VIN is logic low (i.e., 0), NMOS transistor 631 is turned off, and when the input signal VIN is logic high (voltage VDDL), NMOS transistor 631 is turned on.

[0057] When NMOS transistor 631 is turned off (input signal VIN is logic low), latch 61 is in an unknown state, and the voltage at node P is raised due to the voltage divider between PMOS transistor 612 and NMOS transistor 631. Then, the voltage at node P is raised, and the voltage at node VR is the voltage at node P plus the threshold voltage of PMOS transistor 642. NMOS transistor 641 is turned on, so the voltage at node O is discharged to equal the voltage (0) of input signal VIN. Thus, latch 61 enters a transition state, and buffer 65 outputs an output signal VOUT with a voltage of 0 based on the voltage (0) at node O.

[0058] When NMOS transistor 631 is turned on (input signal VIN is logic high), the voltage at node P is 0, latch 61 is switched, and the voltage at node VR is the threshold voltage of PMOS transistor 642. NMOS transistor 641 is turned off. Node O is connected to voltage VDDH due to the switch of latch 61. Simultaneously, the excessively high voltage level drops across NMOS transistor 641, allowing it to protect the input circuitry used to form the input signal VIN for voltage VDDL. Finally, buffer 65 outputs an output signal VOUT with voltage VDDH based on the voltage VDDH at node O.

[0059] As can be seen from the above, the voltage converter 6 only requires a single power supply (voltage VDDH) to operate, and the output signal VOUT is not unknown when the power supply is first turned on. Furthermore, the voltage clamping circuit 64 can protect the input circuit used to form the input signal VIN of the voltage VDDL. Compared to Figure 3 and Figure 4 In this embodiment, the voltage converter 6 can also save on the number of NMOS transistors and the configuration of charge storage capacitors through the design of the voltage clamping circuit 64.

[0060] In addition, embodiments of the present invention also provide a circuit system, the circuit system including a voltage converter, an input circuit, and at least one load for receiving an output signal, wherein the voltage converter is electrically connected to the input circuit and the load, and the input circuit is used to generate an input signal VIN having a voltage VDDL. The voltage converter may be the aforementioned Figures 3-5 One of the voltage converters is 4 to 6, and the load can be various types of circuits, such as digital circuits or logic circuits, but the present invention is not limited thereto. Preferably, the circuit system can be integrated into a single chip, but the present invention is not limited thereto.

[0061] In summary, compared to existing technologies, the voltage converter of this invention requires only a single power supply to operate, and the output signal is not unknown when the power supply is first turned on. In other words, the voltage converter of this invention does not suffer from signal mistransmission or incorrect output signal levels due to insufficient power supply availability. Furthermore, through the design of the voltage clamping circuit, the voltage converter can better protect the input circuit used to generate the input signal. Moreover, in one embodiment, the voltage converter can eliminate the need for a charge storage capacitor and reduce the number of NMOS transistors. On the other hand, the voltage converter of this invention can be used in various circuit systems, thus possessing great practicality.

[0062] It will be understood that the above embodiments are cited by way of example only, and the invention is not limited to what has been specifically shown and described above. Instead, the scope of the invention includes combinations and sub-combinations of the various features described above, variations and modifications that would occur to those skilled in the art upon reading the foregoing description, and those not disclosed in known technologies. Documents incorporated herein by reference should be considered part of this application, and the definitions in this specification should be considered, except that the scope of any terms is defined in these incorporated documents in a manner that conflicts with the express or implied definitions in this specification.

Claims

1. A voltage converter, characterized in that, The voltage converter includes: A switch that receives an input signal and opens or closes according to the input signal; A latch that receives power supply voltage; and An input buffer circuit is electrically connected to the input signal, and the input buffer circuit has a buffer node; and A voltage clamping circuit, having a first node, a second node, and a third node, comprising: First NMOS transistor, second NMOS transistor, first PMOS transistor and second PMOS transistor; The source of the second PMOS transistor receives the power supply voltage, and the gate and drain of the second PMOS transistor are electrically connected to each other. The source of the first NMOS transistor receives the input signal, and the drain of the first NMOS transistor is electrically connected to the first node; The gates of the first NMOS transistor and the second NMOS transistor are electrically connected to each other and to the third node; The third node is electrically connected to the drain of the second PMOS transistor and the source of the first PMOS transistor. The drains of the first PMOS transistor and the second NMOS transistor are electrically connected to each other; The gate of the first PMOS transistor is electrically connected to the second node; The source of the second NMOS transistor is electrically connected to the temporary storage node of the input temporary storage circuit; the first node is electrically connected to the output terminal of the latch, the second node and the switch are electrically connected to the other output terminal of the latch, and the third node is a voltage follower node of the second node; When the input signal is at a logic low level, the switch is closed, causing the voltage of the second node to be pulled high. The voltage of the third node is also pulled high because the voltage of the second node is pulled high. The voltage of the first node is equal to the logic low level, and the latch enters a switching state. The output voltage of the output signal at the output terminal of the latch is the logic low level. When the input signal is at a logic high level, the switch is turned on so that the voltage of the second node is at the logic low level, the latch is switched, the voltage of the third node is reduced to a threshold voltage, the voltage of the first node is connected to the power supply voltage, and the output voltage of the output signal at the output terminal of the latch is at the logic high level. The input terminal of the input temporary storage circuit is connected to the input signal, and the temporary storage node is connected to the voltage clamping circuit as an output terminal. The voltage of the temporary storage node is equal to the voltage of the input signal when the input signal is high.

2. The voltage converter as described in claim 1, characterized in that, The temporary storage node is electrically connected to the voltage clamping circuit. When the input signal is at the logic high level, the temporary storage node is used to temporarily store the input signal.

3. The voltage converter as described in claim 1, characterized in that, The input temporary storage circuit includes: The third PMOS transistor and the charge storage capacitor; One end of the charge storage capacitor is electrically connected to ground, the other end of the charge storage capacitor is electrically connected to the temporary node and the drain of the third PMOS transistor, the source of the third PMOS transistor receives the input signal, and the gate of the third PMOS transistor is electrically connected to the switch.

4. The voltage converter as claimed in claim 1, characterized in that, The input temporary storage circuit includes: Diodes and the third NMOS transistor; The diode is connected to the input signal and the temporary storage node, respectively. The gate of the third NMOS transistor is connected to the temporary storage node, and the source and drain of the third NMOS transistor are connected to ground.

5. The voltage converter as claimed in claim 1, characterized in that, The voltage drop between the first node and the input signal is borne by the first NMOS transistor of the voltage clamping circuit.

6. The voltage converter as claimed in claim 1, characterized in that, The latch includes: Two PMOS transistors are provided, with their sources connected to the power supply voltage, and the drains of each PMOS transistor electrically connected to the gate of the other PMOS transistor. The drains of the two PMOS transistors serve as the two output terminals of the latch.

7. The voltage converter as claimed in claim 1, characterized in that, The voltage converter further includes: The buffer is composed of an even number of inverters. The input terminal of the buffer is electrically connected to the first node of the voltage clamping circuit, and the output terminal of the buffer is used to output the output signal.

8. A voltage converter, characterized in that, The voltage converter includes: A switch that receives an input signal and opens or closes according to the input signal; A latch that receives power supply voltage; and A voltage clamping circuit, having a first node, a second node, and a third node, comprising: First NMOS transistor, first PMOS transistor and second PMOS transistor; The source of the first PMOS transistor receives the power supply voltage, the gate and drain of the first PMOS transistor are electrically connected to each other and connected to the third node, the source of the first NMOS transistor receives the input signal, the gate of the first NMOS transistor is electrically connected to the third node, the drain of the first NMOS transistor is electrically connected to the first node, the source of the second PMOS transistor is connected to the third node, the gate of the second PMOS transistor is connected to the second node, and the drain of the second PMOS transistor is connected to ground. The first node is electrically connected to the output terminal of the latch, the second node and the switch are electrically connected to the other output terminal of the latch, and the third node is a voltage follower node of the second node; When the input signal is at a logic low level, the switch is closed, causing the voltage of the second node to be pulled high. The voltage of the third node is also pulled high because the voltage of the second node is pulled high. The voltage of the first node is discharged to the logic low level, and the latch enters a switching state. The output voltage of the output signal at the output terminal of the latch is at the logic low level. When the input signal is at a logic high level, the switch is turned on so that the voltage of the second node is at the logic low level, the latch is switched, the voltage of the third node is reduced to a threshold voltage, the first NMOS transistor is turned off, the voltage of the first node is connected to the power supply voltage, and the output voltage of the output signal at the output terminal of the latch is at the logic high level.

9. A circuit system, characterized in that, The circuit system includes: Input circuitry, load, and voltage converter as described in any one of claims 1 to 8; The voltage converter is electrically connected to the input circuit and the load, the input circuit being used to provide the input signal and the load being used to receive the output signal.

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