Low clock jitter RC oscillator circuit based on multiple independent current sources

Abstract

The invention discloses a low-clock jitter RC oscillator circuit based on multiple independent current sources, which is characterized in that a charging and discharging process is divided into multiple sub-stages and independent current sources are configured, so that low-frequency noise is exponentially attenuated along with the number of the current sources, and the low-clock jitter RC oscillator circuit comprises: 1) at least two independent charging and discharging current source architectures; 2) shaping the noise spectrum of the low-pass filter; and 3) multi-level current source subsection control is carried out. According to the invention, clock jitter can be reduced to a single current source scheme under double current source configuration, the problems of area increase and starting speed reduction caused by a traditional method are avoided, and the method is suitable for a high-precision timing system.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, specifically to a method and circuit structure for reducing clock jitter of an RC oscillator through multiple current sources, applicable to integrated circuit design requiring high-precision clock signals. Background Technology

[0002] An RC oscillator uses a constant current source to periodically charge and discharge a capacitor to generate an oscillation signal. Its output frequency is determined by the current source magnitude, capacitor value, and comparator threshold voltage. Traditional architectures using the same current source for charging and discharging lead to highly correlated noise, causing synchronization disturbances in the charging and discharging time, resulting in significant periodic jitter. Simulation analysis shows that low-frequency noise is directly converted into periodic jitter, and its amplitude is proportional to the current noise ratio I. n / I0 is directly proportional, where I n I represents the effective value of the current noise, and I0 represents the magnitude of the charging and discharging current.

[0003] Existing technologies mainly employ three jitter suppression schemes: 1) inserting a low-pass filter into the current source path to attenuate high-frequency noise; 2) increasing the capacitance of the charging and discharging capacitor to reduce the impact of thermal noise; and 3) using correlated double sampling technology. The Abidi-2006 study, "Phase Noise and Jitter in CMOS Ring Oscillators," reveals the physical mechanisms of the first two methods through theoretical analysis: Equation (64) proves that inserting a large capacitor (e.g., 12nF) into the tail current control path can effectively suppress flicker noise, which is equivalent to the low-pass filtering principle of method (1); in Equation (60)... The quantitative relationship directly verifies the feasibility of increasing the capacitance to reduce thermal noise in method (2). Gagliardi-2022-Low-Phase-Noise CMOSRelaxation Oscillators for On-Chip Timing of IoT Sensing Platforms further proposed method (3), which effectively suppresses comparator noise through correlated double sampling technology. However, these technologies all have inherent defects: low-pass filters will prolong system startup time due to the increase in equivalent noise bandwidth; large-size capacitors will significantly occupy chip area; and correlated double sampling technology can only handle comparator noise, and is completely ineffective for current source noise. Therefore, developing an innovative solution that can achieve the optimal trade-off between current source noise suppression and circuit performance (including startup speed, chip area, etc.) has become a core problem that urgently needs to be solved in the current oscillator design field. Summary of the Invention

[0004] In order to improve the clock precision of the RC oscillator, noise suppression and circuit performance optimization are considered, and a dithering suppression method and circuit structure based on multiple current sources are provided.

[0005] The technical solutions adopted by the present application are as follows:

[0006] A low clock jitter RC oscillator circuit based on multiple independent current sources, the schematic diagram is shown in the accompanying Figure 1 , characterized in that it comprises: an input port, including high and low reference voltage input ports V H and V L ; an output port, including positive and negative clock ports CK and CK~; a charging current array composed of 2 N parallel branches of charging current sources and corresponding 2 N charging control switches , the current output port is I out_charge ; a discharging current array composed of 2 N parallel branches of discharging current sources and corresponding 2 N discharge control switches , the current output port is I out_discharge ; a comparison & logic control module composed of N-bit ADC and N-bit decoder, including signal input port V in and 2 N control signal output ports An RC oscillation module composed of capacitor C, charging and discharging enable switches S up and S down , first comparator A1, second comparator A2 and SR latch, including charging and discharging current input ports I charge and I discharge , capacitor voltage output port V C , and system input and output ports V H , V L , CK and CK~, the clock frequency output by CK and CK~ is f0.

[0007] The charging current array output port I out_charge is connected to the input port I charge of the RC oscillation module, the discharging current array output port I out_discharge is connected to the input port I discharge of the RC oscillation module, the RC oscillation module output port V C is connected to the input port V in of the comparison & logic control module, and the output ports of the comparison & logic control module control the switches of the charging and discharging current array, respectively, and the RC oscillation module VC Voltage range of the port [V L , V H ] is divided into 2 N sub-intervals, each sub-interval corresponds to a unique N-bit binary code, a specific combination of charge and discharge current sources is activated through the decoder, the capacitor charging and discharging process is segmented, and the noise of each segment is not correlated, thereby effectively suppressing clock jitter.

[0008] Further, the low clock jitter RC oscillator circuit based on multiple independent current sources, characterized in that the charging current array comprises 2 N parallel current branches, each branch is composed of a switch S 1i and a current source I 1(i+1) (i=0, 1, …, 2 N -1) in series, and the other end of all switches is connected to the current output port I out_charge of the array.

[0009] Further, the low clock jitter RC oscillator circuit based on multiple independent current sources, characterized in that the charging current array comprises 2 N parallel current branches, each branch is composed of a switch S 2i and a current source I 2(i+1) (i=0, 1, …, 2 N -1) in series, and the other end of all switches is connected to the current output port I out_discharge of the array.

[0010] Further, the low clock jitter RC oscillator circuit based on multiple independent current sources, characterized in that the signal input end of the ADC inside the comparison & logic control module is connected to the module input end V in , the positive and negative power supplies are connected to the system input ports V H and V L respectively, and the output end is connected to the input end of the decoder; the decoder has 2 N output ends, which are respectively used as the control signal output ports of the module.

[0011] Further, the low clock jitter RC oscillator circuit based on multiple independent current sources, characterized in that one end of the capacitor C inside the RC oscillation module is connected to the capacitor voltage output port V C , and the other end is grounded; the charging enable switch S up is connected between the capacitor voltage output port V C and the input port I charge , and its control end is connected to the port CK; the discharge enable switch S down is connected between the capacitor voltage output port VC and input port I discharge Between them, its control terminal is connected to port CK; the non-inverting input terminal of the first comparator A1 is connected to the capacitor voltage output port V. C The inverting input is connected to port V. H The output terminal is connected to the S input terminal of the SR latch; the inverting input terminal of the second comparator A2 is connected to the capacitor voltage output port V. C The non-inverting input terminal is connected to port V. L The output terminal is connected to the R input terminal of the SR latch; the output terminal Q of the SR latch is connected to port CK, and the output terminal Q is connected to port CK.

[0012] Furthermore, the low clock jitter RC oscillator circuit based on multiple independent current sources is characterized in that N is an integer ≥ 0:

[0013] -In general, N≥1;

[0014] When N=0, the comparison & logic control module outputs a fixed high level; the charging current array degenerates into a single current source I. 11 The discharge current array degenerates into a single current source I. 21 The circuit degenerates into an RC oscillation mode with two independent current sources.

[0015] Furthermore, the low clock jitter RC oscillator circuit based on multiple independent current sources is characterized in that the charging current source... and discharge current source A graded current mirror structure is adopted, and schematic diagrams are attached. Figure 2 and attached Figure 3 As shown:

[0016] The charging current is composed of NMOS transistors (M0, M1), PMOS transistors (M2, M3), input reference current source I1, resistor R1, and capacitor C1, and includes the output current port I. out_charge M0 and M1 form the first-stage current mirror, and M2 and M3 form the second-stage current mirror. Specifically, I1 is connected to the drain and gate of M0, the source of M0 is grounded, the gates of M0 and M1 are connected, the source of M1 is grounded, its drain is connected to the drain and gate of M2, the source of M2 is connected to the power supply, the gate of M2 is connected to the gate of M3 through R1, and the drain of M3 is the current port I. out_charge The source is connected to the power supply, and C1 is connected to ground from the gate of M3;

[0017] The discharge current is composed of PMOS transistors (M4, M5), NMOS transistors (M6, M7), input reference current source I2, resistor R2, and capacitor C2, including the output current port I. out_dischargewhere M4 and M5 constitute the first stage current mirror, and M6 and M7 constitute the second stage current mirror; the specific connection is as follows: I2 is connected to the drain and gate of M4, the source of M4 is connected to the power supply, the gates of M4 and M5 are connected, the source of M5 is connected to the power supply, the drain is connected to the drain and gate of M6, the source of M6 is connected to the ground, the gate of M6 is connected to the gate of M7 through R2, and the drain of M7 is the current port I out_discharge , the source is connected to the ground, and C2 is connected from the gate of M7 to the ground;

[0018] The second stage resistance and capacitance of the current source constitute an RC low-pass filter, and the transfer function thereof is H(s) = 1 / (1 + s / ω p ), the cut-off frequency ω p is less than πf0, where f0 is the output frequency of the oscillator;

[0019] The size of the current source satisfies

[0020] Further, the low-clock-jitter RC oscillator circuit based on multiple independent current sources has the characteristics that the N-bit analog-to-digital converter (ADC) adopts a parallel comparison type structure.

[0021] The analog-to-digital conversion is completed through resistance voltage division, a comparator, and a digital part.

[0022] The input voltage range is [V L , V H ].

[0023] On the basis of the multi-current-source architecture, the core mechanism is to realize noise decorrelation and low-pass filtering synergy through segmented control. The basic working principle of the RC oscillator is based on the periodic signal generated by the cyclic charging and discharging of the constant current source to the capacitor, as shown in the accompanying drawing. Figure 4 In the charging phase, when the capacitor voltage V C is less than V L , the current source I0 starts to charge the capacitor until V C reaches V H ; in the discharging phase, when V C is greater than V H , the capacitor discharges at the same current I0 until V C drops to V L . The capacitor voltage V C presents a triangular wave, and the oscillation frequency is determined by the following formula:

[0024]

[0025] where the oscillation period T0 = 1 / f0, which is inversely proportional to the current I0 and the capacitor C. The noise I nWill affect the charge and discharge time, resulting in clock jitter, cycle jitter can be expressed as:

[0026]

[0027] Indicates that the jitter is proportional to the ratio of noise current. The influence of high frequency noise (frequency close to or more than f0) is smaller, and its power spectrum density is:

[0028]

[0029] Where I * is the effective value of single frequency noise, ω n is the noise frequency.

[0030] In the double current source configuration, after introducing the low-pass filter, the power density spectrum of the clock jitter of the double current source configuration is:

[0031]

[0032] The integral of the jitter size is:

[0033]

[0034] And the single current source configuration is:

[0035]

[0036] The ratio Changes with the filter cutoff frequency ω p , when ω p →0, The jitter is reduced to the single current source Further extended to 2 N Current sources, the charge and discharge is divided into multiple independent stages, and the total jitter can be approximately:

[0037]

[0038] Attached Figure 5 Showed that when the charge and discharge process was divided into 2 N Independent stages, the clock jitter curve changed with the filter cutoff frequency ω p (Normalized with the result of N=0)

[0039] Compared with the prior art, the present application has the following advantages:

[0040] 1. The present application realizes noise decorrelation through a multi-independent current source array and a segmented control technology, which suppresses clock jitter while avoiding the large size capacitor required by traditional low-pass filtering, significantly reduces the chip area occupation, and ensures the starting speed of the circuit.

[0041] 2. The present invention reduces the period jitter to that of a single current source architecture by synergizing the multi-current source noise decorrelation with the RC low-pass filtering. The clock jitter is significantly reduced. BRIEF DESCRIPTION OF DRAWINGS

[0042] Figure 1 is a schematic diagram of the present invention.

[0043] Figure 2 is a schematic diagram of the charging current source.

[0044] Figure 3 is a schematic diagram of the discharging current source.

[0045] Figure 4 is the capacitor voltage V C waveform.

[0046] Figure 5 is the clock jitter variation with the filter cutoff frequency ω p (normalized to the N=0 reference).

[0047] Figure 6 is a micrograph of a chip employing the dual current source architecture. DETAILED DESCRIPTION

[0048] To more clearly illustrate the technical solutions of the present invention, a specific embodiment based on a TSMC 180nm semiconductor process and verified by actual chip fabrication is given below.

[0049] In this embodiment, the circuit employs a dual independent current source architecture, corresponding to the case of N=0 in the present invention. The detailed design parameters and measured performance under this configuration are as follows:

[0050] 1. Input and output ports: The input ports of the circuit include high and low reference voltage inputs V H and V L , which are set to V H = 4.5V and V L = 0.5V in this example. The output ports are the non-inverted and inverted clock signals CK and CK~.

[0051] 2. Current source array and parameters:

[0052] - Charging current source: Since N=0, the charging current array degenerates to one independent charging current source I 11 . This current source employs the hierarchical current mirror structure shown in the accompanying drawing, with the following specific parameters: Figure 2 • Input reference current I1 = 5μA.

[0053] • Output current I2 = 5μA.

[0054] • The current amplification factor of the first stage NMOS current mirror (M0, M1) is

[0055] • The current amplification factor of the second stage PMOS current mirror (M2, M3) is

[0056] • The final output charging current I out_charge is about I1x4x5=100μA.

[0057] • The integrated RC low-pass filter is composed of a resistance R1=5.3MΩ and a capacitance C1=12pF, whose noise filtering cutoff frequency ω p is about 2.5kHz.

[0058]

[0059] - Discharge current source: Similarly, the discharge current array degenerates to 1 independent discharge current source I 21 . This current source adopts the hierarchical current mirror structure shown in the figure, and is designed symmetrically with the charging current source to ensure consistent performance: Figure 3

[0060] • The input reference current I2=5μA.

[0061] • The amplification factor of the first stage PMOS current mirror (M4, M5) is

[0062] • The amplification factor of the second stage NMOS current mirror (M6, M7) is

[0063] • The final output discharge current I out_discharge is also about 100μA.

[0064] • The RC low-pass filter of which has a resistance R2=5.3MΩ and a capacitance C2=12pF, and its cutoff frequency ω p is also 2.5kHz.

[0065] 3. Comparison & logic control module:

[0066] - Since the double current source architecture with N=0 is adopted, there is no need to segment the voltage range, so the function of this module is simplified, and its control output always outputs high level, so that the current sources I 11 and I 21 are ready to respond to the control of the upper S up and S down switches at any time.

[0067] 4. RC oscillation module and actual measurement results:

[0068] ​​The core oscillation capacitor C in the RC oscillation module is 6.25 pF.

[0069] Based on the above parameters, the theoretical oscillation frequency f0 of the circuit is calculated as follows:

[0070]

[0071] After actual flow test, the measured oscillation frequency of the circuit is highly consistent with the theoretical value, and is stable at 2 MHz. The final chip micrograph of the embodiment is shown in FIG. 6. The measured clock cycle jitter is only 113 ps, which is due to the synergistic effect of the independent double current source noise decorrelation technology and the RC low-pass filtering proposed in the present application, and the oscillator exhibits excellent precision. Figure 6

[0072] It should be noted that the above embodiments are not intended to limit the protection scope of the present application, and equivalent transformations or replacements made on the basis of the above technical solutions all fall within the protection scope of the claims of the present application.​

Claims

1. A multi-independent current source based low clock jitter RC oscillator circuit, characterized by, Comprise: - input ports, containing high, low reference voltage input ports V H and V L ; - output ports, including positive and negative phase clock ports CK and CK~; - a charging current array consisting of 2 N parallel branches of charging current sources and corresponding 2 N charging control switches with a current output port I out_charge ; - an array of discharge currents consisting of 2 N discharge current sources and corresponding 2 N discharge control switches in parallel branches, the current output port being I out_discharge ; - comparison & logic control module, consisting of N-bit ADC and N-bit decoder, containing signal input port V in and 2 N control signal output ports - RC oscillation module, composed of capacitor C, charge and discharge enable switch S up and S down , first comparator A1, second comparator A2 and SR latch, including charge and discharge current input port I charge and I discharge , capacitor voltage output port V C and system input and output port V H , V L , CK and CK~, the clock frequency of CK and CK~ output is f0; The charging current array output port I out_charge Connect the input port I of the RC oscillation module charge Discharge current array output port I out_discharge Connect the input port I of the RC oscillation module discharge RC oscillation module output port V C Connect the input port V of the comparison & logic control module in The output port of the comparison & logic control module Control the switching of the charging and discharging current arrays separately, and turn the RC oscillation module V... C Port voltage range [V L V H Divided into 2 equal parts N Each sub-interval corresponds to a unique N-bit binary code. By activating a specific combination of charging and discharging current sources through a decoder, the charging and discharging process of the capacitor is segmented, and the noise of each segment is independent of each other, thereby effectively suppressing clock jitter.

2. The low-jitter RC oscillator circuit based on multiple independent current sources according to claim 1, characterized in that, The charging current array comprises 2 N parallel current branches, each branch being formed by a switch S 1i in series with a current source I 1(i+1) (i = 0, 1,..., 2 N -1), and the other end of all switches being connected to a current output port I out_charge of the array.

3. The low-jitter RC oscillator circuit based on multiple independent current sources of claim 1, wherein, The discharge current array comprises 2 N parallel current branches, each branch being formed by a switch S 2i in series with a current source I 2(i+1) (i = 0, 1,..., 2 N -1), and the other end of all switches being connected to a current output port I out_discharge of the array.

4. The low-jitter RC oscillator circuit based on multiple independent current sources of claim 1, wherein, The signal input end of the ADC inside the comparison & logic control module is connected with the module input end V in , the positive and negative power supply is connected with the system input port V H and V L respectively, and the output end is connected with the decoder input end; the decoder has two output ends, which are respectively the module control signal output port N .

5. The low-jitter RC oscillator circuit based on multiple independent current sources of claim 1, wherein, One end of the capacitor C inside the RC oscillation module is connected to a capacitor voltage output port V C , and the other end is grounded; a charge enable switch S up is connected between the capacitor voltage output port V C and an input port I charge , and its control end is connected to a port CK; a discharge enable switch S down is connected between the capacitor voltage output port V C and the input port I discharge , and its control end is connected to a port CK~; a positive input end of a first comparator A1 is connected to the capacitor voltage output port V C , a negative input end is connected to a port V H , and an output end is connected to an S input end of an SR latch; a negative input end of a second comparator A2 is connected to the capacitor voltage output port V C , a positive input end is connected to a port V L , and an output end is connected to an R input end of the SR latch; an output end Q of the SR latch is connected to the port CK, and an output end Q~ is connected to the port CK~.

6. The low-jitter RC oscillator circuit based on multiple independent current sources of claim 1, wherein, The N is an integer ≥ 0: - Generally, N ≥ 1; - when N=0, the comparison & logic control module outputs a fixed high level; the charging current array degenerates into a single current source I 11 , the discharging current array degenerates into a single current source I 21 ; the circuit degenerates into an RC oscillation mode of two independent current sources.

7. The low-jitter RC oscillator circuit based on multiple independent current sources of claim 1, wherein, The charging current source and the discharging current source With a hierarchical current mirror structure: - the charging current is composed of NMOS transistors (M0, M1), PMOS transistors (M2, M3), an input reference current source II, a resistor R1 and a capacitor C1, comprising an output current current port I out_charge , wherein M0 and M1 constitute a first stage current mirror, M2 and M3 constitute a second stage current mirror; the specific connection is: II is connected to the drain and gate of M0, the source of M0 is grounded, the gates of M0 and M1 are connected, the source of M1 is grounded, the drain is connected to the drain and gate of M2, the source of M2 is connected to the power supply, the gate of M2 is connected to the gate of M3 through R1, the drain of M3 is the current current port I out_charge , the source is connected to the power supply, C1 is connected from the gate of M3 to ground; - the discharge current is composed of PMOS transistors (M4, M5), NMOS transistors (M6, M7), an input reference current source I2, a resistor R2 and a capacitor C2, comprising an output current current port I out_discharge , wherein M4 and M5 constitute a first stage current mirror, and M6 and M7 constitute a second stage current mirror; the specific connection is that I2 is connected to the drain and gate of M4, the source of M4 is connected to a power supply, the gates of M4 and M5 are connected, the source of M5 is connected to a power supply, the drain is connected to the drain and gate of M6, the source of M6 is connected to ground, the gate of M6 is connected to the gate of M7 through R2, and the drain of M7 is the current current port I out_discharge , the source is connected to ground, and C2 is connected from the gate of M7 to ground; - the second stage resistance and capacitance of the current source form an RC low pass filter with a transfer function the cut-off frequency ω p less than πf0, where f0is the oscillator output frequency; - the current source size satisfies 8. The low-jitter RC oscillator circuit based on multiple independent current sources of claim 1, wherein, The N-bit analog-to-digital converter (ADC) adopts a parallel comparison type structure: - Complete analog-to-digital conversion through resistance voltage division, comparator and digital part; - the input voltage range is [V L , V H ].

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