Ultra-wideband linearity improving power amplifier

Abstract

The invention discloses an ultra-wideband linearity improving power amplifier which comprises an input matching network, an intermediate-stage linearity improving network and an output matching network. The intermediate-stage linearity improving network comprises two matching branches with the same structure, and the two matching branches are connected in parallel to the output end of the input matching network; and the outputs of the two matching branches are respectively connected with the output-stage matching network. The integral matching circuit mainly adopts a capacitor, a microstrip line, an inductor and a resistor to isolate alternating current and improve stability.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of microwave integrated circuits, and particularly relates to an ultra-wideband linearity-improved power amplifier. BACKGROUND

[0002] Monolithic microwave integrated circuits (MMICs) play a key role in radar electronic countermeasure systems due to their excellent reliability, high integration and miniaturization. Microwave transistors based on III-V semiconductor materials (such as GaAs and GaN) can provide excellent power density and stability due to their outstanding high electron mobility and carrier concentration, and thus become an ideal choice to meet the demand for high power. Therefore, III-V MMIC power amplifiers constitute the core of modern radar electronic warfare high-power transmission links. In the face of increasingly complex electromagnetic countermeasure environment, ultra-wideband power amplifiers with strong anti-interference ability and wide applicability have become indispensable key components.

[0003] Traditional active radar jamming technology generally adopts a constant power jamming strategy. In this mode, III-V solid-state power amplifiers are usually driven to high saturation to pursue the highest power-added efficiency. However, this working state has obvious disadvantages: on the one hand, it limits the dynamic regulation ability of jamming power, which is not conducive to the realization of multi-target synchronous jamming; on the other hand, the strong nonlinear characteristics of high saturation will induce significant signal distortion, which is specifically manifested as amplitude modulation to amplitude modulation (AM / AM) distortion, amplitude modulation to phase modulation (AM / PM) distortion, and intermodulation distortion (IMD) under multi-frequency jamming conditions, ultimately leading to a serious decline in jamming effectiveness. The current mainstream ultra-wideband power amplifier chips mainly focus on high power and high efficiency, and lack consideration of power amplifier linearity, which limits their application to high-power and high-efficiency scenarios and cannot meet the needs of various complex application scenarios, especially in communication.

[0004] In 2015, Philippe Dennler et al. of Fraunhofer Institute for Applied Solid State Physics designed a GaN MMIC 8W power amplifier working at 6-18GHz. The gain of this amplifier is 21dB, but the PAE is only 10%, and the linearity is improved. See [Dennler P, Maroldt S, Quay R, et al. Monolithic three-stage 6-18GHz high power amplifier with distributed interstage in GaN technology [C]. 2015 10th European Microwave Integrated Circuits Conference (EuMIC), Paris, 2015, 29-32].

[0005] In 2018, Bei Liu et al. of Nanyang Technological University in Singapore designed a power amplifier working at 2.6-6.4GHz using GaN technology. The power amplifier has an output power greater than 34.3dBm and a drain efficiency greater than 62% within the operating bandwidth, and the linearity is improved. See [Liu B, Mao M, Khanna D, et al. A Novel 2.6-6.4GHz Highly Integrated Broadband GaN Power Amplifier [J]. IEEE Microwave & Wireless Components Letters, 2017, PP(99): 1-3].

[0006] Macom's product CMPA2560025D uses GaN HEMT technology, and its working frequency is 2-6GHz, output power is 45dBm, large signal gain is greater than 20dB, PAE is higher than 30%, but the third-order intermodulation IMD3 is only-25dBc when the power backoff is 10dB, and the linearity is improved. See [https: / / www.macom.com / products / product-detail / CMPA2560025].

[0007] The product QPA1013D of Qorvo company adopts GaN HEMT process, the working frequency is 6-18 GHz, the small signal gain is 25 dB, the large signal gain is 20 dB, the output power is 40 dBm, but the third-order intermodulation IMD3 is only -20 dBc when the power backoff is 10 dB, and there is no specific linearization design. See [https: / / www.qorvo.com / products / p / QPA1013D].

[0008] It can be seen that at present, the ultra-wideband power amplifier chip mainly focuses on high power and high efficiency, and there is no good way to improve the linearity to meet the linear amplification or communication demand, and the linear improvement circuit needs to be added in specific application. SUMMARY

[0009] The purpose of the present application is to overcome the shortcomings of the prior art, and provide an ultra-wideband linearity improvement power amplifier, which can improve the linearity to a certain extent while maintaining ultra-wideband, high power and high efficiency.

[0010] The purpose of the present application is achieved by the following technical scheme: an ultra-wideband linearity improvement power amplifier, comprising an input matching network, an intermediate stage linearity improvement network and an output matching network;

[0011] (1) The input matching network comprises a DC blocking capacitor C0, microstrip lines MLIN1-MLIN3, a stable resistor-capacitor pair Rb1 and Cb1, a first transistor Q1, a microstrip line MLIN5 and a DC blocking capacitor C4, and input matching capacitors C1, C2 and C3, a first gate power supply circuit and a first drain matching circuit; the DC blocking capacitor C0 is connected with the radio frequency input Input Pad, and the stable resistor-capacitor pair Rb1 and Cb1 is connected with the gate of the first transistor Q1; the drain of the first transistor Q1 is connected with MLIN5, and the source is grounded; the capacitor C4 is connected with the intermediate stage linearity improvement network;

[0012] One end of the microstrip line MLIN1 is connected between the DC blocking capacitor C0 and the capacitor C1, one end of the capacitor C2 is connected between C1 and MLIN2, one end of the capacitor C3 is connected between MLIN2 and MLIN3, and the other ends of MLIN1, C2 and C3 are grounded; one end of the first gate power supply circuit is connected in parallel between MLIN3 and the stable resistor-capacitor pair Rb1 and Cb1, and the other end is connected with the first gate power supply to provide gate bias voltage for the first transistor Q1; one end of the first drain matching circuit is connected between MLIN5 and the capacitor C4, and the other end is connected with the first drain power supply;

[0013] (2) The intermediate-stage linearity enhancement network comprises two matching branches with the same structure, and the two matching branches are connected in parallel at the output end of the capacitor C4; each matching branch comprises three matching circuits connected in series;

[0014] ① The first-stage matching circuit comprises the microstrip line MLIN6, the microstrip line MLIN7, the stable resistor-capacitor pair Rb2 and Cb2, the second transistor Q2, the microstrip line MLIN9, the DC blocking capacitor C7, the DC blocking capacitor C8, and a second gate power supply circuit, a second drain matching circuit, a cold module linearization matching circuit and a power supply matching circuit connected in series; the MLIN6 is connected to the output end of the capacitor C4, and the output end of the capacitor C8 is connected to the second-stage matching circuit;

[0015] The stable resistor-capacitor pair Rb2 and Cb2 are connected to the gate of the second transistor Q2; the drain of the second transistor Q2 is connected to the MLIN9, and the source is grounded; one end of the second gate power supply circuit is connected between the MLIN7 and the stable resistor-capacitor pair Rb2 and Cb2, and the other end is connected to the second gate power supply to provide a gate bias for the second transistor Q2; one end of the second drain matching circuit is connected between the capacitor C7 and the MLIN9, and the other end is connected to the second drain power supply;

[0016] The cold module linearization matching circuit comprises the cold module tube Q3; the drain of the cold module tube Q3 is connected between the capacitors C7 and C8, the source is grounded, and the gate of the cold module tube Q3 is connected to the power supply matching circuit; the power supply matching circuit is connected to the power supply Vc through an air bridge across the MLIN9 and the capacitor C7;

[0017] ② The second-stage matching circuit comprises two second-stage matching branches with the same structure, and the two second-stage matching branches are connected in parallel at the output end of the capacitor C8; the second-stage matching branch comprises the microstrip line MLIN10, the third transistor Q4 and the microstrip line MLIN11 connected in series, and a third gate power supply circuit; one end of the MLIN10 is connected to the capacitor C8, and the other end is connected to the gate of the third transistor Q4; the drain of the third transistor Q4 is connected to the MLIN11, and the source is grounded; one end of the third gate power supply circuit is connected between the MLIN10 and the third transistor Q4, and the other end is connected to the third gate power supply to provide a gate bias for the third transistor Q4;

[0018] ③ The third-stage matching circuit comprises the microstrip lines MLIN13, MLIN14 and MLIN15 connected in series, a series capacitor C12 and a third drain matching circuit; the outputs of the two second-stage matching branches are respectively connected to the MLIN13, the MLIN14 is between the MLIN13 and the MLIN15, and the MLIN15 is connected to the output matching network after being connected in series with the capacitor C12; one end of the third drain matching circuit is connected between the second-stage matching branch and the MLIN13, and the other end is connected to the third drain power supply;

[0019] (3) The output matching network includes a microstrip line MLIN16 and a DC blocking capacitor C13 connected in parallel. Its parallel end is connected to the output of the two matching branches of the intermediate linearity enhancement network. The other end of the microstrip line MLIN16 is grounded, and the other end of the DC blocking capacitor C13 is the RF output terminal Output Pad.

[0020] The beneficial effects of this invention are as follows: This invention proposes an ultra-wideband linearity-enhancing power amplifier. The overall scheme is a three-stage amplifier circuit, with each stage's matching network and transistor arrangement being completely symmetrical, and a drive ratio of 1:2:4. The matching network is divided into an input stage matching circuit, an intermediate stage matching circuit, and an output stage matching circuit. Through this three-stage matching circuit, high gain can be provided to the signal, while simultaneously achieving high output power and high efficiency. A cold-mode linearization matching circuit composed of cold-mode transistors is added to the intermediate stage matching circuit, combining cold-mode linearization technology with wideband gain compensation technology. This achieves wideband positive slope gain matching and improves the power amplifier's linearity. Furthermore, by adjusting the control voltage of the cold-mode transistors, linearity can be further improved at different output powers and frequencies. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the ultra-wideband linearity enhancement power amplifier of the present invention;

[0022] Figure 2 This is a power efficiency simulation diagram of Embodiment 1 of the present invention;

[0023] Figure 3 This is a comparison diagram of AM-AM and third-order intermodulation simulations at 6GHz, 10GHz, 14GHz and 18GHz in Embodiment 1 of the present invention.

[0024] Figure 4 This is a simulation diagram of the third-order intermodulation of the 10GHz regulating control voltage in Embodiment 1 of the present invention. Detailed Implementation

[0025] The technical solution of the present invention will be further described below with reference to the accompanying drawings.

[0026] like Figure 1 As shown in the figure, this embodiment provides a 6-18GHz ultra-wideband linearity enhancement power amplifier circuit, including an input matching network, an intermediate stage linearity enhancement network, and an output matching network. In the figure, C, Cb, and Cc all represent capacitors (they play different roles in the circuit, hence the different letters for distinction), R and Rb represent resistors, L represents inductors, MLIN represents microstrip lines, and Q1 to Q4 are all transistors (they have different roles in the circuit and are named differently). The overall matching circuit mainly uses capacitors and microstrip lines; inductors and resistors are used for crosstalk isolation and to improve stability. A wideband cold-dial transistor linearization structure is introduced in the second and third stage inter-stage matching circuits to improve linearity across the entire frequency band.

[0027] (1)The input matching network includes series connection of a DC blocking capacitor C0, microstrip lines MLIN1-MLIN3, a stable resistor-capacitor pair Rb1 and Cb1; the stable resistor-capacitor pair in the embodiment includes one resistor and two capacitors symmetrically connected in parallel on both sides of the resistor, and the two capacitors have the same capacitance value; the stable resistor-capacitor pair can also adopt a structure of one resistor and one capacitor connected in parallel, without affecting the effect; the specific number of capacitors and resistors can be selected according to actual needs. The first transistor Q1, the microstrip line MLIN5 and the DC blocking capacitor C4, and the input matching capacitors C1, C2 and C3, the first gate power supply circuit, and the first drain matching circuit; the DC blocking capacitor C0 is connected with the RF input Input Pad, and the stable resistor-capacitor pair Rb1 and Cb1 is connected with the gate of the first transistor Q1; the drain of the first transistor Q1 is connected with MLIN5, and the source is grounded; the capacitor C4 is connected with the intermediate-stage linearity improvement network;

[0028] One end of the microstrip line MLIN1 is connected between the DC blocking capacitor C0 and the capacitor C1, one end of the capacitor C2 is connected between C1 and MLIN2, one end of the capacitor C3 is connected between MLIN2 and MLIN3, and the other end of MLIN1, C2 and C3 is grounded; the input matching microstrip lines MLIN1, MLIN2 and MLIN3 and the input matching capacitors C1, C2 and C3 constitute a three-order LC matching network. One end of the first gate power supply circuit is connected in parallel between MLIN3 and the stable resistor-capacitor pair Rb1 and Cb1, and the other end is connected with the first-stage gate power supply to provide a gate bias for the first transistor Q1; one end of the first drain matching circuit is connected between MLIN5 and the capacitor C4, and the other end is connected with the first drain power supply;

[0029] (2)The intermediate-stage linearity improvement network includes two matching branches M1 and M2 with the same structure, and the two matching branches are connected in parallel at the output end of the capacitor C4; each matching branch includes a three-stage matching circuit;

[0030] ①The first-stage matching circuit includes series connection of the microstrip line MLIN6, the microstrip line MLIN7, the stable resistor-capacitor pair Rb2 and Cb2, the second transistor Q2, the microstrip line MLIN9, the DC blocking capacitor C7, the DC blocking capacitor C8, and the second gate power supply circuit, the second drain matching circuit, the cold mode linearization matching circuit and the power supply matching circuit; MLIN6 is connected with the output end of the capacitor C4, and the output end of the capacitor C8 is connected with the second-stage matching circuit;

[0031] The stable resistor-capacitor pair Rb2 and Cb2 is connected to the gate of the second transistor Q2; the drain of the second transistor Q2 is connected to MLIN9, and the source is grounded; one end of the second gate power supply circuit is connected between MLIN7 and the stable resistor-capacitor pair Rb2 and Cb2, and the other end is connected to the second gate power supply to provide the gate bias of the second transistor Q2; one end of the second drain matching circuit is connected between the capacitor C7 and MLIN9, and the other end is connected to the second drain power supply;

[0032] The cold mode linearization matching circuit comprises a cold mode tube Q3; the drain of the cold mode tube Q3 is connected between the capacitors C7 and C8, the source is grounded, and the gate is connected to the power supply matching circuit; the power supply matching circuit is connected across MLIN9 and the capacitor C7 through an air bridge,

[0033] The power supply Vc is connected to supply power;

[0034] ②The second-stage matching circuit comprises two second-stage matching branches M3 and M4 which are structurally identical and are connected in parallel at the output end of the capacitor C8; each second-stage matching branch comprises a microstrip line MLIN10, a third transistor Q4 and a microstrip line MLIN11 connected in series, and a third gate power supply circuit; one end of the microstrip line MLIN10 is connected to the capacitor C8, and the other end is connected to the gate of the third transistor Q4; the drain of the third transistor Q4 is connected to the microstrip line MLIN11, and the source is grounded; one end of the third gate power supply circuit is connected between the microstrip line MLIN10 and the third transistor Q4, and the other end is connected to the third gate power supply to provide the gate bias of the third transistor Q4;

[0035] ③The third-stage matching circuit comprises a microstrip line MLIN13, a microstrip line MLIN14 and a microstrip line MLIN15 connected in series, a capacitor C12 connected in series, and a third drain matching circuit; the outputs of the two second-stage matching branches are connected to the microstrip line MLIN13, the microstrip line MLIN14 is between the microstrip line MLIN13 and the microstrip line MLIN15, and the microstrip line MLIN15 is connected to the output matching network after being connected in series with the capacitor C12; one end of the third drain matching circuit is connected between the second-stage matching branch and the microstrip line MLIN13, and the other end is connected to the third drain power supply.

[0036] (3)The output matching network comprises a microstrip line MLIN16 and a blocking capacitor C13 connected in parallel, the parallel ends of which are connected to the outputs of the two matching branches of the intermediate-stage linearity improvement network, the other end of the microstrip line MLIN16 is grounded, and the other end of the blocking capacitor C13 is the radio frequency output end Output Pad.

[0037] The amplifier further comprises a plurality of matching capacitors: C5, C6, C9, C10, C11; wherein one end of the capacitor C5 is connected with the output end of the capacitor C4, and the other end is grounded; one end of the capacitor C6 is connected between the microstrip lines MLIN6 and MLIN7, and the other end is grounded; the microstrip lines MLIN6 and MLIN7 and the capacitors C5 and C6 constitute a two-stage LC matching network, wherein the overall S21 of the matching network presents a positive slope gain curve with low low-frequency gain and high high-frequency gain, and compensates the gain roll-off trend of the transistor. One end of the capacitor C9 is connected to the output end of the capacitor C8, and the other end is grounded; MLIN10 and the capacitor C9 constitute a first-order LC matching network. One end of the capacitor C10 is connected between the microstrip lines MLIN13 and MLIN13, and the other end is grounded; one end of the capacitor C11 is connected between MLIN14 and MLIN15, and the other end is grounded. The microstrip lines MLIN13, MLIN14, MLIN15 and the matching capacitors C10, C11 and C12 form a three-stage LC matching network.

[0038] The structures of the first gate power supply circuit, the second gate power supply circuit and the third gate power supply circuit are the same; each comprises a direct-current isolation inductor L1 / L2 / L3 and a decoupling capacitor Cc1 / Cc3 / Cc6, and the direct-current isolation inductor L1 / L2 / L3 and the decoupling capacitor Cc1 / Cc3 / Cc6 are connected in parallel to form a low-pass filter structure (the direct-current isolation inductor L1 and the decoupling capacitor Cc1 are connected in parallel to form a low-pass filter structure, the direct-current isolation inductor L2 and the decoupling capacitor Cc3 are connected in parallel to form a low-pass filter structure, and the direct-current isolation inductor L3 and the decoupling capacitor Cc6 are connected in parallel to form a low-pass filter structure), and the parallel end is connected with the first / second / third gate power supply; the other end of the direct-current isolation inductor L1 is connected between MLIN3 and a stable resistor-capacitor pair Rb1 and Cb1, the other end of the direct-current isolation inductor L2 is connected between MLIN7 and a stable resistor-capacitor pair Rb2 and Cb2, and the other end of the direct-current isolation inductor L3 is connected between MLIN10 and the third transistor Q4; the other end of the decoupling capacitor Cc1 / Cc3 / Cc6 is grounded.

[0039] The structures of the first drain matching circuit, the second drain matching circuit and the third drain matching circuit are the same; the first drain matching circuit comprises a microstrip line MLIN4, a decoupling capacitor Cc2 and a microstrip line MLIN8, the microstrip line MLIN4 and the decoupling capacitor Cc2 are connected in parallel, the parallel end of the microstrip line MLIN4 is connected with a first drain power supply, the other end of the microstrip line MLIN4 is connected between the microstrip line MLIN5 and a capacitor C4, the microstrip line MLIN8 and the decoupling capacitor Cc2 are connected in parallel, the parallel end of the microstrip line MLIN8 is connected with a second drain power supply, the other end of the microstrip line MLIN8 is connected between the microstrip line MLIN9 and a capacitor C7, the other end of the decoupling capacitor Cc2 is grounded. The microstrip line MLIN4 constitutes a low-pass filter structure with the decoupling capacitor Cc2 on one hand and participates in the intermediate-stage matching network with the blocking capacitor C4 on the other hand. The microstrip line MLIN8 constitutes a low-pass filter structure with the decoupling capacitor Cc2 on one hand and participates in the intermediate-stage matching network on the other hand. The microstrip line MLIN12 participates in the intermediate-stage matching network on one hand and constitutes a low-pass filter structure with the decoupling capacitor Cc4 on the other hand.

[0040] The power supply matching circuit comprises a resistor R1 and a decoupling capacitor Cc5, the resistor R1 and the decoupling capacitor Cc5 are connected in parallel, the parallel end of the resistor R1 is connected with a power supply Vc, the other end of the resistor R1 is connected with the gate of a transistor Q5 through an air bridge across the microstrip line MLIN9 and the capacitor C7, the other end of the decoupling capacitor Cc5 is grounded. The resistor R1 uses a large resistance to play a role in blocking the alternating current; the decoupling capacitor Cc5 is used to filter out the ripple. The Vc voltage is flexibly adjusted according to the working condition to achieve the optimal linearization effect.

[0041] The size of the cold mode tube needs to be selected according to the optimal input impedance of the transistor Q4 to control the insertion loss within 3dB, and at the same time the overall matching circuit S21 needs to present a positive slope gain curve with low low-frequency gain and high high-frequency gain to compensate for the gain roll-off trend of the transistor.

[0042] The cold mode tube works in the deep triode region, that is, Vds << 2(Vgs-Vth), where Vds is the drain-source voltage, Vgs is the gate-source voltage, and Vth is the threshold voltage. At this time, it is equivalent to a resistor, and the resistance value changes with Vgs, which is called a cold mode tube. The resistance value of the cold mode tube gradually increases with the increase of power, and if it is connected in parallel in the circuit, it will bring the phenomenon that S21 increases with the increase of input power, that is, gain expansion, which is exactly used to compensate for the gain compression of the power amplifier and improve the linearity. The input impedance of the cold mode tube changes little with frequency, and the resistance value can be adjusted by Vgs. When the power amplifier is close to the saturation state, the self-impedance of the cold mode transistor is much larger than the input impedance, so it is approximately open circuit and will not affect the saturated output power and efficiency of the power amplifier, while improving the linearity at power backoff.

[0043] The cold model tube size is selected by the input impedance Zin in front of the power tube; the input impedance Zin in front of the power tube gin The Zin control can be added by S parameter simulation, and the calculation formula of the cold model tube insertion loss is The equivalent circuit of the cold model tube is composed of three parts, in which C off and R off are the equivalent off-state capacitance and off-state equivalent resistance of the cold model tube, respectively, R ds is the equivalent internal resistance of the cold model tube, and ω is the frequency. The transistor off-state impedance R off is small and can be approximately ignored, so the equivalent internal resistance R ds of the cold model tube and the equivalent off-state capacitance C off of the cold model tube can be directly obtained from the real part and the imaginary part of the input impedance Z din of the cold model tube, and the insertion loss IL of the cold model tube is further converted into the drain input impedance Z din of the cold model tube and the calculation formula of the input impedance Z gin in front of the power tube By selecting the cold model tube size, the insertion loss is changed to be less than 3 dB and presents a positive slope insertion loss curve with high high-frequency insertion loss and low low-frequency differential loss.

[0044] Figure 2 The output power simulation diagram of Example 1 is shown in FIG. 6, from which it can be seen that the output power of the amplification circuit is greater than 40 dBm and the power added efficiency is greater than 24% in the entire working frequency range of 6-18 GHz. Figure 2

[0045] Figure 3 (a), (c), (e), (g) are respectively the third-order intermodulation simulation comparison diagrams of 6 GHz, 10 GHz, 14 GHz and 18 GHz in Example 1, Figure 3 (b), (d), (f), (h) are respectively the AM-AM simulation comparison diagrams of 6 GHz, 10 GHz, 14 GHz and 18 GHz in Example 1, the power amplifier is in the common AB class with a gate width of 100 mA / mm, the cold model tube is closed corresponding to a Vc=-20V bias, and the cold model tube is turned on corresponding to a Vc near-2V optimal voltage at each frequency point. From Figure 3 it can be seen that the third-order intermodulation of the power amplifier in the entire frequency band is obviously improved, the high linear output power point is improved to 30 dBm, the P1dB compression point is obviously improved, the linearity is improved, and the opening of the cold model transistor does not affect the saturated output power and the power added efficiency of the ultra-wideband power amplifier at all.

[0046] Figure 4 The 10 GHz adjustment control voltage third-order intermodulation simulation diagram of Example 1 is shown in FIG. 8, from which it can be seen that the third-order intermodulation of the power amplifier in the entire frequency band is obviously improved, the high linear output power point is improved to 30 dBm, the P1dB compression point is obviously improved, the linearity is improved, and the opening of the cold model transistor does not affect the saturated output power and the power added efficiency of the ultra-wideband power amplifier at all. Figure 4 ​It can be seen that adjusting the cold mode tube grid voltage Vc can flexibly adjust the third-order intermodulation curve, adapt to different output power conditions, and can combine the envelope tracking system to simultaneously improve the efficiency and linearity of the power back-off point. For example, when the output is 34dBm, Vc=-1V can be selected to have optimal linearity effect, when the output is 31dBm, Vc=-1.5V can be selected to have optimal linearity effect, and other frequency points are similar.

[0047] Those skilled in the art will understand that the embodiments described herein are for the purpose of helping the reader understand the principles of the present application, and should be understood as not limiting the scope of protection of the present application to such specific statements and embodiments. Those skilled in the art can make various other specific modifications and combinations according to the technical inspiration disclosed in the present application without departing from the essence of the present application, and these modifications and combinations are still within the scope of protection of the present application.

Claims

1. A wideband high linearity power amplifier, characterized by, The input matching network, the intermediate linear enhancement network and the output matching network are included. (1) The input matching network includes a series connection of a DC blocking capacitor C0, microstrip lines MLIN1-MLIN3, a stable resistor-capacitor pair Rb1 and Cb1, a first transistor Q1, a microstrip line MLIN5 and a DC blocking capacitor C4, and input matching capacitors C1, C2 and C3, a first gate power supply circuit and a first drain matching circuit; the DC blocking capacitor C0 is connected with a radio frequency input Input Pad, and the stable resistor-capacitor pair Rb1 and Cb1 is connected with a gate of the first transistor Q1; a drain of the first transistor Q1 is connected with the MLIN5, and a source is grounded; and the capacitor C4 is connected with the intermediate linear enhancement network; One end of the microstrip line MLIN1 is connected between the DC blocking capacitor C0 and the capacitor C1, one end of the capacitor C2 is connected between the C1 and the MLIN2, one end of the capacitor C3 is connected between the MLIN2 and the MLIN3, and the other ends of the MLIN1, C2 and C3 are grounded; one end of the first gate power supply circuit is connected in parallel between the MLIN3 and the stable resistor-capacitor pair Rb1 and Cb1, and the other end is connected with a first gate power supply to provide a gate bias for the first transistor Q1; one end of the first drain matching circuit is connected between the MLIN5 and the capacitor C4, and the other end is connected with a first drain power supply; (2) The intermediate linear enhancement network includes two matching branches with the same structure, and the two matching branches are connected in parallel at an output end of the capacitor C4; each matching branch includes a three-stage matching circuit; ① The first-stage matching circuit includes a series connection of a microstrip line MLIN6, a microstrip line MLIN7, a stable resistor-capacitor pair Rb2 and Cb2, a second transistor Q2, a microstrip line MLIN9, a DC blocking capacitor C7, a DC blocking capacitor C8, and a second gate power supply circuit, a second drain matching circuit, a cold module linearization matching circuit and a power supply matching circuit; the MLIN6 is connected with the output end of the capacitor C4, and the output end of the capacitor C8 is connected with a second-stage matching circuit; the stable resistor-capacitor pair Rb2 and Cb2 is connected with a gate of the second transistor Q2; a drain of the second transistor Q2 is connected with the MLIN9, and a source is grounded; one end of the second gate power supply circuit is connected between the MLIN7 and the stable resistor-capacitor pair Rb2 and Cb2, and the other end is connected with a second gate power supply to provide a gate bias for the second transistor Q2; one end of the second drain matching circuit is connected between the capacitor C7 and the MLIN9, and the other end is connected with a second drain power supply; the cold module linearization matching circuit includes a cold module tube Q3; a drain of the cold module tube Q3 is connected between the capacitors C7 and C8, a source is grounded, and a gate is connected with the power supply matching circuit; the power supply matching circuit is connected with a power supply Vc through an air bridge across the MLIN9 and the capacitor C7. The second-stage matching circuit includes two second-stage matching branches with the same structure, and the two second-stage matching branches are connected in parallel at the output end of the capacitor C8; the second-stage matching branch includes the microstrip line MLIN10, the third transistor Q4 and the microstrip line MLIN11 connected in series, and a third gate power supply circuit; one end of the microstrip line MLIN10 is connected with the capacitor C8, and the other end is connected with the gate of the third transistor Q4; the drain of the third transistor Q4 is connected with the microstrip line MLIN11, and the source is grounded; one end of the third gate power supply circuit is connected between the microstrip line MLIN10 and the third transistor Q4, and the other end is connected with the third gate power supply to provide the gate bias voltage for the third transistor Q4; The third-stage matching circuit includes the microstrip lines MLIN13, MLIN14 and MLIN15 connected in series, a series capacitor C12 and a third drain matching circuit; the outputs of the two second-stage matching branches are connected to the microstrip line MLIN13, the microstrip line MLIN14 is between the microstrip lines MLIN13 and MLIN15, and the microstrip line MLIN15 is connected with the output matching network after being connected with the series capacitor C12; one end of the third drain matching circuit is connected between the second-stage matching branch and the microstrip line MLIN13, and the other end is connected with the third drain power supply. The output matching network includes the microstrip line MLIN16 and the DC blocking capacitor C13 connected in parallel, the parallel ends of the microstrip line MLIN16 and the DC blocking capacitor C13 are connected with the outputs of the two matching branches of the intermediate-stage linearity improvement network, the other end of the microstrip line MLIN16 is grounded, and the other end of the DC blocking capacitor C13 is the radio frequency output end Output Pad.

2. A wideband high linearity power amplifier as claimed in claim 1, characterized in that, The amplifier further includes a plurality of matching capacitors: C5, C6, C9, C10 and C11; one end of the capacitor C5 is connected with the output end of the capacitor C4, and the other end is grounded; one end of the capacitor C6 is connected between the microstrip lines MLIN6 and MLIN7, and the other end is grounded; one end of the capacitor C9 is connected at the output end of the capacitor C8, and the other end is grounded; one end of the capacitor C10 is connected between the microstrip lines MLIN13 and MLIN13, and the other end is grounded; one end of the capacitor C11 is connected between the microstrip lines MLIN14 and MLIN15, and the other end is grounded.

3. The wideband high linearity power amplifier of claim 1, wherein, The first gate power supply circuit, the second gate power supply circuit and the third gate power supply circuit have the same structure; the DC blocking inductors L1 / L2 / L3 and the decoupling capacitors Cc1 / Cc3 / Cc6 are connected in parallel to form a low-pass filter structure, and the parallel ends are connected with the first / second / third gate power supply; the other end of the DC blocking inductor L1 is connected between the microstrip line MLIN3 and the stable resistor-capacitor pair Rb1 and Cb1, the other end of the DC blocking inductor L2 is connected between the microstrip line MLIN7 and the stable resistor-capacitor pair Rb2 and Cb2, and the other end of the DC blocking inductor L3 is connected between the microstrip line MLIN10 and the third transistor Q4; the other end of the decoupling capacitor Cc1 / Cc3 / Cc6 is grounded.

4. The wideband high linearity power amplifier of claim 1, wherein, The structure of the first drain matching circuit, the second drain matching circuit and the third drain matching circuit is the same; it comprises a microstrip line MLIN4 / MLIN8 / MLIN12 and a decoupling capacitor Cc2 / Cc4 / Cc7, the microstrip line MLIN4 / MLIN8 / MLIN12 and the decoupling capacitor Cc2 / Cc4 / Cc7 are connected in parallel, the parallel end is connected with the first / second / third drain power supply; the other end of the microstrip line MLIN4 is connected between MLIN5 and the capacitor C4, the other end of the microstrip line MLIN8 is connected between MLIN9 and the capacitor C7, and the other end of the microstrip line MLIN12 is connected between the second matching branch and MLIN13; the other end of the decoupling capacitor Cc2 / Cc4 / Cc7 is grounded.

5. The wideband high linearity power amplifier of claim 1, wherein, The power supply matching circuit comprises a resistor R1 and a decoupling capacitor Cc5, the resistor R1 and the decoupling capacitor Cc5 are connected in parallel, the parallel end is connected with the power supply Vc, the other end of the resistor R1 is connected between the microstrip line MLIN9 and the capacitor C7, and the other end of the decoupling capacitor Cc5 is grounded.

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