A multi-functional test chip and method based on PXI architecture

Abstract

The application provides a multifunctional test chip and method based on a PXI architecture, and relates to the technical field of test chips; the chip comprises a bus interface, a functional module group and an address controller; the bus interface interacts with an upper computer through a PXI bus; the functional module group comprises pulse sending, detection, analog quantity acquisition / output, serial communication, a storage controller and a temperature acquisition module, and can realize pulse signal transceiving, analog quantity processing, serial communication, data storage and temperature acquisition; the address controller divides an address space into eight subspaces, and precise control is realized. The control method comprises the steps of initializing an interface circuit, executing pulse sending and detection, analog quantity output and acquisition, EEPROM operation, UART communication and temperature acquisition and the like. The application integrates special modules, replaces traditional FPGA design, improves performance and reliability, reduces resource waste, reduces cost, shortens the development cycle, and is suitable for complex test scenes such as spaceflight measurement and control.

Description

Technical Field

[0001] This invention relates to the field of test chip technology, and specifically to a multifunctional test chip and method based on the PXI architecture. Background Technology

[0002] Ground-based testing equipment widely adopts the PXI bus architecture to achieve interaction with host computers, but significant technical problems exist in practical applications. Specifically, traditional solutions often rely on FPGA chips in conjunction with interface circuits to implement testing functions, such as instruction output, instruction acquisition, analog output, analog acquisition, serial communication, and storage. This leads to inefficient use of FPGA resources, as FPGAs, as general-purpose devices, need to be programmed to implement single functions, resulting in hardware resource redundancy and waste. At the same time, FPGA development involves complex code writing and debugging processes, increasing hardware design costs and software maintenance overhead, making the overall system costly and the development cycle lengthy, making it difficult to adapt to the rapidly iterating testing requirements.

[0003] Furthermore, existing technologies suffer from shortcomings in resource management and communication efficiency, leading to frequent resource conflicts between functional modules and difficulties in upper-level computer configuration and control. Signal processing capabilities are weak; for example, pulse transmission lacks dynamic adjustment mechanisms and anti-interference designs, and pulse detection lacks configurable filtering and full recording functions, resulting in low test signal accuracy and poor data integrity, such as the easy omission of constantly high / low states and pulse width data. The analog signal acquisition section lacks effective noise suppression algorithms, resulting in insufficient data accuracy, while the analog output range is limited and waveform stability is poor, affecting the reliability of test results. Existing systems are at risk of data loss; serial communication lacks buffer management mechanisms, and the communication protocol is singular, making data loss prone to occur during high-speed interactions. Storage management efficiency is low, with EEPROM data loading relying on manual operation, extending startup time. Simultaneously, the lack of real-time monitoring of board status, such as temperature acquisition, reduces system reliability. Overall functional scheduling is uncoordinated, with independent operation of each module lacking unified collaboration, leading to inefficient testing processes and difficulty in handling complex multi-condition testing scenarios.

[0004] Furthermore, the overall architecture development process of existing technologies still requires extensive FPGA programming, increasing labor costs and debugging difficulty; it also limits the application of testing equipment in high-requirement fields such as aerospace telemetry and control. Based on the above situation, we developed a chip based on the PXI bus architecture, supplemented by peripheral circuits to replace FPGA functions, to realize functions such as instruction input and output, analog signal acquisition and output, serial communication, and EEPROM storage, all of which can be directly configured through a host computer. It can be fully applied to most ground testing conditions, and reduces FPGA development investment and hardware costs, achieving software debugging-free operation, which is of great significance. Summary of the Invention

[0005] To address the problems existing in the background technology, the present invention provides a multi-functional test chip based on the PXI architecture, including: a bus interface for data interaction with a host computer via the PXI bus;

[0006] The functional module group includes a pulse transmission module, a pulse detection module, an analog signal acquisition module, an analog signal output module, a serial communication module, a storage controller module, and a temperature acquisition module;

[0007] The pulse transmitting module connects to the bus interface to send pulse signals; the pulse detection module receives instructions from the host computer through the subspace allocated by the address controller and detects the input pulse signals; the analog signal acquisition module connects to the ADC acquisition subspace of the bus interface to acquire analog signals and process the data using a partitioned averaging algorithm; the analog signal output module includes an SPI controller, which communicates with the digital-to-analog converter through the DAC output subspace managed by the address controller to output analog signals; the serial communication module is configured as a UART protocol converter, which interacts with the host computer through the serial port subspace of the bus interface; the storage controller module acts as an EEPROM controller, connected to the EEPROM read / write subspace of the bus interface, performs calibration data storage and automatic loading into RAM upon power-on, and shares the configuration register with the temperature acquisition module; the temperature acquisition module acquires the board temperature through the interface sensor via the temperature subspace allocated by the address controller and writes the data to the register;

[0008] The address controller divides the address space of the bus interface into multiple subspaces, each subspace corresponding to a functional module, enabling the host computer to configure and control the functional module group.

[0009] In a preferred embodiment, the pulse transmission module is configured to transmit pulse signals and supports both a storage-type transmission mode and a register-type transmission mode. The storage-type transmission mode changes the pulse information data stream in real time, while the register-type transmission mode maintains a fixed pulse information format. The pulse transmission module outputs test signals with adjustable pulse width and frequency through 32 channels.

[0010] In a preferred embodiment, the pulse detection module detects the input pulse signal and supports both register acquisition and storage acquisition methods. The register acquisition method updates the pulse information in an overlay manner, while the storage acquisition method records all pulse information. The pulse detection module performs configurable filtering on the 32-channel IO input pulses and uploads data on constant high and constant low states, dual-edge time, pulse width, and period.

[0011] In a preferred embodiment, the analog signal acquisition module acquires analog signals and processes the sampled data using a partitioned mean algorithm, including partitioning the sampled data into 128 partitions and calculating the mean; the analog signal acquisition module is compatible with the AD7606BSTZ acquisition chip and supports simultaneous acquisition of 32 channels of analog signals.

[0012] In a preferred embodiment, the analog output module includes an SPI controller that communicates with the digital-to-analog converter to achieve analog output; the clock frequency of the SPI controller is half of the system clock, and it interacts with the DA chip through two rounds of read and write operations.

[0013] In a preferred embodiment, the serial communication module is configured with UART protocol conversion and interacts with the host computer through a 256-byte FIFO buffer; the storage controller module is configured as an EEPROM controller for calibration data storage, supporting host computer read / write operations and reset operations; when the board is powered on, it automatically reads EEPROM data into the chip's internal RAM; the temperature acquisition module is configured to interface with an 18B20 temperature sensor to acquire the board's operating temperature and store the temperature value in a register.

[0014] In a preferred embodiment, the address controller divides the address space into eight subspaces, including a system bus subspace, a pulse transmission subspace, a pulse reception subspace, an EEPROM read / write subspace, an ADC acquisition subspace, a DAC output subspace, a serial port subspace, and a temperature subspace.

[0015] This invention provides a control method for a multifunctional test chip based on the PXI architecture, comprising the following steps:

[0016] S1: Receives function configuration parameters from the host computer via the PXI bus and initializes the interface circuit;

[0017] S2: Executes control pulse transmission and generates test signal output;

[0018] S3: Perform pulse detection, collect IO input data and upload the constant high or constant low status;

[0019] S4: Analog output is achieved via SPI communication;

[0020] S5: Perform analog data acquisition and upload the processing results;

[0021] S6: Perform EEPROM read / write operations;

[0022] S7: Data interaction via UART communication;

[0023] S8: Perform temperature acquisition.

[0024] Furthermore, the specific processes of S2-S8 include:

[0025] S21: Select the pulse transmission mode based on configuration parameters; the storage mode generates a variable data stream in real time, or the register mode has a fixed information format.

[0026] S22: Outputs test signals with adjustable pulse width and frequency through 32 channels;

[0027] S31: Configurable filtering of 32-channel IO input pulses;

[0028] S32: Use register acquisition method to overwrite and update real-time data, or use storage acquisition method to record pulse information in full;

[0029] S33: Upload pulse detection data, including constant high and constant low states, dual-edge time, pulse width, and period;

[0030] S41: Configure the SPI controller clock frequency to be half the system clock frequency;

[0031] S42: Write analog output data to the DA chip;

[0032] S43: Obtain DA chip register data through two rounds of read operations;

[0033] S51: Acquire analog signals;

[0034] S52: Execute the partition mean algorithm, partition the sampled data into 128 partitions and calculate the mean;

[0035] S53: Upload the mean data to the register;

[0036] S61: Start EEPROM read / write via configuration register;

[0037] S62: Automatically reads EEPROM data into the chip's internal RAM upon power-up;

[0038] S63: Responds to the host computer reset operation;

[0039] S71: Configure UART parameters, including baud rate, start bit, data bits, parity bit, and stop bit;

[0040] S72: Sends and receives data through a 256-byte FIFO buffer;

[0041] S73: Employs a dual interrupt mechanism to trigger data reading, including data volume interrupt and timeout interrupt;

[0042] S81: Initiate temperature acquisition via the 18B20 interface;

[0043] S82: Read the temperature value and write it to the register.

[0044] Furthermore, it also includes:

[0045] S9: Manages eight subspaces via the address controller, including system bus, pulse transmission, pulse reception, EEPROM read / write, ADC acquisition, DAC output, serial port, and temperature subspace.

[0046] The beneficial effects achieved by this invention are as follows:

[0047] First, the multi-functional test chip based on the PXI architecture designed in this invention significantly improves the performance and reliability of the test chip by integrating dedicated functional modules to replace the general-purpose design of traditional FPGAs. The address controller divides the 16MB address space of the bus interface into eight logical subspaces, each of which independently corresponds to functional modules such as pulse transmission, pulse detection, analog signal acquisition, analog signal output, serial communication, storage control, and temperature acquisition. This enables precise resource allocation and control, avoids signal conflicts and resource waste, and greatly enhances the modularity and scalability of the system. The centralized management mechanism simplifies the communication process, reduces latency, ensures efficient data interaction capabilities, and eliminates the complex requirements of FPGA debugging. Only external interface circuits and host computer configuration are needed to cover multiple operating condition test scenarios, significantly shortening the development cycle and reducing hardware costs.

[0048] Secondly, the pulse transmission module designed in this invention supports a dual-mode switching mechanism. The storage-type mode can generate dynamically changing pulse data streams in real time to adapt to complex testing requirements, while the register mode maintains a fixed pulse information format to ensure output stability. It outputs test signals with adjustable pulse width and frequency through 32 channels, effectively improving signal accuracy and anti-interference capabilities. The pulse detection module adopts a configurable filtering design and dual acquisition methods. The register acquisition method optimizes real-time data updates to save resources, while the storage-type acquisition method completely records all pulse information to prevent omissions by the host computer. This ensures the integrity of pulse information, including normal high / low states, double-edge timing, pulse width, and period, significantly improving data reliability and noise immunity.

[0049] Third, the analog signal acquisition module designed in this invention is compatible with dedicated acquisition chips and applies a partitioned averaging algorithm to process sampled data. By partitioning the raw data and calculating the average, the impact of noise is significantly reduced, and data accuracy and real-time performance are improved. The analog signal output module achieves wide-range output through an SPI controller, with stable and accurate waveforms. Combined with the UART protocol conversion and 256-byte FIFO buffer design of the serial communication module, data flow control is optimized and the risk of data loss is reduced. The automatic loading mechanism of the storage controller module quickly reads EEPROM calibration data into the chip's internal RAM upon board power-up, shortening startup time and simplifying storage management. Meanwhile, the temperature acquisition module monitors the board's operating status in real time, further improving the overall reliability and lifespan of the system.

[0050] Fourth, this invention designs a control method for a multi-functional test chip based on the PXI architecture. By coordinating the scheduling of each subspace through an address controller, it ensures the orderly execution of steps such as pulse transmission, detection, analog output and acquisition, EEPROM operation, UART communication, and temperature acquisition, covering the entire process of initialization, signal generation, data acquisition, and status monitoring. This modular scheduling mechanism optimizes the efficient execution of test tasks, significantly improves the system's anti-interference capability and adaptability, and can meet the complex testing needs of aerospace telemetry and control and other fields. At the same time, it significantly reduces maintenance costs and development difficulty, and enhances the stability and practicality of the test system. Attached Figure Description

[0051] Figure 1 It is a chip functional block diagram, showing the core functional modules and their interrelationships of a multi-functional test chip based on the PXI architecture.

[0052] Figure 2 This is a schematic diagram of the FPGA chip structure, showing the dimensions of the FPGA chip in the Artix-7 FPGAs model.

[0053] Figure 3 This is a waveform of the TTL command sending function, verifying the TTL command output waveform of the pulse sending module, demonstrating the test signal function with adjustable pulse width and frequency.

[0054] Figure 4 This is a diagram showing the analog signal acquisition function, illustrating the working status of the 32-channel analog signal acquisition module.

[0055] Figure 5 It displays the waveform of a 1V analog output, showing the waveform when the analog output module generates a 1V voltage. The output effect of the DA chip can be captured using an oscilloscope.

[0056] Figure 6 It is an analog output -10V waveform diagram, showing the waveform when the analog output module generates a -10V voltage, verifying the stability of the negative voltage output.

[0057] Figure 7 It displays the +10V waveform of the analog output module, showing the waveform when the analog output module generates a +10V voltage, verifying the accuracy of the positive voltage output.

[0058] Figure 8 This is a test of the 32-channel analog output function, showing the real-time display diagram of the host computer for the test of the 32-channel analog output and acquisition function.

[0059] Figure 9 This is a schematic diagram of the ASIC03 multi-functional test chip structure of the present invention. Detailed Implementation

[0060] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. In addition, the forms of the various structures described in the following embodiments are merely illustrative. The present invention is not limited to the structures described in the following embodiments. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0061] Reference Figures 1-9 This invention provides a multi-functional test chip based on the PXI architecture, codenamed ASIC03. Its structure includes a bus interface, functional module groups, and an address controller. These components work collaboratively through internal hardware connections to achieve data interaction with a host computer and various testing functions. The bus interface is located at the front end of the chip and connects directly to the host computer via the PXI bus, enabling bidirectional transmission of all data, including command sending and result receiving. This ensures efficient data interaction capabilities and reduces the complexity of external circuitry. The address controller is integrated within the chip, dividing the 16MB address space of the bus interface into eight logical subspaces. Each subspace corresponds to a functional module. The pulse sending module is mapped to the 0x2_0000 address subspace, and the pulse detection module is mapped to the 0x4_0000 address subspace. This allows the host computer to precisely configure and control each module, avoiding resource conflicts and improving the overall system's modularity and scalability.

[0062] The PXI bus signal sent by the host computer first enters the bus interface, and then the address controller routes it to the subspace of the corresponding functional module according to the address mapping. The result signal after the module is processed is then sent back to the host computer through the bus interface. This hierarchical signal flow simplifies the communication process, reduces latency, and thus shortens the power-on startup time to the microsecond level, which is 99% faster than the traditional FPGA solution.

[0063] The chip integrates multiple dedicated modules to replace the general functions of an FPGA, enabling code-free debugging. Only external interface circuitry and host computer configuration are needed to cover most test conditions, significantly reducing development cycle and cost. The host computer sends configuration parameters to the address controller via the PXI bus. The controller parses the instructions and allocates them to the corresponding subspace, thereby initializing or controlling the operation of functional modules, such as setting pulse transmission modes or initiating temperature acquisition. This centralized control mechanism enhances the system's flexibility and reliability.

[0064] The functional module group is the core functional unit of the chip, including a pulse transmission module, a pulse detection module, an analog signal acquisition module, an analog signal output module, a serial communication module, a storage controller module, and a temperature acquisition module. Each module is connected to the bus interface through a specific subspace and is managed uniformly by the address controller. The pulse transmission module is connected to the pulse transmission subspace (address 0x2_0000) allocated by the address controller. After receiving instructions from the host computer, it generates a pulse signal output. This module supports dual-mode switching: the storage mode changes the pulse data stream in real time to meet dynamic testing requirements, while the register mode maintains a fixed pulse format to prevent data anomalies. The module outputs test signals with adjustable pulse width and frequency through 32 channels, such as TTL instruction waveforms, suitable for applications such as OC instruction transmission and relay control, improving the accuracy and stability of the test signal while avoiding FPGA resource waste. The waveform output of this module matches expectations, and the pulse width can be precisely adjusted, demonstrating the high reliability of the chip.

[0065] The pulse detection module receives instructions from the host computer through the pulse receiving subspace (address 0x4_0000), detects the input pulse signal, performs configurable filtering on 32 I / O inputs, collects and uploads the data. The module supports dual acquisition modes: register acquisition mode overwrites and updates real-time data to save memory, and storage acquisition mode records all pulse information to prevent the host computer from missing any. The detection is initiated by routing host computer instructions through the address controller. This design ensures the integrity of the pulse information, including dual-edge time, pulse width and period data. The configurable filtering range improves anti-interference capability and reduces hardware debugging costs by 90% compared to traditional FPGA solutions.

[0066] The analog signal acquisition module connects to the bus interface via the ADC acquisition subspace (address 0x8_0000) to acquire and process analog signals. This module operates independently of other functions, avoiding signal interference. It is compatible with the AD7606BSTZ acquisition chip and supports simultaneous acquisition of 32 channels of analog signals. Data is processed using a partitioned averaging algorithm: the average of 128 sampled data points is calculated and then written to a register. The module allows for expansion of the channel count by controlling an external MAX306 switch via a host computer. Without control, it can acquire 8 channels; with control, it can acquire up to 32 channels. This processing optimizes data accuracy and real-time performance. Acquisition is initiated by receiving commands from the host computer via an address controller, reducing noise impact and improving acquisition efficiency, making it suitable for multi-channel testing scenarios.

[0067] The analog output module includes an SPI controller that communicates with the digital-to-analog converter (DAC) via the DAC output subspace (address 0xA_0000) to output analog signals. The address controller isolates the subspace to ensure independent operation. The SPI controller clock frequency is set to half the system clock, such as 16.5MHz. Through two rounds of read / write operations, the first round writes output data, and the second round reads the DAC chip register to achieve analog output, such as generating 1V, -10V, or +10V voltages. The waveform output is stable and accurate. The module only performs SPI protocol conversion; the specific protocol is implemented by the host computer. Output is initiated via routing instructions from the address controller. The output range is wide, such as -10V to +10V. Verification of its work in conjunction with the acquisition module during measurement ensures data consistency.

[0068] The serial communication module is configured as a UART protocol converter, interacting with the host computer through the serial port subspace (address 0xC_0000), with communication independent of other functional modules. Data is transmitted and received via a 256-byte FIFO buffer. After the host computer sets parameters such as baud rate and start bit, the module employs a dual interrupt mechanism: data volume interrupt and timeout interrupt trigger reading. Limited to protocol conversion, it does not handle other protocols. Communication is initiated by the address controller receiving the host computer's configuration. The FIFO design optimizes data flow control, reducing the risk of data loss and making it suitable for high-speed serial communication. The storage controller module acts as an EEPROM controller, connected to the bus interface through the EEPROM read / write subspace (address 0x6_0000), sharing configuration registers with the temperature acquisition module to reduce redundancy. Upon power-up, the board automatically reads EEPROM data into the chip's internal RAM for subsequent access by the host computer for calibration data storage. It supports read, write, and reset operations, managing data through address controller routing instructions. The automatic loading mechanism shortens startup time and saves external storage costs. The temperature acquisition module interfaces with an 18B20 sensor via the temperature subspace (address 0xE_0000), and its independent design ensures temperature data isolation. After acquiring the temperature from the board, it writes it to the register. The host computer only needs to start or stop the acquisition, and the address controller processes the instructions, monitoring the board status in real time, which improves the system's reliability and lifespan.

[0069] The chip manages all subspaces, including the system bus subspace for global configuration, through an address controller, ensuring that all modules are arranged in an orderly manner within the address space and avoiding signal conflicts. After the host computer sends function parameters to initialize the interface circuit, it sequentially executes steps such as pulse transmission, detection, analog output, acquisition, EEPROM operation, UART communication, and temperature acquisition. For example, in step S2, the pulse transmission mode is selected based on the configuration, covering most of the needs of ground testing. The address controller coordinates all processes to ensure efficient execution. The chip area is reduced by 69% compared to FPGA, from 729 mm² to 225 mm², power consumption is reduced by 98%, and the development cycle is shortened by more than 50%.

[0070] The chip has passed testing on verification boards and derivative products, such as analog acquisition cards and TTL command transmission cards, and its functions meet expectations, demonstrating its practicality in the field of aerospace telemetry and control.

[0071] The ASIC03 multi-interface chip requires no FPGA debugging; only the corresponding interface circuits need to be configured, and the host computer needs to be configured accordingly to achieve the desired functions, covering most ground testing conditions. Currently, this chip mainly interacts with the host computer via the PXI bus to achieve control pulse transmission, pulse detection data (constant high, constant low) upload, SPI communication analog output, analog data acquisition and upload, EEPROM read / write operations, UART communication, temperature acquisition, IO input, and test signal output. The hardware chip functional block diagram is shown below. Figure 1 As shown.

[0072] This chip replaces the FPGA, reducing chip area by more than 45%, price by 83%, power consumption by 98%, and power-on startup time to the microsecond level, shortening it by 99%. At the same time, the development cycle is shortened by more than 50%.

[0073] The ASIC03 chip area is reduced by more than 45% compared to the traditional FPGA area, such as... Figure 2 and Figure 9 As shown, the actual area of ​​ASIC03 is approximately 225 mm². 2 The comparable FPGA size is approximately 729mm². 2 The actual chip area is reduced by 69%.

[0074] ASIC03 eliminates the need for FPGA programming, further reducing labor costs and significantly shortening the development cycle. Compared to FPGA, development costs can be reduced by more than 90%.

[0075] The pulse transmission includes 32 channels, applicable to common instruction control designs such as OC instruction transmission, emitter-follower instruction transmission, relay control, and TTL transmission. Each channel transmits pulses using a dual-mode cold-switching approach: a stored-mode transmission mode, which allows for continuous real-time changes to the pulse information data stream; and a register-mode transmission mode, where the transmitted pulse information has a fixed format, effectively preventing malfunctions in the stored-mode transmission. The PC can configure registers via the PCI bus to determine which mode the interface pulse transmission uses. Figure 3 The waveform shown is for the TTL command sending function. The pulse width, frequency, etc. are all consistent with the expected settings.

[0076] The pulse detection system includes 32 channels, and the chip records interface pulse information in real time. Each channel's received pulses can be filtered according to user requirements; the PC can set the filtering range before data acquisition. Simultaneously, the chip records interface pulse information in real time, including dual-edge timing information, pulse width information, pulse period information, pulse channel number information, pulse count information, maximum and minimum periods, and pulse width information.

[0077] The pulse acquisition employs a dual-mode hot standby approach, consisting of register-based acquisition and storage-based acquisition. In register-based acquisition mode, the chip updates interface pulse information using an overwrite method. In storage-based acquisition mode, the chip can comprehensively store and record all pulse information from the chip's input, effectively preventing PC from missing data.

[0078] This design is adapted to an AD7606BSTZ data acquisition chip, and currently focuses on adapting to common, high-volume chips. For example... Figure 4 The image shows the simultaneous acquisition status of 32 channels.

[0079] Low-speed analog signal acquisition. Data from each channel is averaged after 128 acquisitions, and the averaged data is stored in a register for the host computer to read. The number of acquisition channels can be expanded later using analog switches and other devices to adapt to multi-channel acquisition needs.

[0080] The low-speed analog signal acquisition data is written to the chip's internal register using a partitioned mean algorithm. The partitioned mean algorithm first partitions the interface sampling data into 128 values, then calculates the mean of the partitioned data, and finally writes the mean data to the register in an overwrite manner.

[0081] The PC can control whether the chip can control the external MAX306 by configuring the PCI register. Without controlling the external MAX306, 8 channels can be acquired simultaneously; with control, 32 channels can be acquired simultaneously.

[0082] The analog output function of the SPI controller is as follows: one SPI controller communicates with the DA chip (AD5372). The ASIC03 only performs SPI protocol conversion; the specific application protocol is implemented by the CPU. For example... Figure 5 As shown, the host computer sets typical output values ​​of 1V, -10V, and 10V, and captures the DA output waveform using an oscilloscope.

[0083] like Figure 8 The diagram shows the real-time display function of the host computer in comparison with the 32-channel analog output function of the ASIC03 and the analog acquisition function of the ASIC03.

[0084] The SPI controller can read and write registers at a clock frequency that is half the system clock (16.5MHz). A write operation is a single write of data (analog output data). A read operation reads data from the DA chip's internal registers (divided into two rounds: the first round sends the read command, and the second round reads the returned data), interacting with the CPU using registers.

[0085] For UART communication, the ASIC03 only performs UART protocol conversion (it does not process other protocols), and communicates with the CPU for data transmission and reception via a FIFO. The FIFO's transmit and receive capacity is 256 bytes.

[0086] When sending UART data, the host computer controls the transmission flow by polling (checking the number of fillable bytes in the FIFO). When receiving UART data, the ASIC03 uses interrupts to instruct the CPU to read the data. UART data reception interrupts support both timeout interrupts and data volume interrupts (after receiving an interrupt, the CPU reads the interrupt status, clears the interrupt, reads the FIFO data volume, and finally reads the data).

[0087] The transmit and receive baud rates are configurable, as are the start bit, data bits, parity bit, and stop bit. Data is transmitted as soon as it is available; no word or frame intervals are specified.

[0088] The 18B20 temperature measurement interface measures the operating temperature of the circuit board for status monitoring. The CPU can start or stop temperature acquisition. The acquired temperature value is obtained via registers.

[0089] The EEPROM controller is used for AD calibration, and the CPU can read and write to the E2PROM interface. After the board is powered on, the software automatically reads the E2PROM data into the internal RAM of the ASIC03 chip, and then the CPU retrieves the E2PROM data from the internal RAM. The CPU can configure the control word of the E2PROM, and the CPU can perform a reset operation on the E2PROM; there is a reset procedure.

[0090] The PCI bus uses BAR2 to communicate with the host. BAR2 has a space of 16MB and divides the bus address space into 8 subspaces, as shown in Table 1. Each register is the subspace address plus the offset address of the response module.

[0091] Table 1 Subspace Partitioning

[0092] Serial Number definition address 0 System bus 0x0_0000 1 Second pulse transmission 0x2_0000 2 Second pulse reception 0x4_0000 3 EEPROM Read / Write 0x6_0000 4 ADC acquisition 0x8_0000 5 DAC output 0xA_0000 6 serial port 0xC_0000 7 temperature 0xE_0000

[0093] This invention also provides a control method for a multifunctional test chip based on a PXI architecture, comprising the following steps:

[0094] S1: Receive function configuration parameters from the host computer via PXI bus and initialize the interface circuit; S2: Execute control pulse transmission and generate test signal output; S3: Execute pulse detection, collect IO input data and upload constant high or constant low status; S4: Implement analog output via SPI communication; S5: Execute analog data acquisition and upload processing results; S6: Execute EEPROM read / write operations; S7: Perform data interaction via UART communication; S8: Execute temperature acquisition.

[0095] The specific process includes:

[0096] S21: Select the pulse transmission mode based on configuration parameters; in storage mode, generate a variable data stream in real time, or in register mode, use a fixed information format. S22: Output test signals with adjustable pulse width and frequency through 32 channels. S31: Perform configurable filtering on the 32-channel IO input pulses. S32: Use register acquisition to overwrite and update real-time data, or use storage acquisition to record all pulse information. S33: Upload pulse detection data, including constant high and constant low states, double-edge time, pulse width, and period. S41: Configure the SPI controller clock frequency to half the system clock. S42: Write analog output data to the DA chip. S43: Obtain DA chip register data through two rounds of read operations. S51: S52: Acquire analog signals; S53: Execute the partitioned averaging algorithm, partition the sampled data into 128 partitions and calculate the average; S64: Upload the average data to the register; S65: Start EEPROM read / write through the configuration register; S66: Automatically read EEPROM data to the chip's internal RAM upon power-up; S67: Respond to the host computer reset operation; S78: Configure UART parameters, including baud rate, start bit, data bits, parity bit, and stop bit; S79: Send and receive data through a 256-byte FIFO buffer; S70: Trigger data reading using a dual interrupt mechanism, including data volume interrupt and timeout interrupt; S81: Start temperature acquisition through the 18B20 interface; S82: Read the temperature value and write it to the register.

[0097] It also includes S9: managing eight subspaces via the address controller, including the system bus, pulse transmission, pulse reception, EEPROM read / write, ADC acquisition, DAC output, serial port, and temperature subspace.

[0098] In the above process, the execution flow of each functional module is uniformly coordinated by the address controller to ensure efficient system operation. The host computer sends functional configuration parameters to the chip bus interface via the PXI bus, initializes all interface circuits, and establishes the basic communication environment for subsequent functional operations. The control process systematically executes pulse transmission operations, selecting either a stored transmission mode or a register transmission mode based on the configuration parameters. The former generates dynamically changing pulse data streams in real time to adapt to complex testing requirements, while the latter maintains a fixed pulse information format to ensure output stability. Test signals with adjustable pulse width and frequency are output through 32 independent channels.

[0099] When performing pulse detection operations synchronously, configurable filtering is applied to the 32 input pulse signals to eliminate interference. Depending on the requirements, register acquisition is used to overwrite and update real-time data to optimize resource usage, or storage acquisition is enabled to fully record all pulse information to prevent data loss. Finally, detection data containing information on constant high / low states, dual-edge time, pulse width, and period is uploaded.

[0100] Analog output is implemented via an SPI controller, whose clock frequency is configured to a specific division value of the system clock to match communication timing. The analog data set by the host computer is written to the digital-to-analog converter chip, and the accuracy of the output data is verified synchronously through two rounds of read / write operations. Analog acquisition is performed by a dedicated acquisition chip that obtains multiple signals. A partitioned averaging algorithm is used to process the raw sampled data; that is, the data is partitioned a fixed number of times, and the average value of each partition is calculated to improve data accuracy. Finally, the processing results are uploaded to a register for the host computer to read.

[0101] Storage control operations are executed by the EEPROM controller, which responds to host computer commands to initiate the calibration data read / write process. Upon power-up, the board automatically loads the EEPROM-stored data into the chip's internal RAM for rapid initialization and supports reset operations to restore the stored state. Serial communication operations configure the UART protocol's baud rate, start bit, data bits, parity bit, and stop bit parameters. Data flow is managed through a 256-byte FIFO buffer, and a dual interrupt mechanism (data threshold interrupt and timeout interrupt) is used to trigger data readings to ensure real-time performance. Temperature acquisition operations initiate temperature measurement through a dedicated sensor interface, writing the acquired board operating temperature value into a register for status monitoring.

[0102] The execution of all functional modules is dynamically managed by the address controller to achieve coordinated scheduling across eight logical subspaces, including system bus configuration space, pulse transmission space, pulse reception space, EEPROM storage space, analog signal acquisition space, analog signal output space, serial communication space, and temperature acquisition space. Each subspace is independently addressable to avoid resource conflicts. This method fully covers the core processes of chip initialization, signal generation, data acquisition, communication interaction, and status monitoring. The modular scheduling mechanism ensures efficient execution of test tasks and system reliability, meeting the requirements of multi-condition testing.

[0103] Example 1 describes the practical application of the PXI-based multifunctional test chip ASIC03 and its control method in aerospace ground testing scenarios.

[0104] In this embodiment 1, an industrial computer is used as the host computer, interacting with the ASIC03 chip via the PXI bus to ensure efficient execution of test signal generation, data acquisition, and status monitoring. The specific implementation steps are described in detail below:

[0105] The host computer first sends the function configuration parameters S1 to the ASIC03 chip via the PXI bus, including pulse mode selection, filtering range and UART baud rate, triggering the address controller to initialize all interface circuits, including bus interface and subspace mapping of each functional module. Due to the reduction of external circuit complexity and startup delay, a stable foundation is established for subsequent testing. The initialization process only takes microseconds, which is 99% faster than the traditional FPGA solution.

[0106] Next, in step S2, the control pulse transmission is executed. The host computer selects a stored transmission mode based on the configuration and generates a variable data stream pulse signal in real time to simulate the dynamic requirements of satellite relay control. The ASIC03 chip outputs adjustable pulse width and frequency test signals through 32 channels. For example, in satellite communication module testing, TTL commands are output to verify relay response. Precise signal adjustment ensures test reliability. The dual-mode switching mechanism avoids data anomalies and FPGA resource waste. Simultaneously, the 32-channel output supports common scenarios such as OC command transmission, reducing hardware debugging costs by 90%.

[0107] Subsequently, pulse detection step S3 performs configurable filtering on the 32 input pulses, sets the filtering range to eliminate noise interference, and uses register acquisition to overwrite and update real-time data, ensuring the constant high or low state, dual-edge time, pulse width, and period information of the uploaded satellite module. In the test, this method completely recorded the pulse information, preventing data loss from the host computer. The full recording function of the storage-type acquisition method enhances data integrity, while configurable filtering improves anti-interference capability and reduces debugging overhead by 90% compared to traditional solutions.

[0108] The analog output step S4 is implemented via SPI communication. The SPI controller clock frequency is configured to be half the system clock, approximately 16.5MHz. Analog data is written to the AD5372 chip, and output stability is verified through two rounds of read operations. In satellite module testing, 1V, -10V, and +10V voltages are generated to calibrate the power supply response. The wide output range (-10V to +10V) and high waveform stability make the high-precision output suitable for multi-channel testing scenarios. Furthermore, the SPI protocol conversion simplifies the design, eliminating the need for additional code development.

[0109] When the analog signal acquisition step S5 is executed, the AD7606BSTZ chip is used to acquire 32 channels of analog signals. The data is processed using a partitioned averaging algorithm, and the average of the 128 samples is calculated and uploaded to the register. In satellite module testing, this process acquires multiple voltage and current signals. The host computer expands the number of channels by controlling the external MAX306 switch, which reduces the impact of noise, improves data accuracy and real-time performance, supports the simultaneous acquisition of 32 signals, and optimizes test efficiency.

[0110] EEPROM read / write operation S6 is initiated through the configuration register. Upon power-up, it automatically reads calibration data into the chip's internal RAM and responds to the host computer's reset command. In Example 1, this step stores the calibration parameters of the satellite module and quickly restores the state after reset. The automatic loading mechanism shortens the startup time and saves external storage costs. This design achieves microsecond-level initialization when the board is powered on.

[0111] UART communication step S7 configures parameters such as baud rate and start bit, and sends and receives data through a 256-byte FIFO buffer. It adopts a dual interrupt mechanism, with data volume interrupt and timeout interrupt triggering reading. In the test, this method was used to upload satellite status data to the monitoring system. The FIFO design optimizes data flow control, reduces the risk of data loss, is suitable for high-speed communication, and improves the reliability of interaction.

[0112] Temperature acquisition step S8 is initiated via the 18B20 interface, reading the board temperature value and writing it to the register. In Example 1, this process monitors the operating temperature of the ASIC03 chip in real time to prevent overheating and abnormalities. Real-time status monitoring improves system reliability, and the document shows that this design extends the life of the device.

[0113] The entire process manages eight subspaces S9 through the address controller, including the system bus, pulse transmission, pulse reception, EEPROM read / write, ADC acquisition, DAC output, serial port, and temperature subspace, ensuring that each module can be addressed independently and executed in an orderly manner. In satellite testing, this mechanism avoids resource conflicts, such as separating the pulse transmission subspace address 0x2_0000 from the pulse reception subspace address 0x4_0000, improving overall modularity and scalability, reducing chip area by 69% and power consumption by 98%, and shortening the development cycle by more than 50%.

[0114] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A multi-functional test chip based on PXI architecture, characterized in that, The chip is an ASIC chip, which includes: a bus interface for data interaction with the host computer via a PXI bus; The functional module group includes a pulse transmission module, a pulse detection module, an analog signal acquisition module, an analog signal output module, a serial communication module, a storage controller module, and a temperature acquisition module; The pulse transmitting module connects to the bus interface to send pulse signals; the pulse detection module receives instructions from the host computer through the subspace allocated by the address controller and detects the input pulse signals; the analog signal acquisition module connects to the ADC acquisition subspace of the bus interface to acquire analog signals and process the data using a partitioned averaging algorithm; the analog signal output module includes an SPI controller, which communicates with the digital-to-analog converter through the DAC output subspace managed by the address controller to output analog signals; the serial communication module is configured as a UART protocol converter, which interacts with the host computer through the serial port subspace of the bus interface; the storage controller module acts as an EEPROM controller, connected to the EEPROM read / write subspace of the bus interface, performs calibration data storage and automatic loading into RAM upon power-on, and shares the configuration register with the temperature acquisition module; the temperature acquisition module acquires the board temperature through the temperature subspace allocated by the address controller and the interface sensor, and writes the data into the register; The address controller divides the address space of the bus interface into multiple subspaces, each subspace corresponding to a functional module, enabling the host computer to configure and control the functional module group.

2. The test chip according to claim 1, characterized in that, The pulse transmission module is configured to transmit pulse signals and supports both storage-type transmission mode and register-type transmission mode. In storage-type transmission mode, the pulse information data stream is changed in real time, while in register-type transmission mode, the pulse information format is kept fixed. The pulse transmission module outputs test signals with adjustable pulse width and frequency through 32 channels.

3. The test chip according to claim 1, characterized in that, The pulse detection module detects the input pulse signal and supports register acquisition mode and storage acquisition mode; wherein, the register acquisition mode updates the pulse information by overwriting, and the storage acquisition mode records all pulse information; the pulse detection module performs configurable filtering on 32-channel IO input pulses and uploads constant high, constant low state, dual edge time, pulse width and period data.

4. The test chip according to claim 1, characterized in that, The analog signal acquisition module acquires analog signals and processes the sampled data using a partitioned mean algorithm, including partitioning the sampled data into 128 partitions and calculating the mean. The analog signal acquisition module is compatible with the AD7606BSTZ acquisition chip and supports simultaneous acquisition of 32 channels of analog signals.

5. The test chip according to claim 1, characterized in that, The analog output module includes an SPI controller that communicates with the digital-to-analog converter to achieve analog output; the clock frequency of the SPI controller is half of the system clock, and it interacts with the DA chip through two rounds of read and write operations.

6. The test chip according to claim 1, characterized in that, The serial communication module is configured with UART protocol conversion and interacts with the host computer through a 256-byte FIFO buffer; the storage controller module is configured as an EEPROM controller for calibration data storage and supports host computer read / write operations and reset operations; when the board is powered on, it automatically reads EEPROM data into the chip's internal RAM; the temperature acquisition module is configured to interface with an 18B20 temperature sensor to acquire the board's operating temperature and store the temperature value in a register.

7. The test chip according to claim 1, characterized in that, The address controller divides the address space into eight subspaces, including the system bus subspace, pulse transmission subspace, pulse reception subspace, EEPROM read / write subspace, ADC acquisition subspace, DAC output subspace, serial port subspace, and temperature subspace.

8. The control method for a multi-functional test chip based on a PXI architecture as described in any one of claims 1-7, characterized in that, Includes the following steps: S1: Receives function configuration parameters from the host computer via the PXI bus and initializes the interface circuit; S2: Executes control pulse transmission and generates test signal output; S3: Perform pulse detection, collect IO input data and upload the constant high or constant low status; S4: Analog output is achieved via SPI communication; S5: Perform analog data acquisition and upload the processing results; S6: Perform EEPROM read / write operations; S7: Data interaction via UART communication; S8: Perform temperature acquisition.

9. The method according to claim 8, characterized in that, The specific processes of S2-S8 include: S21: Select the pulse transmission mode based on configuration parameters; the storage mode generates a variable data stream in real time, or the register mode has a fixed information format. S22: Outputs test signals with adjustable pulse width and frequency through 32 channels; S31: Configurable filtering of 32-channel IO input pulses; S32: Use register acquisition method to overwrite and update real-time data, or use storage acquisition method to record pulse information in full; S33: Upload pulse detection data, including constant high and constant low states, dual-edge time, pulse width, and period; S41: Configure the SPI controller clock frequency to be half the system clock frequency; S42: Write analog output data to the DA chip; S43: Obtain DA chip register data through two rounds of read operations; S51: Acquire analog signals; S52: Execute the partition mean algorithm, partition the sampled data into 128 partitions and calculate the mean; S53: Upload the mean data to the register; S61: Start EEPROM read / write via configuration register; S62: Automatically reads EEPROM data into the chip's internal RAM upon power-up; S63: Responds to the host computer reset operation; S71: Configure UART parameters, including baud rate, start bit, data bits, parity bit, and stop bit; S72: Sends and receives data through a 256-byte FIFO buffer; S73: Employs a dual interrupt mechanism to trigger data reading, including data volume interrupt and timeout interrupt; S81: Initiate temperature acquisition via the 18B20 interface; S82: Read the temperature value and write it to the register.

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