Display panel and display device

Abstract

The invention discloses a display panel and a display device. In the display panel, a first pixel circuit comprises a first reset transistor, and the first reset transistor is electrically connected with a first reset line and a first light-emitting element; the second pixel circuit comprises a second reset transistor, and the second reset transistor is electrically connected with a second reset line and a second light-emitting element; the first reset line comprises a first branch line and a second branch line, the first branch line extends in the first direction, the second branch line extends in the second direction, and the first branch line and the second branch line are electrically connected and located on different film layers; the second reset line comprises a third branch line and a fourth branch line which are electrically connected, the third branch line extends in the first direction, the fourth branch line extends in the second direction, the third branch line and the fourth branch line are located on different film layers, and the third branch line and the first branch line are located on different film layers; in the thickness direction of the display panel, the first branch line and the third branch line are at least partially overlapped. The display effect of the display panel can be improved.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel and display device. Background Technology

[0002] With the development of display technology, display panels are becoming increasingly common, and users have higher and higher requirements for the display effect of display panels. How to improve the display effect of display panels has been a research direction that those skilled in the art have been committed to. Summary of the Invention

[0003] This application provides a display panel and a display device that can improve the display effect of the display panel.

[0004] In a first aspect, embodiments of this application provide a display panel, including a first pixel circuit, a first light-emitting element, and a first reset line. The first pixel circuit includes a first reset transistor, which is electrically connected to the first reset line and a first electrode of the first light-emitting element. The panel also includes a second pixel circuit, a second light-emitting element, and a second reset line. The second pixel circuit includes a second reset transistor, which is electrically connected to the second reset line and the first electrode of the second light-emitting element. The first reset line includes a first branch line and a second branch line, the first branch line extending along a first direction and the second branch line extending along a second direction. The first branch line and the second branch line are electrically connected and located in different film layers, and the first direction and the second direction intersect. The second reset line includes a third branch line and a fourth branch line, which are electrically connected. The third branch line extends along the first direction and the fourth branch line extends along the second direction. The third branch line and the fourth branch line are electrically connected and located in different film layers, and the third branch line and the first branch line are located in different film layers. In the thickness direction of the display panel, the first branch line and the third branch line at least partially overlap.

[0005] Secondly, embodiments of this application provide a display device, including a display panel as described in the first aspect embodiment.

[0006] According to the display panel and display device provided in the embodiments of this application, on the one hand, the first reset line is electrically connected to the first light-emitting element, and the second reset line is electrically connected to the second light-emitting element. In this way, different reset signals can be transmitted to the first light-emitting element and the second light-emitting element using different reset lines to reset the first light-emitting element and the second light-emitting element to different degrees, which can improve or even avoid the problems of color deviation and uneven display of low grayscale. On the other hand, both the first reset line and the second reset line have a grid structure, which can reduce the voltage drop of the reset line, thereby better solving the problems of color deviation and uneven display. Furthermore, the third sub-line and the first sub-line overlap at least partially, which can reduce the area occupied by the third sub-line and the first sub-line in the top view, thereby saving drawing space and improving resolution while realizing the gridding of the first reset line and the second reset line. Attached Figure Description

[0007] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals denote the same or similar features, and the drawings are not drawn to scale.

[0008] Figure 1 This illustration shows a schematic diagram of a pixel circuit in a display panel provided in an embodiment of this application;

[0009] Figure 2 This illustration shows a schematic diagram of a film layer structure of a display panel provided in an embodiment of this application;

[0010] Figure 3 Show Figure 2 A schematic diagram of the first part of the structure;

[0011] Figure 4 Show Figure 2 A schematic diagram of the second part of the structure;

[0012] Figure 5 A schematic diagram of an auxiliary metal layer corresponding to 2 is shown;

[0013] Figure 6 Show Figure 2 A schematic diagram of a structure of the first semiconductor layer in the middle;

[0014] Figure 7 Show Figure 2 A schematic diagram of a structure of the first gate layer in the middle;

[0015] Figure 8 Show Figure 2 A schematic diagram of a structure of a capacitor metal layer;

[0016] Figure 9 Show Figure 2 A schematic diagram of a structure of the second semiconductor layer in the middle;

[0017] Figure 10 Show Figure 2 A schematic diagram of a structure of the second gate layer in the middle;

[0018] Figure 11 Show Figure 2 A schematic diagram of a structure of the first metal layer in the middle;

[0019] Figure 12 Show Figure 2 A schematic diagram of a structure of the second metal layer in the middle;

[0020] Figure 13 Show Figure 2 A corresponding cross-sectional structural diagram;

[0021] Figure 14 This diagram illustrates another film layer structure of the display panel provided in an embodiment of this application.

[0022] Figure 15 Show Figure 14 A schematic diagram of the first part of the structure;

[0023] Figure 16 Show Figure 14 A schematic diagram of the second part of the structure;

[0024] Figure 17 Show Figure 14 A schematic diagram of the third part of the structure;

[0025] Figure 18 A schematic diagram of a structure for the auxiliary metal layer corresponding to 14 is shown;

[0026] Figure 19 Show Figure 14 A schematic diagram of a structure of the first semiconductor layer in the middle;

[0027] Figure 20 Show Figure 14 A schematic diagram of a structure of the first gate layer in the middle;

[0028] Figure 21 Show Figure 14 A schematic diagram of a structure of a capacitor metal layer;

[0029] Figure 22 Show Figure 14 A schematic diagram of a structure of the second semiconductor layer in the middle;

[0030] Figure 23 Show Figure 14 A schematic diagram of a structure of the second gate layer in the middle;

[0031] Figure 24 Show Figure 14 A schematic diagram of a structure of the first metal layer in the middle;

[0032] Figure 25 Show Figure 14 A schematic diagram of a structure of the second metal layer in the middle;

[0033] Figure 26 Show Figure 14 A schematic diagram of a structure of the third metal layer in the middle;

[0034] Figure 27 Show Figure 14 A schematic diagram of a structure consisting of a third metal layer and an anode metal layer;

[0035] Figure 28 Show Figure 14 A corresponding cross-sectional structural diagram;

[0036] Figure 29 This illustration shows a schematic diagram of a pixel circuit in a display panel provided in an embodiment of this application;

[0037] Figure 30 This diagram illustrates yet another film layer structure of the display panel provided in an embodiment of this application;

[0038] Figure 31 This is a schematic diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0039] The features and exemplary embodiments of various aspects of this application will now be described in detail. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain this application and are not configured to limit this application. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples of this application.

[0040] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0041] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0042] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0043] In the embodiments of this application, the term "electrical connection" can refer to a direct electrical connection between two components, or it can refer to an electrical connection between two components via one or more other components. The display panel can be a display device or a module / part of a display device.

[0044] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this application can be combined with each other without contradiction.

[0045] Display panels typically undergo reliability aging tests (RA) before leaving the factory. RA testing subjects the display panel to high-temperature conditions to verify the durability of its materials, structure, and performance. Because RA testing involves high temperatures, the parasitic capacitance of the light-emitting elements in the display panel will experience varying degrees of brightness decay after the test, potentially leading to color distortion issues when the display is shown.

[0046] In addition, tandem technology is a breakthrough design in the field of organic light-emitting diode (OLED) displays, which significantly improves the performance of display panels by stacking multiple light-emitting layers. However, display panels based on tandem technology suffer from severe lateral leakage in the charge generation layer (CGL), affecting the uniformity of low grayscale display.

[0047] In addition, with the development of display technology, the pursuit of display panel resolution is also relatively high. Therefore, how to balance the resolution and display effect of the display panel is a difficult problem faced by those skilled in the art.

[0048] This application provides a display panel and a display device. The embodiments of this application will be described below with reference to the accompanying drawings.

[0049] The display panel provided in this application embodiment includes pixel circuitry and light-emitting elements, wherein the pixel circuitry is used to drive the light-emitting elements to emit light. Light-emitting elements include, but are not limited to, OLED devices.

[0050] like Figure 1 As shown, the pixel circuit includes a first pixel circuit 11 and a second pixel circuit 12, and the light-emitting elements include a first light-emitting element 21 and a second light-emitting element 22. The first pixel circuit 11 is electrically connected to the first light-emitting element 21, and the second pixel circuit 12 is electrically connected to the second light-emitting element 22.

[0051] The display panel also includes a first reset line Vref1 and a second reset line Vref2.

[0052] The pixel circuit includes a reset transistor T7 for resetting the first electrode of the light-emitting element. The first electrode of the light-emitting element may be the anode.

[0053] Specifically, the first pixel circuit 11 includes a first reset transistor T71. The first terminal of the first reset transistor T71 is electrically connected to the first reset line Vref1, and the second terminal of the first reset transistor T71 is electrically connected to the first terminal of the first light-emitting element 21. The first reset signal on the first reset line Vref1 is used to reset the first terminal of the first light-emitting element 21.

[0054] The second pixel circuit 12 includes a second reset transistor T72. The first terminal of the second reset transistor T72 is electrically connected to the second reset line Vref2, and the second terminal of the second reset transistor T72 is electrically connected to the first terminal of the second light-emitting element 22. The second reset signal on the second reset line Vref2 is used to reset the first terminal of the second light-emitting element 22.

[0055] The first light-emitting element 21 and the second light-emitting element 22 emit different colors. For example, the first light-emitting element 21 is a red light-emitting element, and the second light-emitting element 22 is a green light-emitting element or a blue light-emitting element.

[0056] Since the first light-emitting element 21 and the second light-emitting element 22 are electrically connected to different reset lines, different reset signals can be transmitted to the first light-emitting element 21 and the second light-emitting element 22 respectively using different reset lines, so as to reset the first light-emitting element 21 and the second light-emitting element 22 to different degrees, which can improve or even avoid the problems of color deviation and uneven low grayscale display.

[0057] The arrangement of pixel circuits can be diverse. In the structural diagram of the pixel circuit provided in this application, the pixel circuit is illustrated using "8T1C" as an example, which is not intended to limit this application. Here, "T" represents a transistor and "C" represents a capacitor. Those skilled in the art can make adaptive adjustments to the pixel circuit according to their needs.

[0058] The types of transistors in a pixel circuit can be diverse. Transistors include indium gallium zinc oxide (IGZO) transistors and low-temperature polysilicon (LTPS) transistors. Oxide transistors have advantages such as low leakage current, while LTPS transistors have advantages such as high switching speed, high carrier mobility, and low power consumption. A pixel circuit may include LTPS transistors, or it may include both oxide transistors and LTPS transistors simultaneously. The type of transistor in a pixel circuit can be adaptively adjusted according to actual needs, and this application does not impose specific limitations on this aspect.

[0059] The display panel is composed of multiple overlapping film layers, among which, Figures 2 to 13 The diagram shows schematic representations of the film layer structure of the display panel in some design approaches. Figures 14 to 28 The diagram shows the film layer structure of the display panel in some other design schemes. Figure 30 This diagram illustrates the film layer structure of the display panel in yet another design approach. Wherein, Figures 2 to 12 Structures with the same filling pattern represent the structure of the same film layer, while structures with different filling patterns represent the structures of different film layers. Similarly, Figures 14 to 27 Structures with the same filling pattern represent the structure of the same membrane layer, while structures with different filling patterns represent the structures of different membrane layers.

[0060] by Figures 1 to 13 For example, the first reset line Vref1 includes a first branch line Vref11 and a second branch line Vref12. The first branch line Vref11 extends along a first direction X, and the second branch line Vref12 extends along a second direction Y. Multiple first branch lines Vref11 and multiple second branch lines Vref12 are electrically connected to each other, and the first branch lines Vref11 and the second branch lines Vref12 are located in different film layers. The first branch lines Vref11 and the second branch lines Vref12 can be electrically connected through vias.

[0061] The first direction X intersects the second direction Y. The first direction X and the second direction Y can be perpendicular, for example, the first direction X is the row direction and the second direction Y is the column direction.

[0062] Multiple first branch lines Vref11 and multiple second branch lines Vref12 are electrically connected to each other to form a grid-like first reset line Vref1. This reduces the voltage drop of the first reset line Vref1, thus better solving the problems of color distortion and uneven display.

[0063] The second reset line Vref2 includes electrically connected third branch line Vref23 and fourth branch line Vref24. Third branch line Vref23 extends along a first direction X, and fourth branch line Vref24 extends along a second direction Y. Multiple third branch lines Vref23 and multiple fourth branch lines Vref24 are electrically connected to each other, and the third branch lines Vref23 and fourth branch lines Vref24 are located in different film layers. Third branch lines Vref23 and fourth branch lines Vref24 can be electrically connected to each other vias.

[0064] Multiple third-line Vref23 and multiple fourth-line Vref24 are electrically connected to each other to form a grid-like second reset line Vref2. This reduces the voltage drop of the second reset line Vref2, thus better solving the problems of color distortion and uneven display.

[0065] like Figure 4 As shown, both the third sub-line Vref23 and the first sub-line Vref11 extend along the first direction X. The third sub-line Vref23 and the first sub-line Vref11 are located in different film layers, and in the thickness direction of the display panel, the third sub-line Vref23 and the first sub-line Vref11 at least partially overlap. In other words, the orthographic projections of the third sub-line Vref23 and the first sub-line Vref11 on the substrate of the display panel at least partially overlap. Because the third sub-line Vref23 and the first sub-line Vref11 at least partially overlap, the area occupied by the third sub-line Vref23 and the first sub-line Vref11 in the top view can be reduced, thereby achieving a high resolution display panel while ensuring that both the first reset line Vref1 and the second reset line Vref2 are gridded.

[0066] It should be noted that the third sub-line Vref23 and the first sub-line Vref11 can simply extend along the first direction X, and are not limited to being straight lines. For example, the third sub-line Vref23 and the first sub-line Vref11 can be broken lines extending along the first direction. The same applies to other routing lines, which will not be explained in detail here.

[0067] According to the display panel provided in the embodiments of this application, on the one hand, the first reset line Vref1 is electrically connected to the first light-emitting element 21, and the second reset line Vref2 is electrically connected to the second light-emitting element 22. In this way, different reset signals can be transmitted to the first light-emitting element 21 and the second light-emitting element 22 respectively using different reset lines to reset the first light-emitting element 21 and the second light-emitting element 22 to different degrees, which can improve or even avoid the problems of color deviation and uneven display of low grayscale. On the other hand, the first reset line Vref1 and the second reset line Vref2 are both in a grid structure, which can reduce the voltage drop of the reset line, thereby better solving the problems of color deviation and uneven display. Furthermore, the third sub-line Vref23 and the first sub-line Vref11 overlap at least partially, which can reduce the area occupied by the third sub-line Vref23 and the first sub-line Vref11 in the top view. Thus, while realizing that the first reset line Vref1 and the second reset line Vref2 are both in a grid structure, it can save drawing space to improve the resolution of the display panel.

[0068] In some embodiments, such as Figure 13 As shown, the display panel includes a substrate 01 and a first semiconductor layer B1, a first gate layer M1, a capacitor metal layer MC, a second semiconductor layer B2, and a second gate layer MG, which are sequentially located away from the substrate 01.

[0069] Please refer to the reference. Figure 4 , Figure 8 , Figure 10 and Figure 13 The first branch line Vref11 is located in the second gate layer MG, and the third branch line Vref23 is located in the capacitor metal layer MC.

[0070] Substrate 01 includes, but is not limited to, a flexible substrate. The material of substrate 01 includes, but is not limited to, polyimide (PI).

[0071] The first semiconductor layer B1 includes the active layer of a first type of transistor. The second semiconductor layer B2 includes the active layer of a second type of transistor. For example, the first type of transistor includes a P-type transistor, and the second type of transistor includes an N-type transistor. The material of the first semiconductor layer B1 includes LTPS, and the material of the second semiconductor layer B2 includes IGZO.

[0072] The first gate layer M1 is used to set the gate of the first type of transistor. The first gate layer M1 can also be used to set the scan line connected to the gate of the first type of transistor.

[0073] The pixel circuit includes multiple transistors and at least one storage capacitor Cst. The lower plate c11 of the storage capacitor Cst is located in the first gate layer M1. At least one of the multiple metal transistors is a driving transistor T3. The lower plate c11 of the storage capacitor Cst and the gate g3 of the driving transistor T3 are multiplexed; that is, the same metal block serves as both the lower plate c11 of the storage capacitor Cst and the gate g3 of the driving transistor T3. The upper plate c12 of the storage capacitor Cst is located in the capacitor metal layer MC.

[0074] The pixel circuit typically includes an initialization transistor T5 and a threshold compensation transistor T4. Both T5 and T4 are electrically connected to the gate of the driving transistor T3. Initialization transistor T5 initializes the gate potential of the driving transistor T3, and threshold compensation transistor T4 compensates for the threshold of the driving transistor T3. To reduce the leakage current at the gate of the driving transistor T3, oxide transistors can be used for both initialization transistor T5 and threshold compensation transistor T4. The gate of initialization transistor T5 is electrically connected to the first scan line S1N, and the gate of threshold compensation transistor T4 is electrically connected to the second scan line S2N. A second gate layer MG can be used to set the first scan line S1N and the second scan line S2N; and / or, a capacitive metal layer MC can also be used to set the first scan line S1N and the second scan line S2N.

[0075] The first gate layer M1, the second gate layer MG, and the capacitor metal layer MC are film layers that a display panel typically needs to include. In this embodiment, the first branch line Vref11 is set on the second gate layer MG, and the third branch line Vref23 is set on the capacitor metal layer MC. This allows the grid design of the reset line to be achieved using the original film layers of the display panel without adding film layers, thus eliminating the need for additional manufacturing processes (masks).

[0076] In some embodiments, such as Figure 1 As shown, the display panel also includes an initialization signal line Vini, which provides an initialization signal to the driving transistor T3 in the pixel circuit. For example, the first terminal of the initialization transistor T5 is electrically connected to the initialization signal line Vini, and the second terminal of the initialization transistor T5 is electrically connected to the gate of the driving transistor T3. The initialization signal on the initialization signal line Vini is written to the gate of the driving transistor T3 via the initialization transistor T5, thus initializing the gate of the driving transistor T3 and facilitating subsequent better writing of data signals to the gate of the driving transistor T3.

[0077] by Figure 1For example, the first pixel circuit 11 and the second pixel circuit 12 can be electrically connected to the same initialization signal line Vini. Of course, in other embodiments, the first pixel circuit 11 and the second pixel circuit 12 can be electrically connected to different initialization signal lines to achieve different initializations of the driving transistors in the first pixel circuit 11 and the second pixel circuit 12.

[0078] Please refer to the reference. Figure 1 , Figure 3 , Figure 8 The initialization signal line Vini includes a first initialization signal line Vini1 extending along the first direction X, and the first initialization signal line Vini1 is located in the capacitor metal layer MC.

[0079] Alternatively, please refer to the following: Figure 1 , Figure 15 , Figure 20 The initialization signal line Vini includes a first initialization signal line Vini1 extending along the first direction X, and the first initialization signal line Vini1 is located in the first gate layer M1.

[0080] The capacitor metal layer MC typically needs to have an upper plate c12 for storing capacitor Cst. The capacitor metal layer MC may also have a first scan line S1N and a second scan line S2N. The first gate layer M1 typically needs to have scan lines (e.g., scan lines SP, SPX, and light emission control line EM) connected to the gates of the first type of transistors. The first gate layer M1 and the capacitor metal layer MC are film layers typically included in a display panel. In this embodiment, the first initialization signal line Vini1 is placed on the first gate layer M1 or the capacitor metal layer MC. This allows for the initialization of the driving transistors using the existing film layers of the display panel without adding additional film layers, thus eliminating the need for additional manufacturing processes (masks).

[0081] In some embodiments, such as Figure 8 As shown, when the first initialization signal line Vini1 is located in the capacitor metal layer MC, within the capacitor metal layer MC, along the second direction Y, the first initialization signal line Vini1 is located between the first scan line S1N and the third branch line Vref23. The third branch line Vref23 is used to transmit the second reset signal to the first electrode of the second light-emitting element. The first initialization signal line Vini1 is used to transmit the initialization signal to the gate of the driving transistor.

[0082] Within multiple consecutive refresh frames, the second reset signal and initialization signal are typically fixed signals, while the scan signal on the first scan line S1N is a transition signal (jumping between high and low levels). Within the same capacitor metal layer MC, the first initialization signal line Vini1 separates the first scan line S1N and the third branch line Vref23. The first initialization signal line Vini1 can shield the coupling effect of the first scan line S1N to the third branch line Vref23, thereby ensuring the stability of the signal transmitted by the third branch line Vref23.

[0083] In some embodiments, such as Figure 1 As shown, the display panel also includes a bias signal line DVH, which provides a bias adjustment signal to the driving transistor T3 of the pixel circuit. The bias signal is used to adjust the bias state of the driving transistor T3, thereby improving the display uniformity of the display panel.

[0084] For example, the pixel circuit includes a bias adjustment transistor T8, the first terminal of which is electrically connected to the bias signal line DVH, and the second terminal of which is electrically connected to the first terminal of the driving transistor T3. Of course, in other embodiments, the second terminal of the bias adjustment transistor T8 may be electrically connected to the second terminal of the driving transistor T3.

[0085] by Figure 1 For example, the first pixel circuit 11 and the second pixel circuit 12 can be electrically connected to the same bias signal line DVH. Of course, in other embodiments, the first pixel circuit 11 and the second pixel circuit 12 can be electrically connected to different bias signal lines to achieve different bias adjustments to the driving transistors in the first pixel circuit 11 and the second pixel circuit 12.

[0086] Please refer to the reference. Figure 1 , Figure 3 , Figure 4 , Figure 10 The bias signal line DVH includes a first bias signal line DVH1 extending along the first direction X, and the first bias signal line DVH1 is located in the second gate layer MG. The second gate layer MG is a film layer that is usually required in the display panel. In this embodiment, the first bias signal line DVH1 is set in the second gate layer MG, which can realize the design of the first bias signal line DVH1 using the original film layer of the display panel without adding a film layer, so that no additional process (mask) is required.

[0087] like Figure 10As shown, within the second gate layer MG, along the second direction Y, the first branch line Vref11 is located between the first bias signal line DVH1 and the second scan line S2N. The first bias signal line DVH1 is used to transmit a bias adjustment signal to the driving transistor T3. The first branch line Vref11 is used to transmit a first reset signal to the first electrode of the first light-emitting element. The scan signal on the second scan line S2N is used to control the state of the threshold compensation transistor T4.

[0088] Within multiple consecutive refresh frames, the first reset signal and bias adjustment signal are typically fixed signals, while the scan signal on the second scan line S2N is a transition signal (jumping between high and low levels). Within the same second gate layer MG, the first branch line Vref11 separates the first bias signal line DVH1 and the second scan line S2N. The first branch line Vref11 can shield the coupling effect of the second scan line S2N to the first bias signal line DVH1, thereby ensuring the stability of the signal transmitted by the first bias signal line DVH1.

[0089] In some embodiments, such as Figure 1 As shown, the bias signal line DVH is electrically connected to the bias adjustment transistor T8, and the gate of the bias adjustment transistor T8 is electrically connected to the third scan line SPX.

[0090] like Figure 3 As shown, the first bias signal line DVH1 and the third scan line SPX at least partially overlap in the thickness of the display panel.

[0091] The first bias signal line DVH1 and the third scan line SPX are located on different film layers. The first bias signal line DVH1 is located on the second gate layer MG. The bias adjustment transistor T8 can be a first type transistor, and the third scan line SPX can be located on the first gate layer M1.

[0092] The first bias signal line DVH1 and the third scan line SPX need to be electrically connected to different poles of the bias adjustment transistor T8. In this embodiment, the first bias signal line DVH1 and the third scan line SPX overlap at least partially, which is equivalent to setting them close to each other, thereby facilitating their connection to the same bias adjustment transistor T8. In addition, it can reduce the area occupied by the first bias signal line DVH1 and the third scan line SPX in the top view, saving drawing space and thus improving the resolution of the display panel.

[0093] exist Figures 2 to 13 In the design shown, the initialization signal line Vini includes a first initialization signal line Vini1 extending along the first direction X.

[0094] In other embodiments, please refer to Figures 14 to 18The design shown includes an initialization signal line Vini in the display panel. This initialization signal line Vini provides initialization signals to the driving transistors of the pixel circuitry. The initialization signal line Vini includes a second initialization signal line Vini2 extending along the second direction Y, as shown... Figure 24 As shown, the second branch line Vref12, the fourth branch line Vref24, and the second initialization signal line Vini2 are located in the same film layer. The second branch line Vref12, the fourth branch line Vref24, and the second initialization signal line Vini2 can be located in the first metal layer SD1. Figure 28 As shown, the first metal layer SD1 is located on the side of the second gate layer MG away from the substrate 01.

[0095] In this embodiment, the second branch line Vref12, the fourth branch line Vref24, and the second initialization signal line Vini2, which have the same extension direction, are set on the same film layer. This allows multiple signal lines to be arranged on the same film layer, thereby reducing the total number of film layers and enabling the display panel to be made thinner and lighter.

[0096] The second branch line Vref12 is used to provide a first reset signal to the first electrode of the first light-emitting element, the fourth branch line Vref24 is used to transmit a second reset signal to the first electrode of the second light-emitting element, and the second initialization signal line Vini2 is used to provide an initialization signal to the driving transistor. Within multiple consecutive refresh frames, the first reset signal, the second reset signal, and the initialization signal are usually fixed signals. By centrally placing the second branch line Vref12, the fourth branch line Vref24, and the second initialization signal line Vini2—which transmit fixed signals and extend in the same direction—on the same film layer, it is beneficial to maintain the stability of the signals transmitted by the second branch line Vref12, the fourth branch line Vref24, and the second initialization signal line Vini2.

[0097] In some embodiments, such as Figure 16 or Figure 17 As shown, the initialization signal line Vini includes not only a second initialization signal line Vini2 extending along the second direction Y, but also a first initialization signal line Vini1 extending along the first direction X. Multiple first initialization signal lines Vini1 and multiple second initialization signal lines Vini2 are electrically connected to each other, and the first initialization signal lines Vini1 and Vini2 are located in different film layers. The first initialization signal lines Vini1 and Vini2 can be electrically connected to each other vias.

[0098] For example, the first initialization signal line Vini1 may be located in the first gate layer M1, and the second initialization signal line Vini2 may be located in the first metal layer SD1.

[0099] In this embodiment, multiple first initialization signal lines Vini1 and multiple second initialization signal lines Vini2 are electrically connected to each other in a cross pattern, thereby forming a grid-like initialization signal line Vini. This reduces the voltage drop of the initialization signal line Vini, improves the initialization consistency of the driving transistors at different locations, and improves the uniformity of the display.

[0100] in addition, Figures 14 to 27 In the design shown, the first reset line Vref1 is simultaneously gridded, the second reset line Vref2 is gridded, and the initialization signal line Vini is gridded.

[0101] In some embodiments, such as Figure 1 As shown, the display panel also includes a bias signal line DVH, which provides a bias adjustment signal to the driving transistor T3 of the pixel circuit. The bias adjustment signal is used to adjust the bias state of the driving transistor T3, thereby improving the display uniformity of the display panel.

[0102] like Figure 16 or Figure 17 As shown, the bias signal line DVH includes a second bias signal line DVH2 extending along the second direction Y. The second bias signal line DVH2, the second branch line Vref12, the fourth branch line Vref24, and the second initialization signal line Vini2 are located in the same film layer.

[0103] For example, such as Figure 24 As shown, the second bias signal line DVH2, the second branch line Vref12, the fourth branch line Vref24, and the second initialization signal line Vini2 can be located in the first metal layer SD1.

[0104] In this embodiment, the second bias signal line DVH2, the second branch line Vref12, the fourth branch line Vref24, and the second initialization signal line Vini2, which have the same extension direction, are set in the same film layer. This allows multiple signal lines to be arranged in the same film layer, thereby reducing the total number of film layers and enabling the display panel to be thinner. Furthermore, the layout of at least four signal lines in the same film layer further optimizes the layout design.

[0105] In addition, within multiple consecutive refresh frames, the first reset signal, the second reset signal, and the initialization signal are usually fixed signals, and the bias adjustment signal transmitted by the second bias signal line DVH2 is also usually a fixed signal. By centrally setting the second bias signal line DVH2, the second branch line Vref12, the fourth branch line Vref24, and the second initialization signal line Vini2, which transmit fixed signals and have the same extension direction, on the same film layer, it is beneficial to maintain the stability of the signals transmitted by the second bias signal line DVH2, the second branch line Vref12, the fourth branch line Vref24, and the second initialization signal line Vini2.

[0106] For example, such as Figure 24 As shown, in the first direction X, the signal lines can be arranged in the pattern of a second initialization signal line Vini2, a fourth branch line Vref24, a second branch line Vref12, and a second bias signal line DVH2.

[0107] Taking the second direction Y as the column direction as an example, for every two columns of pixel circuits, there is a second initialization signal line Vini2, a fourth branch line Vref24, a second branch line Vref12, and a second bias signal line DVH2.

[0108] In some embodiments, please refer to the reference Figure 16 and Figure 23 The bias signal line DVH includes not only a second bias signal line DVH2 extending along the second direction Y, but also a first bias signal line DVH1 extending along the first direction X. Multiple first bias signal lines DVH1 and multiple second bias signal lines DVH2 are electrically connected, and the first bias signal lines DVH1 and second bias signal lines DVH2 are located in different film layers. The first bias signal lines DVH1 and second bias signal lines DVH2 can be electrically connected through vias.

[0109] For example, such as Figure 23 and Figure 24 As shown, the first bias signal line DVH1 can be located in the second gate layer MG, and the second bias signal line DVH2 can be located in the first metal layer SD1.

[0110] In this embodiment, multiple first bias signal lines DVH1 and multiple second bias signal lines DVH2 are electrically connected to each other in a cross pattern to form a grid-like bias signal line DVH. This reduces the voltage drop of the bias signal line DVH, improves the consistency of bias adjustment of the driving transistors at different locations, and improves display uniformity.

[0111] in addition, Figures 14 to 27In the design shown, the first reset line Vref1 is simultaneously gridded, the second reset line Vref2 is gridded, the initialization signal line Vini is gridded, and the bias signal line DVH is gridded.

[0112] In some embodiments, such as Figure 1 As shown, the display panel also includes a third pixel circuit 13 and a third light-emitting element 23. The third pixel circuit 13 includes a third reset transistor T73, which is electrically connected to the second reset line Vref2 and the first electrode of the third light-emitting element 23.

[0113] Specifically, the first terminal of the third reset transistor T73 is electrically connected to the second reset line Vref2, and the second terminal of the third reset transistor T73 is electrically connected to the first terminal of the third light-emitting element 23. The first terminal of the second reset transistor T72 is electrically connected to the second reset line Vref2, and the second terminal of the second reset transistor T72 is electrically connected to the first terminal of the second light-emitting element 22. The second reset signal on the second reset line Vref2 is used to reset the first terminals of the second light-emitting element 22 and the third light-emitting element 23.

[0114] The first light-emitting element 21, the second light-emitting element 22, and the third light-emitting element 23 emit different colors.

[0115] For example, when the first light-emitting element 21 is reset individually using the first reset line Vref1, and the second light-emitting element 22 and the third light-emitting element 23 are reset together using the second reset line Vref2, the characteristics of the second light-emitting element 22 and the third light-emitting element 23 can be relatively similar. For instance, the luminous efficiency of the second light-emitting element 22 and the third light-emitting element 23 can be relatively similar.

[0116] In this embodiment, the second reset line Vref2 is shared by the second light-emitting element 22 and the third light-emitting element 23, which can achieve the reset effect for different light-emitting elements and save signal lines, thus improving the resolution of the display panel.

[0117] in, Figures 2 to 12 The design method shown and Figures 14 to 27 In the design shown, the second reset line Vref2 is shared by the second light-emitting element 22 and the third light-emitting element 23.

[0118] In other embodiments, such as Figure 29 As shown, the display panel also includes a third pixel circuit 13 and a third light-emitting element 23. The third pixel circuit 13 includes a third reset transistor T73, which is electrically connected to the third reset line Vref3 and the first electrode of the third light-emitting element 23.

[0119] In this embodiment, the first reset line Vref1 is used to reset the first light-emitting element 21, the second reset line Vref2 is used to reset the second light-emitting element 22, and the third reset line Vref3 is used to reset the third light-emitting element 23. The reset lines of the three light-emitting elements are independent of each other, which can flexibly match the reset requirements of different light-emitting elements.

[0120] In some embodiments, when the third light-emitting element 23 is reset by the third reset line Vref3, such as Figure 30 As shown, the third reset line Vref3 includes a fifth branch line Vref35 and a sixth branch line Vref36 that are electrically connected. The fifth branch line Vref35 extends along a first direction X, and the sixth branch line Vref36 extends along a second direction Y. The fifth branch line Vref35 and the sixth branch line Vref36 are located in different film layers. The fifth branch line Vref35 and the sixth branch line Vref36 can be electrically connected through vias.

[0121] Multiple fifth branch lines Vref35 and multiple sixth branch lines Vref36 are interconnected to form a grid-like third reset line Vref3. This reduces the voltage drop of the third reset line Vref3, thus better solving the problems of color distortion and uneven display.

[0122] In this embodiment, the first reset line Vref1, the second reset line Vref2, and the third reset line Vref3 are all gridded.

[0123] In some embodiments, such as Figure 30 As shown, the display panel also includes a light-emitting control line EM, which extends along a first direction X. The fifth branch line Vref35 and the light-emitting control line EM are located in different film layers. In the thickness direction of the display panel, the fifth branch line Vref35 and the light-emitting control line EM at least partially overlap.

[0124] For example, such as Figure 29 As shown, the pixel circuit includes a first light-emitting control transistor T1 and a second light-emitting control transistor T6. The first terminal of the first light-emitting control transistor T1 is electrically connected to the first power line PVDD, and the second terminal of the first light-emitting control transistor T1 is electrically connected to the first terminal of the driving transistor T3. The first terminal of the second light-emitting control transistor T6 is electrically connected to the second terminal of the driving transistor T3, and the second terminal of the second light-emitting control transistor T6 is electrically connected to the first terminal of the light-emitting element. The gates of both the first light-emitting control transistor T1 and the second light-emitting control transistor T6 are electrically connected to the light-emitting control line EM.

[0125] The first light-emitting control transistor T1 and the second light-emitting control transistor T6 can be transistors of the first type.

[0126] Please refer to the reference. Figure 28 , Figure 29 and Figure 30 The active layers of the first light-emitting control transistor T1 and the second light-emitting control transistor T6 can be located in the first semiconductor layer B1, the light-emitting control line EM can be located in the first gate layer M1, and the fifth branch line Vref35 can be located in the second gate layer MG.

[0127] In this embodiment, the fifth sub-line Vref35 and the light-emitting control line EM at least partially overlap, which can reduce the area occupied by the fifth sub-line Vref35 and the light-emitting control line EM in the top view. Thus, while achieving the gridding of the first reset line Vref1, the second reset line Vref2, and the third reset line Vref3, the high resolution of the display panel can also be achieved.

[0128] In some embodiments, the fifth dividing line Vref35 and the first dividing line Vref11 are located in the same film layer. For example, one first dividing line Vref11 is provided for every two rows of pixel circuits, and one fifth dividing line Vref35 is provided for every two rows of pixel circuits. Within the film layer containing the fifth dividing line Vref35 and the first dividing line Vref11, in the second direction Y, the fifth dividing line Vref35 and the first dividing line Vref11 can be arranged alternately.

[0129] For example, please refer to the reference. Figure 28 and Figure 30 The fifth branch line Vref35 and the first branch line Vref11 can be located in the second gate layer MG.

[0130] In this embodiment, the fifth branch line Vref35 and the first branch line Vref11, which have the same extension direction, are set on the same film layer. This allows multiple signal lines to be arranged on the same film layer, thereby reducing the total number of film layers and enabling the display panel to be made thinner and lighter.

[0131] In some embodiments, the second branch line Vref12, the fourth branch line Vref24, and the sixth branch line Vref36 are located in the same film layer.

[0132] For example, please refer to the reference. Figure 28 and Figure 30 The second sub-line Vref12, the fourth sub-line Vref24, and the sixth sub-line Vref36 can be located in the third metal layer SD3.

[0133] In this embodiment, the second branch line Vref12, the fourth branch line Vref24, and the sixth branch line Vref36 with the same extension direction are set on the same film layer. This allows multiple signal lines to be arranged on the same film layer, thereby reducing the total number of film layers and enabling the display panel to be made thinner and lighter.

[0134] In the film layer containing the second branch line Vref12, the fourth branch line Vref24, and the sixth branch line Vref36, the proportion of the second branch line Vref12, the fourth branch line Vref24, and the sixth branch line Vref36 can be reduced so that there is space in the film layer to place other traces.

[0135] As an example, each of the twelve pixel circuits is provided with a second dividing line Vref12, a fourth dividing line Vref24, and a sixth dividing line Vref36. Specifically, the four pixel circuits are provided with a second dividing line Vref12, the four pixel circuits are provided with a fourth dividing line Vref24, and the four pixel circuits are provided with a sixth dividing line Vref36.

[0136] In some embodiments, when the third reset line Vref3 is meshed, such as Figure 30 As shown, the display panel may also include a bias signal line DVH, which provides a bias adjustment signal to the driving transistor T3 of the pixel circuit. The bias adjustment signal is used to adjust the bias state of the driving transistor T3, thereby improving the display uniformity of the display panel.

[0137] The bias signal line DVH includes a second bias signal line DVH2 extending along the second direction Y. The second bias signal line DVH2, the second branch line Vref12, the fourth branch line Vref24, and the sixth branch line Vrerf36 are located in the same film layer.

[0138] For example, such as Figure 30 As shown, the second bias signal line DVH2, the second branch line Vref12, the fourth branch line Vref24, and the sixth branch line Vrerf36 can be located in the third metal layer SD3.

[0139] In this embodiment, the second bias signal line DVH2, the second branch line Vref12, the fourth branch line Vref24, and the sixth branch line Vrerf36, which have the same extension direction, are set in the same film layer. This allows multiple signal lines to be arranged in the same film layer, thereby reducing the total number of film layers and enabling the display panel to be thinner. Furthermore, the layout of at least four signal lines in the same film layer further optimizes the layout design.

[0140] In addition, within multiple consecutive refresh frames, the first reset signal, the second reset signal, the third reset signal, and the bias adjustment signal are usually fixed signals. The second bias signal line DVH2, the second branch line Vref12, the fourth branch line Vref24, and the sixth branch line Vrerf36, which transmit fixed signals and have the same extension direction, are concentrated in the same film layer. This helps to maintain the stability of the signals transmitted by the second bias signal line DVH2, the second branch line Vref12, the fourth branch line Vref24, and the sixth branch line Vrerf36.

[0141] In the first direction X, the lines can be arranged according to the pattern of a second branch line Vref12, a second bias signal line DVH2, a sixth branch line Vrerf36, a second bias signal line DVH2, a fourth branch line Vref24, and a second bias signal line DVH2.

[0142] Taking the second direction Y as the column direction as an example, in a twelve-column pixel circuit, the pixel circuits of the first and second columns are respectively equipped with a second branch line Vref12, the pixel circuits of the third and fourth columns are respectively equipped with a second bias signal line DVH2, the pixel circuits of the fifth and sixth columns are respectively equipped with a sixth branch line Vrerf36, the pixel circuits of the seventh and eighth columns are respectively equipped with a second bias signal line DVH2, the pixel circuits of the ninth and tenth columns are respectively equipped with a fourth branch line Vref24, and the pixel circuits of the eleventh and twelfth columns are respectively equipped with a second bias signal line DVH2.

[0143] In some embodiments, please refer to the reference Figure 4 , Figure 11 and Figure 12 The display panel also includes auxiliary lines FIAA, at least some of which are electrically connected to the data lines.

[0144] The auxiliary line FIAA is located in the display area of ​​the display panel in the first direction X. The display area includes an edge display area and a middle display area. The data lines in the edge display area are electrically connected to the driver chip through the auxiliary line FIAA. This is equivalent to embedding the fan-out traces of the lower bezel into the display area, which can achieve a narrow bezel.

[0145] The auxiliary line FIAA includes a first auxiliary line FIAA1 extending along the first direction X, and the third branch line Vref23, the first branch line Vref11, and the first auxiliary line FIAA located in different film layers.

[0146] like Figure 3 As shown, in the thickness direction of the display panel, the first sub-line Vref11 and the first auxiliary line FIAA1 at least partially overlap. Additionally, in the thickness direction of the display panel, the first sub-line Vref11 and the third sub-line Vref23 at least partially overlap.

[0147] For example, in the thickness direction of the display panel, the first auxiliary line FIAA1 and the third sub-line Vref23 may at least partially overlap. In this example, the orthographic projections of the first sub-line Vref11, the third sub-line Vref23, and the first auxiliary line FIAA1 on the substrate of the display panel at least partially overlap.

[0148] In this embodiment, the first dividing line Vref11 and the first auxiliary line FIAA1 overlap at least partially, which can reduce the area occupied by the first dividing line Vref11 and the first auxiliary line FIAA1 in the top view, thereby achieving a narrow bezel based on the auxiliary line FIAA while also achieving a high resolution of the display panel.

[0149] In some embodiments, please refer to the reference Figure 3 , Figure 10 and Figure 11 The bias adjustment transistor T8 and the driving transistor T3 in the pixel circuit are connected by a connecting line 32. The display panel also includes a shielding structure 31, which overlaps with the connecting line 32 at least partially in the thickness direction of the display panel.

[0150] For example, the shielding structure 31 and the connecting line 32 are located in different film layers. For instance, the shielding structure 31 and the first bias signal line DVH1 are located in the same film layer, and the connecting line 32 and the first auxiliary line FIAA1 are located in the same film layer.

[0151] For example, the shielding structure 31 may be electrically connected to a fixed voltage signal line. For instance, the shielding structure 31 may be electrically connected to a first power line PVDD.

[0152] In this embodiment, the shielding structure 31 can be used to shield the mutual influence between the connecting line 31 and the auxiliary line FIAA, thereby maintaining the stability of the potential on the connecting line 32, so as to maintain the stability of the potential of one pole of the driving transistor T3 connected to the connecting line 32.

[0153] In some embodiments, such as Figure 12 As shown, the auxiliary line FIAA also includes a second auxiliary line FIAA2 extending along the second direction Y. The second branch line Vref12, the fourth branch line Vref24 and the second auxiliary line FIAA2 are located in the same film layer.

[0154] For example, such as Figure 12 As shown, the display panel also includes a second bias signal line DVH2 extending along the second direction Y. The second bias signal line DVH2 is used to provide a bias adjustment signal to the driving transistor. The second bias signal line DVH2, the second branch line Vref12, the fourth branch line Vref24, and the second auxiliary line FIAA2 are located in the same film layer.

[0155] For example, the data line data, the first power line PVDD, the second bias signal line DVH2, the second branch line Vref12, the fourth branch line Vref24, and the second auxiliary line FIAA2, which extend along the second direction Y, are located in the same film layer.

[0156] In this embodiment, multiple signal lines are arranged on the same film layer, which can reduce the total number of film layers and achieve a thinner and lighter display panel.

[0157] Please continue to refer to this. Figure 12 As an example, each pair of adjacent data lines is a data line group. At least one second auxiliary line FIAA2 is provided between the two data lines in the same data line group. A second branch line Vref12 is provided between the two data lines in some data line groups. A second bias signal line DVH2 is provided between the two data lines in some data line groups. A fourth branch line Vref24 is provided between the two data lines in some data line groups.

[0158] For example, the second bias signal line DVH2, the second branch line Vref12, and the fourth branch line Vref24 are arranged in the first direction X according to the pattern of one second branch line Vref12, one second bias signal line DVH2, one fourth branch line Vref24, and one second bias signal line DVH2.

[0159] For example, the data line data, the first power line PVDD, the second bias signal line DVH2, the second branch line Vref12, the fourth branch line Vref24, and the second auxiliary line FIAA2 are located in the second metal layer SD2, which is located on the side of the first metal layer SD1 away from the substrate 01.

[0160] In some embodiments, such as Figure 12 As shown, at least a portion of the second auxiliary line FIAA2 transmits the same signal as the second branch line Vref12, and at least a portion of the second auxiliary line FIAA2 transmits the same signal as the fourth branch line Vref24.

[0161] For example, at least a portion of the second auxiliary line FIAA2 is electrically connected to the second branch line Vref12. When the second auxiliary line FIAA2 and the second branch line Vref12 transmit the same signal, it is equivalent to increasing the number of second branch lines Vref12, making the grid of the first reset line Vref1 finer, which can further reduce the voltage drop of the first reset line Vref1, thereby improving display uniformity.

[0162] At least a portion of the second auxiliary line FIAA2 is electrically connected to the fourth branch line Vref24. Since the second auxiliary line FIAA2 and the fourth branch line Vref24 transmit the same signal, this effectively increases the number of fourth branch lines Vref24, making the grid of the second reset line Vref2 finer. This further reduces the voltage drop of the second reset line Vref2, thereby improving display uniformity.

[0163] In some embodiments, please refer to the reference Figure 8 and Figure 11The display panel also includes an initialization signal line Vini, which provides an initialization signal to the driving transistor T3 in the pixel circuit. The initialization signal line Vini includes a first initialization signal line Vini1 extending along a first direction X, and at least a portion of the second auxiliary line FIAA2 transmits the same signal as the first initialization signal line Vini1.

[0164] At least a portion of the second auxiliary line FIAA2 is electrically connected to the first initialization signal line Vini1. The second auxiliary line FIAA2 and the first initialization signal line Vini1 intersect each other. When at least a portion of the second auxiliary line FIAA2 and the first initialization signal line Vini1 transmit the same signal, it is equivalent to realizing a gridded design of the initialization signal line Vini, which can reduce the voltage drop of the initialization signal line Vini and thus better improve the display uniformity.

[0165] In some embodiments, please refer to the reference Figure 10 and Figure 12 The display panel also includes a bias signal line DVH, which provides a bias adjustment signal to the driving transistor T3 of the pixel circuit. The bias signal line DVH includes a first bias signal line DVH1 extending along a first direction X, and at least a portion of the second auxiliary line FIAA2 transmits the same signal as the first bias signal line DVH1.

[0166] At least a portion of the second auxiliary line FIAA2 is electrically connected to the first bias signal line DVH1. The second auxiliary line FIAA2 and the first bias signal line DVH1 intersect each other. When at least a portion of the second auxiliary line FIAA2 and the first bias signal line DVH1 transmit the same signal, they essentially form a gridded bias signal line DVH, which can bias the voltage drop of the signal line DVH, thereby improving the uniformity of the display.

[0167] Additionally, please refer to the following: Figure 10 and Figure 12 The bias signal line DVH also includes a second bias signal line DVH2 extending along the second direction Y. The second bias signal line DVH2 is electrically connected to the first bias signal line DVH1. At least a portion of the second auxiliary line FIAA2 is electrically connected to the first bias signal line DVH1, making the grid of the bias signal line DVH finer and further reducing the voltage drop of the bias signal line DVH, thereby improving the display uniformity.

[0168] Figures 2 to 12The illustrated design exemplifies the case where the second branch line Vref12, the fourth branch line Vref24, and the second auxiliary line FIAA2 are located in the same film layer. In other embodiments, the second auxiliary line FIAA2 and the second branch line Vref12 may also be located in different film layers.

[0169] Please refer to the reference. Figure 16 , Figure 17 , Figure 24 , Figure 25 , Figure 26 and Figure 28 The auxiliary line FIAA also includes a second auxiliary line FIAA2 extending along the second direction Y. The second branch line Vref12 and the fourth branch line Vref24 are located in the same film layer, while the second auxiliary line FIAA2 is located in another film layer. For example, the film layer where the second auxiliary line FIAA2 is located is on the side of the film layer where the first auxiliary line FIAA1 is located that is away from the film layer where the second branch line Vref12 is located.

[0170] For example, the display panel includes a first metal layer SD1, a second metal layer SD2, and a third metal layer SD3, which are sequentially located away from the second gate layer MG. The second branch line Vref12 and the fourth branch line Vref24 are located in the first metal layer SD1, the first auxiliary line FIAA1 is located in the second metal layer SD2, and the second auxiliary line FIAA2 is located in the third metal layer SD3.

[0171] The third metal layer SD3 is also provided with a data line extending along the second direction Y and a first power line PVDD.

[0172] In some embodiments, please refer to the reference Figure 17 , Figure 20 and Figure 24 The display panel also includes an initialization signal line Vini, which provides an initialization signal to the driving transistor T3 in the pixel circuit. The initialization signal line Vini includes a first initialization signal line Vini1 extending along a first direction X and a second initialization signal line Vini2 extending along a second direction Y; multiple first initialization signal lines Vini1 and multiple second initialization signal lines Vini2 are electrically connected to each other. The first initialization signal line Vini1 and the second initialization signal line Vini2 are located in different film layers. The second initialization signal line Vini2 and the second branch line Vref12 are located in the same film layer. In this embodiment, the first reset line Vref1, the second reset line Vref2, and the initialization signal line Vini are all gridded, and the second initialization signal line Vini2 and the second branch line Vref12 are designed in the same film layer, which can reduce the number of film layers while achieving a gridded arrangement of multiple signal lines.

[0173] And / or, the display panel further includes a bias signal line DVH, which provides a bias adjustment signal to the driving transistor T3 of the pixel circuit. The bias signal line DVH includes a first bias signal line DVH1 extending along a first direction X and a second bias signal line DVH2 extending along a second direction Y; the second bias signal line DVH2 and the second branch line Vref12 are located in the same film layer. In this embodiment, the first reset line Vref1, the second reset line Vref2, and the bias signal line DVH are all gridded, and the second bias signal line DVH2 and the second branch line Vref12 are designed in the same film layer, which can reduce the number of film layers while realizing the gridding of multiple signal lines.

[0174] For example, such as Figure 24 As shown, the second initialization signal line Vini2, the second branch line Vref12, the fourth branch line Vref24, and the second bias signal line DVH2 are all located in the same film layer.

[0175] In some embodiments, the first light-emitting element 21 is a red light-emitting element, the second light-emitting element 22 is a green light-emitting element, and the third light-emitting element 23 is a blue light-emitting element.

[0176] For example, such as Figure 13 or Figure 28 As shown, the display panel also includes multiple insulating layers, including a buffer layer, a first gate insulating layer GI1, a capacitor insulating layer IMD, a first interlayer dielectric layer ILD1, a second gate insulating layer GI2, a third gate insulating layer GI3, a second interlayer dielectric layer ILD2, a first planarization layer PLN1, a via insulating layer VIA, and a pixel definition layer PDL. The display panel also includes an auxiliary metal layer M0, whose patterned structure can be used to shield the effective channel region within the first semiconductor layer B1. An anode layer RE is used to set the anode of the light-emitting element.

[0177] Figure 28 and Figure 13 The differences include: Figure 28 Compare Figure 13 The structure shown has an additional third metal layer SD3 and a second planarization layer PLN2.

[0178] The specific film structure of the display panel can be adapted to actual needs, such as adding or removing some film layers. Moreover, any of the above film layers can contain at least one sub-layer. This application does not impose specific limitations on this.

[0179] This application also provides a display device, including the display panel provided in this application. Please refer to... Figure 31 , Figure 31 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Figure 31 The provided display device 1000 includes a display panel 100, which includes the display panel provided in any of the above embodiments of this application. Figure 31 This embodiment uses a mobile phone as an example to illustrate the display device 1000. It is understood that the display device provided in this application embodiment can be other display devices with display functions, such as wearable products, computers, televisions, and in-vehicle display devices; this application does not impose specific limitations on these. The display device provided in this application embodiment has the beneficial effects of the display panel provided in this application embodiment. For details, please refer to the specific descriptions of the display panel in the above embodiments; these will not be repeated here.

[0180] The embodiments described above are not exhaustive, nor do they limit the application to the specific embodiments described herein. Clearly, many modifications and variations can be made based on the above description. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A display panel, characterized in that, include: The first pixel circuit includes a first light-emitting element and a first reset line. The first pixel circuit includes a first reset transistor, which is electrically connected to the first reset line and the first electrode of the first light-emitting element. The second pixel circuit includes a second light-emitting element and a second reset line. The second pixel circuit includes a second reset transistor, which is electrically connected to the second reset line and the first electrode of the second light-emitting element. The first reset line includes a first branch line and a second branch line. The first branch line extends along a first direction, and the second branch line extends along a second direction. The first branch line and the second branch line are electrically connected and located in different film layers. The first direction and the second direction intersect. The second reset line includes a third branch line and a fourth branch line that are electrically connected. The third branch line extends along the first direction, and the fourth branch line extends along the second direction. The third branch line and the fourth branch line are located in different film layers, and the third branch line and the first branch line are located in different film layers. In the thickness direction of the display panel, the first dividing line and the third dividing line at least partially overlap.

2. The display panel according to claim 1, characterized in that, The display panel includes a substrate, a first semiconductor layer, a first gate layer, a capacitor metal layer, a second semiconductor layer, and a second gate layer, which are sequentially located away from the substrate. The first branch line is located in the second gate layer, and the third branch line is located in the capacitor metal layer.

3. The display panel according to claim 2, characterized in that, The display panel further includes an initialization signal line, which is used to provide an initialization signal to the driving transistor of the pixel circuit; the initialization signal line includes a first initialization signal line extending along the first direction, which is located in the first gate layer or the capacitor metal layer.

4. The display panel according to claim 3, characterized in that, The first initialization signal line is located in the capacitor metal layer, the gate of the initialization transistor is electrically connected to the first scan line, and the first initialization signal line is located between the first scan line and the third branch line in the capacitor metal layer along the second direction.

5. The display panel according to claim 2, characterized in that, The display panel further includes a bias signal line for providing a bias signal to the driving transistor of the pixel circuit. The bias signal line includes a first bias signal line extending along the first direction. The first bias signal line is located in the second gate layer and along the second direction within the second gate layer. The first branch line is located between the first bias signal line and the second scan line. The second scan line is electrically connected to the gate of the threshold compensation transistor in the pixel circuit.

6. The display panel according to claim 5, characterized in that, The bias signal line is electrically connected to the bias adjustment transistor, and the gate of the bias adjustment transistor is electrically connected to the third scan line. The first bias signal line and the third scan line at least partially overlap on the thickness of the display panel.

7. The display panel according to claim 1, characterized in that, The display panel further includes an initialization signal line, which is used to provide an initialization signal to the driving transistor of the pixel circuit; the initialization signal line includes a second initialization signal line extending along the second direction, and the second branch line, the fourth branch line, and the second initialization signal line are located in the same film layer.

8. The display panel according to claim 7, characterized in that, The initialization signal line further includes a first initialization signal line extending along the first direction, and multiple first initialization signal lines and multiple second initialization signal lines are electrically connected, with the first initialization signal line and the second initialization signal line located in different film layers.

9. The display panel according to claim 7, characterized in that, The display panel further includes a bias signal line, which is used to provide a bias signal to the driving transistor of the pixel circuit. The bias signal line includes a second bias signal line extending along the second direction. The second bias signal line, the second branch line, the fourth branch line, and the second initialization signal line are located in the same film layer.

10. The display panel according to claim 9, characterized in that, The bias signal line further includes a first bias signal line extending along the first direction, and multiple first bias signal lines and multiple second bias signal lines are electrically connected, wherein the first bias signal lines and the second bias signal lines are located in different film layers.

11. The display panel according to claim 1, characterized in that, The display panel further includes a third pixel circuit and a third light-emitting element. The third pixel circuit includes a third reset transistor, which is electrically connected to the second reset line and the first electrode of the third light-emitting element.

12. The display panel according to claim 1, characterized in that, The display panel further includes a third pixel circuit, a third light-emitting element, and a third reset line. The third pixel circuit includes a third reset transistor, which is electrically connected to the third reset line and the first electrode of the third light-emitting element.

13. The display panel according to claim 12, characterized in that, The third reset line includes a fifth branch line and a sixth branch line that are electrically connected. The fifth branch line extends along the first direction, and the sixth branch line extends along the second direction. The fifth branch line and the sixth branch line are located in different film layers.

14. The display panel according to claim 13, characterized in that, The display panel further includes a light-emitting control line extending along the first direction. The fifth branch line and the light-emitting control line are located in different film layers. In the thickness direction of the display panel, the fifth branch line and the light-emitting control line at least partially overlap.

15. The display panel according to claim 13, characterized in that, The fifth dividing line is located in the same film layer as the first dividing line.

16. The display panel according to claim 13, characterized in that, The second dividing line, the fourth dividing line, and the sixth dividing line are located in the same film layer.

17. The display panel according to claim 13, characterized in that, The display panel further includes a bias signal line, which is used to provide a bias signal to the driving transistor of the pixel circuit, and the bias signal line includes a second bias signal line extending along the second direction; The second branch line, the fourth branch line, the sixth branch line, and the second bias signal line are located in the same film layer.

18. The display panel according to claim 1, characterized in that, The display panel also includes auxiliary lines, at least some of which are electrically connected to the data lines; The auxiliary line includes a first auxiliary line extending along the first direction, and the third branch line, the first branch line, and the first auxiliary line are located in different film layers. In the thickness direction of the display panel, the first dividing line and the first auxiliary line at least partially overlap.

19. The display panel according to claim 18, characterized in that, The display panel also includes a shielding structure. In the thickness direction of the display panel, the bias adjustment transistor and the driving transistor in the pixel circuit are connected by a connecting line, and the shielding structure and the connecting line at least partially overlap.

20. The display panel according to claim 18, characterized in that, The auxiliary line includes a second auxiliary line extending along the second direction, and the second branch line, the fourth branch line, and the second auxiliary line are located in the same film layer.

21. The display panel according to claim 20, characterized in that, At least a portion of the auxiliary line transmits the same signal as the second branch line, and at least a portion of the second auxiliary line transmits the same signal as the fourth branch line.

22. The display panel according to claim 20, characterized in that, The display panel further includes an initialization signal line, which is used to provide an initialization signal to the driving transistor of the pixel circuit; the initialization signal line includes a first initialization signal line extending along the first direction, and at least a portion of the second auxiliary line transmits the same signal as the first initialization signal line.

23. The display panel according to claim 20, characterized in that, The display panel further includes a bias signal line for providing a bias signal to the driving transistor of the pixel circuit. The bias signal line includes a first bias signal line extending along the first direction, and at least a portion of the second auxiliary line transmits the same signal as the first bias signal line.

24. The display panel according to claim 18, characterized in that, The auxiliary line includes a second auxiliary line extending along the second direction; The second branch line and the fourth branch line are located in the same film layer, and the film layer where the second auxiliary line is located is located on the side of the film layer where the first auxiliary line is located that is far away from the film layer where the second branch line is located.

25. The display panel according to claim 18, characterized in that, The display panel further includes an initialization signal line, which is used to provide an initialization signal to the driving transistor of the pixel circuit; the initialization signal line includes a first initialization signal line extending along the first direction and a second initialization signal line extending along the second direction; the second initialization signal line and the second branch line are located in the same film layer; And / or, the display panel further includes a bias signal line for providing a bias signal to the driving transistor of the pixel circuit; the bias signal line includes a first bias signal line extending along the first direction and a second bias signal line extending along the second direction; the second bias signal line and the second branch line are located in the same film layer.

26. The display panel according to claim 14, characterized in that, The display panel further includes a bias signal line for providing a bias signal to the driving transistor of the pixel circuit; the bias signal line includes a second bias signal line extending along the second direction. In the first direction, the second branch line, the second bias signal line, the sixth branch line, the second bias signal line, the fourth branch line, and the second bias signal line are arranged in a specific pattern.

27. The display panel according to claim 11 or 13, characterized in that, The first light-emitting element includes a red light-emitting element, the second light-emitting element includes a green light-emitting element, and the third light-emitting element includes a blue light-emitting element.

28. A display device, characterized in that, include: The display panel as described in any one of claims 1 to 27.

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