Scheduling method and related device

Abstract

The embodiment of the invention provides a scheduling method, which does not directly discard a current scheduling sequence when the current scheduling sequence violates a time constraint of a target equipment module, delays wafer output, re-plans the current scheduling sequence and re-judges whether the time constraint of the target equipment module is violated or not. Instead, in the current scheduling sequence, a first key action and a second key action corresponding to the target equipment module are determined, and the execution starting moment of the target scheduling action in the current scheduling sequence is updated according to the target delay so as to obtain an updated current scheduling sequence; thus, the updated current scheduling sequence has the possibility of meeting the time constraint of the target equipment module through the adjustment of the scheduling actions for limited times, the times of re-planning the scheduling sequence are reduced, and the efficiency of determining the available target scheduling sequence by the scheduling method is improved.

Description

TECHNICAL FIELD

[0001] The present specification relates to the technical field of semiconductor technology, in particular, to the technical field of semiconductor technology, more particularly, to a scheduling method and device, a semiconductor process equipment and a computer readable storage medium. BACKGROUND

[0002] The semiconductor process equipment for semiconductor wafer manufacturing can include an aligner, a robot, a load lock, a load port, and a plurality of process chambers.

[0003] The scheduling sequence of the wafer is an important factor in determining the work efficiency of the semiconductor process equipment, so it is necessary to determine a scheduling sequence with higher efficiency and meeting time constraints based on a scheduling method, but the current scheduling sequence determination efficiency is low. SUMMARY

[0004] The embodiments of the present specification provide a scheduling method and related device to achieve the purpose of improving the determination efficiency of the scheduling sequence.

[0005] To achieve the above technical purpose, the embodiments of the present specification provide the following technical solutions:

[0006] In a first aspect, one embodiment of the present specification provides a scheduling method applied to a semiconductor process equipment, the semiconductor process equipment including a plurality of equipment modules, the scheduling method comprising:

[0007] obtaining a current scheduling sequence, the current scheduling sequence including a plurality of scheduling actions;

[0008] According to the time constraints of the target equipment module, the current scheduling sequence is traversed, and if the current scheduling sequence violates the time constraints of the target equipment module, the first key action and the second key action corresponding to the target equipment module are determined in the current scheduling sequence; the first key action includes a scheduling action that ends the time constraint counting duration of the target equipment module after execution is completed, and the second key action includes a scheduling action whose execution sequence is before the first key action and whose execution start time affects the time constraint counting duration of the target equipment module;

[0009] According to the target delay, the start execution time of the target scheduling action in the current scheduling sequence is updated to obtain an updated current scheduling sequence, and the step of traversing the current scheduling sequence according to the time constraints of the target equipment module is returned, the target scheduling action includes the second key action, and the target delay includes the timeout duration of the time constraints of the target equipment module for the current scheduling sequence.

[0010] In a second aspect, an embodiment of the present specification provides a semiconductor process scheduling device, characterized in that comprising: a processor and a memory; the memory stores a computer program, and the processor executes the computer program to implement the scheduling method described in any one of the above aspects to obtain a target scheduling sequence, wherein the target scheduling sequence comprises a current scheduling sequence satisfying a time constraint of a target device module; and the target scheduling sequence is used to determine a processing order of a wafer in the plurality of device modules.

[0011] In a third aspect, an embodiment of the present specification provides a semiconductor process device comprising a semiconductor process scheduling device and a plurality of device modules.

[0012] The semiconductor process scheduling device is configured to determine a target scheduling sequence according to the scheduling method described in any one of the above aspects, wherein the target scheduling sequence comprises a current scheduling sequence satisfying a time constraint of a target device module; and the target scheduling sequence is used to determine a processing order of a wafer in the plurality of device modules.

[0013] In a fourth aspect, an embodiment of the present specification further provides a computing device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor executes the computer program to implement the scheduling method described above.

[0014] In a fifth aspect, an embodiment of the present specification further provides a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the computer program is executable on a processor to implement the scheduling method described above.

[0015] In a sixth aspect, an embodiment of the present specification provides a computer program product or a computer program, wherein the computer program product comprises a computer program stored in a computer readable storage medium; and a processor of the computer device reads the computer program from the computer readable storage medium, and the processor executes the computer program to implement the steps of the scheduling method described above.

[0016] It can be seen from the technical solution that the scheduling method provided by the embodiments of the present specification does not directly discard the current scheduling sequence when the current scheduling sequence violates the time constraint of the target device module, delays the wafer out of the sheet, replans the current scheduling sequence, and determines the first key action and the second key action corresponding to the target device module in the current scheduling sequence, and updates the starting execution time of the target scheduling action in the current scheduling sequence according to the target delay to obtain an updated current scheduling sequence. In this way, through limited adjustment of the scheduling action, the updated current scheduling sequence has the possibility of meeting the time constraint of the target device module, reducing the number of times of replanning the scheduling sequence, and being conducive to improving the efficiency of the scheduling method in determining the available target scheduling sequence. In addition, by adjusting the target scheduling action in the current scheduling sequence that violates the time constraint, the updated current scheduling sequence has the possibility of not violating the time constraint, avoiding the situation that directly discarding the current scheduling sequence that violates the time constraint may lead to the loss of feasible solutions. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present specification or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only embodiments of the present specification, and those skilled in the art can obtain other drawings according to the provided drawings without creative labor.

[0018] FIG. 1 A structural schematic diagram of a semiconductor process equipment;

[0019] FIG. 2 A flowchart of a scheduling method provided by an embodiment of the present specification;

[0020] FIG. 3 A flowchart of a scheduling method provided by another embodiment of the present specification;

[0021] FIG. 4 A structural schematic diagram of a computing device provided by an embodiment of the present specification. DETAILED DESCRIPTION

[0022] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present specification should be understood as the usual meaning understood by those skilled in the art to which the present specification belongs. The "first", "second" and similar words used in the embodiments of the present specification do not represent any order, quantity or importance, but are only set to avoid confusion of the constituent elements.

[0023] Unless the context otherwise requires, throughout this specification, "a plurality of" means "at least two," and "including" is interpreted as open-ended or encompassing, that is, "including, but not limited to." In the description of this specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this specification. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example.

[0024] The technical solutions in the embodiments of this specification will now be described with reference to the accompanying drawings. All other embodiments obtained by those skilled in the art based on the embodiments in this specification without inventive effort are within the scope of protection of this specification.

[0025] SUMMARY

[0026] refer to FIG. 1 Taking cluster-type equipment as an example, FIG. 1 A schematic diagram of a semiconductor process equipment is shown. The equipment may include a robotic arm and multiple equipment modules. The robotic arm may include a first robotic arm 10, and the equipment modules may include a wafer loading / unloading station 21, a calibration module 22, a cooling tray 23, and multiple processing modules 11, etc.

[0027] Each wafer loading / unloading position 21 can hold one wafer box, and each wafer box can hold multiple wafers.

[0028] The calibration module 22 may include a slot, and the calibration module 22 can calibrate the wafer placed in the slot.

[0029] Processing Module 11: Each processing module 11 has a slot that can hold a wafer for processing.

[0030] Cooler 23 is used to cool the wafers after processing.

[0031] The first robotic arm 10 can be a dual-arm robotic arm. The two arms of the dual-arm robotic arm can be at a 180° angle and remain fixed. Each arm has a slot, and each slot can hold a wafer. Under normal circumstances, the two arms cannot perform wafer picking and placing operations at the same time. The first robotic arm 10 is responsible for transporting wafers between the vacuum lock 30 and multiple process chambers 11.

[0032] In addition, in some embodiments, the semiconductor process equipment may also include structures such as a vacuum lock and a second robotic arm. The vacuum lock (LoadLock) may have two slots, each capable of holding one wafer. The vacuum lock can switch between atmospheric and vacuum states. When the vacuum lock is in atmospheric state, the wafer located on the second robotic arm side can be fed into the vacuum lock; when the vacuum lock is in vacuum state, the wafer located on the first robotic arm side can be fed into the vacuum lock. The second robotic arm may be a single-arm robotic arm, with one slot for holding one wafer. The second robotic arm is responsible for moving the wafer between the wafer loading / unloading position 11, the calibration module 22, and the vacuum lock.

[0033] The wafer process path can include the multiple process nodes the wafer passes through in semiconductor process equipment and the process time required for each process node. This process path can be specifically formulated by process engineers according to the wafer process requirements and can be flexibly changed. For example, the wafer process path can include: wafer loading / unloading position -> second robot (3 seconds) -> calibration module (1 second) -> second robot (3 seconds) -> vacuum lock (3 seconds) -> first robot (3 seconds) -> first process chamber (60 seconds) -> first robot (3 seconds) -> second process chamber (120 seconds) -> first robot (3 seconds) -> third process chamber (60 seconds) -> first robot (3 seconds) -> fourth process chamber (60 seconds) -> first robot (3 seconds) -> vacuum lock (3 seconds) -> second robot (3 seconds) -> cooling tray (1 second) -> wafer loading / unloading position.

[0034] A scheduling sequence can refer to a set of scheduling actions performed by a robot arm in chronological order when controlling the scheduling of wafers according to the process path. Taking the wafer process path above as an example, the corresponding scheduling sequence can include wafer gripping actions and wafer placement actions for each equipment module. For example, it can include actions such as: gripping a wafer from the wafer loading / unloading position, placing the wafer in the calibration module, gripping a wafer from the calibration module, placing the wafer in the vacuum lock, and gripping a wafer from the vacuum lock.

[0035] Time constraints refer to the constraints set for the dwell or handling time of wafers in equipment modules (mostly processing modules). For example, time constraints can include dwell time constraints, which stipulate that the dwell time of a wafer after processing in an equipment module cannot exceed the set maximum dwell time. For example, for process chamber A, in order to avoid quality problems caused by the residual high temperature or residual gas in process chamber A due to the wafer being dwelled in process chamber A for a long time after processing, a dwell time constraint can be set for process chamber A to not exceed the set time. If, when wafer scheduling is performed according to a certain scheduling sequence, the dwell time of a certain wafer in process chamber A exceeds the set time, it is said that the scheduling sequence violates the dwell time constraint.

[0036] For example, time constraints can also include Q-time constraints. Q-time constraints refer to the maximum process interval between two equipment modules. Specifically, it refers to the maximum time from the completion of the process in one equipment module to the start of the process in the next. Q-time constraints are designed to prevent quality problems that may result from prolonged exposure of the wafer outside the process chamber or prolonged gripping by a robotic arm. Suppose that the Q-time constraint for process chamber B is set to 10 seconds. In the scheduling sequence, the next equipment module after process chamber B is process chamber C. The timer starts when the wafer's process in process chamber B is completed and continues until the robotic arm picks up the wafer from process chamber B and places it into process chamber C. The entire process cannot take more than 10 seconds. If, during wafer scheduling according to a certain sequence, the process interval between a wafer in process chamber B and process chamber C exceeds 10 seconds, then the scheduling sequence is said to have violated the Q-time constraint.

[0037] In the process of generating a scheduling sequence, a current scheduling sequence is typically generated first based on the wafer's process recipe. Then, it is determined whether the current scheduling sequence violates the time constraints set for a specific device module (hereinafter referred to as the target device module). In related technologies, if the current scheduling sequence violates the time constraints of the target device module, the principle that a scheduling sequence satisfying the time constraints can always be found by continuously delaying the wafer's ejection time from the wafer loading / unloading station is applied (because the wafer ejection time is delayed, the device modules of the semiconductor process equipment can process other wafers based on the delayed time, potentially resulting in some device modules being idle, allowing the wafer start processing time to be advanced, thus possibly solving the time constraint problem). The wafer ejection time of the wafer in the current scheduling sequence is delayed, and the current scheduling sequence is re-planned based on the delayed wafer ejection time, and the time constraint violation is checked again. This entire process requires repeatedly planning the current scheduling sequence, resulting in a long time consumption for the entire scheduling sequence generation process. Furthermore, the inventors discovered through research that directly delaying the wafer ejection time may lead to the loss of some feasible scheduling sequences. For example, if a current scheduling sequence violates the time constraint of a certain device module, it may be possible to meet the time constraint of the device module simply by adjusting the start time of some scheduling actions. However, in related technologies, if the wafer unloading time is directly delayed and the current scheduling sequence is replanned based on the delayed wafer unloading time, the original current scheduling sequence will be directly discarded, resulting in the loss of feasible solutions.

[0038] To address this issue, the inventors discovered that if the current scheduling sequence violates the time constraints of the target device module, a first key action and a second key action corresponding to the target device module can be determined in the current scheduling sequence. The first key action includes a scheduling action that ends the time constraint timing duration of the target device module after execution, and the second key action includes a scheduling action that is executed before the first key action and whose start time affects the time constraint timing duration of the target device module.

[0039] After confirming the key action, the start time of the target scheduling action in the current scheduling sequence can be updated according to the target delay to obtain the updated current scheduling sequence. Then, the steps of traversing the current scheduling sequence according to the time constraint of the target device module are returned. The target scheduling action includes the second key action, and the target delay includes the timeout duration of the current scheduling sequence for the time constraint of the target device module.

[0040] When the current scheduling sequence violates the time constraints of the target device module, this method does not directly discard the current scheduling sequence, delay wafer unloading, re-plan the current scheduling sequence, and re-determine whether it violates the time constraints of the target device module. Instead, it determines the first and second key actions corresponding to the target device module in the current scheduling sequence, and updates the start time of the target scheduling action in the current scheduling sequence according to the target delay to obtain the updated current scheduling sequence. In this way, by adjusting the scheduling actions a limited number of times, the updated current scheduling sequence may meet the time constraints of the target device module, reducing the number of times the scheduling sequence is re-planned, which helps to improve the efficiency of the scheduling method in determining the available target scheduling sequence. In addition, by adjusting the target scheduling actions in the current scheduling sequence that violates the time constraints, the updated current scheduling sequence may not violate the time constraints, avoiding the loss of feasible solutions that may be caused by directly discarding the current scheduling sequence that violates the time constraints.

[0041] Based on the above concept, the embodiments of this specification provide a scheduling method, which will be described exemplarily below with reference to the accompanying drawings.

[0042] Exemplary method

[0043] To be applied FIG. 2 Taking the controller of the semiconductor process equipment shown as an example, the controller can be a host computer or a slave computer of the semiconductor process equipment. Some embodiments of this specification provide a scheduling method. The semiconductor process equipment also includes multiple equipment modules. The scheduling method includes:

[0044] S201: Obtain the current scheduling sequence, which includes multiple scheduling actions; the scheduling actions may include one of a wafer grabbing action and a wafer placement action for the device module.

[0045] The current scheduling sequence can be generated by a scheduling algorithm. When generating the current scheduling sequence, the scheduling algorithm follows the principle of starting as early as possible. That is, as long as the state of each module of the semiconductor process equipment allows, the execution time of each generated scheduling action is as early as possible. In this way, the generated current scheduling sequence can meet the principle of maximizing wafer processing scheduling efficiency.

[0046] As the topology of semiconductor process equipment becomes increasingly complex, the number of wafers that can be processed simultaneously also increases. This poses a significant challenge to scheduling algorithms in generating the current scheduling sequence. The scheduling algorithm first needs to generate a large number of feasible candidate scheduling sequences based on the state of the semiconductor process equipment and the process path of the wafer to be scheduled. Then, it traverses a large number of candidate scheduling sequences and selects the most efficient candidate scheduling sequence as the current scheduling sequence, proceeding to the subsequent step of judging whether it meets the time constraints. Therefore, reducing the number of times the scheduling sequence is generated can greatly improve the efficiency of determining the scheduling sequence and reduce the required time.

[0047] S202: Based on the time constraint of the target device module, traverse the current scheduling sequence. If the current scheduling sequence violates the time constraint of the target device module, determine the first key action and the second key action corresponding to the target device module in the current scheduling sequence. The first key action includes a scheduling action that ends the time constraint timing duration of the target device module after execution. The second key action includes a scheduling action that is executed before the first key action and whose execution start time affects the time constraint timing duration of the target device module.

[0048] If the current scheduling sequence does not violate the time constraints of the target device module, it indicates that the current scheduling sequence is a target scheduling sequence with high scheduling efficiency and meets the time constraints of the target device module. This target scheduling sequence can be used as a sequence to control the semiconductor process equipment to process the wafer.

[0049] The target device module refers to a device module with time constraints. In actual production, there can be one or more target device modules. The types of time constraints can include dwell time constraints and Q-time constraints. A single target device module can be set with one type of time constraint or multiple types of time constraints at the same time. This specification does not limit this and depends on the actual situation.

[0050] The first critical action refers to the scheduling action that affects the duration of the time constraint, specifically the scheduling action that ends the time constraint timing of the target device module after its execution. The second critical action refers to the scheduling action that is executed before the first critical action and whose start time affects the duration of the time constraint timing of the target device module, specifically the scheduling action whose start time affects the start time of the time constraint timing of the target device module. For example, suppose device module A has a dwell time constraint. After device module A finishes processing the wafer, it will start timing the dwell time constraint. If this timing exceeds a certain value, it is considered a violation of the dwell time constraint. The action of grabbing the wafer from device module A is the first critical action that continues to increase the end time. That is, for the dwell time constraint, the wafer grabbing action of the target device module can be considered the first critical action. Correspondingly, the action of placing the wafer into device module A will affect the start time of the dwell time constraint of device module A. This is because device module A has a dwell time constraint. The wafer process duration is fixed. If the wafer placement action in device module A is delayed, the process start time of device module A will be delayed accordingly, and the start time of the dwell time constraint of device module A will be delayed accordingly. With the start time of the first critical action (wafer gripping action) unchanged, delaying the wafer placement action in device module A can effectively shorten the dwell time constraint of device module A, thereby potentially avoiding the occurrence of violations of the dwell time constraint of device module A. Therefore, in this example, the wafer placement action for device module A can be regarded as the second critical action.

[0051] However, in some cases, semiconductor process equipment may prohibit the robotic arm from holding a wafer for a certain period of time without placing it into equipment module A, even when the wafer placement conditions are met. In this case, the wafer gripping action before the wafer placement action for equipment module A (when the robotic arm is empty and there is no wafer on the robotic arm) can be considered as the second critical action. This is because the delay in the start of the wafer gripping action will cause a delay in the start of the wafer placement action for equipment module A. Based on the same principle described above, the delay in the start of the wafer placement action for equipment module A will shorten the dwell time for equipment module A. In this case, the wafer gripping action before the wafer placement action for equipment module A can be considered as the second critical action.

[0052] A target scheduling action refers to a scheduling action whose start time needs to be adjusted due to a violation of time constraints. In other words, a target scheduling action refers to the second critical action whose start time needs to be adjusted, as well as related actions whose start times need to be adjusted accordingly because the start time of the second critical action has been adjusted. That is, a target scheduling action must at least include the second critical action; the specific reasons can be found in the relevant description above. In addition, a target scheduling action may also include related actions whose start times need to be adjusted accordingly because the second critical action has been adjusted. These related actions are scheduling actions that follow the second critical action, but not all scheduling actions that follow the second critical action are related actions.

[0053] For example, suppose the second critical action in the scheduling sequence includes a wafer placement action in process chamber PM1, with a start time of 10 and a finish time of 15. In the scheduling sequence, following the second critical action, there is also a wafer processing action in process chamber PM1, with a start time of 15 and a finish time of 50. In this case, suppose the start time of the second critical action is delayed by 5 units of time, then the start time of the second critical action is delayed to 15 and the finish time is delayed to 20. At this time, due to the delay in the start time of the second critical action, the start time of the wafer processing action in process chamber PM1 is also delayed to 20, that is, this scheduling action is also included as one of the target scheduling actions.

[0054] When the current scheduling sequence violates the time constraint, since the current scheduling sequence is based on the principle of starting as early as possible, the start time of the first critical action is already the earliest time in the current state. It is impossible to shorten the time constraint by advancing the start time of the first critical action. Therefore, it is necessary to adjust the target scheduling actions, including the second critical action, so that the updated current scheduling sequence no longer violates the time constraint.

[0055] S203: Based on the target delay, update the start time of the target scheduling action in the current scheduling sequence to obtain the updated current scheduling sequence, and return the step of traversing the current scheduling sequence according to the time constraint of the target device module. The target scheduling action includes the second key action, and the target delay includes the timeout duration of the current scheduling sequence for the time constraint of the target device module.

[0056] In this embodiment, when the current scheduling sequence violates the time constraint of the target device module, the scheduling method does not directly discard the current scheduling sequence, delay wafer unloading, re-plan the current scheduling sequence, and re-determine whether it violates the time constraint of the target device module. Instead, it determines the first and second key actions corresponding to the target device module in the current scheduling sequence, and updates the start time of the target scheduling action in the current scheduling sequence according to the target delay to obtain the updated current scheduling sequence. In this way, by adjusting the scheduling actions a limited number of times, the updated current scheduling sequence may meet the time constraint of the target device module, reducing the number of times the scheduling sequence is re-planned, which helps to improve the efficiency of the scheduling method in determining the available target scheduling sequence. In addition, by adjusting the target scheduling actions in the current scheduling sequence that violates the time constraint, the updated current scheduling sequence may not violate the time constraint, avoiding the loss of feasible solutions that may be caused by directly discarding the current scheduling sequence that violates the time constraint.

[0057] Based on the above concept, one embodiment of this specification provides a feasible way to determine the first critical action and the second critical action for different types of time constraints. Specifically, the time constraints include at least one of dwell time constraints and Q-time constraints. The dwell time constraint represents the maximum time the wafer is allowed to dwell in the target device module, and the Q-time constraint represents the maximum process interval time of the wafer between the previous device module and the next device module.

[0058] The step of determining the first key action and the second key action corresponding to the target device module in the current scheduling sequence includes:

[0059] When the time constraint of the target device module includes a dwell time constraint, the wafer grabbing action in the target device module in the current scheduling sequence is determined as the first key action; the target placement action or target grabbing action in the current scheduling sequence that precedes the first key action is determined as the second key action; the target placement action includes: the wafer placement action in the target device module; the target grabbing action includes: the wafer grabbing action in the current scheduling sequence that precedes the target placement action;

[0060] As mentioned earlier, the start time of the second critical action can affect the timing duration of the device module's time constraints. For time constraints such as assistant time constraints or Q-time constraints, the second critical action can be the target placement action, i.e., the wafer placement action on the target device module. By delaying the start time of the wafer placement action, the timing duration of the time constraint can be shortened, which is beneficial for improving the situation of time constraint violations. However, in some cases, due to considerations such as process quality, semiconductor process equipment may prohibit the wafer from staying on the robotic arm (if the start time of the wafer placement action is delayed, the situation of the wafer staying on the robotic arm will be involved). In this case, the target grasping action can be used as the second critical action.

[0061] When the time constraint of the target device module includes a Q-time constraint, the wafer placement action of the next device module in the current scheduling sequence is determined as the first key action, and the target placement action or the target grabbing action in the current scheduling sequence that precedes the first key action is determined as the second key action.

[0062] Regarding the dwell time constraint, this implementation defines the first key action as the wafer grabbing action of the target device module. This is because once a dwell time constraint is violated, the occurrence of this action cannot be delayed (because delaying this action will further aggravate the violation of the dwell time constraint) nor can it be brought forward (as mentioned above, this is because the current scheduling sequence follows the principle of starting as early as possible, and the start time of this action is already the earliest time). After this action is completed, the dwell time constraint timing stops.

[0063] For Q-time constraints, the actions involved are wafer pick-up in the target device module and wafer placement in the next device module. Since the timing of the Q-time constraint depends on the wafer placement action in the next device module, this placement action determines the duration of the Q-time constraint's timing; that is, the Q-time constraint's timing stops after the wafer placement action is completed. Similarly, when a Q-time constraint is violated, the start time of the first critical action cannot be delayed or advanced.

[0064] Once the first key action is determined, the second key action that needs to be adjusted can be found based on the first key action. By determining the first and second key actions in this way, the scheduling action that needs to be adjusted can be quickly located, which is beneficial to improving the execution efficiency of the method.

[0065] Regarding the determination of the second key action, one implementation provides a feasible method. Specifically, if the semiconductor process equipment prohibits the wafer from remaining on the robotic arm, the step of taking the target placement action or target grasping action in the current scheduling sequence that precedes the first key action as the second key action includes:

[0066] The target grabbing action that precedes the first key action in the current scheduling sequence is designated as the second key action.

[0067] When semiconductor process equipment does not prohibit the wafer from staying on the robot arm, the target placement action that precedes the first key action can be used as the second key action. This reduces the number of scheduling actions that need to be adjusted and improves the efficiency of the method execution.

[0068] When semiconductor process equipment prohibits wafers from remaining on the robotic arm due to wafer quality control requirements (i.e., after the robotic arm picks up the wafer, it should perform the wafer placement action as soon as possible; it is prohibited to pick up the wafer on the robotic arm without performing the wafer placement action when the conditions for execution exist), the first empty-handed robotic arm action before the first key action (generally the target picking action; therefore, when performing the target picking action, the robotic arm will have a slot without a picked-up wafer) can be considered as the second key action. In this embodiment, the requirements for determining the second key action can be met in both cases where the semiconductor process equipment allows wafers to remain on the robotic arm and cases where wafers are prohibited from remaining on the robotic arm, which is beneficial to improving the applicability of the method.

[0069] In one implementation, a feasible method for updating the current scheduling sequence is provided. Specifically, updating the start time of the target scheduling action in the current scheduling sequence according to the target delay includes:

[0070] Based on the target delay and reference parameters, the start execution time of the second key action and the start execution time of other scheduled actions in the current scheduling sequence that are located after the second key action are adjusted in sequence.

[0071] The reference parameter is empty, or the reference parameter includes at least one of the following: the update result of the previous scheduling action and the time for the robot to wait for the device module to process the wafer.

[0072] When updating the current scheduling sequence, it is not simply a matter of delaying the start time of the second critical action and all subsequent scheduling actions by the target delay. Instead, it is necessary to comprehensively determine the update based on the update result of the previous scheduling action and reference parameters such as the processing time of the wafer by the robot waiting equipment module, so that the updated current scheduling sequence is more in line with the actual process conditions.

[0073] To further improve the execution efficiency of the method, in one implementation, reference is made to... FIG. 3 Before the step of returning and traversing the current scheduling sequence according to the time constraint of the target device module, the method further includes:

[0074] S301: Determine whether the start time of the first key action in the updated current scheduling sequence has been adjusted. If yes, discard the updated current scheduling sequence and regenerate a new current scheduling sequence. If no, return to the step of traversing the current scheduling sequence according to the time constraint of the target device module.

[0075] In this embodiment, after updating the current scheduling sequence, before returning to traverse the current scheduling sequence, it is first determined whether the start time of the first critical action in the updated current scheduling sequence has been adjusted. If so, according to the previous description, due to the early start principle, the start time of the first critical action cannot be delayed or advanced. If the start time of the first critical action has been adjusted, it indicates that the current scheduling sequence cannot meet the time constraint, and the current scheduling sequence can be discarded and a new current scheduling sequence can be generated. Then, step S202 is returned to determine whether the time constraint is violated in the newly generated current scheduling sequence. In this way, repeated judgment and adjustment of the current scheduling sequence that cannot meet the time constraint can be avoided, which is beneficial to improving the execution efficiency of the method.

[0076] To further improve the execution efficiency of the method, in one embodiment, determining the first key action and the second key action corresponding to the target device module in the current scheduling sequence includes:

[0077] Traverse the current scheduling sequence in reverse order to determine the first critical action in the current scheduling sequence;

[0078] Starting from the first key action, continue to traverse the current scheduling sequence in reverse order to determine the second key action.

[0079] In this embodiment, by traversing the current scheduling sequence in reverse order and starting from the first key action, the current scheduling sequence is updated and adjusted. This avoids repeated adjustments to the scheduling actions, thereby improving the execution efficiency of the method.

[0080] One embodiment of this specification provides a feasible method for calculating target latency. Specifically, the time constraints include: dwell time constraints, or Q-time constraints, wherein the dwell time constraints characterize the maximum time the wafer is allowed to dwell in the target device module, and the Q-time constraints characterize the maximum process interval duration of the wafer between the previous device module and the next device module.

[0081] The target delay corresponding to the dwell time constraint is calculated based on a first preset formula;

[0082] The first preset formula includes:

[0083]

[0084] Where Δ represents the target delay, and max() represents the maximum value operation. This indicates the moment when the wafer finishes processing in the target device module. This indicates the maximum time a wafer is allowed to reside in the target device module after processing. Indicates the start time of capturing the wafer from the target device module;

[0085] The target delay corresponding to the Q-time constraint is calculated based on a second preset formula;

[0086]

[0087] Where Δ represents the target delay, and max() represents the maximum value operation. This indicates the moment when the wafer is placed in the next device module of the target device module. This indicates the maximum process interval time between the target device module and the next device module of the target device module.

[0088] The first and second preset formulas can obtain the target delay calculation result based on simple subtraction and maximum value operations, which has the characteristics of low computational load.

[0089] Accordingly, this specification also provides a method for determining whether the current scheduling sequence violates the time constraints of the target device module based on the above-mentioned target delay calculation method. Specifically, the method for determining whether the current scheduling sequence violates the time constraints of the target device module includes:

[0090] According to the first preset formula and / or the second preset formula, the target delay of the scheduling action for the target device module is calculated. When the target delay of the scheduling action for the target device module is greater than 0, it is determined that the current scheduling sequence violates the time constraint of the target device module.

[0091] Similarly, judging whether the target delay calculated based on the first and second preset formulas violates the time constraint has the characteristics of low computational load and easy execution.

[0092] This specification provides several examples of feasible scheduling sequence adjustments using the scheduling methods provided in this specification, based on a specific implementation method.

[0093] Specifically, in the following example, LP1 represents wafer loading / unloading position 1, PM1 represents process chamber 1, LP2 represents wafer loading / unloading position 2, and PM2 represents process chamber 2; Pick@X represents the wafer picking action in device module X, Place@X represents the wafer placement action in device module X, and Process@X represents the wafer processing action in device module X.

[0094] The first scenario is when the scheduling sequence violates the dwell time constraint. Assume the current scheduling sequence is: Pick@LP1(0,5)~Place@PM1(5,10)~Process@PM1(10,30)~Pick@LP2(10,15)~Place@PM2(15,20)~Process@PM2(20,30)~Pick@PM1(30,35)~Place@LP1(35,40)~Pick@PM2(40,45)~Place@LP2(45,50). Specifically, the robot arm picks up a wafer from LP1 and puts it into PM1 for processing, then picks up a wafer from LP2 and puts it into PM2 for processing, then picks up the processed wafer from PM1 and puts it back into LP1, and finally picks up the processed wafer from PM2 and puts it into LP2.

[0095] This involves the processing and scheduling of two wafers by a robotic arm. The start and end times of each scheduling action are shown in parentheses. For simplicity, the robotic arm's movement time is included in the Pick / Place action time. It should be noted that since the Process action and the Pick / Place action are the actions of the process chamber and the robotic arm, respectively, after the robotic arm places the wafer into the processing module, the Process action of the processing module and the Pick / Place action of the robotic arm to the next module can start simultaneously without affecting each other.

[0096] Consider the following scenario: only PM2 has a dwell time constraint of 7, while other device modules have no time constraints. Following the above process, check the actions in the current scheduling sequence in reverse order to see if any time constraints are violated: First, check the action Place@LP2(45,50). Since LP2 does not involve a dwell time constraint, continue searching in reverse order until the action Pick@PM2 is found. Then, based on the aforementioned dwell constraint delay time calculation formula... (i.e., the first preset formula), If the start time of the action Pick@PM2 is 40, and module i is the target device module PM2, then... The action Process@PM2(20,30) ends at time 30. The dwell time constraint for PM2 is set to 7. Substituting this into the formula above, we can calculate Δ = 40 - 30 - 7 = 3, which is greater than 0, indicating a violation of the dwell time constraint. According to the definition of the first critical action, the first critical action of the dwell time constraint is the grabbing action on the target device module (PM2). Therefore, Pick@PM2 is the first critical action in the current scheduling sequence. According to the adjustment strategy, we need to find the placement action (the second critical action) on this module and postpone its time by Δ units. Therefore, we find the robot's placement action on PM2 in the scheduling sequence as Place@PM2(15,20), and adjust its start time by adding Δ to (18,23), thus allowing the second wafer to be placed on the robot. The wafer stays on the robot arm for 3 units of time before being placed in PM2 for processing. If the machine does not allow the wafer to stay on the robot arm, according to the aforementioned adjustment strategy, it is necessary to start from the placement action being adjusted and continue backward to find the first action when the robot arm is empty, which is usually a grasping action (because once grasped, the action that occurs is definitely not empty). Therefore, in this scheduling sequence, starting from the Place@PM2 action, find the first action when the robot arm is empty, which is Pick@LP2, and adjust its time to (13, 18). Starting from this action, calculate and update subsequent actions one by one:

[0097] (1) Because Pick@LP2 is delayed by 3 units of time, the subsequent action Place@PM2 of the robot arm is updated to (18,23);

[0098] (2) Because Place@PM2 has been updated, the subsequent process action Process@PM2 calculation is updated to (23,33);

[0099] (3) For the action Pick@PM1(30,35), the start time of this action depends on the completion of the previous action of the robot and the time when the wafer is processed in PM1. According to the updated calculation results, the end time of the previous action Place@PM2 of the robot is 23, and the time when the wafer is processed in PM1 is 30. Therefore, this action does not need to be updated.

[0100] (4) Since the Pick@PM1(30,35) action was not updated, subsequent actions do not need to be calculated and updated.

[0101] At this point, the original scheduling sequence has been adjusted and updated to Pick@LP1(0,5)~Place@PM1(5,10)~Process@PM1(10,30)~Pick@LP2(13,18)~Place@PM2(18,23)~Process@PM2(23,33)~Pick@PM1(30,35)~Place@LP1(35,40)~Pick@PM2(40,45)~Place@LP2(45,50). The bolded scheduling actions indicate the actions that have been adjusted and updated. According to the process, the action Pick@PM2(40,45) was just checked. The preceding actions Place@LP1(35,40), Pick@PM1(30,35) and so on are checked in reverse order. Since LP1, PM1, and LP2 have no time constraints, the scheduling sequence has not violated any time constraints so far, and the calculation ends and the process exits.

[0102] The second scenario involves the current scheduling sequence violating the Q-time constraint. Assume the current scheduling sequence is: Pick@LP1(0,5)~Place@PM1(5,10)~Process@PM1(10,30)~Pick@LP2(10,15)~Place@PM2(15,20)~Process@PM2(20,30)~Pick@PM1(30,35)~Place@LP1(35,40)~Pick@PM2(40,45)~Place@PM3(45,5)~Place@PM3(45,5)~Place@PM2(40,45)~Place@PM3(45,5)~Place@PM2(40,45)~Place@PM2 ... 0), specifically described as follows: the robotic arm picks up a wafer from LP1 and places it into PM1 to start the process, then picks up a wafer from LP2 and places it into PM2 to start the process, then picks up a wafer from PM1 and places it into LP1, and finally picks up a wafer from PM2 and places it into PM3. From the perspective of the flow of each wafer, the first wafer starts from LP1, completes processing in PM1, and then returns to LP1. The second wafer starts from LP2, completes processing in PM2, and then continues to PM3 for subsequent processing. Therefore, for the second wafer, it goes through two processing modules: the first is PM2, and the second is PM3.

[0103] Consider the following scenario: only PM3 has a Q-time constraint of 15, while other modules have no time constraints. Following the above process, check the actions in the scheduling sequence in reverse order to see if any time constraints are violated: First, check the action Place@PM3(45,50), using the aforementioned Q-time constraint delay calculation formula (i.e., the second preset formula). The action Place@PM3(45,50) ends at time 50. The wafer is in the previous chamber, meaning the processing time of the PM2 process (Process@PM2(20,30)) is 30. The Q-time constraint for PM3 is set to 15. Substituting this into the formula above, we can calculate Δ = 50 - 30 - 15 = 5, which is greater than 0, indicating a violation of the dwell constraint. According to the definition of the first critical action, the first critical action of the Q-time constraint is the placement action of the next device module after the target device module. In this scheduling sequence, this is the placement action Place@PM3(45,50) in PM3. According to the adjustment strategy, we need to find the placement action in module i (i.e., the target device module) and postpone its time by Δ units. In this scheduling sequence, this means finding the placement action Place@PM2(15,20) in PM2, and adjusting its time by adding Δ to (20,25). This means the second wafer stays on the robotic arm for 5 units before being placed in PM2 for processing. (Thus, the start time of processing the second wafer in PM2 is delayed by 5 units, while the process duration of the second wafer in PM2 remains unchanged. Therefore, the completion time of the process in PM2 is also delayed.) The time interval is 5 units, but the wafer placement action Place@PM3(45,50) of the next equipment module PM3 in PM2 does not change. Therefore, the timing duration of the Q-time constraint of the second wafer in PM2 (from the time the second wafer is completed in PM2 to the time the second wafer is placed in PM3) is shortened by 5 units, thus avoiding the situation where the second wafer violates the Q-time constraint in PM2. If the machine does not allow the wafer to stay on the robot arm, according to the aforementioned adjustment strategy, it is necessary to start from the placement action being adjusted and find the first action when the robot arm is empty, which is usually the gripping action. Starting from the Place@PM2 action, find the first action Pick@LP2 when the robot arm is empty and adjust its time to (15,20). Starting from this action, calculate and update the subsequent actions one by one.

[0104] (1) Because Pick@LP2 is delayed by 5, it is updated to (20,25) according to the scheduling sequence Place@PM2;

[0105] (2) Because Place@PM2 was updated, Process@PM2 was updated to (25,35);

[0106] (3) For the action Pick@PM1(30,35), the start time of this action depends on the completion of the previous action of the robot and the time when the wafer is processed in PM1. According to the updated calculation results, the end time of the previous action Place@PM2 of the robot is 25, and the time when the wafer is processed in PM1 is 30. Therefore, this action does not need to be updated.

[0107] (4) Since the Pick@PM1(30,35) action was not updated, subsequent actions do not need to be updated.

[0108] At this point, the original current scheduling sequence has been adjusted and updated to Pick@LP1(0,5)~Place@PM1(5,10)~Process@PM1(10,30)~Pick@LP2(15,20)~Place@PM2(20,25)~Process@PM2(25,35)~Pick@PM1(30,35)~Place@LP1(35,40)~Pick@PM2(40,45)~Place@PM3(45,50). The bold text indicates the actions that have been adjusted and updated. According to the process, Place@PM3(45,50) was just checked. The preceding actions Pick@PM2(40,45), Place@LP1(35,40) and so on are checked in reverse order. Since LP1, PM1, LP2 and PM2 have no time constraints, the scheduling sequence has not violated any time constraints so far. The calculation ends and the process exits.

[0109] The third scenario involves a scheduling sequence that violates dwell time and Q-time constraints. Assume the current scheduling sequence is: Pick@LP1(0,5)~Place@PM1(5,10)~Process@PM1(10,20)~Pick@LP2(10,15)~Place@PM2(15,20)~Process@PM2(20,30)~Pick@PM1(30,35)~Place@LP1(35,40)~Pick@PM2(40,45)~Place@PM3(45,50). Specifically, the robot picks a wafer from LP1 and places it into PM1 to begin the process, then picks a wafer from LP2 and places it into PM2 to begin the process, then picks a wafer from PM1 and places it into LP1, and finally picks a wafer from PM2 and places it into PM3. This current scheduling sequence is the same as the current scheduling sequence in the second scenario described above.

[0110] Consider the following scenario: PM3 has a Q-time constraint of 15, PM1 has a dwell time constraint of 7, and other device modules have no time constraints. Check the scheduling sequence in reverse order to see if any time constraints are violated: First, check the action Place@PM3(45,50), based on the aforementioned Q-time constraint delay calculation formula. The action Place@PM3(45,50) ends at time 50. The wafer is in the previous chamber, meaning the processing time of the PM2 process (Process@PM2(20,30)) is 30. The Q-time constraint for PM3 is set to 15. Substituting this into the formula above, we can calculate that Δ = 50 - 30 - 15 = 5, which is greater than 0, indicating a violation of the Q-time constraint. According to the definition of the first critical action, the first critical action of the Q-time constraint is the placement action in the next module. In the current scheduling sequence, that is, the placement action Place@PM3(45,50) in PM3, according to the adjustment strategy, it is necessary to find the placement action in module i (target device module) and postpone the placement action time by Δ units of time. In the scheduling sequence, that is, find the placement action Place@PM2(15,20) in PM2, and adjust its time by adding Δ to (20,25), that is, let the second wafer stay on the robot arm for 5 units of time before placing it in PM2 for processing; if the machine does not allow the wafer to stay on the robot arm, according to the aforementioned adjustment strategy, it is necessary to start from the placement action being adjusted and find the first action when the robot arm is empty, which is usually the gripping action. Starting from the Place@PM2 action, find the first action when the robot arm is empty, Pick@LP2, and adjust its time to (15,20); starting from this action, calculate and update the subsequent actions one by one:

[0111] (1) Because Pick@LP2 is delayed by 5, it is updated to (20,25) according to the scheduling sequence Place@PM2;

[0112] (2) Because Place@PM2 was updated, Process@PM2 was updated to (25,35);

[0113] (3) For the action Pick@PM1(30,35), the start time of this action depends on the completion of the previous action of the robot and the time when the wafer is processed in PM1. According to the updated calculation results, the end time of the previous action Place@PM2 of the robot is 25, and the time when the wafer is processed in PM1 is 30. Therefore, this action does not need to be updated.

[0114] (4) Since the Pick@PM1(30,35) action was not updated, subsequent actions do not need to be updated.

[0115] At this point, the original current scheduling sequence has been adjusted and updated to Pick@LP1(0,5)~Place@PM1(5,10)~Process@PM1(10,20)~Pick@LP2(15,20)~Place@PM2(20,25)~Process@PM2(25,35)~Pick@PM1(30,35)~Place@LP1(35,40)~Pick@PM2(40,45)~Place@PM3(45,50). The bold text indicates the action that was adjusted and updated.

[0116] Based on the adjusted scheduling sequence, continue checking the action Pick@PM2(40,45) in reverse order. Since PM2 has no time constraint, continue checking the action Place@LP1(35,40) in reverse order. Since LP1 has no time constraint, continue checking the action Pick@PM1(30,35) in reverse order. According to the aforementioned formula for calculating dwell constraint delay time... If the start time of the action Pick@PM1 is 30, and module i (target device module) is PM1, then... The action Process@PM1(10,20) ends at time 20. The dwell time constraint for PM1 is set to 7. Substituting this into the formula above, we can calculate Δ = 30 - 20 - 7 = 3, which is greater than 0, indicating a violation of the dwell time constraint. According to the definition of the first critical action, the first critical action of the dwell time constraint is the grabbing action on the target device module (PM1). Therefore, Pick@PM1 is the first critical action in this scheduling sequence. Based on the aforementioned adjustment strategy, we need to find the placement action on this module and delay its time by Δ units. Therefore, we find the robot's placement action on PM1 in the scheduling sequence as Place@PM1(5,10), and adjust its start time by adding Δ to (8,13), thus allowing the first wafer to remain on the robot for 3 seconds. Each unit of time is used to place the wafer into PM1 for processing. If the machine does not allow the wafer to remain on the robotic arm, according to the aforementioned adjustment strategy, it is necessary to start from the placement action being adjusted and find the first action when the robotic arm is empty, which is usually the grasping action (because once grasped, the action that occurs must be in a non-empty state). Therefore, in this scheduling sequence, starting from the Place@PM1 action, find the first action when the robotic arm is empty, which is Pick@LP1, and adjust its time to (3,8). Starting from this action, calculate and update the subsequent actions one by one:

[0117] (1) The subsequent action of Pick@LP1 is the adjusted Place@PM1, and no further updates to the subsequent action are needed.

[0118] At this point, the original current scheduling sequence has been adjusted and updated to Pick@LP1(3,8)~Place@PM1(8,13)~Process@PM1(13,23)~Pick@LP2(15,20)~Place@PM2(20,25)~Process@PM2(25,35)~Pick@PM1(30,35)~Place@LP1(35,40)~Pick@PM2(40,45)~Place@PM3(45,50). The bold text indicates the actions that have been adjusted and updated. According to the process, Pick@PM1(30,35) was just checked. Based on the above-mentioned adjusted scheduling sequence, the actions Place@PM2(20,25), Pick@LP2(15,20) and so on are checked in reverse order. Since LP1 and PM2 do not have dwell time constraints, the scheduling sequence has not violated the time constraints so far, and the calculation ends and the process exits.

[0119] In this example, the first thing detected is a violation of the Q-time constraint. However, in real-world applications, this depends on the order of actions in the actual scheduling sequence. For instance, if the last action in a scheduling sequence is a grabbing action in a certain process module, the first action when traversing the sequence in reverse order is the grabbing action. Based on this grabbing action, the only constraint that can be checked is the wafer's dwell time constraint in that process module.

[0120] This doesn't mean that the wafer didn't violate Q-time constraints in the preceding actions, or that such violations weren't checked. It simply means that, according to the process, each action needs to be checked sequentially during the reverse traversal. Once a violation is detected, it must be addressed first before continuing to check the preceding actions. All violations are checked and handled sequentially during the reverse traversal; the process is simply one by one, checking and handling each violation before moving on to the next…

[0121] Therefore, the order of checking Q-time constraints first and then dwell time constraints in the example above is not a specification of the process in this invention, but depends on the order of actions in the input scheduling sequence. However, once a corresponding time constraint is found to be violated, the calculation and solution process is consistent with the example, and the order of checking constraints depends only on the order of actions in the scheduling sequence.

[0122] The fourth scenario involves a scheduling sequence that violates both residency time and Q-time constraints. However, unlike the third scenario, this violation occurs within the same device module. In other words, this device module has both residency time and Q-time constraints. Assume the current scheduling sequence is: Pick@LP2(0,5)~Place@PM3(5,10)~Process@PM3(10,25)~Pick@LP1(10,15)~Place@PM1(15,20)~Process@PM1(20,40)~Pick@PM3(25,30)~Place@LP2(30,35)~Pick@LP3(35,40)~Place@PM4(40, 45)~Process@PM4(45,70)~Pick@PM1(40,45)~Place@PM2(45,50)~Process@PM2(50,65)~Pick@PM4(70,75)~Place@LP3(75,80)~Pick@PM2(80,85), specifically described as follows: the robot arm picks up the first wafer from LP2 and puts it into PM3 to start the process, then picks up the second wafer from LP1 and puts it into PM3 to start the process, then picks up the first wafer from PM3 and puts it back into LP2, then picks up the third wafer from LP3 and puts it into PM4 to start the process, then picks up the second wafer from PM1 and puts it into PM2 to start the process, then picks up the third wafer from PM4 and puts it back into LP3, then picks up the second wafer from PM2.

[0123] Consider the following scenario: PM1, PM2, PM3, and PM4 all have a dwell time constraint of 10 and a Q-time constraint of 10. Following the above process, check the actions in the current scheduling sequence in reverse order to see if any time constraints are violated: First, check the action Pick@PM2(80,85). Then, based on the aforementioned formula for calculating the dwell time constraint delay... If the start time of the action Pick@PM2 is 80, and module i is PM2, then... The end time of the action Process@PM2(50,65) is 65. The dwell time constraint for PM2 is set to 10. Substituting this into the formula above, we can calculate Δ = 80 - 65 - 10 = 5, which is greater than 0, indicating a violation of the dwell time constraint. According to the definition of a critical action, the critical action for the dwell time constraint is the grabbing action in this module (i.e., PM2). Therefore, Pick@PM2 is the critical action in this scheduling sequence. Based on the aforementioned adjustment strategy, we need to find the placement action in this module and delay its time by Δ units. Therefore, we find the robot's placement action on PM2 in the scheduling sequence as Place@PM2(45, 50), and adjust its start time by adding Δ to (50, 55), meaning the second wafer will remain on the robot for 5 units. Then, place the wafer into PM2 for processing. If the machine does not allow the wafer to remain on the robotic arm, according to the adjustment strategy, it is necessary to start from the placement action being adjusted and find the first action when the robotic arm is empty, which is usually a grasping action (because once grasped, the action that occurs is definitely not empty). Therefore, in this scheduling sequence, starting from the Place@PM2 action, find the first action when the robotic arm is empty, which is Pick@PM1, and adjust its time to (45, 50). Starting from this action, calculate and update subsequent actions one by one:

[0124] (1) Because Pick@PM1 was delayed by 5 units of time, the subsequent action Place@PM2 of the robot arm was updated to (50,55);

[0125] (2) Because Place@PM2 has been updated, the subsequent process action Process@PM2 calculation is updated to (55,70);

[0126] (3) For the action Pick@PM4(70,75), the start time of this action depends on the completion of the previous action of the robot and the time when the wafer is processed in PM4. According to the updated calculation results, the end time of the previous action Place@PM2 of the robot is 55, and the time when the wafer is processed in PM4 is 70. Therefore, this action does not need to be updated.

[0127] (4) Since the Pick@PM4(70,75) action was not updated, subsequent actions do not need to be calculated and updated.

[0128] At this point, the original scheduling sequence has been adjusted and updated to Pick@LP2(0,5)~Place@PM3(5,10)~Process@PM3(10,25)~Pick@LP1(10,15)~Place@PM1(15,20)~Process@PM1(20,40)~Pick@PM3(25,30)~Place@LP2(30,35)~Pick@LP3(35,40)~Place@PM4(40,45)~Process@PM4(45,70)~Pick@PM1(45,50)~Place@PM2(50,55)~Process@PM2(55,70)~Pick@PM4(70,75)~Place@LP3(75,80)~Pick@PM2(80,85).

[0129] Based on the adjusted scheduling sequence, and following the process, we checked the action Pick@PM2(80,85) in reverse order. We then checked the action Place@LP3(75,80) in reverse order. Since LP3 has no time constraint, we checked Pick@PM4(70,75) in reverse order, using the aforementioned dwell constraint delay time calculation formula. If the start time of the action Pick@PM4 is 70, and module i is PM4, then... The action Process@PM4(45,70) ends at time 70. The dwell time constraint for PM4 is set to 10. Substituting this into the formula above, we can calculate Δ = 70 - 70 - 10 = -10, which is less than 0. Therefore, there is no violation of the dwell time constraint. Continuing to check Place@PM2(50, 55) in reverse order, according to the aforementioned Q-time constraint delay time calculation formula... The action Place@PM2(50,55) ends at time 55. This means that the processing time of the wafer in the previous chamber, namely PM1, is 30 seconds. The Q-time constraint for PM2 is set to 10. Substituting this into the formula above, we can calculate that Δ = 55 - 40 - 10 = 5, which is greater than 0, indicating a violation of the residency constraint. According to the definition of critical actions, the critical action in the Q-time constraint is the placement action in the next module. In this scheduling sequence, that is, the placement action Place@PM2(50,55) in PM2. According to the aforementioned adjustment strategy, it is necessary to find the placement action in module i and postpone its time by Δ units. In this scheduling sequence, that is, find the placement action Place@PM1(15,20) in PM1 and adjust its time by adding Δ to (20,25), that is, let the second wafer stay on the robot arm for 5 units before placing it in PM1 for processing. If the machine does not allow the wafer to stay on the robot arm, according to the aforementioned adjustment strategy, it is necessary to start from the placement action being adjusted and find the first action when the robot arm is empty, which is usually the gripping action. Starting from the Place@PM1 action, find the first action when the robot arm is empty, Pick@LP1, and adjust its time to (15,20). From this action, calculate and update the subsequent actions one by one:

[0130] (1) Because Pick@LP1 is delayed by 5, it is updated to (20,25) according to the scheduling sequence Place@PM1.

[0131] (2) Because Place@PM1 was updated, Process@PM1 was updated to (25,40);

[0132] (3) For the action Pick@PM3(25,30), the start time of this action depends on the completion of the previous action of the robot and the time when the wafer is processed in PM3. According to the updated calculation results, the end time of the previous action Place@PM2 of the robot is 25, and the time when the wafer is processed in PM3 is 25, so this action does not need to be updated.

[0133] (4) Since the Pick@PM3(25,30) action was not updated, subsequent actions do not need to be updated.

[0134] At this point, the original scheduling sequence has been adjusted and updated to Pick@LP2(0,5)~Place@PM3(5,10)~Process@PM3(10,25)~Pick@LP1(15,20)~Place@PM1(20,25)~Process@PM1(25,45)~Pick@PM3(25,30)~Place@LP2(30,35)~Pick@LP3(35,40)~Place@PM4(40,45)~Process@PM4(45,70)~Pick@PM1(45,50)~Place@PM2(50,55)~Process@PM2(55,70)~Pick@PM4(70,75)~Place@LP3(75,80)~Pick@PM2(80,85).

[0135] Based on the adjusted scheduling sequence, and following the process, we checked the action Place@PM2(50,55) in reverse order. Then we checked the actions Pick@PM1(45,50), Place@PM4(40,45), and so on. Finally, we found that the entire scheduling sequence did not violate the time constraints, so we ended the calculation and exited.

[0136] The examples above demonstrate that the scheduling method provided in this specification directly calculates and solves the existing current scheduling sequence, without discarding current scheduling sequences that violate time constraints, thus avoiding the loss of feasible solutions. Similarly, the scheduling method only re-searches and generates a new current scheduling sequence after calculation reveals it to be infeasible. This reduces the number of times the scheduling algorithm searches to generate the current scheduling sequence, thereby reducing the time required for the scheduling method. Furthermore, the scheduling method requires relatively little computation, only adjusting the time parameters of the scheduling actions, and can obtain the updated current scheduling sequence after a finite number of calculation steps, exhibiting the characteristics of low computational load and high processing speed.

[0137] The scheduling method provided in this specification defines and identifies key actions (e.g., the first key action) and proposes clear judgment conditions to determine whether the current scheduling sequence meets the time constraints. Compared with the process of continuous adjustment, re-searching, and continuous checking in related technologies, the scheduling method provided in this specification ensures that the calculation process for the same current scheduling sequence has a definite termination condition, that is, either the scheduling sequence does not violate the constraints after adjustment, or the key action is adjusted and the scheduling sequence is determined to be infeasible. It has the advantage of controllable computation time.

[0138] Exemplary apparatus

[0139] In one exemplary embodiment of this specification, a scheduling device is also provided, applied to a semiconductor process apparatus, the semiconductor process apparatus including a plurality of device modules, the scheduling device comprising:

[0140] A sequence acquisition module is used to acquire the current scheduling sequence, which includes multiple scheduling actions.

[0141] The action recognition module is used to traverse the current scheduling sequence according to the time constraint of the target device module. If the current scheduling sequence violates the time constraint of the target device module, then in the current scheduling sequence, a first key action and a second key action corresponding to the target device module are determined. The first key action includes a scheduling action that ends the time constraint timing duration of the target device module after execution. The second key action includes a scheduling action that is executed before the first key action and whose execution start time affects the time constraint timing duration of the target device module.

[0142] The sequence update module is used to update the start time of the target scheduling action in the current scheduling sequence according to the target delay, so as to obtain the updated current scheduling sequence, and return the steps of traversing the current scheduling sequence according to the time constraint of the target device module. The target scheduling action includes the second key action, and the target delay includes the timeout duration of the current scheduling sequence for the time constraint of the target device module.

[0143] Specific limitations regarding the scheduling device can be found in the limitations regarding the scheduling method above, and will not be repeated here. Each module in the aforementioned scheduling device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware within or independently of the processor in the computer device, or stored in software within the memory of the computer device, so that the processor can invoke and execute the operations corresponding to each module.

[0144] Accordingly, embodiments of this specification also provide a semiconductor process scheduling device, including: a processor and a memory; the memory stores a computer program, and when the processor executes the computer program, it implements the scheduling method described in any of the above embodiments to obtain a target scheduling sequence, the target scheduling sequence including a current scheduling sequence that satisfies the time constraints of a target device module; the target scheduling sequence is used to determine the processing order of the wafer in the plurality of device modules.

[0145] Accordingly, embodiments of this specification also provide a semiconductor process apparatus, including a semiconductor process scheduling device and multiple device modules;

[0146] The semiconductor process scheduling device is configured to determine a target scheduling sequence according to the scheduling method described in any of the above embodiments, the target scheduling sequence including a current scheduling sequence that satisfies the time constraints of a target device module; the target scheduling sequence is used to determine the processing order of the wafer in the plurality of device modules.

[0147] Exemplary computing device

[0148] Another embodiment of this specification also proposes a computing device, see [link to documentation]. FIG. 4 As shown, an exemplary embodiment of this specification also provides a computing device, including: a memory and a processor, the memory storing a computer program, the processor executing the computer program and performing steps in the scheduling methods according to various embodiments of this specification described in the foregoing embodiments.

[0149] The internal structure of the computing device can be as follows: FIG. 4 As shown, the computing device includes a processor, memory, network interface, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The network interface is used to communicate with external terminals via a network connection. When the computer program is executed by the processor, it follows the steps of the scheduling methods according to various embodiments of this specification described in the above embodiments.

[0150] The processor may include the main processor, as well as baseband chips, modems, etc.

[0151] The memory stores a program that executes the technical solution of this invention, and may also store an operating system and other critical business functions. Specifically, the program may include program code, which includes computer operation instructions. More specifically, the memory may include read-only memory (ROM), other types of static storage devices capable of storing static information and instructions, random access memory (RAM), other types of dynamic storage devices capable of storing information and instructions, disk storage, flash memory, etc.

[0152] The processor can be a general-purpose processor, such as a general-purpose central processing unit (CPU), a microprocessor, etc., or an application-specific integrated circuit (ASIC), or one or more integrated circuits used to control the execution of the program of the present invention. It can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), an off-the-shelf programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0153] Input devices may include devices that receive data and information input by the user, such as keyboards, mice, cameras, scanners, light pens, voice input devices, touch screens, pedometers, or gravity sensors.

[0154] Output devices may include devices that allow information to be output to the user, such as displays, printers, speakers, etc.

[0155] The communication interface may include any transceiver-like device for communicating with other devices or communication networks, such as Ethernet, Radio Access Network (RAN), Wireless Local Area Network (WLAN), etc.

[0156] The processor executes programs stored in memory and calls other devices, which can be used to implement the various steps of any of the scheduling methods provided in the above embodiments of this specification.

[0157] The computing device may also include a display component and a voice component. The display component may be a liquid crystal display screen or an e-ink display screen. The input device of the computing device may be a touch layer covering the display component, or a button, trackball or touchpad set on the casing of the computing device, or an external keyboard, touchpad or mouse, etc.

[0158] Those skilled in the art will understand that FIG. 4 The structures shown are merely block diagrams of some structures related to the solutions in this specification and do not constitute a limitation on the computing devices on which the solutions in this specification are applied. Specific computing devices may include more or fewer components than those shown in the figures, or combine certain components, or have different component arrangements.

[0159] Exemplary computer program product and storage medium

[0160] In addition to the methods and devices described above, the scheduling methods provided in the embodiments of this specification can also be computer program products, which include computer program instructions that, when executed by a processor, cause the processor to perform the steps in the scheduling methods according to various embodiments of this specification as described in the "Exemplary Methods" section above.

[0161] The aforementioned computer program product can be implemented through hardware, software, or a combination thereof. In one optional embodiment, the computer program product is specifically embodied in a computer storage medium; in another optional embodiment, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.

[0162] The computer program product described herein can be written in any combination of one or more programming languages ​​to perform the operations of the embodiments described herein. These programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0163] Furthermore, embodiments of this specification also provide a computer-readable storage medium having a computer program stored thereon, the computer program being executed by a processor of the steps in the scheduling methods according to various embodiments of this specification as described in the "Exemplary Methods" section above.

[0164] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the methods described above. Any references to memory, storage, databases, or other media used in the embodiments provided in this specification can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and RAMbus dynamic RAM (RDRAM), etc.

[0165] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0166] The embodiments described above are merely illustrative of several implementation methods outlined in this specification. While the descriptions are specific and detailed, they should not be construed as limiting the scope of the solutions provided in this specification. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this specification, and these all fall within the scope of protection of this specification. Therefore, the scope of protection for this patent should be determined by the appended claims.

Claims

1. A scheduling method, characterized in that, Applied to semiconductor process equipment, the semiconductor process equipment comprising multiple equipment modules, the scheduling method includes: Obtain the current scheduling sequence, which includes multiple scheduling actions; Based on the time constraints of the target device module, the current scheduling sequence is traversed. If the current scheduling sequence violates the time constraints of the target device module, then in the current scheduling sequence, a first key action and a second key action corresponding to the target device module are determined. The first key action includes a scheduling action that ends the time constraint timing duration of the target device module after execution. The second key action includes a scheduling action that is executed before the first key action and whose execution start time affects the time constraint timing duration of the target device module. Based on the target delay, update the start time of the target scheduling action in the current scheduling sequence to obtain the updated current scheduling sequence, and return the step of traversing the current scheduling sequence according to the time constraint of the target device module. The target scheduling action includes the second key action, and the target delay includes the timeout duration of the current scheduling sequence for the time constraint of the target device module.

2. The method according to claim 1, characterized in that, The time constraints include at least one of dwell time constraints and Q-time constraints, wherein the dwell time constraint characterizes the maximum time the wafer is allowed to dwell in the target device module, and the Q-time constraint characterizes the maximum process interval duration of the wafer between the previous device module and the next device module. The step of determining the first key action and the second key action corresponding to the target device module in the current scheduling sequence includes: When the time constraint of the target device module includes a dwell time constraint, the wafer grabbing action in the target device module in the current scheduling sequence is determined as the first key action; the target placement action or target grabbing action in the current scheduling sequence that precedes the first key action is determined as the second key action; the target placement action includes: the wafer placement action in the target device module; the target grabbing action includes: the wafer grabbing action in the current scheduling sequence that precedes the target placement action; When the time constraint of the target device module includes a Q-time constraint, the wafer placement action of the next device module in the current scheduling sequence is determined as the first key action, and the target placement action or the target grabbing action in the current scheduling sequence that precedes the first key action is determined as the second key action.

3. The method according to claim 2, characterized in that, If the semiconductor process equipment prohibits the wafer from remaining on the robotic arm, the step of using the target placement action or target grasping action in the current scheduling sequence that precedes the first key action as the second key action includes: The target grabbing action that precedes the first key action in the current scheduling sequence is designated as the second key action.

4. The method according to claim 1, characterized in that, The step of updating the start time of the target scheduling action in the current scheduling sequence according to the target delay includes: Based on the target delay and reference parameters, the start execution time of the second key action and the start execution time of other scheduled actions in the current scheduling sequence that are located after the second key action are adjusted in sequence. The reference parameter is empty, or the reference parameter includes at least one of the following: the update result of the previous scheduling action and the time for the robot to wait for the device module to process the wafer.

5. The method according to claim 1, characterized in that, Before the step of returning and traversing the current scheduling sequence according to the time constraint of the target device module, the method further includes: Determine whether the start time of the first critical action in the updated current scheduling sequence has been adjusted. If yes, discard the updated current scheduling sequence and regenerate a new current scheduling sequence. If no, return to the step of traversing the current scheduling sequence according to the time constraint of the target device module.

6. The method according to any one of claims 1 to 5, characterized in that, The step of determining the first key action and the second key action corresponding to the target device module in the current scheduling sequence includes: Traverse the current scheduling sequence in reverse order to determine the first critical action in the current scheduling sequence; Starting from the first key action, continue to traverse the current scheduling sequence in reverse order to determine the second key action.

7. The method according to any one of claims 1 to 5, characterized in that, The time constraints include: dwell time constraints, or Q-time constraints, wherein the dwell time constraints characterize the maximum time the wafer is allowed to dwell in the target device module, and the Q-time constraints characterize the maximum process interval duration of the wafer between the previous device module and the next device module; The target delay corresponding to the dwell time constraint is calculated based on a first preset formula; The first preset formula includes: Where Δ represents the target delay, and max() represents the maximum value operation. This indicates the moment when the wafer finishes processing in the target device module. This indicates the maximum time a wafer is allowed to reside in the target device module after processing. Indicates the start time of capturing the wafer from the target device module; The target delay corresponding to the Q-time constraint is calculated based on the second preset formula; Where Δ represents the target delay, and max() represents the maximum value operation. This indicates the moment when the wafer is placed in the next device module after the target device module. This indicates the maximum process interval time between the target device module and the next device module of the target device module.

8. The method according to claim 7, characterized in that, The method for determining whether the current scheduling sequence violates the time constraints of the target device module includes: According to the first preset formula and / or the second preset formula, the target delay of the scheduling action for the target device module is calculated. When the target delay of the scheduling action for the target device module is greater than 0, it is determined that the current scheduling sequence violates the time constraint of the target device module.

9. A semiconductor process scheduling device, characterized in that, include: Processor and memory; The memory stores a computer program. When the processor executes the computer program, it implements the scheduling method according to any one of claims 1 to 8 to obtain a target scheduling sequence. The target scheduling sequence includes a current scheduling sequence that satisfies the time constraints of the target device module. The target scheduling sequence is used to determine the processing order of the wafer in the plurality of device modules.

10. A semiconductor process apparatus, characterized in that, Includes semiconductor process scheduling equipment and multiple equipment modules; The semiconductor process scheduling device is configured to determine a target scheduling sequence according to the scheduling method according to any one of claims 1 to 8, the target scheduling sequence including a current scheduling sequence that satisfies the time constraints of a target device module; the target scheduling sequence is used to determine the processing order of the wafer in the plurality of device modules.

11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the scheduling method according to any one of claims 1 to 8.

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