Semiconductor temperature measuring device

Abstract

The embodiment of the present disclosure discloses a semiconductor temperature measuring device, comprising: a first wafer and a second wafer which are stacked; a temperature measuring assembly which is at least partially located between the first wafer and the second wafer; the temperature measuring assembly comprises a temperature measuring device, a power supply and a master control which are coupled through an interconnection circuit; a plurality of conductive columns which are located between the first wafer and the second wafer, the plurality of conductive columns are coupled with the first wafer and the second wafer; the plurality of conductive columns are located between the outer edge of the temperature measuring assembly and the side edge of the first wafer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor temperature measuring device. Background Technology

[0002] Temperature is an extremely important parameter in integrated circuit manufacturing, especially as chip dimensions continue to shrink, making wafer surface temperature measurement and control crucial. For example, in etching and deposition processes, precise temperature measurement of the wafer is essential to improve etching and deposition rates and ensure uniform temperature distribution. This precise temperature control guarantees optimal process performance. Therefore, a temperature measurement device is needed to record wafer temperature information during the manufacturing process. Engineers can analyze this information to adjust equipment parameters and processes, thereby improving chip manufacturing yield.

[0003] Some wafer temperature sensing devices use wired signal transmission. Wired wafer temperature measurement devices embed or attach temperature sensors to the wafer surface and transmit signals via wires. While this type of device is simple in structure, it has several problems, such as introducing contamination, disrupting the temperature field on the wafer surface with the wires, and obstructing temperature measurement. If a wireless transmission method is used, wireless sensing devices are susceptible to various electrical interferences from high-voltage DC and multi-frequency radio waves. Therefore, there is still considerable room for improvement in some wafer sensing devices. Summary of the Invention

[0004] According to some aspects of embodiments of this disclosure, a semiconductor temperature measuring device is provided, comprising: a first wafer and a second wafer stacked together; a temperature measuring component, at least partially located between the first wafer and the second wafer; the temperature measuring component including a temperature measuring device, a power supply, and a main controller coupled via interconnect circuits; a plurality of conductive pillars, at least partially located between the first wafer and the second wafer, the plurality of conductive pillars being coupled to the first wafer and the second wafer; the plurality of conductive pillars being located between the outer edge of the temperature measuring component and the side edge of the first wafer.

[0005] In some embodiments, the plurality of conductive pillars are spaced apart along the circumferential direction of the first wafer.

[0006] In some embodiments, the plurality of conductive pillars surround the outer edge of the temperature sensing component.

[0007] In some embodiments, the temperature sensing component further includes: an antenna coupled to the main controller; the antenna being located at the center of the first wafer and the second wafer; a plurality of temperature sensing devices arranged in a circumferential direction around the antenna; and the interconnect circuit including a plurality of first interconnect circuits coupled to the temperature sensing devices, the first interconnect circuits being spaced apart in a circumferential direction around the antenna.

[0008] In some embodiments, a first temperature measuring device among the plurality of temperature measuring devices is located at the outer edge of the temperature measuring assembly; the conductive post is located on the side of the first temperature measuring device away from the antenna.

[0009] In some embodiments, the conductive post is located between adjacent first interconnect circuits.

[0010] In some embodiments, the semiconductor temperature measuring device further includes: a first conductive layer located on a first surface of the first wafer, a second conductive layer located on a second surface of the second wafer; a conductive pillar located between the first conductive layer and the second conductive layer; and the conductive pillar being coupled to both the first conductive layer and the second conductive layer.

[0011] In some embodiments, the semiconductor temperature measuring device further includes: a capacitor structure, at least partially located between the first conductive layer and the second conductive layer; the capacitor structure includes a first electrode, a second electrode, and a dielectric layer, the dielectric layer being located between the first electrode and the second electrode; the first electrode is coupled to the first conductive layer, and the second electrode is coupled to the second conductive layer.

[0012] In some embodiments, at least one of the first wafer and the second wafer has a groove for accommodating at least a portion of the temperature sensing component; the first conductive layer extends into the inner wall of the groove; the capacitor structure is located in a corresponding groove, and the first electrode is coupled to the first conductive layer on the inner wall of the groove.

[0013] In some embodiments, the temperature sensing component further includes: a voltage regulator coupled to the interconnect circuit; the capacitor structure is symmetrically distributed on the outside of the electrical appliance of the temperature sensing component; and / or, the capacitor structure is spaced apart around the circumferential direction of the electrical appliance; wherein the electrical appliance of the temperature sensing component includes at least one of the temperature sensing device, the power supply, the main controller, and the voltage regulator.

[0014] This disclosure provides a semiconductor temperature measuring device that can be used to simulate the temperature distribution of a wafer during a process and measure temperature values. The semiconductor temperature measuring device includes a first wafer and a second wafer stacked together, and a temperature measuring component located at least partially between the first wafer and the second wafer. The temperature measuring component includes temperature measuring devices, a power supply, and a main controller coupled through interconnect circuits. It also includes a plurality of conductive pillars located between the first wafer and the second wafer, and the plurality of conductive pillars are coupled to the first wafer and the second wafer. The plurality of conductive pillars are located at the edges of the first wafer and the second wafer, and are located outside the temperature measuring component. When the first wafer and the second wafer accumulate plasma, charge, or are subjected to high voltage current, spike current, or multi-frequency radio frequency current, the conductive pillars guide the spike current to flow from the edge or outside of the wafer without passing through the inside of the temperature measuring component, thereby reducing interference and damage to the various devices of the temperature measuring component. Attached Figure Description

[0015] Figures 1 to 5 This is a schematic diagram of a semiconductor temperature measuring device according to an embodiment of the present disclosure;

[0016] Figure 6 and Figure 7 This is a schematic diagram of a capacitor structure according to an embodiment of the present disclosure;

[0017] Figure 8 This is a schematic diagram of a semiconductor temperature measuring device with a groove, exemplified by an embodiment of the present disclosure.

[0018] Figure 9 and Figure 10 This is a schematic diagram illustrating the distribution of conductive pillars according to an embodiment of this disclosure. Detailed Implementation

[0019] Exemplary embodiments disclosed herein will now be described in more detail with reference to the accompanying drawings. It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers.

[0020] It should be understood that references to "some embodiments" or "an embodiment" throughout the specification mean that a particular feature, structure, or characteristic relating to an embodiment is included in at least one embodiment of this disclosure. Furthermore, these particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0021] In some etching, vapor deposition, or epitaxial wafer systems, wafers are transported into the process cavity and fixed on a wafer carrier tray, which can be held by electrostatic adsorption, vacuum adsorption, or mechanical grippers. Within the process cavity, the wafer undergoes etching, deposition, and other processes. Temperature control components on the wafer carrier tray can heat or cool the wafer to provide and maintain the process temperature, improving process yield. In some embodiments, factors such as defects in the temperature control performance of the wafer carrier tray, deviations in the adjustment or setting of the temperature control components, or misalignment of the wafer on the wafer carrier tray may lead to uneven temperature distribution on the wafer, resulting in reduced process yield. For example, this may cause uneven etching rates or uneven deposition rates in different areas of the wafer. Detecting or measuring the temperature in different areas of the wafer allows for adjustments to the temperature control components or the wafer position to ensure that the temperature in each area of ​​the wafer meets the process control standards.

[0022] In some embodiments, to accurately simulate and measure the temperature distribution in different regions of a wafer, the disclosed embodiments provide a semiconductor temperature measuring device, the shape and size of which are the same as the product wafer, or in other words, a temperature measuring component including but not limited to temperature measuring devices is set on the wafer. This semiconductor temperature measuring device can also be called a temperature measuring wafer. The semiconductor temperature measuring device or temperature measuring wafer is transferred to a wafer carrier disk in the process cavity and adsorbed, the process is started, and the test signals of the temperature measuring devices distributed in different positions of the semiconductor temperature measuring device are obtained. This can simulate the temperature distribution of the product wafer in the relevant process, thereby realizing in-situ temperature testing of different regions of the product wafer in the process.

[0023] In some embodiments, the test signal for the semiconductor temperature measuring device or the temperature-measuring wafer can be transmitted via wired or wireless transmission. For example, the test signal characterizing the temperature value can be transmitted to an external host or processing unit for data processing via a transmission line; or a wireless transmission module, such as a Bluetooth module or a Wi-Fi module, can transmit the signal through an antenna and have it received by an external host for data processing. In some embodiments, the semiconductor temperature measuring device may be equipped with a memory device, such as a non-volatile memory device like a flash memory card, SSD, or hard disk, to store test data. After the test is completed, the semiconductor temperature measuring device is removed from the process chamber, and the memory device is read to retrieve the test data.

[0024] In some embodiments, taking process equipment with a plasma environment, such as plasma etching equipment or plasma-enhanced vapor deposition equipment (PCVD equipment), as examples, process gases form plasma within the process chamber to etch or deposit product wafers. These process chambers typically contain plasma generators or plasma deflectors, and power supplies such as high-voltage DC and multi-frequency radio frequency (RF) can cause significant interference to semiconductor temperature measuring devices. For example, high-voltage DC and RF can generate spike currents in the semiconductor temperature measuring device, or plasma or charges accumulating on the surface of the device can generate currents, causing electrical interference to the temperature measuring components within the device, potentially even damaging some devices, or generating interference noise that reduces signal transmission stability. Therefore, embodiments of this disclosure may incorporate a capacitor structure within the semiconductor temperature measuring device to accommodate charges or absorb spike currents, reducing spike current interference; or conductive pillars may be incorporated within the device to transmit spike currents, further reducing interference. In the accompanying drawings of this disclosure, the first direction can be the thickness direction of the wafer or a vertical direction. The x and y directions can be horizontal, intersecting or perpendicular. The z direction intersects or is perpendicular to the plane formed by the x and y directions, such as the xoy plane. The x and y directions can also be denoted as a second or third direction, which will not be elaborated further below.

[0025] According to some aspects of embodiments of this disclosure, Figures 1 to 3 A semiconductor temperature measuring device 10 is provided, comprising:

[0026] like Figure 1 The first wafer 101 and the second wafer 102 are stacked as shown; the stacking direction can be the z-direction; the temperature measuring component 110 is at least partially located between the first wafer 101 and the second wafer 102;

[0027] like Figure 2 As shown, the temperature sensing component 110 includes a temperature sensing device 111, a power supply 113, and a main controller 114 coupled through an interconnect circuit 112; at least a portion of the interconnect circuit 112 is located between the first wafer 101 and the second wafer 102; the interconnect circuit 112 may include a single layer or multiple layers of wiring layers, and each wiring layer may include multiple interconnect lines; the interconnect lines of adjacent wiring layers may extend in the same direction, intersect, or be perpendicular; the interconnect circuit 112 or the interconnect lines may include a strip interconnect circuit (first interconnect circuit 1121) and a ring interconnect circuit 1122; the interconnect circuit 112 may be carried on a circuit board (PCB) or a flexible circuit board (flexible PCB);

[0028] Figure 3The plurality of conductive pillars 106 shown are at least partially located between the first wafer 101 and the second wafer 102, and are coupled to both the first wafer 101 and the second wafer 102; the plurality of conductive pillars 106 are located between the outer edge of the temperature sensing component 110 and the side edge of the first wafer 101; the plurality of conductive pillars 106 are located at the edges of the first wafer 101 and the second wafer 102. A schematic diagram of the distribution of the plurality of conductive pillars 106 relative to the first wafer 101 or the second wafer 102 in the xoy plane is shown below. Figure 4 The example provided.

[0029] Reference Figure 1 As shown, the semiconductor temperature measuring device may include a first wafer 101, a temperature measuring component 110, and a second wafer 102 arranged sequentially in the z-direction. The first wafer 101 and the second wafer 102 serve as carriers or cover plates for the temperature measuring component 110, providing protection for the component and simulating the temperature distribution of the product wafer. The first wafer 101 and the second wafer 102 are aligned or substantially aligned in the z-direction. The temperature measuring component 110 is adapted to fit the shape of the first wafer 101 and the second wafer 102 and is positioned between them. The temperature measuring component 110 includes multiple temperature measuring devices 111 distributed in different areas of the first wafer 101 and the second wafer 102 to obtain temperature values ​​in different areas. The temperature measuring devices 111 may include various temperature sensors, which collect temperature signals and convert them into electrical signals for output. The first wafer 101 can serve as the bottom wafer of the semiconductor temperature measuring device, used to contact wafer fixing devices such as wafer carrier trays. The temperature measuring component 110 is supported on the first wafer 101, and the second wafer 102 serves as a cover layer to protect the temperature measuring component 110. Alternatively, the positions of the first wafer 101 and the second wafer 102 can be interchanged.

[0030] Reference Figure 2 The diagram shows the layout of the temperature sensing component 110 on the xoy plane. The temperature sensing component 110 may include at least: a temperature sensing device 111, a power supply 113, a main controller 114, and interconnecting circuits 112 or interconnecting lines coupling the various parts. The interconnecting circuits 112 may be mounted on a circuit board (PCB) or a flexible circuit board (flexible PCB). Flexible circuit boards facilitate flexible layout of leads and components, adapting to various installation spaces. The main controller 114 may include various computing units or processors, including but not limited to: a microcontroller unit (MCU). The temperature sensing component 110 may also include an ADC acquisition chip or an ADC analog-to-digital converter coupled to the temperature sensing device 111. The ADC acquisition chip converts the analog signal from the temperature sensing device 111 into a digital signal and transmits it to the main controller 114. Alternatively, the temperature sensing device 111 may be a digital sensor with analog-to-digital conversion function, which can directly convert analog signals into digital signals and transmit them to the main controller 114.

[0031] This disclosure does not limit the number of layers or wiring on the circuit board, but it may include at least a power supply circuit and a data transmission circuit. The temperature sensing component 110 may include multiple strip-shaped or arc-shaped interconnecting circuits 112 to achieve coupling between different devices, power supply in series or parallel, and communication interconnection in serial or parallel modes. Alternatively, the temperature sensing component 110 may be mounted on a circular PCB board and interconnected through the interconnecting circuits 112 on the PCB board.

[0032] In some embodiments, the first wafer 101 and the second wafer 102 can be stacked and fixed by bonding adhesive, hot-temperature adhesive, resin or other adhesive medium, or the first wafer 101 and the second wafer 102 can be stacked by thermo-press bonding. During testing, the internal temperature of the first wafer 101 and the second wafer 102 is measured by the temperature measuring device 111, and the obtained temperature data is uploaded by the main controller 114 to an external host or cloud, or stored in the memory device in the temperature measuring component 110. The power supply 113 can be a battery or a wired power supply connected to an external power source. The power supply 113 supplies power to the main controller 114 and the temperature measuring device 111.

[0033] The main controller 114 of the semiconductor temperature measuring device can be connected to an external host via a data cable for wired transmission, or the semiconductor temperature measuring device has a wireless transmission module that sends test data to an external host or cloud server via the antenna 115 of the wireless transmission module. In the semiconductor temperature measuring device using wireless transmission, the power supply 113 can be an energy storage device such as a battery; there are no restrictions on the type or quantity of the battery, and it can be a rechargeable lithium-ion battery or other types of batteries. Wireless transmission semiconductor temperature measuring devices can eliminate some of the contamination associated with wired temperature measurement and avoid the need for through-holes in the processing chamber, reducing manufacturing difficulty and providing better temperature measurement results.

[0034] In some embodiments, the temperature sensing component 110 may be located between the first wafer 101 and the second wafer 102, or at least one of the first wafer 101 and the second wafer 102 may have a recess, and components of the temperature sensing component 110 may be disposed in the recess, as described below. Figure 8 The example is a first groove 1081. For example, a groove can be formed in the first wafer 101, and the temperature measuring device 111, power supply 113, and main controller 114 of the temperature measuring component 110 are disposed in the groove of the first wafer 101. The interconnect circuit 112 of the temperature measuring component 110 can be disposed in the groove, or disposed on the surface of the first wafer 101 without being disposed in the groove; the second wafer 102 may not have a groove, and the second wafer 102 can be thinned and disposed on the temperature measuring component 110 to cover the temperature measuring component 110.

[0035] In some other embodiments, both the first wafer 101 and the second wafer 102 are provided with grooves. The grooves of the first wafer 101 and the second wafer 102 are aligned in the z-direction to form a cavity. The device of the temperature measuring component 110 is disposed in the cavity, which helps to reduce the thickness of the first wafer 101 and the second wafer 102 and improve the temperature measurement accuracy.

[0036] In some embodiments, refer to Figure 3 As shown, at least one conductive post 106 is disposed between the first wafer 101 and the second wafer 102. The conductive post 106 may be located at the edge of the first wafer 101 and the second wafer 102. The two ends of the conductive post 106 in the z-direction are coupled to the first wafer 101 and the second wafer 102, respectively. The conductive post 106 may be electrically connected to the first wafer 101 and the second wafer 102 through direct contact, or through contact with the conductive layer on the surface of the first wafer 101, and through contact with the conductive layer on the second wafer 102. The shape of the conductive post 106 is not limited; it may be cylindrical or spherical. The cross-sectional shape of the conductive post 106 in the xoy plane may be rectangular, circular, or elliptical, or an irregular arc, polygon, or other irregular shape.

[0037] In some embodiments, Figure 3 The conductive post 106 can extend into or penetrate the first wafer 101 in the z-direction; the conductive post 106 can also extend into or penetrate the second wafer 102 in the z-direction. In some embodiments, the first surface of the first wafer 101 is coupled to the bottom of the conductive post 106, and the second surface of the second wafer 102 is coupled to the top of the conductive post 106; ion implantation can be performed on the landing site of the conductive post 106 on the first surface of the first wafer 101 to form a first doped region coupled to the conductive post 106, reducing the contact resistance between the first wafer 101 and the conductive post 106; ion implantation can be performed on the landing site of the conductive post 106 on the second surface of the second wafer 102 to form a second doped region coupled to the conductive post 106, reducing the contact resistance between the second wafer 102 and the conductive post 106. The first surface is the surface of the first wafer 101 in the positive z-direction, and the second surface is the surface of the second wafer 102 in the negative z-direction.

[0038] In some embodiments, Figure 3 The conductive pillar 106 is located at or near the edges of the first wafer 101 and the second wafer 102. The conductive pillar 106 can be located as close as possible to the sides of the first wafer 101 and the second wafer 102, or on the sides of the first wafer 101 and the second wafer 102, provided that the manufacturing process allows. For example... Figure 2As exemplified, the temperature sensing assembly 110 may include multiple devices and interconnect circuitry 112, such as a main controller 114, a power supply 113, and a voltage regulator (described later) disposed on the first wafer 101. Figure 9 The voltage regulator 116 shown in the figure and multiple temperature measuring devices 111 are shown in the figure. The outer edge of the temperature measuring component 110 is the device closest to the wafer side on the xoy plane. It can be multiple devices, and it can be the outer edge of the outermost device. Figure 2 As illustrated, to facilitate temperature measurement of different regions of the wafer, multiple temperature measuring devices 111 are arranged at intervals along the circumferential direction surrounding the center of the first wafer 101. Multiple rings of temperature measuring devices 111 are arranged sequentially from the inside to the outside of the first wafer 101 in the radial direction. The outer edge of the temperature measuring assembly 110 is the outermost ring of temperature measuring devices 111, and the conductive post 106 is located outside the outermost ring of temperature measuring devices 111, that is, the conductive post 106 is located outside all the devices in the temperature measuring assembly 110.

[0039] In some other embodiments, the extension of the temperature measuring device 111 may be provided with other devices, such as the main controller 114 or the voltage regulator 116, and is not limited to the temperature measuring device 111.

[0040] In this embodiment, the conductive post 106 is located between the epitaxial layer of the temperature sensing component 110 and the side edge of the first wafer 101. This allows the conductive post 106 to be positioned outside all devices in the temperature sensing component 110, enabling peak currents, accumulated charges, or plasma from the first wafer 101 and the second wafer 102 to flow from the outside of the temperature sensing component 110, or from the edge of the wafer, without being conducted through the interior of the temperature sensing component 110. This reduces interference and damage to the individual devices in the temperature sensing component 110. This also avoids the problem of excessive current concentration in the temperature sensing component 110 area leading to overload of active devices. Conductors in a radio frequency environment exhibit a significant skin effect, where current tends to conduct outside the transmission line. The proximity of the conductive post 106 to the wafer side allows more current to flow through the conductive post 106, rather than being conducted through the internal temperature sensing component 110.

[0041] In some embodiments, a plurality of conductive posts 106 are spaced apart along the circumferential direction of the first wafer 101. In some embodiments, the plurality of conductive posts 106 surround the outer edge of the temperature sensing component 110, and the conductive posts 106 are located on the side of the outer edge of the temperature sensing component 110 away from the center of the first wafer 101.

[0042] Reference Figure 4As shown, multiple conductive pillars 106 are distributed at intervals on the inner side of the first wafer 101 and the second wafer 102, and along the circumferential direction of the side of the first wafer 101. The multiple conductive pillars 106 can form a circle, an ellipse, or other irregular polygons or arcs when connected. The multiple conductive pillars 106 can surround the outer edge of the temperature sensing component 110, or the outermost part of the temperature sensing component 110, or in other words, the multiple conductive pillars 106 can surround all the components of the temperature sensing component 110.

[0043] For example, refer to Figure 3 As shown, the spike current can be transmitted through the second wafer 102, the conductive pillar 106, and the first wafer 101 to the ground terminal of the wafer carrier disk 200, or transmitted to the capacitor structure 105 to be absorbed.

[0044] In some embodiments, Figure 4 and Figure 9 As shown, the temperature sensing component 110 further includes: an antenna 115 coupled to the main control unit 114; the antenna 115 is located at the center of the first wafer 101 and the second wafer 102; a plurality of temperature sensing devices 111 arranged in a circumferential direction around the antenna 115; and an interconnect circuit 112 including a plurality of first interconnect circuits 1121 coupled to the temperature sensing devices 111, the first interconnect circuits 1121 being spaced apart in a circumferential direction around the antenna 115. The first interconnect circuits 1121 may extend radially along the first wafer 101.

[0045] The temperature sensing component 110 also includes a wireless transmission module coupled to the main controller 114, which may include, but is not limited to, a Bluetooth module, a Wi-Fi module, etc. The wireless transmission module may include an antenna 115 to transmit wireless signals. The antenna 115 is a ring coil located at the center of the first wafer 101 and the second wafer 102, and may include multiple nested coils, such as, but not limited to, RF coils. Multiple temperature sensing devices 111 may also be disposed within the internal area of ​​the antenna 115. In some other examples, the antenna 115 may be located near the center of the first wafer 101 and the second wafer 102, including a horizontally positioned antenna 115.

[0046] Reference Figure 1 and Figure 4As shown, the interconnect circuit 112 has multiple components, including a ring-shaped or near-ring-shaped portion, such as a ring-shaped interconnect circuit 1122, and multiple first interconnect circuits 1121 with strip-shaped portions, such as those spaced apart along the circumferential direction of the outer periphery of the antenna 115. The first interconnect circuits 1121 extend radially along the first wafer 101 and connect to multiple temperature sensing devices 111. The temperature sensing devices 111 are arranged along the extension direction of the first interconnect circuits 1121 and coupled to them. The included angles between any two adjacent first interconnect circuits 1121 can be equal or substantially equal, allowing the temperature sensing devices 111 to be distributed more uniformly in different areas within the wafer, enabling temperature detection in different areas of the wafer.

[0047] In some embodiments, multiple temperature measuring devices 111 are arranged in a circular pattern around the antenna 115, which can be multiple rings of temperature measuring devices 111 arranged sequentially from the inside to the outside with the antenna 115 as the center.

[0048] In some embodiments, the first temperature measuring device 111a among the plurality of temperature measuring devices 111 is located at the outer edge of the temperature measuring assembly 110; the conductive post 106 is located on the side of the first temperature measuring device 111a away from the antenna 115.

[0049] Reference Figure 4 As shown, multiple temperature sensing devices 111 are arranged at intervals around the center of the first wafer 101 or around the antenna 115 at the center of the first wafer 101, forming multiple layers or rings of temperature sensing devices 111. The first temperature sensing device 111a can be any one of the multiple temperature sensing devices 111 in the outermost ring. The conductive post 106 is located on the side of the first temperature sensing device 111a away from the antenna 115 in the x or y direction. The conductive post 106 is located outside the outermost first temperature sensing device 111a, and all temperature sensing devices 111 are located between the conductive post 106 and the antenna 115. Alternatively, multiple conductive posts 106 are arranged around the outermost first temperature sensing device 111a, spaced apart along the circumferential direction outside the outermost temperature sensing devices 111.

[0050] In some embodiments, refer to Figure 4 As shown, the conductive post 106 is located between adjacent first interconnect circuits 1121.

[0051] For example, Figure 4 As shown, multiple first interconnect circuits 1121 divide the first wafer 101 into multiple temperature measurement zones. One or more conductive pillars 106 are located between adjacent first interconnect circuits 1121. All conductive pillars 106 are uniformly distributed along the edge of the first wafer 101, and the spacing between adjacent conductive pillars 106 is equal or substantially equal. For example, a spike current can be transferred through the second wafer 102, the second conductive layer 104, the conductive pillars 106, the first conductive layer 103, and the first wafer 101 to... Figure 3The ground terminal of the wafer carrier disk 200, or the signal transmitted to the capacitor structure 105, is absorbed.

[0052] In some specific embodiments, 65 temperature sensing devices 111 can be disposed on the first wafer 101. The 65 temperature sensors are evenly distributed in 16 directions, with each interval having an included angle of 22.5°, thus uniformly distributing the wafer into 16 sector-shaped temperature sensing areas. The sector-shaped temperature sensing areas are divided by first interconnect circuits 1121 extending radially along the first wafer 101 and arranged at intervals. Conductive pillars 106 can be disposed within the sector-shaped temperature sensing areas, that is, between pairs of adjacent first interconnect circuits 1121. The number of conductive pillars 106 is 16 or a multiple thereof, and one or more conductive pillars 106 can be disposed in one temperature sensing area. All conductive pillars 106 can be evenly distributed in each temperature sensing area.

[0053] The conductive post 106 is placed as close as possible to the side of the first wafer 101, provided that installation permits. Taking a 12-inch wafer as an example, the wafer diameter is 300mm to 305mm. The outermost temperature sensing device 111 is located 147mm away from the center of the first wafer 101, and the conductive post 106 is located between 147mm and 150mm away from the center of the first wafer 101.

[0054] In some embodiments, the conductive post 106 is located near the sides of the first wafer 101 and the second wafer 102, on the outermost side of the temperature sensing component 110, between adjacent first interconnect circuits 1121, or between extensions of adjacent first interconnect circuits 1121. Figure 9 As shown, the maximum size of the temperature sensing component 110 in the xoy plane is smaller than that of the first wafer 101, meaning the outermost extension of the temperature sensing component 110 is still inside the side edge of the first wafer 101, and the first interconnect circuit 1121 has not yet extended to the side edge of the first wafer 101. In this case, the outermost conductive post 106 of the temperature sensing component 110 can be located between the extension lines of adjacent first interconnect circuits 1121. For example... Figure 4 and Figure 10 As shown, the first interconnect circuit 1121 may extend radially beyond the outermost temperature sensing device 111 along the first wafer 101 to facilitate leading, and the conductive post 106 may be located between adjacent first interconnect circuits 1121 but outside the outermost temperature sensing device 111.

[0055] In some embodiments, refer to Figure 5As shown, the first wafer 101 and the second wafer 102 are stacked along the z-direction. The semiconductor temperature measuring device further includes: a first conductive layer 103 located on a first surface of the first wafer 101, a second conductive layer 104 located on a second surface of the second wafer 102, and a conductive pillar 106 located between the first conductive layer 103 and the second conductive layer 104. The conductive pillar 106 is coupled to both the first conductive layer 103 and the second conductive layer 104. The first surface is the surface of the first wafer 101 in the positive z-direction, and the second surface is the surface of the second wafer 102 in the negative z-direction.

[0056] The first conductive layer 103 may extend and lie flat on the first surface of the first wafer 101, at least covering a portion of the first surface of the first wafer 101; the second conductive layer 104 may extend and lie flat on the second surface of the second wafer 102, at least covering a portion of the second surface of the second wafer 102. The materials of the first conductive layer 103 and the second conductive layer 104 may be the same or different; the constituent materials of the first conductive layer 103 and the second conductive layer 104 may include conductive materials with high magnetic permeability, and may be a single-layer structure or a multi-layer structure, including but not limited to: conductive materials such as silver, copper, aluminum, tungsten, gold, silver, platinum, nickel, titanium, tin, etc., or easily curable materials including the above-mentioned conductive metal materials, such as organosilicon, polymers, etc., which include conductive metal materials.

[0057] In some embodiments, the first conductive layer 103 can be formed by curing a conductive paste. The conductive paste may include metal microspheres, metal powder, or other microstructured conductive materials and easily curable substrates; it may include, but is not limited to, powders such as gold, silver, copper, and aluminum, and may also include non-metallic microstructured materials such as graphite powder or carbon nanotubes; for example, the conductive paste may be conductive gold paste, conductive silver paste, or conductive copper paste. By selecting the particle size and solid content of the conductive silver paste, a high-density first conductive layer 103 can be formed, which has good conductivity. In some embodiments, a conductive paste is uniformly coated on the first surface of the first wafer 101. The particle size of the conductive material (such as metal powder) in the conductive paste may be less than 0.3 micrometers, and the solid content may be greater than >80%, which allows the first conductive layer 103 to form a complete shielding layer with a thickness of micrometers. While shielding some external electromagnetic noise interference, it can also form a good conductive circuit with the conductive pillar 106, absorb peak current, and reduce the interference and damage of peak current. The first conductive layer 103, the second conductive layer 104, and the conductive pillar 106 are connected to form a Faraday cage or a Faraday cage-like structure, thereby reducing electromagnetic interference.

[0058] In some embodiments, taking the first conductive layer 103 as an example, the first conductive layer 103 may also be a metal material layer formed by processes such as physical and chemical deposition, sputtering, and electroplating.

[0059] In some embodiments, the semiconductor temperature sensing device further includes: a conductive ring located between the first wafer 101 and the second wafer 102; the conductive ring surrounds the outer edge of the temperature sensing component 110, and is coupled to the first conductive layer 103 and the second conductive layer 104. The position of the conductive ring may be relative to... Figure 4 The position of the intermediate conductive pillar 106 is the same, and it is about to be Figure 4 The conductive post 106 is replaced with a conductive ring, which can be a wire mesh structure or a wall structure. Alternatively, in... Figure 4 A conductive ring is provided around the conductive post 106. The conductive ring is connected to the first conductive layer 103 and the second conductive layer 104 to form a shielding structure, such as a Faraday cage or a Faraday cage-like structure, to reduce electromagnetic interference.

[0060] In some embodiments, refer to Figure 5 As shown, the semiconductor temperature measuring device further includes: a capacitor structure 105, at least partially located between the first conductive layer 103 and the second conductive layer 104; the capacitor structure 105 includes Figure 6 The example includes a first electrode 1051, a second electrode 1052, and a dielectric layer 1055, with the dielectric layer 1055 located between the first electrode 1051 and the second electrode 1052; the first electrode 1051 is coupled to the first conductive layer 103, and the second electrode 1052 is coupled to the second conductive layer 104.

[0061] A capacitor structure 105 is provided between the first wafer 101 and the second wafer 102. The capacitor structure 105 may be part of the temperature sensing component 110 or not. The capacitor structure 105 may be located near electrical appliances such as the temperature sensing device 111, power supply 113, main controller 114, voltage regulator 116, and wireless transmission module. It may be arranged symmetrically or asymmetrically, specifically in or around the circumference of the electrical appliance, such as near the contacts or pins connecting the electrical appliance and the interconnection circuit 112, to reduce the interference of peak current on the electrical appliance.

[0062] The capacitor structure 105 may include a first electrode 1051, a second electrode 1052, and a dielectric layer 1055 located between the first electrode 1051 and the second electrode 1052. The capacitor structure 105 may include, but is not limited to, a parallel plate capacitor, a cylindrical capacitor, or other physical structures. The first electrode 1051 of the capacitor structure 105 is coupled to a first surface of a first wafer 101, or to a first conductive layer 103 on the first surface; the second electrode 1052 of the capacitor structure 105 is coupled to a second surface of a second wafer 102, or to a second conductive layer 104 on the second surface. The first surface and the second surface are arranged face-to-face in the z-direction. The first electrode 1051 of the capacitor structure 105 is provided with contact points, pins, or other connection structures to couple with the first wafer 101, and the second electrode 1052 of the capacitor structure 105 is provided with contact points, pins, or other connection structures to couple with the second wafer 102. The coupling may be a direct contact electrical connection or an electrical connection through other conductive structures.

[0063] When using a semiconductor temperature measuring device for temperature testing, if the first wafer 101 or the second wafer 102 experiences a peak current, the peak current of the first wafer 101 or the second wafer 102 charges the capacitor. The peak current is absorbed by the capacitor, reducing interference to the temperature measuring component 110. For example... Figure 3 As shown, when the first wafer 101 contacts the wafer carrier disk 200, the second wafer 102 is exposed to the process cavity. When plasma is generated, a spike current is generated or plasma is concentrated on the second wafer 102. The spike current flows from the second wafer 102 to the first wafer 101 and is absorbed by the capacitor structure 105, reducing the interference and damage of the spike current to the semiconductor temperature measuring device and the wafer carrier disk 200.

[0064] In some embodiments, the capacitor structure 105 may include a first electrode 1051, a second electrode 1052, and a dielectric layer 1055 that electrically isolates the two electrodes; the capacitor structure 105 may also include Figure 6 The capacitor with multilayer electrodes shown, such as a multilayer ceramic capacitor, may have a ceramic dielectric material as the dielectric layer 1055; this achieves miniaturization of the capacitor structure 105 while increasing the voltage or current carrying capacity of the capacitor structure 105.

[0065] In some embodiments, refer to Figure 6As shown, the capacitor structure 105 includes a plurality of alternately arranged first electrodes 1051 and second electrodes 1052; a first connection structure 1053 coupled to the plurality of first electrodes 1051; and a second connection structure 1054 coupled to the plurality of second electrodes 1052. The first connection structure 1053 is coupled to a first conductive layer 103, and the second connection structure 1054 is coupled to a second conductive layer 104. The first electrodes 1051 and second electrodes 1052 can be internal electrodes, and the first connection structure 1053 and second connection structure 1054 can serve as external electrodes for connecting to external structures.

[0066] like Figure 6 As illustrated, the first electrode 1051 and the second electrode 1052 can be rectangular, circular, or elliptical, or irregularly polygonal or arc-shaped. The first electrode 1051 and the second electrode 1052 can be, for example... Figure 6 As shown, extending along the xoy plane, the first electrode 1051 and the second electrode 1052 partially overlap in the z-direction. The first electrode 1051 and the second electrode 1052 are offset from each other in the electrode extension direction, as shown in... Figure 6 The first electrode 1051 and the second electrode 1052 are misaligned in the z-direction on the first side (left side) of the first electrode 1051 in the x-direction; or, in other words, the dimensions of the first electrode 1051 and the second electrode 1052 are equal or substantially equal in the x-direction, with only partial overlap. A first connecting structure 1053 is located on one side of the electrode extension direction of the first electrode 1051 and is coupled to a plurality of spaced-apart first electrodes 1051. A second connecting structure 1054 is located on one side of the electrode extension direction of the second electrode 1052 and is coupled to a plurality of spaced-apart second electrodes 1052. The first connecting structure 1053 and the second connecting structure 1054 are arranged opposite each other in the extension direction of the first electrode 1051 and are electrically isolated.

[0067] In some embodiments, refer to Figure 6As shown, the first electrode 1051 has a first end and a second end disposed opposite to each other in the electrode extension direction. The first end of the first electrode 1051 is coupled to the first connecting structure 1053, and the second end is floating or not connected to electricity. The second electrode 1052 also has a first end and a second end disposed opposite to each other in the electrode extension direction. The first end of the first electrode 1051 is coupled to the second connecting structure 1054, and the second end is floating or not connected to electricity. The first end of the first electrode 1051 and the second end of the second electrode 1052 are not aligned in the perpendicular electrode direction (z-direction), and the second end of the second electrode 1052 is away from the first connecting structure 1053. The first end of the second electrode 1052 and the second end of the first electrode 1051 are not aligned in the z-direction, and the second end of the first electrode 1051 is away from the second connecting structure 1054.

[0068] The first connection structure 1053 is coupled to the first conductive layer 103 on the first wafer 101, and the second connection structure 1054 is coupled to the second conductive layer 104 on the second wafer 102, thereby realizing the coupling and conduction of the capacitor structure 105 with the first wafer 101 and the second wafer 102. This disclosure embodiment does not limit the connection method of the first connection structure 1053 and the second connection structure 1054; for example, the first wafer 101 can be... Figure 6 Below the capacitor structure 105, the second wafer 102 can... Figure 6 Above the capacitor structure 105, the bottom of the first connection structure 1053 is in contact with the first conductive layer 103, and the top of the first connection structure 1053 is electrically isolated from the second conductive layer 104 without contact; the top of the second connection structure 1054 is in contact with the second conductive layer 104, and the bottom of the second connection structure 1054 is electrically isolated from the first conductive layer 103 without contact.

[0069] In some embodiments, a conductive layer may be provided on either the first wafer 101 or the second wafer 102, or a conductive layer may be provided on both wafers. (Refer to...) Figure 7 As shown, it can be Figure 6 The capacitor structure 105 shown is rotated and positioned between the first conductive layer 103 and the second conductive layer 104.

[0070] like Figure 8 As exemplified, a first conductive layer 103 is disposed on the surface of the first wafer 101, extending to the inner wall of the first groove 1081, and a capacitor structure 105 is coupled to the first conductive layer 103 and the second wafer 102. In other examples, referring to the arrangement of the first conductive layer 103 in the first groove 1081, a second conductive layer 104 is disposed on the surface of the second wafer 102, extending to the inner wall of the second groove 1082, and a capacitor structure 105 is coupled to the second conductive layer 104 and the first wafer 101.

[0071] In some embodiments, it may be possible Figure 8 A second conductive layer 104 is further disposed on the surface of the second wafer 102, and the capacitor structure 105 is coupled to the two conductive layers. The first wafer 101, the first conductive layer 103, the first connection structure 1053, the second connection structure 1054, the second conductive layer 104, and the second wafer 102 are stacked in the z direction. The first connection structure 1053 is in contact with the first conductive layer 103, and the second connection structure 1054 is in contact with the second conductive layer 104. This reduces the lead distance of the capacitor structure 105, which is beneficial for reducing the thickness of the semiconductor temperature measuring device.

[0072] In some embodiments, refer to Figure 8 As shown, at least one of the first wafer 101 and the second wafer 102 has a groove for accommodating at least a portion of the temperature sensing component 110; a first conductive layer 103 extends into the inner wall of the groove; a capacitor structure 105 is located in its corresponding groove, and a first electrode 1051 is coupled to the first conductive layer 103 on the inner wall of the groove. In some embodiments, reference is made to... Figure 8 As shown, grooves are provided in both the first wafer 101 and the second wafer 102, and the depth of the grooves is less than the device thickness of the temperature sensing component 110. The grooves of the first wafer 101 and the second wafer 102 are aligned. A portion of the temperature sensing component 110 is located in the groove of the first wafer 101, and another portion is located in the groove of the second wafer 102, thereby reducing the thickness of the first wafer 101 and the second wafer 102. At this time, a portion of the temperature sensing component 110 is located within the wafer. For example, taking the temperature sensing device 111 as an example, the bottom of the temperature sensing device 111 is located in the first groove 1081 of the first wafer 101, and the upper part of the temperature sensing device 111 is located in the second groove 1082 of the second wafer 102. The first groove 1081 and the second groove 1082 are aligned in the z-direction. A portion of the interconnect circuit 112 connecting the temperature sensing device 111 is disposed within the first recess 1081, specifically extending along the sidewall and bottom of the first recess 1081. The contacts at the bottom of the temperature sensing device 111 are coupled to the interconnect circuit 112 at the bottom of the first recess 1081. This portion of the interconnect circuit 112 extends from the bottom of the first recess 1081 along the sidewall and is coupled to other devices within the first recess 1081, such as the main controller 114, the power supply 113, or the voltage regulator 116. The first wafer 101 and the second wafer 102 may have corresponding recesses to accommodate the interconnect circuit 112, or some portions of the interconnect circuit 112 may be disposed on the surface of the first wafer 101, with another portion located within the first recess 1081 of the first wafer 101 to couple to the corresponding devices.

[0073] In some embodiments, Figure 8As shown, the capacitor structure 105 can be disposed in the cavity formed by the first groove 1081 and the second groove 1082. The first connection structure 1053 of the capacitor structure 105 can be directly coupled to the first wafer 101, or a contact can be provided on the first connection structure 1053 to be coupled to the first wafer 101. The second connection structure 1054 can be directly coupled to the second wafer 102, or a contact can be provided on the second connection structure 1054 to be coupled to the second wafer 102.

[0074] Taking the first wafer 101 as an example, a first groove 1081 can be formed in the first wafer 101. A first conductive layer 103 extends on the first surface of the first wafer 101 and extends to the sidewalls and bottom of the first groove 1081 below the first surface. A capacitor structure 105 is disposed in the first groove 1081. A first electrode 1051 or a first connection structure 1053 is coupled to the first conductive layer 103 at the bottom of the first groove 1081. The second wafer 102 may not have a groove. A second conductive layer 104 extends on the second surface of the second wafer 102. After the second wafer 102 is thinned, it covers the temperature sensing component 110. The second conductive layer 104 is coupled to the second electrode 1052 or the second connection structure 1054.

[0075] like Figure 8 As shown, the second wafer 102 may be provided with a second groove 1082, the second conductive layer 104 extends on the second surface of the second wafer 102 and extends on the sidewall and bottom of the second groove 1082, the capacitor structure 105 is disposed in the cavity formed by aligning the first groove 1081 and the second groove 1082, and the second electrode 1052 or the second connection structure 1054 is coupled to the second conductive layer 104 at the bottom of the second groove 1082.

[0076] In some embodiments, the first conductive layer 103 extends into the inner wall of the first groove 1081, and the second conductive layer 104 extends into the inner wall of the second groove 1082. The temperature sensing device 111 or main control device 114 of the temperature sensing assembly 110 may be located within the first groove 1081. The interconnect circuit 112 or a circuit board including the interconnect circuit 112 is located on the first conductive layer 103 within the first groove 1081. The contacts of the temperature sensing device 111 or main control device 114 are coupled to the interconnect circuit 112, and a fixed connection between the contacts or pins and the interconnect circuit 112 can be achieved by soldering. The circuit board carrying the interconnect circuit 112 may be a flexible circuit board with a strip, arc, or other irregular shape adapted to the wafer groove and lead layout; the shape of the circuit board is not limited. An insulating material may be provided between the interconnect circuit 112 and the first conductive layer 103 for isolation.

[0077] In some embodiments, refer to Figure 8As shown, the semiconductor temperature measuring device also includes an adhesive layer 107 located between the first wafer 101 and the second wafer 102 for bonding and fixing the first wafer 101 and the second wafer 102. The adhesive layer 107 can be a bonding adhesive, a hot-dip mordant, resin, or other adhesive medium. The adhesive layer 107 may include a curable dielectric material, such as resin. The adhesive layer 107 can fill the first groove 1081 of the first wafer 101 and the second groove 1082 of the second wafer 102. After the two wafers are aligned and contacted, they are cured. The temperature measuring component 110 is wrapped and fixed in the corresponding groove by the adhesive layer 107 or adhesive material. The first conductive layer 103 and the second conductive layer 104 are separated by the intermediate adhesive layer 107.

[0078] In some embodiments, a groove can be formed in either the first wafer 101 or the second wafer 102. The depth of the groove can be greater than or equal to the thickness of the corresponding temperature sensing component 110. The other wafer can be thinned to serve as a cover layer and may not have a groove formed. For example, a first groove 1081 can be formed in the first wafer 101 to accommodate the temperature sensing component 110, and the second wafer 102 can be thinned to serve as a cover layer to cover the temperature sensing component 110 and the first wafer 101.

[0079] In some embodiments, refer to Figure 9 As shown, the temperature sensing component 110 further includes: a voltage regulator 116 coupled to the interconnection circuit 112; capacitor structures 105 symmetrically distributed on the outside of the electrical appliance of the temperature sensing component 110; and / or, the capacitor structures 105 are arranged at intervals around the circumferential direction of the electrical appliance; wherein the electrical appliance of the temperature sensing component 110 includes at least one of the following: a temperature sensing device 111, a power supply 113, a main controller 114, and a voltage regulator 116.

[0080] The input terminal of the voltage regulator 116 is coupled to the power supply 113, and the output terminal of the voltage regulator 116 is coupled to the main controller 114, the temperature measuring device 111, the wireless transmission module and other electrical appliances for power supply. Multiple voltage regulators 116 may be used to supply power to different branches in parallel. The voltage regulator 116 is connected to the power supply 113 and outputs a relatively stable power supply.

[0081] In some embodiments, a voltage regulator 116 supplies power to multiple temperature sensing devices 111, which can constitute a temperature sensing circuit 119 or at least a portion of a temperature sensing circuit 119; the multiple temperature sensing devices 111 can be divided into multiple temperature sensing circuits 119, and each circuit can be powered by a separate voltage regulator 116 to improve power supply stability. For example, the multiple temperature sensing devices 111 can be powered by... Figure 9 The dashed line divides the area into multiple sector-shaped regions, each equipped with a voltage regulator 116 to power multiple temperature measuring devices 111 within the sector-shaped region. Figure 9The division of the power supply area for the temperature sensing device 111, as well as the setting and number of voltage regulators 116, are merely examples and do not limit other division methods or the number and arrangement of voltage regulators 116. For example, voltage regulators 116a, 116b, 116c, and 116d supply power to the temperature sensing devices 111 in four sector areas, respectively; voltage regulator 116e supplies power to the main controller 114. A voltage regulator, such as voltage regulator 116b, supplying power to multiple temperature sensing devices 111 can constitute a temperature sensing circuit 119 or at least a part of a temperature sensing circuit 119. The multiple temperature sensing devices 111 belonging to a temperature sensing circuit 119 can... Figure 9 The fan-shaped region distribution is shown.

[0082] Reference Figure 9 As shown, the interconnect circuit 112 of the temperature sensing circuit 119 may include a plurality of first interconnect circuits 1121 spaced apart in the circumferential direction along the outer periphery of the antenna 115, the plurality of first interconnect circuits 1121 being radially spaced along the first wafer 101, and including a plurality of branches such as second interconnect circuits 1123 on the first interconnect circuits 1121, the second interconnect circuits 1123 intersecting or perpendicular to the first interconnect circuits 1121; the plurality of second interconnect circuits 1123 located on the same first interconnect circuit 1121 have different lengths, and from the center of the first wafer 101 outwards, the size of the second interconnect circuits 1123 gradually increases to meet the electrical interconnection requirements of the temperature sensing device 111 being uniformly distributed radially. The interconnect circuit 112 may include a power supply circuit and a data transmission circuit.

[0083] The electrical appliance in this embodiment can be any device other than the interconnecting circuit 112. The voltage regulator 116 can include, but is not limited to, a low dropout regulator (LDO). The input terminal of the voltage regulator 116 is coupled to the output terminal of the power supply 113, and the output terminal of the voltage regulator 116 is coupled to electrical appliances such as the main controller 114 and the temperature measuring device 111. The voltage regulator 116 can filter noise from the power supply 113, regulate the voltage output, and provide a stable power supply voltage.

[0084] The arrangement and quantity of capacitor structure 105 can be set according to the interference tolerance and withstand level of the electrical appliance. Capacitor structure 105 needs to be placed near appliances with high power supply stability. Taking the main controller 114 as an example, the main controller 114 operates by default in a circuit environment with a stable voltage supply. Its input voltage window is narrow. If a surge current causes a spike, it may cause the entire semiconductor temperature measuring device to shut down, or even cause irreversible damage to the main controller 114. Surge currents on the voltage regulator 116 (or the voltage regulator chip 113) may cause breakdown of the electrical appliance, resulting in irreversible damage. Figure 9As shown, a capacitor structure 105 can be set near the pins or contacts of electrical appliances such as the main controller 114 and the voltage regulator 116.

[0085] In some embodiments, refer to Figure 10 As shown, capacitor structures 105 can be symmetrically arranged near the pins or contacts of electrical appliances such as the main controller 114 and voltage regulator 116. There can be two, three, four, or more capacitor structures 105. Multiple capacitor structures 105 can be arranged at intervals around the circumference of the electrical appliance, and can be symmetrically or asymmetrically distributed, such as four capacitor structures 105. The four capacitor structures 105 form a rectangle or other quadrilateral to enhance the absorption of peak currents and improve the anti-interference performance of the electrical appliance.

[0086] According to some aspects of embodiments of this disclosure, a method for manufacturing a semiconductor temperature measuring device is provided.

[0087] A first wafer 101 is provided, and a plurality of first grooves 1081 are formed on a first surface of the first wafer 101;

[0088] A first conductive layer 103 is formed on the first surface of the first wafer 101, and the first conductive layer 103 extends into the sidewall and bottom of the first groove 1081;

[0089] Align the temperature measuring component 110 with the first groove 1081, and place each component of the temperature measuring component 110 in the corresponding first groove 1081; and set a capacitor structure 105 in at least one first groove 1081.

[0090] Multiple conductive pillars 106 are formed on the outermost first conductive layer 103 of the temperature sensing component 110; or, conductive pillars 106 are formed between the device closest to the side of the first wafer 101 in the temperature sensing component 110 and the side of the first wafer 101, and the conductive pillars 106 may be formed on the side of the first wafer 101.

[0091] An adhesive layer 107 is formed on the first surface of the first wafer 101, and the adhesive layer 107 can fill the first groove 1081; the adhesive layer 107 exposes the conductive pillar 106;

[0092] A second wafer 102 is provided, and a plurality of second grooves 1082 are formed on the second surface of the second wafer 102 corresponding to the distribution position of the first grooves 1081 on the first wafer 101.

[0093] A second conductive layer 104 is formed on the second surface of the second wafer 102, and the second conductive layer 104 extends into the sidewalls and bottom of the second groove 1082;

[0094] Align the second wafer 102 with the first wafer 101, combine the second wafer 102 with the first wafer 101, and align the second groove 1082 with the first groove 1081.

[0095] In some embodiments, the methods for forming the first groove 1081 and the second groove 1082 may include, but are not limited to, dry etching, wet etching, or a combination thereof. Taking the fabrication method of the first conductive layer 103 as an example, a conductive paste is uniformly coated on the surface of the first wafer 101 having the first groove 1081, and the first conductive layer 103 is formed after the conductive paste is cured. Alternatively, the first conductive layer 103 can be formed by physical or chemical deposition, sputtering, or electroplating on the surface of the first wafer 101 having the first groove 1081.

[0096] In some embodiments, the outermost device of the temperature sensing component 110 is a temperature sensing device 111. A conductive paste is coated between the outermost temperature sensing device 111 and the side of the first wafer 101. After the conductive paste is cured, a conductive pillar 106 is formed. The shape of the conductive pillar 106 is not limited; it can be cylindrical or spherical. The cross-sectional shape of the conductive pillar 106 in the xoy plane can be rectangular, circular, or elliptical, or an irregular arc, polygon, or other irregular shape.

[0097] In some embodiments, after the first conductive layer 103 is formed, an insulating material is formed on the inner wall of the first groove 1081 of each device corresponding to the temperature sensing component 110 or the interconnect circuit 112 coupled to each device of the temperature sensing component 110, so that the temperature sensing component 110 and the interconnect circuit 112 are electrically isolated from the first conductive layer 103. Alternatively, in some embodiments, the interconnect circuit 112 coupled to each device of the temperature sensing component 110 is carried on a flexible PCB board, and the back side of the flexible PCB is coated with an insulating film to electrically isolate the first conductive layer 103.

[0098] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A semiconductor temperature measuring device, characterized in that, include: The first and second wafers are stacked together; The temperature sensing component is at least partially located between the first wafer and the second wafer; The temperature measuring assembly includes a temperature measuring device, a power supply, and a main controller, which are coupled together via interconnecting circuits. A plurality of conductive pillars are located at least partially between the first wafer and the second wafer, and the plurality of conductive pillars are coupled to the first wafer and the second wafer; The plurality of conductive pillars are located between the outer edge of the temperature measuring component and the side edge of the first wafer; A first conductive layer is located on the first surface of the first wafer. The second conductive layer is located on the second surface of the second wafer; the conductive pillar is located between the first conductive layer and the second conductive layer; the conductive pillar is coupled to the first conductive layer and the second conductive layer; the conductive pillar is located outside all devices in the temperature sensing assembly, and the conductive pillar allows the plasma and peak current gathered on the first wafer or the second wafer to be conducted from the outside of the temperature sensing assembly.

2. The semiconductor temperature measuring device according to claim 1, characterized in that, The plurality of conductive pillars are spaced apart along the circumferential direction of the first wafer.

3. The semiconductor temperature measuring device according to claim 1, characterized in that, The plurality of conductive pillars surround the outer edge of the temperature measuring component.

4. The semiconductor temperature measuring device according to claim 1, characterized in that, The temperature measuring component also includes: An antenna, which is coupled to the main controller; the antenna is located at the center of the first wafer and the second wafer; Multiple temperature measuring devices are arranged in a circumferential direction around the antenna; The interconnect circuit includes a plurality of first interconnect circuits coupled to the temperature measuring device, the first interconnect circuits being spaced apart in a circumferential direction around the antenna.

5. The semiconductor temperature measuring device according to claim 4, characterized in that, The first temperature measuring device among the plurality of temperature measuring devices is located at the outer edge of the temperature measuring assembly; the conductive post is located on the side of the first temperature measuring device away from the antenna.

6. The semiconductor temperature measuring device according to claim 4, characterized in that, The conductive post is located between adjacent first interconnect circuits.

7. The semiconductor temperature measuring device according to claim 1, characterized in that, The semiconductor temperature measuring device also includes: A capacitor structure, at least partially located between the first conductive layer and the second conductive layer; the capacitor structure includes a first electrode, a second electrode, and a dielectric layer, the dielectric layer being located between the first electrode and the second electrode; The first electrode is coupled to the first conductive layer, and the second electrode is coupled to the second conductive layer.

8. The semiconductor temperature measuring device according to claim 7, characterized in that, At least one of the first wafer and the second wafer has a groove for accommodating at least a portion of the temperature sensing component; The first conductive layer extends into the inner wall of the groove; the capacitor structure is located in the corresponding groove, and the first electrode is coupled to the first conductive layer on the inner wall of the groove.

9. The semiconductor temperature measuring device according to claim 7, characterized in that, The temperature measuring component also includes: A voltage regulator coupled to the interconnecting circuit; the capacitor structure is symmetrically distributed on the outside of the electrical components of the temperature sensing assembly; and / or, The capacitor structure is arranged at intervals around the circumferential direction of the electrical appliance; wherein, the electrical appliance of the temperature measuring component includes at least one of the temperature measuring device, the power supply, the main controller, and the voltage regulator.

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