Semiconductor device with metal silicide and manufacturing method thereof

Abstract

According to the semiconductor device with the metal silicide and the manufacturing method of the semiconductor device, on the premise that the feature size and other performance of the device are not affected, the forming area and the line width of the metal silicide on the substrate on the outer side of the gate structure are enlarged by conducting side digging on part of the bottom of the side wall on the side wall of the gate structure, and the semiconductor device with the metal silicide is obtained. Therefore, smaller metal silicide resistance can be obtained, the influence of the line width effect of the metal silicide is weakened, further miniaturization of the size of a semiconductor device is facilitated, and for some products needing a high-temperature process in a back-end process (such as a metal interconnection process), the production cost is reduced. The invention provides a new thought and scheme in the aspect of avoiding thermal instability and line width effect of the metal silicide.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit manufacturing technology, and particularly relates to a semiconductor device with metal silicide and a manufacturing method thereof. BACKGROUND

[0002] With the continuous development of integrated circuit manufacturing technology, in order to improve the integration of integrated circuits, and to improve the working speed of the device and reduce its power consumption, the feature size of MOS transistors is continuously reduced, and MOS devices face a series of challenges, such as the increase of the equivalent series resistance of the source and drain regions of the MOS transistor and the contact resistance of the contact hole, the increase of the gate-related resistance-capacitance delay, and the like.

[0003] In order to reduce the equivalent series resistance of the source and drain regions of the MOS transistor and the contact resistance of the contact hole, and to shorten the gate-related resistance-capacitance delay, the metal silicide (Salicide) process of WSi2, TiSi2, CoSi2, NiSi, and the like is introduced in the current CMOS technology.

[0004] However, when the integrated circuit manufacturing technology advances to below the 65nm node (such as 45nm or 28nm, etc.), the line width effect of the metal silicide (i.e., the resistance of the metal silicide will increase with the decrease of the line width or contact area) becomes one of the factors that restrict the further improvement of the performance of the MOS device.

[0005] Therefore, how to improve the line width effect of the metal silicide has become one of the technical problems that the person skilled in the art needs to solve. SUMMARY

[0006] The purpose of the present application is to provide a semiconductor device with metal silicide and a manufacturing method thereof, which can improve the line width effect of the metal silicide and is beneficial to the further miniaturization of the semiconductor device size.

[0007] In order to achieve the above-mentioned purpose, the present application provides a manufacturing method of a semiconductor device with metal silicide, which comprises the following steps:

[0008] providing a substrate with a gate structure formed on the surface thereof;

[0009] depositing a side wall dielectric material layer on the gate structure and the surface of the substrate, and etching the side wall dielectric material layer to form a first side wall on the side wall of the gate structure, and the bottom of the first side wall is partially side-etched from the outside to expose more substrate surface outside the gate structure;

[0010] forming a metal silicide on the substrate surface exposed outside the gate structure, and the metal silicide extends into the bottom region of the first side wall removed by side-etching.

[0011] Optionally, the first sidewall is an outer sidewall, and an inner sidewall is formed on the sidewall of the gate structure before the deposition of the sidewall dielectric material layer.

[0012] Optionally, after the formation of the inner sidewall and before the deposition of the sidewall dielectric material layer, LDD ion implantation is performed on the substrate on both sides of the gate structure.

[0013] Optionally, the width of the bottom region of the first sidewall removed by the side etching is not greater than 1 / 2 of the line width of the first sidewall or the line width of the bottom region of the first sidewall removed by the side etching is 5-15 nm; and / or the height of the bottom region of the first sidewall removed by the side etching is not greater than 1 / 2 of the height of the first sidewall.

[0014] Optionally, the etching of the sidewall dielectric material layer comprises: first performing main etching on the sidewall dielectric material layer from the longitudinal direction to remove the sidewall dielectric material on the top of the gate structure and the substrate to form the first sidewall on the sidewall of the gate structure, and then adjusting the process parameters to perform over-etching on the first sidewall from the lateral direction to side-etch part of the bottom of the first sidewall from the outside of the first sidewall.

[0015] Optionally, after the main etching and before or after the over-etching, source-drain ion implantation is performed on the substrate on both sides of the gate structure, and annealing is performed for activation.

[0016] Optionally, the formation of the metal silicide on the exposed substrate surface on both sides of the gate structure comprises: first depositing a metal layer on the gate structure and the exposed substrate surface on both sides of the gate structure, and performing a first annealing process to form a high-resistance phase of metal silicide; and performing a second annealing process to convert the metal silicide from the high-resistance phase to a low-resistance phase.

[0017] Optionally, the manufacturing method further comprises at least one of the following steps:

[0018] (1) After the deposition of the metal layer and before the first annealing process, a cap protection layer is further deposited on the metal layer to perform the first annealing process under the masking of the cap protection layer;

[0019] (2) After the deposition of the metal layer and before the first annealing process, a cap protection layer and a dielectric buffer layer are sequentially deposited on the metal layer to perform the first annealing process under the masking of the dielectric buffer layer or to perform the first annealing process and the second annealing process under the masking of the dielectric buffer layer;

[0020] (3) After the first annealing process is completed and before the second annealing process is performed, the unreacted metal layer is removed and a dielectric buffer layer is further deposited on the metal silicide so that the second annealing process is performed under the cover of the dielectric buffer layer.

[0021] (4) After the second annealing process is completed, and before the contact etching stop layer is deposited, a third annealing process is performed;

[0022] (5) Before depositing the metal layer, the substrate on both sides of the gate structure is etched to form source drain trenches extending into the substrate exposed by the bottom region where the first sidewall is side-cut away, and then embedded germanium silicon source drains are epitaxially grown in the source drain trenches.

[0023] (6) Before depositing the metal layer, a silicide barrier layer is deposited on the substrate, the first sidewall and the gate structure, and the silicide barrier layer is photolithographically and etched to define the area to be formed of metal silicide, the area to be formed of metal silicide including the substrate area exposed by the bottom area of ​​the first sidewall being side-cut away.

[0024] Optionally, embedded germanium-silicon source drains are formed in the substrates on both sides of the gate structure, and the area where the metal silicide is to be formed also includes the top of the embedded germanium-silicon source drain and the top of the gate structure; after the etching of the silicide barrier layer is completed and before the metal silicide is formed, ion implantation is performed on the embedded germanium-silicon source drain to suppress excessive diffusion of metal, germanium and silicon, while reducing the top of the sidewalls on the sidewalls of the gate structure to expose more of the top of the gate structure.

[0025] Optionally, embedded germanium-silicon source / drain is formed in the substrate on both sides of the gate structure. Before forming the metal silicide, a pure silicon capping layer is formed on top of the embedded germanium-silicon source / drain. The metal silicide is formed on the surface of the pure silicon capping layer. The pure silicon capping layer includes at least one of polycrystalline silicon, microcrystalline silicon, and monocrystalline silicon.

[0026] Optionally, at least one of the second annealing process, the third annealing process, is flash annealing, laser spike annealing, or dynamic surface annealing.

[0027] Based on the same inventive concept, the present invention also provides a semiconductor device having a metal silicide, comprising:

[0028] Substrate;

[0029] A gate structure is formed on a portion of the surface of the substrate;

[0030] a first sidewall formed on the sidewall of the gate structure and having a portion of bottom removed by etching to expose more substrate surface outside the gate structure;

[0031] a metal silicide formed on at least the substrate surface exposed outside the gate structure and extending into the bottom region of the first sidewall removed by etching.

[0032] Optionally, the semiconductor device further comprises at least one of the following features:

[0033] (1) the first sidewall is an outer sidewall, and an inner sidewall is further formed between the first sidewall and the sidewall of the gate structure;

[0034] (2) LDD ion implantation regions and source / drain regions are formed in the substrate on both sides of the gate structure;

[0035] (3) source / drain recesses are formed in the substrate exposed by the etching of the bottom region of the first sidewall, and embedded GeSi source / drain is epitaxially grown in the source / drain recesses, and the metal silicide is formed on at least the top of the embedded GeSi source / drain.

[0036] Optionally, the width of the bottom region of the first sidewall removed by etching is not greater than 1 / 2 of the line width of the first sidewall, and / or the height of the bottom region of the first sidewall removed by etching is not greater than 1 / 2 of the height of the outer sidewall.

[0037] Optionally, the top of the embedded GeSi source / drain is doped with ions for inhibiting excessive diffusion of metal, germanium and silicon; and / or a pure silicon cap layer is formed on the top of the embedded GeSi source / drain, and the metal silicide is formed on at least the pure silicon cap layer, and the pure silicon cap layer comprises at least one of polysilicon, microcrystalline silicon and monocrystalline silicon.

[0038] Compared with the prior art, the technical scheme of the present application has at least one of the following beneficial effects:

[0039] (1) Without affecting the feature size and other performance of the device, by etching a portion of the bottom of the first sidewall on the sidewall of the gate structure, the formation area and line width of the metal silicide on the substrate outside the gate structure are expanded, so that smaller metal silicide resistance can be obtained, the influence of the line width effect of the metal silicide is weakened, and the further miniaturization of the semiconductor device size is facilitated.

[0040] (2) Since it can improve the linewidth effect of metal silicides, it allows the introduction of metal silicide materials (such as CoSi) that were originally restricted by the linewidth effect from being used in advanced nodes and are more heat-resistant. For some back-end processes (such as metal interconnect processes) that require high-temperature processes, this invention provides new ideas and solutions to avoid the thermal instability and linewidth effect of metal silicides.

[0041] (3) The second annealing process is second-level annealing, millisecond-level annealing, microsecond-level annealing or nanosecond-level annealing and the annealing temperature is relatively high (e.g., 1050℃~1300℃), such as flash annealing, laser peak annealing or dynamic surface annealing, which can shorten the process time, improve the efficiency of metal silicide transition from high-resistivity phase to low-resistivity phase (and at the same time prevent excessive diffusion of various ions), and the high temperature and short time annealing conditions can, to a certain extent, not only avoid the problem of deactivation of elements doped in the previous process due to long-term annealing, but also activate the elements doped in the previous process, thereby improving the speed of the device, and thus improving the performance of the device. Attached Figure Description

[0042] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0043] Figure 1 This is a schematic diagram of the manufacturing process of a semiconductor device with metal silicide according to the first embodiment of the present invention.

[0044] Figures 2A to 2G This is a schematic cross-sectional view of the device structure in the manufacturing method of a semiconductor device with metal silicide according to the first embodiment of the present invention.

[0045] Figure 3 This is a schematic cross-sectional view of the device structure in the manufacturing method of a semiconductor device with metal silicide according to the second embodiment of the present invention.

[0046] Figure 4 This is a schematic cross-sectional view of the device structure in the manufacturing method of a semiconductor device with metal silicide according to the third embodiment of the present invention.

[0047] Figure 5 This is a schematic cross-sectional view of the device structure in the manufacturing method of a semiconductor device with metal silicide according to the fourth embodiment of the present invention.

[0048] Figure 6 This is a schematic cross-sectional view of the device structure in the manufacturing method of a semiconductor device with metal silicide according to the fifth embodiment of the present invention.

[0049] Figure 7is a device structure cross-sectional schematic diagram in a manufacturing method of a semiconductor device with metal silicide of a sixth embodiment of the present application. DETAILED DESCRIPTION

[0050] In the following description, numerous specific details are set forth to provide a more thorough understanding of the present application. However, it will be apparent to one of skill in the art that the present application can be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present application. It should be understood that the present application can be practiced with modification and alteration, and that the present application is not limited to the embodiments described. Rather, the embodiments are provided as examples to fully and entirely disclose the present application, and to fully and entirely convey the scope of the present application to those skilled in the art. Like reference numerals refer to like elements throughout the specification. It should be understood that when an element is referred to as being "connected to" another element, it can be directly connected to the other element, or intervening elements can be present. In contrast, when an element is referred to as being "directly connected to" another element, there are no intervening elements present. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0051] The technical solutions of the present application are further described in detail below in combination with the drawings and specific embodiments. The advantages and features of the present application will be more apparent according to the following description. It should be noted that the drawings are very simplified and use non-precise proportions, only for the purpose of facilitating and clearly assisting the description of the embodiments of the present application.

[0052] First Embodiment

[0053] Reference Figure 1 The present embodiment provides a manufacturing method of a semiconductor device with metal silicide, which comprises the following steps:

[0054] S1, providing a substrate with a gate structure formed on a surface thereof;

[0055] S2, depositing a side wall dielectric material layer on the gate structure and the surface of the substrate, and etching the side wall dielectric material layer to form a first side wall on the side wall of the gate structure, and the bottom of the first side wall is partially undercut from the outside to expose more substrate surface outside the gate structure;

[0056] S3, forming a metal silicide on the substrate surface exposed outside the gate structure, the metal silicide extending into the bottom region removed by the first sidewall etching.

[0057] Please refer to Figure 2A In step S1, any suitable substrate 100 can be provided according to the device manufacturing requirement, such as single-crystal silicon (Si), silicon-on-insulator (SOI), single-crystal germanium (Ge), germanium-on-insulator (GeOI), silicon carbide (SiC), gallium arsenide (GaAs), indium phosphide (InP), transparent glass, etc. Further, the substrate 100 can be a substrate processed by device isolation process, well ion implantation process, gate oxide process, polysilicon gate process, inner sidewall process, etc. The device isolation process is, for example, shallow trench isolation (STI) process or local oxidation of silicon (LOCOS) process, etc., aiming to form device isolation structures (not shown, such as shallow trench isolation structures or local oxidation of silicon structures) in the substrate 100 according to the layout design requirement, to define transistor active regions such as pMOS regions and nMOS regions in the substrate 100; the well ion implantation process aims to perform n-type or p-type well ion implantation in each pMOS region and each nMOS region defined by the device isolation structures, to form corresponding n-type well regions (not shown) and p-type well regions (not shown). The gate oxide process aims to form required gate oxide layers 101 on the pMOS regions and nMOS regions of the substrate 100, which can be silicon dioxide, silicon oxynitride, or high-K material (such as hafnium-based oxide, etc.) with dielectric constant K higher than that of silicon dioxide, or a combination thereof. The polysilicon gate process aims to form required polysilicon gates 102 on the pMOS regions and nMOS regions of the substrate 100, the top surface of the polysilicon gate 102 can be partially exposed as part of the region to be formed with metal silicide in the embodiment. The polysilicon gate 102 and the gate oxide layer 101 thereunder form a gate structure.

[0058] As an example, please continue to refer to Figure 2A In step S1, after forming the gate structure, the inner sidewall can be formed on the sidewall of the gate structure by any suitable sidewall process (including deposition and etching of dielectric material, etc.), and LDD (Lightly Doped Drain) ion implantation is performed on the substrate 100, which specifically includes, for example:

[0059] First, please refer to Figure 2AThe inner sidewall can be a single layer of silicon oxide or a multi-layer structure of two or more different sidewall materials, such as ON or ONO structure.

[0060] Then, referring to Figure 2A The substrate 100 outside the gate structure is subjected to LDD ion implantation with the inner sidewall and the gate structure as masks, so as to form a low-doped LDD ion implantation region 104 between the boundary of the polysilicon gate 102 and the subsequently formed source-drain region, which is used to form a gradient of impurity concentration between the source-drain region and the channel, so as to reduce the peak electric field near the drain, thereby improving the hot carrier injection (HCI) effect and device reliability.

[0061] Referring to Figure 2B In step S2, a layer of sidewall medium material is deposited on the inner sidewall, the gate structure and the substrate 100, and then the deposited layer of sidewall medium material is etched to form a first sidewall as an outer sidewall on the outer sidewall of the inner sidewall, and part of the bottom of the first sidewall is partially undercut from the outside to expose more of the surface of the substrate 100 outside the gate structure. The undercutting of the bottom of the first sidewall can be achieved by adjusting the process parameters of the last etching stage of the layer of sidewall medium material, or by switching to another suitable etching process after the first sidewall is formed by etching the layer of sidewall medium material.

[0062] Referring to Figure 2B In this example, the first sidewall is used as an outer sidewall and an inner sidewall to form a sidewall (or gate sidewall) on the sidewall of the polysilicon gate 102. The line width of the first sidewall needs to be controlled in consideration of the position of the to-be-formed source-drain region, the width of the subsequently undercut bottom, and the overall performance of the sidewall required on the gate sidewall. The first sidewall can be a single layer of silicon oxide or a multi-layer structure of two or more different sidewall materials, such as ON or ONO structure. For example, the first sidewall includes a second layer of silicon oxide 105a covering the outer sidewall of the first layer of silicon nitride 103b, and a second layer of silicon nitride 105b covering the outer sidewall of the second layer of silicon oxide 105a.

[0063] In this example, the process of forming the first side wall with a partially undercut bottom in step S2 is as follows:

[0064] First, a second silicon oxide layer 105a and a second silicon nitride layer 105b are sequentially deposited by any suitable deposition process, and the thickness of the second silicon nitride layer 105b can be greater than that of the second silicon oxide layer 105a. The second silicon oxide layer 105a and the second silicon nitride layer 105b form a layer of sidewall dielectric material for fabricating the first side wall.

[0065] Next, the second silicon nitride layer 105b is etched using any suitable etching process, such as a dry etching process, with the second silicon oxide layer 105a as an etching stop layer. This stage is a main etch stage for the layer of sidewall dielectric material for fabricating the first side wall, and the etching direction is controlled to be mainly downward (i.e., the etching direction is longitudinal), so as to remove the second silicon nitride layer 105b on the substrate 100 outside the region where the first side wall is to be formed, while avoiding lateral etching as much as possible, thereby forming the main part of the first side wall.

[0066] Then, referring to Figure 2C The second silicon oxide layer 105a is etched using any suitable etching process, such as a dry etching or wet etching process, with the inner sidewall, the gate structure, and the remaining second silicon nitride layer 105b as a mask. This stage is a first over etch stage for the layer of sidewall dielectric material for fabricating the first side wall, and the etching direction is controlled to be mainly downward (i.e., the etching direction is longitudinal), so as to remove the second silicon oxide layer 105a exposed by the remaining second silicon nitride layer 105b by taking advantage of the high etching selectivity of the second silicon oxide layer 105a to the second silicon nitride layer 105b, while avoiding lateral etching as much as possible, thereby causing the remaining second silicon oxide layer 105a to cover the outer sidewall of the remaining second silicon nitride layer 105b. At this time, the remaining second silicon oxide layer 105a and the remaining second silicon nitride layer 105b form a complete first side wall.

[0067] After that, further referring to Figure 2C, the etching process parameters are adjusted relative to the first over etch stage, such as adjusting the bias and power of the over etch stage, so that the vertical etching (i.e. longitudinal etching) is converted into lateral etching (i.e. transverse etching) at the bottom of the first side wall, and a certain amount of side etching is generated on the second silicon nitride layer 105b and the second silicon oxide layer 105a in the bottom of the first side wall, which is a second over etch stage for the side wall dielectric material layer forming the first side wall, thereby exposing the part of the substrate 100 that was originally covered by the second silicon nitride layer 105b and the second silicon oxide layer 105a of the first side wall, and increasing the exposed area of the substrate. When the metal layer deposition (such as sputtering) is subsequently performed, the second silicon nitride layer 105b and the second silicon oxide layer 105a in the bottom area removed by side etching will also be covered with a metal layer and in contact with the substrate surface, and a metal silicide will be formed under high temperature processing, thereby increasing the line width of the metal silicide accordingly, so that when some metal materials with line width effect such as Co are used, the problem of high resistance of the metal materials due to the limitation of line width effect when forming the metal silicide can be well avoided.

[0068] Obviously, please refer to Figures 2A to 2C , the first side wall process of step S2 of the embodiment, relative to the existing outer side wall process, only process parameter adjustment is essentially performed, which does not bring process sequence increase and process architecture change, the scheme is simple, and the bottom of the second silicon oxide layer 105a and the second silicon nitride layer 105b of the outer side wall is side etched to a certain extent, the area of the substrate not covered by the side wall is expanded, thereby the growth area and line width of the metal silicide are expanded. In addition, compared with the scheme of directly thinning the first side wall from bottom to top as a whole, only the bottom of the first side wall is side etched, which does not affect the source / drain ion implantation and does not damage the substrate after the source / drain ion implantation to cause device degradation.

[0069] Optionally, please refer to Figure 2C , the line width of the first side wall is w0, the height is h0, the line width of the bottom area 106 removed by side etching of the first side wall is w, and the height is h, wherein w Figure 2C), can be less consumed during the acid washing process, can ensure the exposed silicon substrate area for forming metal silicide increases, but will not be excessively increased, and will not cause the metal silicide to be too close to the gate (polysilicon pillar) due to excessive uncontrollable side etching, thereby preventing breakdown.

[0070] In an example, referring to Figure 2C After the bottom of the first side wall is side etched, the line width of the area between adjacent gate structures to be formed into metal silicide is expanded from y to y+2w, and w can be controlled at about 5nm to 15nm according to actual products and requirements.

[0071] In an example, referring to Figure 2C Without affecting the source / drain ion implantation (S / D implantation, vertical implantation), the effective formation area of the metal silicide is effectively expanded by 20% to 60%, thereby avoiding the line width effect of the metal silicide (such as CoSi2, etc.), for example, CoSi2 can be used as the metal silicide material at a process node of 28nm to 40nm.

[0072] Optionally, referring to Figure 2D Before or after the step S2 of side etching the bottom of the first side wall, the substrate 100 on both sides of the gate structure is also subjected to source / drain ion implantation (S / D implantation, vertical implantation) and annealing activation, thereby forming the source / drain region 107 required by the MOS transistor.

[0073] Preferably, after the step S2 is completed and before the step S3 (forming metal silicide) is performed, the substrate 100 on both sides of the gate structure is subjected to source / drain ion implantation by vertical implantation and annealing activation, thereby forming the source / drain region 107 required by the MOS transistor. Thus, since the implantation direction of the source / drain implantation process is vertical implantation, the side etching of the bottom of the first side wall will not adversely affect the source / drain implantation process, thereby avoiding the problem of damaging the source / drain region after the source / drain ion implantation is performed and then the bottom of the first side wall is side etched.

[0074] Optionally, referring to Figure 2DAfter the step S2 (i.e. side etching the bottom of the first side wall) is completed and before the step S3 is performed, a silicide barrier layer (SAB, not shown) is deposited on the side wall, the gate structure and the surface of the exposed substrate 100 by any suitable process such as a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process; then, the silicide barrier layer is photolithographically and etched (or cleaned) to remove the silicide barrier layer on the areas where the metal silicide is to be formed (including the area where the bottom of the outer side wall is removed by side etching) and to keep the silicide barrier layer on the rest of the areas, thereby forming a patterned silicide barrier layer on the substrate 100 and exposing the surface of the areas where the metal silicide is to be formed (including the area where the bottom of the outer side wall is removed by side etching). In an example, the patterned silicide barrier layer not only exposes the surface of the substrate outside the gate structure, but also exposes part or all of the top surface of the gate structure and masks the rest of the areas to prevent the formation of metal silicide on the surface of the materials such as silicon in these areas in the subsequent step S3.

[0075] It should be noted that, since the side etching of the bottom of the first side wall is completed by the step S2 (i.e. side etching the bottom of the side wall), when the silicide barrier layer (SAB) is deposited, a part of the silicide barrier layer will fill in the area where the bottom of the first side wall is removed by side etching. By using the high etching selectivity of the silicide barrier layer to the second silicon nitride layer 105b in the first side wall during the etching or cleaning of the silicide barrier layer (SAB), on the one hand, the silicide barrier layer (SAB) filled in the area where the bottom of the first side wall is removed by side etching can be completely removed, effectively ensuring the area and line width of the bottom of the first side wall which is thinned, allowing a larger area of metal silicide to be formed and avoiding the line width effect of the corresponding metal silicide, and on the other hand, preventing the bottom of the first side wall from being further pushed inwards and affecting the reliability of the side wall on the side wall of the gate structure.

[0076] In the step S3 (forming metal silicide), any suitable metal silicide process technology can be used to form the metal silicide 110 on the surface of the substrate 100 exposed outside the gate structure and the top surface of the polysilicon gate 102 exposed, and the metal silicide 110 on the substrate 100 extends into the area where the bottom of the first side wall is removed by side etching.

[0077] As an example, the process of forming the required metal silicide 110 in the step S3 (forming metal silicide) is as follows:

[0078] First, please refer to Figure 2EA metal layer 108 is deposited on top of the gate structure, on the sidewall and top of the first sidewall, on top of the second sidewall, and on the surface of the exposed substrate 100 (i.e., source / drain region 107) by any suitable process such as a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, or an atomic layer deposition (ALD) process. The material of the metal layer 108 can be at least one of cobalt (Co), manganese (Mn), titanium (Ti), zirconium (Zr), tantalum (Ta), tungsten (W), palladium (Pd), platinum (Pt), nickel (Ni), yttrium (Yb), and can be a single metal or an alloy. For example, the first metal layer is cobalt or a cobalt alloy, and in particular in a scenario with high-temperature processes in the back end of line (BEOL), a metal with higher stability but more line width effect, such as titanium and cobalt, or an alloy thereof, is selected first.

[0079] Optionally, referring back to Figure 2E A cap protection layer 109 is deposited on the metal layer 108 by any suitable process such as a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process. The cap protection layer 109 can be a single layer or a stack of multiple layers, and the material of the cap protection layer 109 is selected from at least one of Ti, W, or TiN. The cap protection layer 109 does not participate in the reaction in the first annealing process, and can be removed together with the unreacted metal layer 108 in the subsequent removal process. The cap protection layer 109 prevents the metal layer 108 from flowing in the first annealing process, and prevents the thickness and resistance of the metal silicide 110 from being non-uniform. The cap protection layer 109 also protects the surface of the metal layer 108 from oxidation.

[0080] Next, referring to Figure 2FThe first anneal process can be performed using any suitable anneal technique in the art, such as a conventional soak anneal, a rapid thermal anneal (RTA), a spike anneal, a flash lamp anneal (FLA), a laser spike anneal (LSA), a dynamic surface anneal (DSA), etc., to cause the metal in the deposited metal layer 108 to react with the silicon in the source / drain regions 107 and the polysilicon gates 102 to form a high-resistivity metal silicide (e.g., CoSi) 110 on the source / drain regions 107 and the polysilicon gates 102. The temperature setting for the first anneal process depends on the material of the metal silicide to be formed. When the deposited metal layer 108 is Co, the anneal temperature for the first anneal process can be set to 400-600 °C, such as 420-550 °C, to form a high-resistivity CoSi. When the deposited metal layer 108 is Ni, the anneal temperature for the first anneal process can be set to 350-550 °C to form a high-resistivity nickel silicide NiSi.

[0081] Afterwards, referring to Figure 2G Any suitable process, such as a wet etch, etc., can be used to remove the cap layer 109 and the unreacted metal layer 108 to prevent them from bridging and causing a short circuit.

[0082] Next, referring to Figure 2G The second anneal process can be performed using any suitable anneal technique in the art, such as a conventional soak anneal, a rapid thermal anneal (RTA), a spike anneal, a flash lamp anneal (FLA), a laser spike anneal (LSA), a dynamic surface anneal (DSA), etc., to convert the metal silicide 110 from a high-resistivity phase to a low-resistivity phase. The temperature setting for the second anneal process is typically higher than that for the first anneal process. When the deposited metal layer 108 is Co, the anneal temperature for the second anneal process can be set to 600-850 °C to convert the high-resistivity CoSi to a low-resistivity CoSi2. When the deposited metal layer 108 is Ni, the anneal temperature for the second anneal process can be set to 600-800 °C to convert the high-resistivity nickel silicide NiSi to a low-resistivity nickel silicide NiSi2.

[0083] In an example, the first annealing process is implemented by using immersion annealing, and the second annealing process is implemented by using flash annealing, laser spike annealing (LSA) or dynamic surface annealing (DSA) to improve the efficiency of the metal silicide process and reduce the influence of thermal budget. The annealing time can be in the order of seconds, milliseconds, microseconds or nanoseconds. In this way, the process time can be shortened, the efficiency of the transition of the metal silicide from a high resistance phase to a low resistance phase can be improved, and the excessive diffusion of various ions can be prevented. In addition, the high-temperature short-time annealing condition can not only avoid the problem of deactivation of the previously doped elements due to long-time annealing, but also activate the previously doped elements, thereby improving the speed of the device and further improving the performance of the device.

[0084] Optionally, after the second annealing process is completed, a third annealing process is further performed, and after the third annealing process is completed, a contact etching stop layer is deposited. In this way, the metal silicide is completely converted from a high resistance phase to a low resistance phase by the third annealing process. In an example, the first annealing process and the second annealing process are both implemented by using immersion annealing, and the third annealing process is implemented by using flash annealing, laser spike annealing (LSA) or dynamic surface annealing (DSA) to completely convert the metal silicide after the second annealing process from a high resistance phase to a low resistance phase by using the third annealing process, thereby further reducing the resistance of the metal silicide. In another example, the first annealing process is implemented by using immersion annealing, and the second annealing process and the third annealing process are both implemented by using flash annealing, laser spike annealing (LSA) or dynamic surface annealing (DSA) to improve the efficiency of the metal silicide process and reduce the influence of thermal budget by using the second annealing process, and to completely convert the metal silicide after the second annealing process from a high resistance phase to a low resistance phase by using the third annealing process, thereby further reducing the resistance of the metal silicide.

[0085] In the embodiment, the bottom side of the first side wall is etched to increase the exposed area of the substrate, and the line width of the metal silicide is also increased accordingly, so that when some metal materials (such as Co) with line width effect are used, the high resistance state of the metal material due to the limitation of the line width during the formation of the metal silicide can be well avoided.

[0086] Generally, for the 28nm-40nm process node, nickel silicide is used as the metal silicide to reduce the contact resistance. However, the nickel silicide material has the problems of poor thermal stability and pipeline defects, and has strict limitations and requirements on the temperature and time of the subsequent thermal process of the product. The cobalt silicide material with better thermal stability has a sharp increase in resistance at a small size due to the line width effect, and is generally only used for process nodes above 55nm.

[0087] The scheme of the embodiment can effectively expand the area of the metal silicide without affecting the source-drain ion implantation, so as to avoid the line width effect of cobalt silicide and use cobalt silicide instead of nickel silicide as the metal silicide material in the 28nm-40nm process node, thereby solving the problems of poor thermal stability and pipeline defects of nickel silicide.

[0088] It should be understood that in other examples of the embodiment, the side wall on the side wall of the gate structure can also be a single-layer structure, and the bottom of the side wall is partially side-etched in step S2 to increase the area and line width of the metal silicide while ensuring the reliability of the side wall.

[0089] Based on the same inventive concept, please refer to Figure 2G The embodiment also provides a semiconductor device with metal silicide, which comprises a substrate 100, a gate structure, a first side wall, an LDD ion implantation region 104, a source-drain region 107 and a metal silicide 110.

[0090] The gate structure is formed on part of the surface of the substrate 100, the first side wall is formed on the side wall of the gate structure, and part of the bottom of the first side wall is side-etched to expose more of the surface of the substrate 100 outside the gate structure. The LDD ion implantation region 104 and the source-drain region 107 are formed in the substrate 100 on both sides of the gate structure.

[0091] The metal silicide 110 is formed at least on the surface of the substrate 100 exposed outside the gate structure (i.e. the surface of the source-drain region 107) and extends into the bottom region of the first side wall which is side-etched.

[0092] Optionally, the first side wall is an outer side wall, and an inner side wall is further formed between the first side wall and the side wall of the gate structure.

[0093] Further optionally, the width w of the bottom region of the first side wall which is side-etched is not greater than 1 / 2 of the line width w0 of the first side wall, and / or the height h of the bottom region of the first side wall which is side-etched is not greater than 1 / 2 of the height h0 of the outer side wall.

[0094] The selection of materials and the like of each structure in the semiconductor device of the embodiment can refer to the related content in the manufacturing method described above, and will not be described here again.

[0095] The semiconductor device of the embodiment has a larger area and a larger line width of the metal silicide on the source-drain region 107, so the contact resistance is lower and the performance is higher.

[0096] Second embodiment

[0097] The present embodiment provides a method for manufacturing a semiconductor device with metal silicide, which also includes Figure 1 The steps S1-S3 are shown in FIG. 1.

[0098] The present embodiment differs from the first embodiment in that, in step S3, referring to (A) in FIG. 2, after the first annealing process is performed to form the high-resistance-phase metal silicide 110 on the top of the gate structure, the sidewall and top of the first sidewall, the top of the inner sidewall, and the surface of the exposed substrate 100 (i.e., the source-drain region 107) and under the mask of the cap protection layer 109, the cap protection layer 109 and the unreacted metal layer 108 are removed by any suitable process, as shown in (B) in FIG. 2, and then any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric with a dielectric constant lower than that of silicon dioxide, high-k dielectric with a dielectric constant higher than that of silicon dioxide, etc., is deposited by any suitable process, such as chemical vapor deposition or physical vapor deposition, to form a dielectric buffer layer 111 covering the entire device surface including the high-resistance-phase metal silicide 110, as shown in (C) in FIG. 2, and then a second annealing process is performed under the mask of the dielectric buffer layer 111 to convert the metal silicide 110 from the high-resistance phase to the low-resistance phase, as shown in (D) in FIG. 2. Figure 3 Figure 3 Figure 3 Figure 3

[0099] In one example, the dielectric buffer layer 111 is silicon oxide, which has small stress and is easy to form and remove.

[0100] After the second annealing process is completed, the dielectric buffer layer 111 can be removed or retained according to the needs of subsequent processes.

[0101] ​​​​It should be understood that, in step S3 of the present embodiment, after the first annealing process is completed and the unreacted metal layer 108 is removed, the dielectric buffer layer 111 is further deposited, and the second annealing process is performed under the mask of the dielectric buffer layer 111, which acts as a heat buffer layer and can change the heat distribution of the second annealing process, especially when a high-temperature and ultra-short-time annealing method is used (high-temperature or short-time annealing methods can bring many benefits, such as reducing ion diffusion, because the time is short, the degree of ion diffusion is greatly reduced, and the situation of over-intense reaction and uneven reaction caused by too high temperature in too short time can be prevented), the annealing heat applied to the metal silicide by the second annealing process will be partially blocked and buffered by the dielectric buffer layer, and will be more uniformly distributed in the metal silicide, thereby preventing the metal silicide from being unevenly heated by the second annealing process (because the annealing is short-time and high-temperature, the applied heat and the metal silicide are prevented from directly contacting each other by the dielectric buffer layer, and the temperature field is prevented from being uneven), so that the metal silicide 110 is heated more uniformly, the reaction in each place is more uniform, which is further beneficial to the conversion of the metal silicide 110 from the high-resistance phase to the low-resistance phase, improves the resistance uniformity of the metal silicide, is beneficial to reducing the resistance of the metal silicide, and can reduce defects (such as cluster or tubular defects, etc.) caused by uneven heating, and preferably, the dielectric buffer layer 111 is a material with low stress (such as silicon oxide and other oxides), which has low stress introduced during the formation of the metal silicide 110, and has a good inhibitory effect on defects such as bubbles, protrusions, clusters, etc. caused by stress aggregation, thereby effectively improving the thickness and resistance uniformity of the low-resistance phase metal silicide 110 formed finally.

[0102] In other examples, the cap protection layer 109 can also be omitted as needed, and the present application does not make specific limitations thereto.

[0103] Third embodiment

[0104] The present embodiment provides a method for manufacturing a semiconductor device with a metal silicide, which also includes Figure 1 the steps S1-S3 shown.

[0105] The difference between the present embodiment and the first embodiment is that, in step S3, please refer to Figure 4(A) of (B) of FIG. 10, after the metal layer 108, the cap protection layer 109 and the dielectric buffer layer 113 are sequentially deposited on the top of the gate structure, the top of the first sidewall, the sidewall, the top of the inner sidewall and the surface of the exposed substrate 100 (i.e. the source / drain region 107) and under the mask of the cap protection layer 109 and the dielectric buffer layer 113, a first annealing process is performed to form the high-resistance phase of the metal silicide 110, and then a second annealing process is performed under the mask of the cap protection layer 109 and the dielectric buffer layer 113 to convert the metal silicide 110 from the high-resistance phase to the low-resistance phase, as shown in (C) of FIG. 10. Figure 4 (B) of FIG. 10, and then the dielectric buffer layer 113 and the cap protection layer 109, the unreacted metal layer 108, etc. are removed, as shown in (C) of FIG. 10. Figure 4 (C) of FIG. 10.

[0106] In the embodiment, the first annealing process and the second annealing process can be implemented by flash annealing, laser spike annealing (LSA) or dynamic surface annealing (DSA), respectively.

[0107] In the embodiment, the thickness of the deposited metal layer 108 is precisely controlled so that, in the first annealing process, the metal layer 108 covering the region to be formed with the metal silicide is substantially consumed and converted into the metal silicide 110.

[0108] In the embodiment, the dielectric buffer layer 113 can be formed by any suitable process such as chemical vapor deposition (CVD) or physical vapor deposition (PVD), and the material thereof includes any one or more suitable dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric with a dielectric constant lower than that of silicon dioxide, high-k dielectric with a dielectric constant higher than that of silicon dioxide, etc. When the first annealing process and the second annealing process are performed under the mask of the dielectric buffer layer 113, the dielectric buffer layer 113 can act as a heat buffer layer to change the heat distribution of the first annealing process and the second annealing process, so that the region to be formed with the metal silicide is heated more uniformly, which is further conducive to forming the high-resistance phase of the metal silicide 110 with uniform thickness and few defects in the first annealing process, and forming the low-resistance phase of the metal silicide with uniform thickness and few defects in the second annealing process, and can reduce the defects such as bubbles and protrusions caused by uneven heating. Preferably, the dielectric buffer layer 113 is a material with low stress (e.g. oxide such as silicon oxide), which introduces less stress during the formation of the metal silicide 110 and has a good inhibitory effect on the defects such as bubbles, protrusions and clusters caused by stress aggregation, thereby effectively improving the thickness and resistance uniformity of the low-resistance phase of the metal silicide 110 finally formed.

[0109] In an example, the dielectric buffer layer 113 is silicon oxide, which has low stress and is easy to form and remove.

[0110] In other examples, the cap protection layer 109 can be omitted as needed, which is not specifically limited in the present application.

[0111] Fourth embodiment

[0112] This embodiment provides a method for manufacturing a semiconductor device having metal silicide, which also includes... Figure 1 The steps S1 to S3 are shown.

[0113] The difference between this embodiment and the first embodiment is that, after completing step S2 and before proceeding to step S3, please refer to... Figure 5 In steps (A) to (C), an embedded germanium-silicon source drain is formed in the substrate 100 exposed on both sides of the polysilicon gate 102 using an embedded source drain process, serving as the source drain region of the pMOS transistor. In subsequent step S3, a metal silicide is formed on the substrate outside the gate structure, forming on top of the embedded germanium-silicon source drain, as shown. Figure 5 (D) in the middle.

[0114] In one example, the step of forming an embedded germanium-silicon source / drain after step S2 includes: first etching the substrate 100 outside the gate structure to form a source / drain recess 107a, such as... Figure 5 As shown in (A) and (B), the source / drain recess 107a extends into the substrate 100 exposed in the bottom region where the first sidewall has been side-cut; then, an embedded germanium-silicon source / drain is epitaxially grown in the source / drain recess 107a using a germanium-silicon epitaxial growth process, as shown in (A) and (B). Figure 5 (C) In subsequent step S3, the metal silicide 110 formed is formed at least on top of the embedded germanium-silicon source / drain, such as Figure 5 As shown in (D) in the diagram.

[0115] Compared with the first embodiment, this embodiment introduces an embedded germanium-silicon source and drain, which can utilize the compressive stress generated by the difference in lattice constants of germanium and silicon to improve the hole mobility and saturation current in the pMOS transistor.

[0116] Based on this, this embodiment also provides a semiconductor device with metal silicide, which differs from the semiconductor device with metal silicide in the first embodiment in that the semiconductor device with metal silicide in this embodiment also has an embedded germanium-silicon source / drain, and the metal silicide 110 is formed at least on top of the embedded germanium-silicon source / drain.

[0117] The semiconductor device with metal silicide in this embodiment has better performance because it has a larger area and linewidth of metal silicide and has embedded germanium-silicon source and drain.

[0118] Fifth embodiment

[0119] This embodiment provides a method for manufacturing a semiconductor device having metal silicide, which also includes...Figure 1 The steps S1-S3 are shown.

[0120] Please refer to (A) to (C) in Figure 6 The difference between this embodiment and the fourth embodiment is that, in the process of forming the embedded GeSi source-drain in step S2 or after forming the embedded GeSi source-drain in step S2 and before step S3, ions for inhibiting excessive diffusion of metal, germanium, silicon and the like are doped in the top of the embedded GeSi source-drain, i.e., a GeSi doped layer 107b doped with ions for inhibiting excessive diffusion of metal, germanium, silicon and the like is formed on the top of the embedded GeSi source-drain.

[0121] The addition of the GeSi doped layer 107b can bring the following effects: (1) It can prevent the mobility and electric field distribution of the embedded GeSi source-drain and the channel region from being affected; (2) It can reduce the consumption of silicon in the embedded GeSi source-drain in each round of metal silicidation process, and ensure the performance of the embedded GeSi source-drain; (3) The ions for inhibiting excessive diffusion of metal, germanium, silicon and the like in the GeSi doped layer 107b are highly concentrated after little diffusion in the second annealing process, and can maintain good position stability between the embedded GeSi source-drain and the metal silicide thereon, thereby playing a pinning role in the SiGe lattice of the GeSi doped layer 107b and exerting a stable barrier effect between the metal and silicon, germanium and the like, and can be used to improve the excessive diffusion of the formed metal silicide on the embedded GeSi source-drain 107 in step S3 or subsequent high-temperature processes, significantly improving the defects such as clusters, bubbles and protrusions in the finally formed metal silicide, improving the resistance uniformity and even line width effect of the metal silicide, reducing its resistance, and improving the thermal stability of the formed low-resistance phase metal silicide in subsequent high-temperature processes. Therefore, the performance of the metal silicide formed in this embodiment and the device having the metal silicide is better.

[0122] Optionally, the impurity ions for inhibiting excessive diffusion of metal, germanium, silicon and the like include at least one of any suitable ions such as B (boron), F (fluorine), C (carbon), Ga (gallium), In (indium) and the like. For example, the ions for inhibiting excessive diffusion of metal, germanium, silicon and the like include B ions, and also include at least one of F, C, Ga, In ions. For another example, the ions for inhibiting excessive diffusion of metal, germanium, silicon and the like include only B ions or F ions.

[0123] In this process, ions used to suppress excessive diffusion of elements such as metal, germanium, and silicon can be doped on top of the embedded germanium-silicon source / drain through ion implantation and / or epitaxial growth processes to form a germanium-silicon doped layer 107b. The ions used to suppress excessive diffusion of elements such as metal, germanium, and silicon in the germanium-silicon doped layer 107b can be uniformly doped or have a doping concentration that gradually decreases from bottom to top. Preferably, the doping concentration of ions used to suppress excessive diffusion of elements such as metals, germanium, and silicon in the germanium-silicon doped layer 107b gradually decreases from bottom to top. This utilizes the high doping concentration of these ions in the lower layer of the germanium-silicon doped layer 107b to block excessive diffusion of elements such as metals, germanium, and silicon, thereby reducing contact resistance. On the other hand, the low doping concentration of these ions in the upper layer of the germanium-silicon doped layer 107b ensures the silicon source for the metal silicide reaction, improves the efficiency of the metal silicide reaction, and prevents these doped ions from hindering the silicide process during the metal silicide reaction, thus ensuring high-quality metal silicides.

[0124] As an example, after the epitaxial growth of the embedded germanium-silicon source / drain is completed, ions used to suppress the excessive diffusion of elements such as metal, germanium, and silicon are implanted into the top of the embedded germanium-silicon source / drain through one or more ion implantation processes, so that the top of the embedded germanium-silicon source / drain is doped with ions used to suppress the excessive diffusion of elements such as metal, germanium, and silicon, forming a germanium-silicon doped layer 107b.

[0125] As another example, after completing the epitaxial growth of the embedded germanium-silicon source / drain, a pure silicon layer or a germanium-silicon layer is further epitaxially grown. Then, through one or more steps of ion implantation process, ions used to suppress the excessive diffusion of elements such as metal, germanium, and silicon are implanted into the pure silicon layer or germanium-silicon layer epitaxially grown on top of the embedded germanium-silicon source / drain, so that the top of the embedded germanium-silicon source / drain is doped with ions used to suppress the excessive diffusion of elements such as metal, germanium, and silicon, forming a germanium-silicon doped layer 107b.

[0126] As another example, please refer to Figure 6 In (A) to (B), after epitaxially growing an embedded germanium-silicon source / drain of a certain thickness, the germanium-silicon source / drain is further epitaxially grown (at this time, the regrown germanium-silicon source / drain should have less germanium, that is, its germanium concentration is lower than that of the previously formed germanium-silicon source / drain), while in situ doping it with ions used to suppress the excessive diffusion of metal, germanium, silicon and other elements, so that the top of the embedded germanium-silicon source / drain is doped with ions used to suppress the excessive diffusion of metal, germanium, silicon and other elements, forming a germanium-silicon doped layer 107b.

[0127] Preferably, an inclined ion implantation process is adopted to dope ions for inhibiting excessive diffusion of metal, germanium, silicon and the like on the top of the embedded germanium-silicon source-drain. The angle of ion implantation (i.e. the angle between the direction of ion implantation and the normal of the top surface of the substrate) is greater than 0° and less than 90°. For example, it is 15°-30°. In this way, on the one hand, the sidewall and top surface of the gate sidewall (including the first sidewall and the inner sidewall) can be trimmed or thinned by the energy of ion implantation during the ion implantation process, while ensuring the isolation and protection of the remaining gate sidewall to the gate structure, so that more polysilicon gate 102 is exposed on the top of the polysilicon gate 102, thereby forming a larger area of metal silicide on the top of the polysilicon gate 102, reducing the gate contact resistance, and at the same time providing a larger process window for the subsequent process of forming a contact hole on the embedded germanium-silicon source-drain, which can save the subsequent process step (such as SPT) of expanding the process window and save costs. On the other hand, the silicide barrier layer around the top of the embedded source-drain can be opened and expanded by the energy of ion implantation during the ion implantation process, so that more area of the substrate around the top of the embedded source-drain is exposed, thereby forming a larger area of metal silicide on the top of the embedded source-drain, reducing the contact resistance of the source-drain region.

[0128] In this embodiment, the germanium-silicon doping layer 107b can be completely or partially consumed to be converted into metal silicide when the metal silicide is formed in step S3.

[0129] It should be understood that the thickness of the germanium-silicon doping layer 107b and the doping concentration of the ions for inhibiting excessive diffusion of metal, germanium, silicon and the like need to be reasonably controlled, both to prevent the doping concentration of the ions for inhibiting excessive diffusion of metal, germanium, silicon and the like from being too high to produce adverse effects, and to prevent the doping concentration of the ions for inhibiting excessive diffusion of metal, germanium, silicon and the like from being too low to achieve the effect of reducing the parasitic resistance of the embedded germanium-silicon source-drain, and also to prevent the thickness of the germanium-silicon doping layer 107b from being too large to cause the distance between the metal silicide formed in the subsequent step S3 and the embedded germanium-silicon source-drain to be too far, the parasitic resistance to increase, and the thickness of the germanium-silicon doping layer 107b to be too small to inhibit the excessive diffusion of germanium, silicon and metal.

[0130] Optionally, the germanium-silicon doped layer 107b formed in the embodiment can be a single layer film structure, or can be a plurality of germanium-silicon layers with different doping concentrations of impurity ions stacked in sequence, and the doping concentrations of the impurity ions in the germanium-silicon layers gradually decrease from bottom to top, which can ensure that the impurity ions do not affect the metal silicide process during the formation of metal silicide between the top of the germanium-silicon doped layer 107b and the metal, and can be beneficial to the formation of more uniform metal silicide. Furthermore, because the closer to the source / drain of silicon germanium, the higher the doping concentration, the better the blocking effect, and the more it can block the movement of elements such as germanium upwards and affect the silicidation process. On this basis, further, if high-temperature annealing in a very short time, such as laser annealing, etc. can be used in the annealing process, it can further prevent the excessive diffusion of doped ions, and the blocking effect of the doped ions that block the diffusion of other ions is better. Especially when high-temperature processes are used in the later stage, and stable metal elements (for example, cobalt, titanium, etc.) must be used to form metal silicide, and these metals are easily affected by elements such as germanium during the silicidation process, and form clusters in the metal silicide, causing serious line width effects. In this case, the gradient setting of the impurity ion concentration in the germanium-free silicon cap layer improves the effect of the line width effect, and by shortening the annealing time, it further helps to reduce the line width effect in this case. At the same time, in this case, the use of a dielectric buffer layer makes it possible to achieve ideal annealing effects such as laser annealing, flash annealing, dynamic surface annealing, etc. Because when high-temperature annealing is used for a very short time, the metal silicidation process or the phase transition process will be more intense, and the intense reaction process is extremely easy to bring about non-uniformity in the reaction process, which in turn leads to non-uniformity of the silicide resistance, affecting the quality. Therefore, when there is a dielectric buffer layer, it can well improve the non-uniformity phenomenon caused by excessive intense reaction, in addition to other benefits brought about by short-time high-temperature, so a more ideal high-quality metal silicide will be obtained.

[0131] Preferably, the germanium-silicon doped layer 107b is free of germanium, or the germanium concentration in the germanium-silicon doped layer 107b gradually decreases from bottom to top, so that the Ge element concentration of the top layer of the germanium-silicon doped layer 107b is very low, thereby reducing the cluster problem and line width effect of the cobalt silicide and other metal silicides formed thereon as much as possible while ensuring good mobility of the device. Preferably, the germanium-silicon doped layer 107b contains a small amount of germanium near the germanium-silicon source / drain, and is free of germanium near the metal silicide, so that the lower layer containing germanium is used to prevent the resistance of the germanium-silicon doped layer 107b from being too large, and the upper layer free of germanium is used to prevent the metal silicide (such as cobalt silicide, etc.) from directly contacting germanium, thereby increasing the distance between the metal silicide and germanium and minimizing the occurrence of cluster problems in the metal silicide.

[0132] Based on this, the embodiment also provides a semiconductor device with metal silicide, which is different from the semiconductor device with metal silicide of the first embodiment in that the semiconductor device with metal silicide of the embodiment further has an embedded germanium-silicon source-drain, ions for inhibiting excessive diffusion of metal, germanium and silicon are doped in the top of the embedded germanium-silicon source-drain, and the metal silicide 110 is formed at least on the top of the embedded germanium-silicon source-drain doped with the ions for inhibiting excessive diffusion of metal, germanium and silicon.

[0133] Compared with the fourth embodiment, the technical solution of the embodiment can form metal silicide with less defects and lower resistance, and the device has higher performance, because ions for inhibiting excessive diffusion of metal, germanium and silicon are doped in the top of the embedded germanium-silicon source-drain.

[0134] Sixth embodiment

[0135] The embodiment provides a manufacturing method of a semiconductor device with metal silicide, which also includes Figure 1 The steps S1-S3 shown.

[0136] Please refer to Figure 7 (A) to (C), the difference between the embodiment and the fifth embodiment is that the step S3 is performed, and after the ions for inhibiting excessive diffusion of metal, germanium, silicon and the like are doped in the top of the embedded germanium-silicon source-drain (i.e., the germanium-silicon doping layer 107b is formed), a pure silicon cap layer 107c is further formed on the top of the embedded germanium-silicon source-drain doped with the ions for inhibiting excessive diffusion of metal, germanium and silicon (i.e., on the top of the germanium-silicon doping layer 107b). The pure silicon cap layer 107c can be single crystal silicon, microcrystalline silicon, polycrystalline silicon, amorphous silicon or a combination of at least two of them.

[0137] In the embodiment, the purposes of forming the germanium-silicon doping layer 107b and the pure silicon cap layer 107c thereon are: (1) to increase the distance between the embedded germanium-silicon source-drain (i.e., 107 in the figure) and the metal layer deposited in the subsequent step S3 within a reasonable range, and to provide the silicon source required for the metal silicide reaction in step S3 by using the pure silicon cap layer 107c, so as to limit the metal silicide reaction in step S3 in the pure silicon cap layer 107c, and reduce the consumption of silicon in the embedded germanium-silicon source-drain in step S3; (2) to increase the distance between the metal silicide and the germanium in the embedded germanium-silicon source-drain, and to use the ions for inhibiting excessive diffusion of metal, germanium and silicon in the germanium-silicon doping layer 107b as a barrier layer for germanium, silicon and metal, so as to reduce the generation of metal silicide clusters and other defect problems in the subsequent step S3 and the subsequent high-temperature process, and to improve the line width effect of the formed metal silicide.

[0138] It should be understood that the thickness of the pure silicon cap layer 107c needs to be reasonably controlled, which is thick enough to ensure that the metal silicide reaction in step S3 is limited in the pure silicon cap layer 107c and the metal silicide 110 with a desired thickness is formed, and is thin enough to avoid the problem that the distance between the formed metal silicide and the embedded germanium-silicon source-drain is too far to cause the increase of the parasitic resistance at the embedded germanium-silicon source-drain. Therefore, according to the formed thickness of the pure silicon cap layer 107c, the pure silicon cap layer 107c can be completely or partially converted into the metal silicide 110 in step S3, and preferably, the pure silicon cap layer 107c is completely converted into the metal silicide 110 to avoid the problem that the distance between the formed metal silicide and the embedded germanium-silicon source-drain is too far to cause the increase of the parasitic resistance at the embedded germanium-silicon source-drain.

[0139] The above description is only a description of the preferred embodiments of the present application, and is not any limitation on the scope of the present application. Any modification or change made by a person skilled in the art according to the above disclosure is within the protection scope of the technical scheme of the present application.

Claims

1. A method for manufacturing a semiconductor device having a metal silicide, characterized in that, include: A substrate with a gate structure formed on its surface is provided; A sidewall dielectric material layer is deposited on the surfaces of the gate structure and the substrate, and the sidewall dielectric material layer is etched to form a first sidewall on the sidewall of the gate structure, and the bottom of the first sidewall is partially removed from the outside to expose more substrate surface on the outside of the gate structure. A metal silicide is formed on the substrate surface exposed outside the gate structure, extending into the bottom region where the first sidewall is side-hollowed out.

2. The manufacturing method as described in claim 1, characterized in that, The first sidewall is an outer sidewall, and an inner sidewall is also formed on the sidewall of the gate structure before the sidewall dielectric material layer is deposited.

3. The manufacturing method as described in claim 2, characterized in that, After the inner sidewalls are formed and before the sidewall dielectric material layer is deposited, LDD ion implantation is performed on the substrates on both sides of the gate structure.

4. The manufacturing method as described in claim 1, characterized in that, The width of the bottom region of the first sidewall that is side-cut out is not greater than 1 / 2 of the line width of the first sidewall, or the line width of the bottom region of the first sidewall that is side-cut out is 5nm to 15nm; and / or, the height of the bottom region of the first sidewall that is side-cut out is not greater than 1 / 2 of the height of the first sidewall.

5. The manufacturing method according to any one of claims 1-4, characterized in that, The step of etching the sidewall dielectric material layer includes: first, performing main etching on the sidewall dielectric material layer in the longitudinal direction to remove the sidewall dielectric material on the top of the gate structure and the substrate to form the first sidewall on the sidewall of the gate structure; then, adjusting the process parameters to perform over-etching on the first sidewall in the transverse direction to side-cut a portion of the bottom of the first sidewall from the outside of the first sidewall.

6. The manufacturing method as described in claim 5, characterized in that, After the main etching and before or after the over-etching, source / drain ion implantation is performed on the substrates on both sides of the gate structure, followed by annealing activation.

7. The manufacturing method according to any one of claims 1-4 or 6, characterized in that, The step of forming metal silicides on the substrate surfaces exposed on both sides of the gate structure includes: first depositing a metal layer on the gate structure and the substrate surfaces exposed on both sides, and performing a first annealing process to form a high-resistivity metal silicide; and performing a second annealing process to transform the metal silicide from a high-resistivity phase to a low-resistivity phase.

8. The manufacturing method as described in claim 7, characterized in that, It also includes at least one of the following steps: (1) After depositing the metal layer and before performing the first annealing process, a capping protective layer is also deposited on the metal layer so that the first annealing process is performed under the cover of the capping protective layer. (2) After depositing the metal layer and before performing the first annealing process, a capping protective layer and a dielectric buffer layer are deposited sequentially on the metal layer so that the first annealing process is performed under the cover of the dielectric buffer layer or the first annealing process and the second annealing process are performed under the cover of the dielectric buffer layer. (3) After the first annealing process is completed and before the second annealing process is performed, the unreacted metal layer is removed and a dielectric buffer layer is further deposited on the metal silicide so that the second annealing process is performed under the cover of the dielectric buffer layer. (4) After the second annealing process is completed, and before the contact etching stop layer is deposited, a third annealing process is performed; (5) Before depositing the metal layer, the substrate on both sides of the gate structure is etched to form source drain trenches extending into the substrate exposed by the bottom region where the first sidewall is side-cut away, and then embedded germanium silicon source drains are epitaxially grown in the source drain trenches. (6) Before depositing the metal layer, a silicide barrier layer is deposited on the substrate, the first sidewall and the gate structure, and the silicide barrier layer is photolithographically and etched to define the area to be formed of metal silicide, the area to be formed of metal silicide including the substrate area exposed by the bottom area of ​​the first sidewall being side-cut away.

9. The manufacturing method as described in claim 8, characterized in that, Embedded germanium-silicon source drains are formed in the substrates on both sides of the gate structure. The area where the metal silicide is to be formed also includes the top of the embedded germanium-silicon source drain and the top of the gate structure. After the silicide barrier layer is etched and before the metal silicide is formed, ion implantation is performed on the embedded germanium-silicon source drain to suppress excessive diffusion of metal, germanium, and silicon, while reducing the top of the sidewalls on the sidewalls of the gate structure to expose more of the top of the gate structure.

10. The manufacturing method as described in claim 8 or 9, characterized in that, Embedded germanium-silicon source drains are formed in the substrates on both sides of the gate structure. Before forming the metal silicide, a pure silicon capping layer is formed on top of the embedded germanium-silicon source drain. The metal silicide is formed on the surface of the pure silicon capping layer. The pure silicon capping layer includes at least one of polycrystalline silicon, microcrystalline silicon, and monocrystalline silicon.

11. The manufacturing method as described in claim 8, characterized in that, At least one of the second annealing process, the third annealing process, is flash annealing, laser spike annealing, or dynamic surface annealing.

12. A semiconductor device having a metal silicide, characterized in that, include: Substrate; A gate structure is formed on a portion of the surface of the substrate; A first sidewall is formed on the sidewall of the gate structure, and a portion of its bottom is side-cut away to expose more substrate surface outside the gate structure. Metal silicides are formed at least on the substrate surface exposed outside the gate structure and extend into the bottom region where the first sidewall is side-hollowed out.

13. The semiconductor device as claimed in claim 12, characterized in that, It also includes at least one of the following features: (1) The first sidewall is an outer sidewall, and an inner sidewall is also formed between the first sidewall and the sidewall of the gate structure; (2) LDD ion implantation regions and source / drain regions are formed in the substrates on both sides of the gate structure; (3) Source drain grooves are formed in the substrates on both sides of the gate structure, extending to the bottom region of the first sidewall that is exposed by side cutting, and embedded germanium-silicon source drains are epitaxially grown in the source drain grooves, and the metal silicide is formed at least on the top of the embedded germanium-silicon source drain.

14. The semiconductor device as claimed in claim 12, characterized in that, The width of the bottom area of ​​the first sidewall that is side-cut away is not greater than 1 / 2 of the line width of the first sidewall, and / or the height of the bottom area of ​​the first sidewall that is side-cut away is not greater than 1 / 2 of the height of the outer sidewall.

15. The semiconductor device as claimed in claim 12, characterized in that, The top of the embedded germanium-silicon source / drain is doped with ions to suppress excessive diffusion of metal, germanium, and silicon; and / or, a pure silicon capping layer is formed on the top of the embedded germanium-silicon source / drain, and the metal silicide is formed at least on the pure silicon capping layer, wherein the pure silicon capping layer includes at least one of polycrystalline silicon, microcrystalline silicon, and monocrystalline silicon.

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