InGaAsP SPAD dead pixel inhibition structure based on deep isolation groove tungsten plug and preparation method thereof

Abstract

The invention discloses an InGaAsP SPAD dead pixel suppression structure based on a deep isolation groove tungsten plug. The InGaAsP SPAD dead pixel suppression structure comprises a heteroepitaxial material which sequentially grows on an n + type InP substrate in an epitaxial mode, wherein the heteroepitaxial material comprises an n + type InGaAs etching cut-off layer, an n + type InP contact layer, an i type InGaAsP absorption layer, an n + type InGaAsP electric field modification layer, an n + type InP charge layer, an i type InP multiplication layer and an n type InGaAsP contact layer and is provided with an absorption multiplication separation structure; a Geiger avalanche diode pixel with a Zn doped region is formed on a heteroepitaxial material, a deep isolation groove is prepared around the pixel, a tungsten plug is prepared in the deep isolation groove for filling, an N electrode is prepared on the surface of a tungsten plug filling region, a P electrode is prepared on the surface of the Zn doped region, and the P electrode and the N electrode are coplanarly led to a readout circuit. Electrical isolation is carried out through a switch channel of the reading circuit, and dead pixel suppression is realized. According to the invention, the independent turn-off of the pixels is realized through the switch, and the inhibition effect on very few dead pixels is effectively enhanced.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor optoelectronic device technology, and relates to an InGaAsPSPAD bad spot suppression structure based on deep isolation trench tungsten plugs and its preparation method. Background Technology

[0002] Single-photon detection (SPD) represents the pinnacle of photoelectric detection technology, enabling not only the measurement of individual photons but also the measurement of weak pulse signals at the energy level of a single photon. Its core component is the single-photon detector, which primarily includes vacuum multiplier, photovoltaic, and photoconductive types. Among these, semiconductor avalanche photodiodes (APDs), which periodically operate above their breakdown voltage, offer advantages such as high gain, high sensitivity, all-solid-state operation, high integration, small size, low power consumption, high repeatability, and high reliability. They are currently the most commonly used single-photon detection solution, and APDs with single-photon detection capabilities are called single-photon avalanche photodiodes (SPADs).

[0003] SPAD materials are primarily designed for different laser wavelengths. For example, silicon (Si) semiconductor materials can cover laser wavelengths such as 532nm and 905nm, while indium gallium arsenide (InGaAs) semiconductor materials can cover laser wavelengths such as 1064nm and 1550nm. Si-based SPADs cover the visible-near-infrared band and can be used for on-chip integration with Si CMOS circuits, while InGaAs-based SPADs cover the near-infrared to short-wave infrared band and are mainstream devices for single-photon laser communication, short-wave infrared imaging, and human eye safety detection. Among them, InGaAsP SPADs using InGaAsP material as the absorption layer enhance absorption at the 1064nm wavelength.

[0004] InGaAsP SPADs can be used for laser pulse time-of-flight detection and photon counting detection. Multiple SPADs can be arranged in a specific pattern on the same substrate to form a focal plane array, thereby realizing laser three-dimensional imaging or photon counting imaging. The technical advantages of laser focal plane detectors fabricated using InGaAsP SPADs are as follows: First, they enable the detection of weak signals from distant targets through single-photon detection technology; second, they enable target planar information imaging through focal plane technology; third, they enable the acquisition of target distance information through high-resolution laser measurement technology; and fourth, they enable high-resolution three-dimensional imaging of targets through comprehensive information processing technology.

[0005] However, current InGaAsP SPADs also suffer from the challenges of controlling the epitaxial growth of InGaAsP materials and the presence of numerous defect centers. This makes it difficult for InGaAsP SPAD-fabricated laser focal plane detectors to achieve high performance consistency and high effective pixel rate, and pixels are prone to defects. Especially when the pixel spacing of InGaAsP SPADs is small, traditional defect suppression structures and methods, such as guard rings, face significant design difficulties due to the lack of suitable spatial locations. Once defects appear, the entire InGaAsP SPAD laser focal plane detector will not be able to operate normally because of the presence of current short-circuit paths. Summary of the Invention

[0006] (I) Purpose of the Invention

[0007] The purpose of this invention is to provide a defect suppression structure and preparation method for InGaAsP SPAD based on deep isolation groove tungsten plugs, which solves the problem that damage to a single pixel in an InGaAsP SPAD affects the normal operation of adjacent pixels or the overall normal operation of the InGaAsP SPAD. By designing a deep isolation groove tungsten plug structure, physical and electrical isolation are achieved, effectively strengthening the redundancy design of the InGaAsP SPAD for a very small number of occasional defects when operating in extreme environments such as high radiation and high overload.

[0008] (II) Technical Solution

[0009] To address the aforementioned technical problems, this invention provides an InGaAsP SPAD bad pixel suppression structure and fabrication method based on deep isolation trench tungsten plugs. Firstly, a deep isolation trench structure is used, etched from the front of the chip to the n+ type InP contact layer, to achieve physical isolation between pixels, solving the problem of a damaged pixel affecting adjacent normal pixels. Secondly, a tungsten plug process is introduced, combined with optimized structural design such as the n+ type InP contact layer and the n+ type InGaAs etching cutoff layer. After removing the substrate, the N electrode is led to the front of the chip, and both the N and P electrodes are connected to the readout circuit. Once a pixel is damaged, the specific location can be determined through the readout circuit, and the readout circuit channel can be actively shut down to achieve electrical isolation, solving the problem of a damaged pixel affecting the normal operation of the InGaAsP SPAD. Ultimately, this effectively improves the bad pixel suppression capability of the InGaAsP SPAD, helping to minimize the extreme impact of newly added bad pixels in special working environments on device failure, meeting the single-photon detection requirements in fields such as precision imaging, near-field sensing, and target detection.

[0010] Specifically, the InGaAsP SPAD bad spot suppression structure based on deep isolation trench tungsten plugs of the present invention includes: a heteroepitaxial material with an absorption multiplication separation structure, which is sequentially epitaxially grown on an n+ type InP substrate 1, including an n+ type InGaAs etching stop layer 2, an n+ type InP contact layer 3, an i type InGaAsP absorption layer 4, an n+ type InGaAsP electric field modification layer 5, an n+ type InP charge layer 6, an i type InP multiplication layer 7, and an n type InGaAsP contact layer 8; a Geiger avalanche diode pixel with a Zn-doped region is formed on the heteroepitaxial material, a deep isolation trench is prepared around the pixel, a tungsten plug is prepared and filled in the deep isolation trench, an N electrode is prepared on the surface of the tungsten plug filling region, a P electrode is prepared on the surface of the Zn-doped region, the P electrode and the N electrode are coplanar and led to the readout circuit, and electrical isolation is achieved through the switching channel of the readout circuit to achieve bad spot suppression.

[0011] This invention also provides a method for preparing an InGaAsP SPAD bad spot suppression structure based on a deep isolation groove tungsten plug, which includes the following steps:

[0012] The first step involves epitaxially growing an n+ type InGaAs etching stop layer 2, an n+ type InP contact layer 3, an i-type InGaAsP absorption layer 4, an n+ type InGaAsP electric field modification layer 5, an n+ type InP charge layer 6, an i-type InP multiplication layer 7, and an n-type InGaAsP contact layer 8 sequentially on an n+ type InP substrate 1 using molecular beam epitaxy and metal-organic chemical vapor deposition (MOCVD) to form a heteroepitaxial material structure.

[0013] The second step involves using a metal-organic chemical vapor deposition (MOCVD) device on the heteroepitaxial material structure to diffuse out Zn-doped regions 9 through a selective diffusion process, thereby forming Geiger avalanche diode pixels.

[0014] The third step involves using an ICP plasma etching device and a dry etching process to prepare a deep isolation trench 10 around the Zn doped region 9 of the Geiger avalanche diode pixel. The deep isolation trench 10 is etched into the n+ type InP contact layer 3.

[0015] The fourth step involves using a plasma-enhanced chemical vapor deposition (PECVD) system to prepare a SiNx passivation layer 11 on the sidewall of the deep isolation trench 10 and the surface of the Zn-doped region 9 via a passivation process.

[0016] The fifth step involves using an atomic layer deposition (ALD) device to prepare a tungsten seed layer on the sidewall of the deep isolation tank 10 through an ALD process.

[0017] The sixth step involves using a plasma-enhanced chemical vapor deposition (PECVD) device to slowly deposit tungsten elements in the deep isolation tank 10 via chemical vapor deposition, thereby preparing a tungsten plug and forming a tungsten plug filling area 12.

[0018] Step 7: Using an electron beam evaporation device, P electrode 13 is prepared on the surface of Zn doped region 9 and N electrode 14 is prepared on the surface of tungsten plug-filled region 12 through photolithography and metal film deposition processes.

[0019] Step 8: In column evaporation deposition equipment is used to prepare In column 15 on P electrode 13 and N electrode 14;

[0020] The ninth step involves using flip-chip bonding equipment and indium pillar flip-chip interconnect technology to achieve interconnection and integration between the photosensitive chip and the readout circuit 17.

[0021] Step 10: Using a dispensing machine, fill the space between the photosensitive chip and the readout circuit 17 with filler glue 16 through a bottom filling process.

[0022] Step 11: After the filler adhesive 16 has cured, a dry etching combined with wet etching process is used. The n+ type InGaAs etching stop layer 2 is used as a sacrificial layer to remove the n+ type InP substrate 1, so that the n+ type InP contact layer 3 is connected to the N electrode 14 through the tungsten plug filling area 12, forming the connection between the P electrode 13 and the N electrode 14 and the readout circuit 17.

[0023] Step 12: On the interconnected chip surface, attach a microlens array 18 externally.

[0024] Furthermore, in the second step, the Zn doped region 9 is a 128×128 array with a junction diameter of 10μm and a pixel pitch of 30μm.

[0025] Furthermore, in the third step, the depth of the deep isolation trench 10 is 10 μm.

[0026] Furthermore, in the fourth step, the thickness of the SiNx passivation layer 11 is 0.2 μm to 1 μm.

[0027] Furthermore, in the fifth step, the thickness of the tungsten seed layer does not exceed 10 nm.

[0028] Furthermore, in step six, the tungsten embolization filling zone 12 has a height of 10 μm.

[0029] Furthermore, in step seven, the thickness of P electrode 13 is 2 μm.

[0030] Furthermore, in step seven, the thickness of the N electrode 14 is 2 μm.

[0031] Furthermore, in step eight, the In column is 15 μm high.

[0032] (III) Beneficial Effects

[0033] The InGaAsP SPAD bad spot suppression structure and preparation method based on deep isolation groove tungsten plugs provided by the above technical solution have the following beneficial effects:

[0034] (1) On an n+ type InP substrate, multilayer heteroepitaxial materials such as indium gallium arsenide phosphide, indium gallium arsenide, and indium phosphide with absorption multiplication separation structure are epitaxially grown. Pixels with extremely small spacing are selectively diffused. Deep isolation trenches are etched around the pixels and tungsten plugs are prepared for complete filling. After removing the substrate, the light absorption effect of the substrate is reduced. The P electrode and N electrode are connected to the readout circuit. The pixels are turned off independently by switching, which effectively enhances the suppression of a very small number of bad pixels.

[0035] (2) Based on molecular beam epitaxy and metal-organic chemical vapor deposition, a novel multifunctional layer epitaxial material is prepared. The method of designing deep isolation grooves around the pixels and filling them with tungsten plugs is adopted to achieve physical isolation between pixels, eliminate electrical crosstalk between pixels, and help solve the problem of the impact of a damaged pixel on the normal operation of adjacent pixels. At the same time, with the readout circuit switch, electrical isolation between pixels is achieved, which facilitates the independent operation of pixels and also helps to solve the problem that the damage of a certain pixel will not lead to the failure of the whole InGaAsP SPAD. This effectively strengthens the redundancy design of the InGaAsP SPAD laser focal plane detector, improves the ability to suppress bad pixels, and meets the needs of single-photon precision imaging, close-range sensing, and target detection in special working environments.

[0036] (3) Innovatively, based on a novel multilayer epitaxial material structure, a deep isolation trench is designed and prepared around the InGaAsP SPAD pixel, and a tungsten plug is prepared by a secondary filling process combining atomic layer deposition and chemical vapor deposition, so as to finally achieve physical and electrical isolation between pixels based on readout circuit control.

[0037] (4) This invention can provide a reference for the design and fabrication of InGaAsP SPADs with high pixel density, large array size and special extreme environment operation. The near-infrared single-photon laser focal plane detector developed according to this invention based on the InGaAsP SPAD bad spot suppression structure with deep isolation groove tungsten plug has achieved effective suppression and independent isolation of new bad spots. This method is practical and feasible. Attached Figure Description

[0038] Figures 1 to 4 This is a schematic diagram illustrating the formation process of the InGaAsP SPAD bad spot suppression structure based on deep isolation groove tungsten plugs in an embodiment of the present invention. Detailed Implementation

[0039] To make the objectives, contents, and advantages of the present invention clearer, the specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.

[0040] Example 1

[0041] This embodiment utilizes a deep-isolation trench tungsten plug-based InGaAsP SPAD bad pixel suppression structure. Molecular beam epitaxy and metal-organic chemical vapor deposition (MOCVD) are employed to sequentially epitaxially grow a heteroepitaxial material with an absorption multiplication separation (SACGM) structure, comprising InGaAsP, InGaAs, and InP multifunctional layers, on an InP substrate. Selective diffusion is used to fabricate a Geiger avalanche diode with extremely small pixel pitch. Dry etching is used to create deep isolation trenches around the pixels for physical isolation. Tungsten plugs are then prepared using atomic layer deposition (ALD) and chemical vapor deposition (CVD) for filling. After substrate removal, the P and N electrodes are coplanarly led to the readout circuit, and electrical isolation is achieved through the switching channel of the readout circuit.

[0042] In this embodiment of the defect suppression structure, deep isolation trenches are etched around each pixel on the InGaAsP SPAD, and tungsten plugs are filled in the deep isolation trenches. The P electrode and N electrode are coplanar and are both connected to the integrated circuit. The integrated circuit controls the independent operation of the pixels to achieve defect suppression.

[0043] Example 2

[0044] This embodiment is based on the preparation method of InGaAsP SPAD bad spot suppression structure with deep isolation trench tungsten plug. A 3-inch n+ type InP substrate is used as the substrate, and a multilayer heteroepitaxial material with absorption multiplication separation structure is epitaxially grown.

[0045] Reference Figures 1 to 4 The method in this embodiment includes the following steps:

[0046] The first step involves using a metal-organic chemical vapor deposition (MOCVD) device to perform epitaxial processes on an n+ type InP substrate 1. This process involves sequentially epitaxially depositing an n+ type InGaAs etching stop layer 2, an n+ type InP contact layer 3, an i-type InGaAsP absorber layer 4, an n+ type InGaAsP electric field modification layer 5, an n+ type InP charge layer 6, an i-type InP multiplication layer 7, and an n-type InGaAsP contact layer 8.

[0047] The second step involves using a metal-organic chemical vapor deposition (MOCVD) device and selective diffusion process to diffuse out a Zn-doped region 9 with an array size of 128×128, a junction diameter of 10μm, and a pixel pitch of 30μm, forming Geiger avalanche diode pixels with extremely small pixel pitch.

[0048] The third step involves using an ICP plasma etching device and a dry etching process to create a deep isolation trench 10 of about 10 μm around the Zn-doped region 9 of the Geiger avalanche diode pixel, which is then directly etched into the n+ type InP contact layer 3.

[0049] The fourth step involves using a plasma-enhanced chemical vapor deposition (PECVD) system to prepare a 0.2 μm to 1 μm thick SiNx passivation layer 11 on the sidewall of the deep isolation trench 10 and the surface of the Zn doped region 9 via a passivation process.

[0050] The fifth step involves using an atomic layer deposition (ALD) device to prepare a tungsten seed layer with a thickness of no more than 10 nm on the sidewall of the deep isolation trench 10 through an ALD process.

[0051] The sixth step involves using a plasma-enhanced chemical vapor deposition (PECVD) device to slowly deposit tungsten elements in a deep isolation tank 10 via chemical vapor deposition, thereby preparing a tungsten plug and forming a 10 μm tungsten plug filling region 12.

[0052] Step 7: Using an electron beam evaporation device, a 2μm thick layer of Au element is prepared on the surface of the Zn doped region 9 as a P electrode 13 through photolithography and metal film deposition processes, and a 2μm thick layer of Au element is prepared on the surface of the tungsten plug-filled region 12 as an N electrode 14.

[0053] Step 8: Using an indium column evaporation deposition apparatus, prepare 15μm high In columns 15.

[0054] The ninth step involves using flip-chip bonding equipment and indium pillar flip-chip interconnection technology to achieve interconnection and integration between the photosensitive chip and the readout circuit 17.

[0055] Step 10: Using a dispensing machine, fill the space between the photosensitive chip and the readout circuit 17 with filler glue 16 through a bottom filling process.

[0056] In the eleventh step, after the filler adhesive 16 has cured, a dry etching combined with wet etching process is used. The n+ type InGaAs etching stop layer 2 is used as a sacrificial layer to completely remove the n+ type InP substrate 1, thereby realizing the connection between the n+ type InP contact layer 3 and the N electrode 14 through the tungsten plug filling area 12, forming an effective connection between the P electrode and the N electrode and the readout circuit 17.

[0057] Step 12: On the interconnected chip surface, a high-precision coupling process is used to attach a microlens array 18 externally to improve the effective fill factor.

[0058] According to the test and evaluation, the InGaAsP SPAD bad spot suppression structure fabrication method based on deep isolation trench tungsten plugs described in this invention, based on a 3-inch n+ type InP substrate wafer, fabricated an InGaAsP SPAD laser focal plane detector with an array size of 128×128, which achieved high-precision laser three-dimensional imaging of 1064nm near-infrared laser wavelength, and realized effective suppression and independent isolation of newly added bad spots.

[0059] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A bad spot suppression structure for InGaAsP SPAD based on deep isolation groove tungsten plugs, characterized in that, include: A heteroepitaxial material with an absorption multiplication separation structure, comprising an n+ type InGaAs etch stop layer (2), an n+ type InP contact layer (3), an i-type InGaAsP absorption layer (4), an n+ type InGaAsP electric field modification layer (5), an n+ type InP charge layer (6), an i-type InP multiplication layer (7), and an n-type InGaAsP contact layer (8), is epitaxially grown sequentially on an n+ type InP substrate (1). A Geiger avalanche diode pixel with a Zn-doped region is formed on the heteroepitaxial material. A deep isolation trench is prepared around the pixel, and a tungsten plug is prepared and filled in the deep isolation trench. An N electrode is prepared on the surface of the tungsten plug filling region, and a P electrode is prepared on the surface of the Zn-doped region. The P electrode and the N electrode are coplanar and led to the readout circuit. Electrical isolation is achieved through the switching channel of the readout circuit to suppress bad pixels.

2. A method for preparing an InGaAsP SPAD bad spot suppression structure based on a deep isolation groove tungsten plug, characterized in that, Includes the following steps: The first step involves epitaxially growing an n+ type InGaAs etch stop layer (2), an n+ type InP contact layer (3), an i-type InGaAsP absorption layer (4), an n+ type InGaAsP electric field modification layer (5), an n+ type InP charge layer (6), an i-type InP multiplication layer (7), and an n-type InGaAsP contact layer (8) sequentially on an n+ type InP substrate (1) using molecular beam epitaxy and metal-organic chemical vapor deposition (MOCVD) processes, thereby forming a heteroepitaxial material structure. The second step is to use a metal-organic chemical vapor deposition device on the heteroepitaxial material structure to diffuse out the Zn doped region (9) through a selective diffusion process to form Geiger avalanche diode pixels. The third step is to use ICP plasma etching equipment and dry etching process to prepare a deep isolation trench (10) around the Zn doped region (9) of the Geiger avalanche diode pixel. The deep isolation trench (10) is etched to the n+ type InP contact layer (3). The fourth step involves using a plasma-enhanced chemical vapor deposition (PECVD) device to prepare a SiNx passivation layer (11) on the sidewall of the deep isolation trench (10) and the surface of the Zn doped region (9) through a passivation process. The fifth step involves using an atomic layer deposition (ALD) device to prepare a tungsten seed layer on the sidewall of the deep isolation trench (10) through an ALD process. The sixth step involves using a plasma-enhanced chemical vapor deposition (PECVD) device to slowly deposit tungsten elements in a deep isolation tank (10) through chemical vapor deposition, thereby preparing a tungsten plug and forming a tungsten plug filling area (12). Step 7: Using an electron beam evaporation device, a P electrode (13) is prepared on the surface of the Zn doped region (9) and an N electrode (14) is prepared on the surface of the tungsten plug-filled region (12) by photolithography and metal film deposition process. Step 8: In column (15) is prepared on P electrode (13) and N electrode (14) using an indium column evaporation deposition apparatus; The ninth step involves using flip-chip bonding equipment and indium pillar flip-chip interconnection technology to achieve interconnection and integration between the photosensitive chip and the readout circuit (17); Step 10: Using a dispensing machine, fill the space between the photosensitive chip and the readout circuit (17) with filler glue (16) through a bottom filling process; In the eleventh step, after the filler adhesive (16) has cured, a dry etching combined with wet etching process is used to remove the n+ type InP substrate (1) by using the n+ type InGaAs etching stop layer (2) as a sacrificial layer, thereby realizing the n+ type InP contact layer (3) to be connected to the N electrode (14) through the tungsten plug filling area (12), forming the connection between the P electrode (13) and the N electrode (14) and the readout circuit (17). Step 12: On the interconnected chip surface, attach a microlens array (18).

3. The method for preparing the InGaAsP SPAD bad spot suppression structure based on deep isolation groove tungsten plugs according to claim 2, characterized in that, In the second step, the Zn doped region (9) is a 128×128 array with a junction diameter of 10μm and a pixel pitch of 30μm.

4. The method for preparing the InGaAsP SPAD bad spot suppression structure based on deep isolation groove tungsten plugs according to claim 3, characterized in that, In the third step, the depth of the deep isolation trench (10) is 10μm.

5. The method for preparing the InGaAsP SPAD bad spot suppression structure based on deep isolation groove tungsten plugs according to claim 4, characterized in that, In the fourth step, the SiNx passivation layer (11) has a thickness of 0.2 μm to 1 μm.

6. The method for preparing the InGaAsP SPAD bad spot suppression structure based on deep isolation trench tungsten plugs according to claim 5, characterized in that, In the fifth step, the thickness of the tungsten seed layer does not exceed 10 nm.

7. The method for preparing the InGaAsP SPAD bad spot suppression structure based on deep isolation trench tungsten plugs according to claim 6, characterized in that, In step six, the height of the tungsten plug filling area (12) is 10 μm.

8. The method for preparing the InGaAsP SPAD bad spot suppression structure based on deep isolation groove tungsten plugs according to claim 7, characterized in that, In step 7, the thickness of the P electrode (13) is 2 μm.

9. The method for preparing the InGaAsP SPAD bad spot suppression structure based on deep isolation groove tungsten plugs according to claim 8, characterized in that, In step seven, the thickness of the N electrode (14) is 2 μm.

10. The method for preparing the InGaAsP SPAD bad spot suppression structure based on deep isolation groove tungsten plugs according to claim 9, characterized in that, In step 8, the In column (15) is 15 μm high.

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