A method for manufacturing a battery cell and a battery cell

Abstract

A preparation method of a battery piece and the battery piece belong to the technical field of photovoltaics. The preparation method of the battery piece at least comprises: providing a wire-cut silicon wafer, the silicon wafer comprising a wire mark area and a non-wire mark area; preparing a plurality of spaced grooves on the front surface of the silicon wafer by laser, and the density of the grooves located in the middle of the silicon wafer is greater than the density of the grooves located at the edge of the silicon wafer; pre-cleaning the silicon wafer; and etching the surface of the silicon wafer by using an etching solution to prepare a textured surface on the surface of the silicon wafer. When texturing, the grooves are beneficial to increase the contact area of the etching solution and the silicon wafer, so that the contact area of the middle of the silicon wafer with the etching solution is greater than the contact area of the edge of the silicon wafer with the etching solution, the reaction rate of the etching solution in the middle of the silicon wafer is improved, the reaction rate of the etching solution in the middle of the silicon wafer and the reaction rate of the etching solution at the edge of the silicon wafer are close to the same, the size difference of the pyramid structures prepared at each position of the surface of the silicon wafer is smaller, and thus a uniform textured surface is prepared on the silicon wafer, and the light trapping property of the battery piece is improved.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic technology, and in particular to a method for preparing a solar cell and the solar cell itself. Background Technology

[0002] Currently, the surface of solar cells is typically textured, usually with a pyramidal structure. This structure effectively reduces the reflectivity of the cell surface and improves light trapping performance. During textured fabrication, anisotropic etching is usually performed on the silicon wafer surface to obtain randomly distributed pyramidal structures. However, the sizes of these random pyramidal structures on the silicon wafer surface often vary, resulting in poor texture uniformity and affecting the light trapping effect of the solar cell. Summary of the Invention

[0003] This application provides a method for preparing a solar cell and a solar cell, which solves the problem of poor uniformity of the textured surface of the solar cell, affecting the light trapping effect of the solar cell.

[0004] The first aspect of this application provides a method for preparing a solar cell, the method comprising at least:

[0005] A wire-cut silicon wafer is provided, the silicon wafer including a wire-cut area and a non-wire-cut area;

[0006] Multiple spaced trenches are laser-fabricated on the front side of the silicon wafer, and the density of the trenches located in the middle of the silicon wafer is greater than the density of the trenches located at the edge of the silicon wafer.

[0007] Pre-clean the silicon wafer;

[0008] The surface of the silicon wafer is etched using an etching solution to create a textured surface on the silicon wafer.

[0009] Specifically, during the etching process on the silicon wafer surface, the etching solution can etch multiple pyramidal structures, thus forming a textured surface. By first laser-fabricating multiple spaced trenches on the front side of the silicon wafer, with the trench density in the center of the wafer being greater than that at the edges, the texturing process utilizes these trenches to increase the contact area between the etching solution and the silicon wafer. This increases the contact area between the center and the etching solution compared to the edges, improving the reaction rate of the etching solution in the center. Consequently, the reaction rate in the center and at the edges becomes closer to the same, resulting in smaller size differences among the pyramids on the wafer surface and smaller morphological differences in the pyramid structures at different locations. This creates a more uniform textured surface, reduces reflectivity, improves the light-trapping properties of the solar cell, and ultimately enhances its photoelectric conversion efficiency.

[0010] In this design, the trench is located within the trace area, and the extension direction of the trench is the same as the direction of the trace on the silicon wafer surface.

[0011] In this scheme, the dimension H of the trench along the thickness direction of the silicon wafer satisfies: 0.1um ≤ H ≤ 0.5um.

[0012] In this scheme, the dimension D of the trench along the length direction of the battery cell satisfies: 0.6um≤D≤1.6um.

[0013] In this scheme, after pre-cleaning the silicon wafer and before etching the surface of the silicon wafer with the etching solution, the method for preparing the solar cell includes the following steps:

[0014] The silicon wafer is subjected to alkaline washing using an alkaline washing solution comprising a first sodium hydroxide solution and a first deionized water. The concentration Q1 of the first sodium hydroxide solution satisfies: 10wt%≤Q1≤60wt%, the amount M1 of the first sodium hydroxide solution satisfies: 4L≤M1≤24L, and the amount M2 of the first deionized water satisfies: 680L≤M2≤710L.

[0015] In this scheme, the alkaline washing temperature T1 satisfies: 50℃≤T1≤70℃, and the alkaline washing time S1 satisfies: 30s≤S1≤120s.

[0016] In this scheme, after the silicon wafer is alkaline washed and before the surface of the silicon wafer is etched using the etching solution, the method for preparing the solar cell includes:

[0017] The silicon wafer is washed with water.

[0018] In this scheme, the etching solution performs anisotropic etching on the surface of the silicon wafer. The etching solution includes a second sodium hydroxide solution, a second deionized water, and an additive. The concentration Q2 of the second sodium hydroxide solution satisfies: 10wt%≤Q2≤60wt%, the amount C1 of the second sodium hydroxide solution satisfies: 2L≤C1≤10.5L, the amount C2 of the additive satisfies: 1L≤C2≤4.5L, and the amount C3 of the second deionized water satisfies: 680L≤C3≤710L.

[0019] The etching temperature T2 satisfies: 75℃≤T2≤90℃, and the etching time S2 satisfies: 200s≤S2≤600s.

[0020] In this scheme, after texturing the surface of the silicon wafer, the method for preparing the solar cell includes:

[0021] The silicon wafer is washed with water;

[0022] The silicon wafer is then post-cleaned;

[0023] The silicon wafer is washed with water;

[0024] The silicon wafer is acid-washed;

[0025] The silicon wafer is washed with water;

[0026] Slowly pull up the silicon wafer;

[0027] The silicon wafer is dried.

[0028] The second aspect of this application provides a battery cell, which is prepared by the battery cell preparation method described above;

[0029] The battery cell includes a textured surface, which includes multiple pyramid structures. The base side length L of the pyramid structure satisfies: 1um ≤ L ≤ 2.5um, and the height F of the pyramid structure satisfies: 0.5um ≤ F ≤ 2um.

[0030] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit this application. Attached Figure Description

[0031] Figure 1 A flowchart illustrating a specific embodiment of the method for preparing the battery cell provided in this application;

[0032] Figure 2 This is a schematic diagram of the structure in which the grooves are formed in the battery cell provided in this application during the manufacturing process;

[0033] Figure 3 A cross-sectional view of the trenches formed during the fabrication process of the battery cell provided in this application;

[0034] Figure 4 for Figure 3 A magnified view of part A in the middle;

[0035] Figure 5 A schematic diagram of the structure of the suede surface provided in this application in a specific embodiment;

[0036] Figure 6 (a) is a scanning electron microscope image of the surface morphology of the silicon wafer prepared using conventional solar cell preparation methods in Comparative Example 1.

[0037] Figure 6 (b) is a scanning electron microscope image of the surface morphology of the silicon wafer prepared using the method for preparing solar cells provided in this application in Example 1, wherein, Figure 6 (a) and Figure 6 (b) is a scanning electron microscope image obtained at the same magnification using the same scanning device.

[0038] Explanation of reference numerals in the attached figures:

[0039] 1-Battery cell;

[0040] 11-Silicon wafer;

[0041] 111 - Groove;

[0042] 112 - Line Mark Area;

[0043] 113 - Non-line mark area;

[0044] 114 - Pyramid structure.

[0045] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. Detailed Implementation

[0046] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0047] In one specific embodiment, the present application will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0048] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0049] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0050] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0051] It should be noted that the directional terms such as "upper," "lower," "left," and "right" described in the embodiments of this application are used to describe the angles shown in the accompanying drawings and should not be construed as limiting the embodiments of this application. Furthermore, in the context, it should be understood that when it is mentioned that an element is connected "upper" or "lower" to another element, it can be directly connected to the other element "upper" or "lower," or indirectly connected to the other element "upper" or "lower" through an intermediate element.

[0052] Currently, during the fabrication of solar cells, when texturing silicon wafers, the etching solution tends to form turbulence and convection at the edges of the wafer. Furthermore, byproducts generated during etching at the edges are quickly carried away by the etching solution, while these byproducts tend to accumulate on the central surface of the wafer. This affects the reaction rate between the etching solution and the central surface of the wafer, resulting in a lower reaction rate between the etching solution and the edges. Consequently, the uniformity of the textured surface on the wafer is poor, impacting the performance of the solar cells.

[0053] To address the aforementioned problems, this application provides a method for preparing battery cell 1, such as... Figure 1 , Figure 2 , Figure 4 , Figure 5 and Figure 6 As shown in (b), the method for preparing the solar cell 1 includes at least the following:

[0054] S1: Provides a wire-cut silicon wafer 11, which includes a wire-cut area 112 and a non-wire-cut area 113.

[0055] S2: Multiple grooves 111 are laser-fabricated on the front side of silicon wafer 11 at intervals, and the density of the grooves 111 located in the middle of silicon wafer 11 is greater than the density of the grooves 111 located at the edge of silicon wafer 11.

[0056] S3: Pre-cleaning silicon wafer 11. Pre-cleaning can remove organic residues and contaminants from the surface of silicon wafer 11 and repair mechanical damage to the surface of silicon wafer 11, which is beneficial for the subsequent preparation of a uniform textured surface on the surface of silicon wafer 11.

[0057] S4: Use an etching solution to etch the surface of the silicon wafer 11, that is, both the front and back sides of the silicon wafer 11 can be etched to create a textured surface on both the front and back sides of the silicon wafer 11.

[0058] Specifically, during the etching process of the etching solution on the surface of the silicon wafer 11, the etching solution can etch multiple pyramid structures 114 on the surface of the silicon wafer 11, thereby forming a textured surface. In step S2, multiple spaced trenches 111 are first laser-fabricated on the front side of the silicon wafer 11, with the density of trenches 111 in the middle of the silicon wafer 11 being greater than that at the edge of the silicon wafer 11. Then, in the subsequent step S4 texturing, the presence of these trenches increases the contact area between the etching solution and the silicon wafer 11, making the contact area between the middle of the silicon wafer 11 and the etching solution greater than that at the edge of the silicon wafer 11. This improves the reaction rate of the etching solution in the middle of the silicon wafer 11, making the reaction rate in the middle of the silicon wafer 11 nearly the same as that at the edge of the silicon wafer 11. This results in smaller size differences in the pyramid structures 114 fabricated at different locations on the surface of the silicon wafer 11, and smaller morphological differences in the pyramid structures 114 at different locations on the silicon wafer 11. This creates a more uniform textured surface on the silicon wafer 11, reduces the reflectivity of the textured surface, improves the light-trapping properties of the solar cell 1, and ultimately improves the photoelectric conversion efficiency of the solar cell 1.

[0059] Meanwhile, the method of preparing trenches 111 by laser and then etching to create texturing is beneficial to preparing a more uniform textured surface on the silicon wafer 11. This is beneficial to improving the process matching window and process compatibility of subsequent preparation of other film layers on the silicon wafer 11, that is, improving the flatness and uniformity of other film layers. For example, depositing a silicon nitride film on the front side of the silicon wafer 11 improves the thickness uniformity of the silicon nitride film, reduces the risk of reddening at the edge of the solar cell 1, improves the aesthetics of the solar cell 1, and further improves the photoelectric conversion efficiency of the solar cell 1.

[0060] It should be noted that in some embodiments, the middle part of the silicon wafer 11 can be a central area that occupies half of the entire front area of ​​the silicon wafer 11. Then, along the length direction of the solar cell 1, the area outside the middle part of the silicon wafer 11 can be the edge of the silicon wafer 11.

[0061] In one possible implementation, such as Figures 2-4 As shown, the trench 111 is disposed within the wire mark area 112, and the extension direction of the trench 111 is the same as the wire mark direction on the surface of the silicon wafer 11. Here, the wire mark refers to the mechanical damage caused to the surface of the silicon wafer 11 by wire cutting, and the direction of the wire mark is perpendicular to the wire cutting direction.

[0062] In this embodiment, since the textured surface prepared by the existing solar cell line mark region is often incomplete, the trench 111 of this application is set in the line mark region 112, and the extension direction of the trench 111 is the same as the line mark direction on the surface of the silicon wafer 11, so that the position of the trench 111 and the line mark protrusion can completely coincide, which is beneficial to increase the contact area between the line mark region 112 and the etching solution, increase the reaction rate between the line mark region 112 and the etching solution, and enable the line mark region 112 to be prepared with a textured surface with a complete pyramid structure 114 morphology. At the same time, the reaction rate between the line mark region 112 and the non-line mark region 113 and the etching solution is made closer to the same, so that the morphological difference of the pyramid structure 114 of the silicon wafer 11 located in the line mark region 112 and the non-line mark region 113 is smaller, and the overall textured surface uniformity is improved.

[0063] In summary, the density of trenches 111 located in the middle of silicon wafer 11 is greater than that of trenches 111 located at the edge of silicon wafer 11. At the same time, the trenches 111 are set within the trace area 112, and the extension direction of the trenches 111 is the same as the direction of the trace on the surface of silicon wafer 11. By simultaneously limiting the position and distribution density of the trenches 111, it is beneficial to make the reaction rate of the etching solution at each position on the surface of silicon wafer 11 approximately the same. The size difference of the pyramid structure 114 prepared at each position on the surface of silicon wafer 11 is smaller, which greatly improves the uniformity of the prepared textured surface, further enhances the light trapping property of the solar cell 1, and thus further improves the photoelectric conversion efficiency of the solar cell 1.

[0064] In one possible implementation, such as Figure 3 and Figure 4 As shown, the dimension H of the trench 111 along the thickness direction of the silicon wafer 11 satisfies: 0.1um ≤ H ≤ 0.5um. This ensures that the range of the dimension H of the trench 111 along the thickness direction of the silicon wafer 11 is moderate, preventing the value of the dimension H of the trench 111 along the thickness direction of the silicon wafer 11 from being too large. This also prevents the contact area between the trench 111 and the etching solution from being too large, ensuring that the reaction rate of the etching solution in the middle of the silicon wafer 11 is moderate. This improves the reliability that the reaction rate of the etching solution in the middle of the silicon wafer 11 is close to the reaction rate of the etching solution at the edge of the silicon wafer 11, and also ensures that the etching solution on the silicon wafer 11... The moderate reaction rate of the line mark region 112 improves the reliability of the reaction rates of the line mark region 112 and the non-line mark region 113 with the etching solution to be close to the same, thereby improving the reliability of forming a uniform textured surface. At the same time, the value of the dimension H of the trench 111 along the thickness direction of the silicon wafer 11 is not too small, so that the contact area between the middle part of the silicon wafer 11 and the line mark region 112 and the etching solution is not too small. This makes the trench 111 conducive to guiding the etching solution to fully react with the middle part of the silicon wafer 11 and the line mark region 112, thereby improving the reliability of preparing a textured surface of a complete pyramid structure 114 and thus improving the uniformity of the textured surface.

[0065] Optionally, H satisfies: 0.1um ≤ H ≤ 0.5um. The value of H can be 0.1um, 0.12um, 0.14um, 0.15um, 0.16um, 0.18um, 0.2um, 0.22um, 0.24um, 0.25um, 0.26um, 0.28um, 0.3um, 0.35um, 0.36um, 0.38um, 0.4um, 0.45um, 0.46um, 0.48um, or 0.5um, or other values ​​within the above range. This embodiment does not impose any restrictions on this.

[0066] In one possible implementation, such as Figure 3 and Figure 4 As shown, the dimension D of the trench 111 along the length of the solar cell 1 satisfies: 0.6µm ≤ D ≤ 1.6µm. This ensures that the width of the trench 111 is within a suitable range, and that the density of the trench 111 in the middle of the silicon wafer 11 and in the trace area 112 is reasonably controlled. This prevents the dimension D of the trench 111 along the length of the solar cell 1 from being too large, thus preventing the contact area between the trench 111 and the etching solution from being too large. This also ensures that the reaction rate of the etching solution in the middle of the silicon wafer 11 is moderate, improving the reliability that the reaction rate of the etching solution in the middle of the silicon wafer 11 is close to the reaction rate at the edge of the silicon wafer 11. Furthermore, it ensures that the reaction rate of the etching solution in the trace area 112 of the silicon wafer 11 is moderate, improving the reliability of the trace area 112. The reliability of the reaction rate between the non-line mark region 113 and the etching solution is close to that of the groove, which improves the reliability of forming a uniform textured surface and is beneficial to improving the structural strength of the silicon wafer 11, reducing the risk of microcracks or fragmentation of the cell 1. At the same time, the dimension D of the groove 111 along the length of the cell 1 is not too small, and the contact area between the middle of the silicon wafer 11 and the line mark region 112 and the etching solution is not too small. This makes the groove 111 conducive to guiding the etching solution to fully react with the middle of the silicon wafer 11 and the line mark region 112, improving the reliability of preparing a complete and uniform textured surface, facilitating the smooth flow of the etching solution, and being able to quickly remove the by-products generated by the etching reaction, further promoting the full reaction between the etching solution and the silicon wafer 11.

[0067] Optionally, the dimension D of the trench 111 along the length direction of the battery cell 1 satisfies: 0.6um ≤ D ≤ 1.6um. The value of D can be 0.6um, 0.65um, 0.7um, 0.75um, 0.8um, 0.85um, 0.9um, 0.95um, 1um, 1.05um, 1.1um, 1.15um, 1.2um, 1.25um, 1.3um, 1.35um, 1.4um, 1.45um, 1.5um, 1.55um, or 1.6um, or other values ​​within the above range. This embodiment does not limit this value.

[0068] In one possible implementation, such as Figure 1As shown, after pre-cleaning the silicon wafer 11 and before etching the surface of the silicon wafer 11 with an etching solution, the method for fabricating the solar cell 1 includes the following steps:

[0069] S31: The silicon wafer 11 is subjected to alkaline washing using an alkaline washing solution, which includes a first sodium hydroxide solution and a first deionized water. The concentration Q1 of the first sodium hydroxide solution satisfies: 10wt%≤Q1≤60wt%, the amount M1 of the first sodium hydroxide solution satisfies: 4L≤M1≤24L, and the amount M2 of the first deionized water satisfies: 680L≤M2≤710L, so as to make the concentration of the alkaline washing solution appropriate.

[0070] In this embodiment, the silicon wafer 11 is subjected to alkaline washing to repair the laser damage caused to the surface of the silicon wafer 11 by the laser-made trenches 111 in step S2, and to polish and clean away any possible laser crystallization layer. This avoids the laser damage and laser crystallization layer affecting the etching reaction rate of the subsequent texturing process, and also helps to improve the flatness of the silicon wafer 11 surface. This facilitates the formation of a silicon wafer 11 substrate with favorable process conditions before performing the texturing process in step S4, thereby enabling the preparation of a uniform and consistent textured surface on the silicon wafer 11. Simultaneously, alkaline washing repairs the laser damage caused to the surface of the silicon wafer 11 by the laser-made trenches 111 in step S2, which helps to improve the quality of the silicon wafer 11, increase carrier lifetime, and improve short-circuit current and open-circuit voltage, thereby further improving the photoelectric conversion efficiency of the solar cell 1.

[0071] Specifically, the first sodium hydroxide solution is used to anisotropically etch the surface of the silicon wafer 11, and deionized water is used to dilute the first sodium hydroxide solution and participate in the etching reaction.

[0072] When the concentration Q1 of the first sodium hydroxide solution satisfies: 10wt%≤Q1≤60wt%, and the amount M1 of the first sodium hydroxide solution satisfies: 4L≤M1≤24L, the range of the amount and concentration of the first sodium hydroxide solution is moderate, ensuring that the concentration of sodium hydroxide in the alkaline washing solution is not too high, preventing excessive corrosion, reducing silicon material loss, improving the mechanical strength of silicon wafer 11, and helping to reduce the surface roughness of silicon wafer 11, so that it is easier to prepare a uniform textured surface in the subsequent process; at the same time, ensuring that the concentration of sodium hydroxide in the alkaline washing solution is not too low, improving the effect of repairing laser damage and removing the laser crystallization layer, and improving the alkaline washing efficiency.

[0073] Optionally, the concentration Q1 of the first sodium hydroxide solution satisfies: 10wt%≤Q1≤60wt%. The value of Q1 can be 10wt%, 15wt%, 20wt%, 25wt%, 30wt%, 35wt%, 40wt%, 45wt%, 50wt%, 55wt%, or 60wt%, or other values ​​within the above range. This embodiment does not impose any restrictions on this.

[0074] Optionally, the amount M1 of the first sodium hydroxide solution satisfies: 4L≤M1≤24L. The value of M1 can be 4L, 5L, 6L, 7L, 8L, 9L, 10L, 11L, 12L, 13L, 14L, 15L, 16L, 17L, 18L, 19L, 20L, 21L, 22L, 23L, or 24L, or other values ​​within the above range. This embodiment does not impose any restrictions on this.

[0075] When the amount of the first deionized water M2 meets the condition of 680L≤M2≤710L, the amount of the first deionized water is moderate, ensuring that the amount of the first deionized water is not excessive. This improves the effect of repairing laser damage and removing the laser crystallization layer, so as to prepare a uniform textured surface in the subsequent process. At the same time, the amount of the first deionized water is not too small, so that the first deionized water can effectively dilute the first sodium hydroxide solution and wash away impurities on the surface of silicon wafer 11, which helps to reduce the surface roughness of silicon wafer 11, so as to prepare a uniform textured surface in the subsequent process.

[0076] Optionally, the amount of the first deionized water, M2, satisfies the following condition: 680L ≤ M2 ≤ 710L. The value of M2 can be 680L, 681L, 682L, 683L, 684L, 685L, 686L, 687L, 688L, 689L, 690L, 691L, 692L, 693L, 694L, 695L, 696L, 697L, 698L, 699L, 700L, or 710L, or other values ​​within the above range. This embodiment does not impose any restrictions on this.

[0077] In one possible implementation, such as Figure 1 As shown, the alkaline washing temperature T1 satisfies: 50℃≤T1≤70℃, and the alkaline washing time S1 satisfies: 30s≤S1≤120s.

[0078] When the alkaline washing temperature T1 meets the following condition: 50℃≤T1≤70℃, the temperature range of the alkaline washing temperature T1 is moderate, ensuring that the temperature T1 is not too high. This prevents the alkaline washing corrosion reaction from being too fast, which is conducive to precise control of the corrosion rate, preventing excessive corrosion, preventing excessive corrosion of the groove 111, and preventing the formation of pits. It also improves the surface roughness of the silicon wafer 11, thus facilitating the reaction rate between the silicon wafer 11 surface and the etching solution to be approximately the same at each location during subsequent texturing. At the same time, ensuring that the temperature T1 is not too low prevents the alkaline washing corrosion reaction from being too slow or insufficient, improving the effect of alkaline washing in repairing laser damage, and also improving the effect of alkaline washing in reducing surface roughness, thereby improving the efficiency of alkaline washing.

[0079] Optionally, the alkaline washing temperature T1 satisfies: 50℃≤T1≤70℃. The value of T1 can be 50℃, 51℃, 52℃, 53℃, 54℃, 55℃, 56℃, 57℃, 58℃, 59℃, 60℃, 61℃, 62℃, 63℃, 64℃, 65℃, 66℃, 67℃, 68℃, 69℃ or 70℃, or other values ​​within the above range. This embodiment does not limit this.

[0080] When the alkaline washing time S1 satisfies the condition of 30s≤S1≤120s, the value of the alkaline washing time S1 is moderate, ensuring that the time S1 is not too large, thus preventing excessive corrosion, preventing excessive corrosion of the trench 111, and preventing the formation of pits. This improves the surface roughness of the silicon wafer 11, which in turn helps to make the reaction rate of the silicon wafer 11 surface with the etching solution approach the same during subsequent texturing. At the same time, ensuring that the time S1 is not too small helps to improve the effect of repairing laser damage and removing the laser crystallization layer, improve the effect of alkaline washing in reducing surface roughness, and improve the reliability of subsequent preparation of a uniform textured surface.

[0081] Optionally, the alkaline washing time S1 satisfies: 30s≤S1≤120s. The value of S1 can be 30s, 35s, 40s, 45s, 50s, 55s, 60s, 65s, 70s, 75s, 80s, 85s, 90s, 95s, 100s, 105s, 110s, 115s or 120s, or other values ​​within the above range. This embodiment does not limit this.

[0082] In summary, when the concentration Q1 of the first sodium hydroxide solution in the alkaline washing solution satisfies: 10wt%≤Q1≤60wt%, the amount M1 of the first sodium hydroxide solution satisfies: 4L≤M1≤24L, the amount M2 of the first deionized water satisfies: 680L≤M2≤710L, the alkaline washing temperature T1 satisfies: 50℃≤T1≤70℃, and the alkaline washing time S1 satisfies: 30s≤S1≤120s, the ratio of the first sodium hydroxide solution to the first deionized water is appropriate, and the temperature and time during alkaline washing are kept appropriate. This allows the alkaline washing to thoroughly repair laser damage and remove the crystallized layer and impurities, improving the surface roughness improvement effect of alkaline washing. Consequently, during subsequent texturing, it is beneficial to promote the reaction rate of the etching solution at various positions on the surface of the silicon wafer 11 to be approximately the same, greatly improving the reliability of the subsequent preparation of a uniform textured surface and improving the efficiency of alkaline washing.

[0083] In one possible implementation, such as Figure 1 As shown, the method for preparing the solar cell 1 after alkaline washing of the silicon wafer 11 and before etching the surface of the silicon wafer 11 with an etching solution includes:

[0084] S32: Wash the silicon wafer 11 with water to clean the alkaline washing solution used in step S31, prevent the alkaline washing solution from interfering with the etching solution in the subsequent step S4, and enable the etching solution to react fully with the silicon wafer 11, thereby improving the reliability of preparing a complete pyramid structure 114 textured surface and further improving the reliability of preparing a uniform textured surface.

[0085] In one possible implementation, such as Figure 1 As shown, during step S4, the etching solution performs anisotropic etching on the surface of the silicon wafer 11. The etching solution includes a second sodium hydroxide solution, a second deionized water, and an additive. The concentration Q2 of the second sodium hydroxide solution satisfies: 10wt%≤Q2≤60wt%, the amount C1 of the second sodium hydroxide solution satisfies: 2L≤C1≤10.5L, the amount C2 of the additive satisfies: 1L≤C2≤4.5L, and the amount C3 of the second deionized water satisfies: 680L≤C3≤710L. The additive is used to promote textured surface growth and can be an organic mixed solvent such as isopropanol, surfactant, or defoamer.

[0086] When the concentration Q2 of the second sodium hydroxide solution satisfies: 10wt%≤Q2≤60wt%, and the amount C1 of the second sodium hydroxide solution satisfies: 2L≤C1≤10.5L, the range of the amount and concentration of the second sodium hydroxide solution is moderate. That is, the concentration of sodium hydroxide in the etching solution is moderate, so that the concentration of sodium hydroxide in the etching solution is not too high, preventing the risk of damage to the already formed inverted pyramid structure 114 due to over-etching, reducing the reflectivity of the textured surface, and helping to prevent the silicon wafer 11 from breaking, which is beneficial to improving the structural strength of the silicon wafer 11. At the same time, the concentration of sodium hydroxide in the etching solution is not too low, preventing the risk of the trench 111 not being completely etched, reducing the nucleation difficulty of the pyramid structure 114, which is beneficial to forming a textured surface with a complete pyramid structure 114. The density and size of the pyramid structure 114 are moderate, which is beneficial to forming a uniform textured surface, reducing reflectivity, improving the light trapping property of the solar cell 1, and improving the texturing efficiency.

[0087] Optionally, the concentration Q2 of the second sodium hydroxide solution satisfies: 10wt%≤Q2≤60wt%. The value of Q2 can be 10wt%, 15wt%, 20wt%, 25wt%, 30wt%, 35wt%, 40wt%, 45wt%, 50wt%, 55wt%, or 60wt%, or other values ​​within the above range. This embodiment does not impose any restrictions on this.

[0088] Optionally, the amount C1 of the second sodium hydroxide solution satisfies: 2L≤C1≤10.5L. The value of C1 can be 2L, 2.5L, 3L, 3.5L, 4L, 4.5L, 5L, 5.5L, 6L, 6.5L, 7L, 7.5L, 8L, 8.5L, 9L, 9.5L, 10L or 10.5L, or other values ​​within the above range. This embodiment does not impose any restrictions on this.

[0089] When the amount of the second deionized water, C3, satisfies the condition of 680L≤C3≤710L, the amount of the second deionized water is moderate, preventing excessive use and avoiding the risk of incomplete etching of the trench 111 due to insufficient alkalinity. This reduces the nucleation difficulty of the pyramid structure 114, thus facilitating the formation of a textured surface with a complete pyramid structure 114. Controlling the density and size of the pyramid structure 114 is also beneficial for forming a uniform textured surface, reducing reflectivity, improving the light-trapping properties of the solar cell 1, and increasing texturing efficiency. Simultaneously, the amount of the second deionized water is not too small, preventing excessive alkalinity of the etching solution. This ensures that the second deionized water effectively dilutes the second sodium hydroxide solution, preventing the risk of damage to the already formed inverted pyramid structure 114 due to over-etching, reducing the reflectivity of the textured surface, and helping to prevent the silicon wafer 11 from cracking, thereby improving the structural strength of the silicon wafer 11.

[0090] Optionally, the amount of the second deionized water, C3, satisfies the following condition: 680L ≤ C3 ≤ 710L. The value of C3 can be 680L, 681L, 682L, 683L, 684L, 685L, 686L, 687L, 688L, 689L, 690L, 691L, 692L, 693L, 694L, 695L, 696L, 697L, 698L, 699L, 700L, 701L, 702L, 703L, 704L, 705L, 706L, 707L, 708L, 709L, or 710L, or other values ​​within the above range. This embodiment does not impose any restrictions on this.

[0091] When the amount of additive C2 satisfies the condition that 1L≤C2≤4.5L, the range of the amount of additive C2 is moderate, which prevents abnormal growth of the pyramid structure 114 and helps to make the size of the pyramid structure 114 at various positions on the surface of the silicon wafer 11 approach the same, which is conducive to the preparation of a uniform textured surface.

[0092] Optionally, the amount of additive C2 satisfies: 1L≤C2≤4.5L. The value of C2 can be 1L, 1.5L, 2L, 2.5L, 3L, 3.5L, 4L, or 4.5L, or other values ​​within the above range. This embodiment does not limit this.

[0093] In one possible implementation, such as Figure 1As shown, during step S4, the etching temperature T2 satisfies: 75℃≤T2≤90℃, and the etching time S2 satisfies: 200s≤S2≤600s.

[0094] When the etching temperature T2 satisfies the condition that 75℃≤T2≤90℃, the value of the etching temperature T2 is moderate, ensuring that the etching temperature T2 is not too low, thus preventing the etching reaction rate from being too slow and increasing the etching reaction rate. At the same time, the etching temperature T2 is not too high, thus preventing the etching reaction rate from being too fast. This is conducive to forming a complete and uniformly sized gold tower structure and improving the uniformity of the entire textured surface.

[0095] Optionally, the etching temperature T2 satisfies: 75℃≤T2≤90℃. The value of T2 can be 75℃, 76℃, 77℃, 78℃, 79℃, 80℃, 81℃, 82℃, 83℃, 84℃, 85℃, 86℃, 87℃, 88℃, 89℃ or 90℃, or other values ​​within the above range. This embodiment does not impose any restrictions on this.

[0096] When the etching time S2 satisfies the condition that 200s≤S2≤600s, the etching time S2 is not too short, and all pyramid structures 114 on the surface of silicon wafer 11 can grow completely, improving the uniformity of the textured surface on the front side and reducing reflectivity. At the same time, the etching time S2 is not too long, preventing over-etching and avoiding the risk of damage to the already formed inverted pyramid structure 114 due to over-etching, improving the quality of the entire textured surface, which is beneficial to improving the structural strength of silicon wafer 11 and improving etching efficiency.

[0097] Optionally, the etching time S2 satisfies: 200s≤S2≤600s. The value of S2 can be 200s, 250s, 300s, 350s, 400s, 450s, 500s, 550s or 600s, or other values ​​within the above range. This embodiment does not limit this.

[0098] In summary, when the concentration Q2 of the second sodium hydroxide solution satisfies: 10wt%≤Q2≤60wt%, the amount C1 of the second sodium hydroxide solution satisfies: 2L≤C1≤10.5L, the amount C2 of the additive satisfies: 1L≤C2≤4.5L, and the amount C3 of the second deionized water satisfies: 680L≤C3≤710L, and simultaneously, the etching temperature T2 satisfies: 75℃≤T2≤90℃, and the etching time S2 satisfies: 200s≤S2≤600s, the ratio of the second sodium hydroxide solution, the second deionized water, and the additive is appropriate, and the temperature and time during texturing are also appropriate. This is conducive to forming a textured surface with a complete pyramid structure 114, making the size of the pyramid structure 114 on the surface of the silicon wafer 11 approximately the same, which in turn is conducive to forming a uniform, high-quality textured surface, reducing reflectivity, improving the light-trapping properties of the solar cell 1, and increasing texturing efficiency.

[0099] In one possible implementation, such as Figure 1 As shown, after texturing the surface of the silicon wafer 11, the method for fabricating the solar cell 1 includes:

[0100] S5: Wash the silicon wafer 11 with water to remove the etching solution used in step S4, prevent the residual etching solution from continuing to etch the surface of the silicon wafer 11, and prevent damage to the textured surface.

[0101] S6: Perform post-cleaning on silicon wafer 11 to remove metallic impurities from the textured surface.

[0102] S7: Wash the silicon wafer 11 with water to clean the post-cleaning solution used in step S6 and prevent it from interfering with other solutions when performing the next process.

[0103] S8: Acid pickling is performed on silicon wafer 11 to achieve further cleaning and to further remove alkaline substances remaining in the etching solution within the textured surface, thereby improving the removal of metal impurities.

[0104] S9: Wash the silicon wafer 11 with water to remove the acid washing solution used in step S8, so that the silicon wafer 11 is electrically neutral.

[0105] S10: Slowly pull up the silicon wafer 11 to allow the water adhering to the silicon wafer 11 to flow off, which facilitates the subsequent rapid drying of the silicon wafer 11;

[0106] S11: Dry the silicon wafer 11 to obtain a dry and clean silicon wafer 11, which provides a good foundation for subsequent doping and diffusion of the silicon wafer 11, thereby facilitating the formation of a solar cell 1 with excellent photoelectric conversion efficiency.

[0107] Example 1: The silicon wafer 11 was prepared using the above-described method, i.e., by sequentially executing steps S1, S2, S3, S31, S32, S4, and S5-S11, to obtain a textured surface structure on the silicon wafer 11 as shown below. Figure 6 As shown in (b).

[0108] Comparative Example 1: A conventional solar cell fabrication method was used, excluding step S2 (laser preparation of trench 111) and step S31 (alkaline washing). All other steps except S2 and S31, as well as the solutions and process conditions used in those steps, were identical to those in Example 1. The resulting silicon wafer exhibited a textured surface structure as shown in Example 1. Figure 6 As shown in (a).

[0109] Therefore, as Figure 6 (a) and Figure 6 As shown in (b), comparing Example 1 and Comparative Example 1, it can be seen that by first preparing trenches 111 on the surface of silicon wafer 11, then washing with alkali, and then texturing, the resulting textured surface has good uniformity, and the morphological differences of the pyramid structure 114 at different positions of the textured surface are smaller.

[0110] This application also provides a battery cell 1, such as Figure 1 and Figure 5 As shown, the battery cell 1 is prepared by the preparation method of battery cell 1 in any of the above embodiments.

[0111] like Figure 5 and Figure 6 As shown in (b), the solar cell 1 includes a textured surface disposed on the surface of the silicon wafer 11. The textured surface includes multiple pyramid structures 114. When the solar cell 1 is prepared by the above-described method for preparing the solar cell 1, it is beneficial to prepare a solar cell 1 with a uniform textured surface. Even if the base size and height size of the pyramid structure 114 at different positions of the solar cell 1 are small, the base side length L of the pyramid structure 114 satisfies: 1um≤L≤2.5um, and the height F of the pyramid structure 114 satisfies: 0.5um≤F≤2um.

[0112] The base side length L of the pyramid structure 114 satisfies: 1um≤L≤2.5um. It can be seen that the difference in the base side length L of the pyramid structure 114 is small. At the same time, the size of the base side length L is within the above range, which makes the distribution density of the pyramid structure 114 moderate and is conducive to reducing reflectivity, improving the light trapping property of the solar cell 1, and improving the photoelectric conversion efficiency of the solar cell 1.

[0113] Optionally, the base side length L of the pyramid structure 114 satisfies: 1um ≤ L ≤ 2.5um. The value of L can be 1um, 1.1um, 1.2um, 1.3um, 1.4um, 1.5um, 1.6um, 1.7um, 1.8um, 1.9um, 2um, 2.1um, 2.2um, 2.3um, 2.4um or 2.5um, or other values ​​within the above range. This embodiment does not impose any restrictions on this.

[0114] The height F of the pyramid structure 114 satisfies: 0.5um≤F≤2um. It can be seen that the difference in the height F of the pyramid structure 114 is small. At the same time, the size of the height F of the pyramid structure 114 is within the above range, which makes the pyramid structure 114 have good light trapping properties and is conducive to reducing carrier recombination, increasing open circuit voltage, and thus improving the photoelectric conversion efficiency of the solar cell 1.

[0115] Optionally, the height F of the pyramid structure 114 satisfies: 0.5um ≤ F ≤ 2um. The value of F can be 0.5um, 0.6um, 0.7um, 0.8um, 0.9um, 1um, 1.1um, 1.2um, 1.3um, 1.4um, 1.5um, 1.6um, 1.7um, 1.8um, 1.9um, or 2um, or other values ​​within the above range. This embodiment does not impose any restrictions on this.

[0116] The types of solar cells 1 in this application include, but are not limited to, back contact (BC), tunnel oxide passivated contact (TOPCon), heterojunction with intrinsic thin-layer (HIT), passivated emitter and rear cell (PERC), or perovskite solar cells.

[0117] In some embodiments, the battery cell 1 can be a back contact battery. For a back contact battery (BC), the emitter, surface field and metal electrode are all located on the back of the battery and are distributed in a cross-directional manner. The front of the battery uses a SiNx / SiOx double-layer anti-reflection passivation film, so that there is no metal electrode blocking the front of the battery, which allows the battery to receive more incident light, reduces optical loss and improves photoelectric conversion efficiency.

[0118] In some embodiments, the battery cell 1 provided in this application can also be a tunnel oxide passivated contact (TOPCON) battery. The TOPCON battery, along its thickness direction, sequentially includes a silver electrode, a front surface silicon nitride passivation layer, a boron-doped emitter, an N-type substrate silicon layer, a diffusion-doped layer, an ultrathin silicon oxide layer, doped polycrystalline silicon, silicon nitride, and a silver electrode. The back side of the battery consists of an ultrathin silicon oxide layer (1nm~2nm) and a phosphorus-doped microcrystalline amorphous mixed Si film, which together form a passivated contact structure, allowing the solder ribbon and busbar to also be disposed on the back side of the battery cell 1. This structure can block minority carrier hole recombination, increasing the battery's open-circuit voltage and short-circuit current. The ultrathin oxide layer allows majority carrier electrons to tunnel into the polycrystalline silicon layer while blocking minority carrier hole recombination. The excellent passivation effect of ultrathin silicon oxide and heavily doped silicon films causes the energy bands on the silicon wafer surface to bend, thereby forming a field passivation effect. This significantly increases the probability of electron tunneling, reduces contact resistance, and improves the open-circuit voltage and short-circuit current of the battery, thus improving the battery conversion efficiency.

[0119] In some embodiments, the battery cell 1 provided in this application may also be a heterojunction with intrinsic thin-layer (HIT) battery. Along its thickness direction, the HIT battery sequentially includes a front low-temperature silver electrode, a front conductive film, an N-type amorphous silicon film, an intrinsic amorphous silicon film, an N-type substrate silicon layer, an intrinsic amorphous silicon film, a P-type amorphous silicon film, a back conductive film, and a back low-temperature silver electrode.

[0120] In some embodiments, the solar cell 1 provided in this application can also be a passivated emitter and rear cell (PERC). Along its thickness direction, the PERC cell sequentially includes a front surface silver electrode, a front surface silicon nitride passivation layer, a phosphorus emitter, a P-type substrate silicon layer, a local aluminum back field, a metallic aluminum back electrode, and a back passivation layer (Al2O3 / SiNx). The PERC cell uses a passivation film to passivate the back side, replacing the all-aluminum back field, enhancing the internal back reflection of light on the silicon substrate, reducing the recombination rate on the back side, and improving the cell efficiency by 0.5%-1%.

[0121] In some embodiments, the battery cell 1 provided in this application can also be a perovskite battery. Along its thickness direction, the perovskite battery sequentially includes a substrate material, a conductive thin film, an electron transport layer (titanium dioxide), a perovskite absorption layer (hole transport layer), and a metal cathode. Perovskite materials have a high light absorption coefficient and a long carrier diffusion distance. After the photons absorbed by the perovskite material are converted into electrons, they are easily collected by the electrodes with low loss, thus generating high photogenerated voltage and current, making the perovskite exhibit high photoelectric conversion efficiency.

[0122] The above descriptions are merely specific implementations of the embodiments of this application, but the protection scope of the embodiments of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the embodiments of this application should be covered within the protection scope of the embodiments of this application. Therefore, the protection scope of the embodiments of this application should be determined by the protection scope of the claims.

Claims

1. A method for preparing a battery sheet, characterized by, The preparation method of the battery piece (1) at least comprises: providing a wire-cut silicon wafer (11), the silicon wafer (11) comprising a wire mark area (112) and a non-wire mark area (113); laser preparing a plurality of spaced grooves (111) on the front surface of the silicon wafer (11); pre-cleaning the silicon wafer (11); etching the surface of the silicon wafer (11) using an etching solution to prepare a textured surface on the surface of the silicon wafer (11); the density of the grooves (111) located in the middle of the silicon wafer (11) is greater than the density of the grooves (111) located at the edge of the silicon wafer (11), so that the contact area of the middle of the silicon wafer (11) with the etching solution is greater than the contact area of the edge of the silicon wafer (11) with the etching solution.

2. The method of claim 1, wherein the step of forming the first and second electrodes is performed by screen printing. The grooves (111) are arranged in the wire mark area (112), and the extension direction of the grooves (111) is the same as the wire mark direction of the surface of the silicon wafer (11).

3. The method of claim 2, wherein the step of applying the conductive paste is performed by screen printing. The size H of the grooves (111) along the thickness direction of the silicon wafer (11) satisfies: 0.1um≤H≤0.5um.

4. The method of claim 3, wherein the step of applying the conductive paste is performed by screen printing. The size D of the grooves (111) along the length direction of the battery piece (1) satisfies: 0.6um≤D≤1.6um.

5. The method of claim 1, wherein the step of forming the first and second electrodes is performed by screen printing. After pre-cleaning the silicon wafer (11) and before etching the surface of the silicon wafer (11) using the etching solution, the preparation method of the battery piece (1) comprises the following steps: alkali washing the silicon wafer (11) using an alkali washing solution, the alkali washing solution comprising a first sodium hydroxide solution and a first deionized water, the concentration Q1 of the first sodium hydroxide solution satisfying: 10wt%≤Q1≤60wt%, the amount M1 of the first sodium hydroxide solution satisfying: 4L≤M1≤24L, and the amount M2 of the first deionized water satisfying: 680L≤M2≤710L.

6. The method of claim 5, wherein the step of applying the conductive paste is performed by screen printing. The temperature T1 of alkali washing satisfies: 50℃≤T1≤70℃, and the time S1 of alkali washing satisfies: 30s≤S1≤120s.

7. The method of claim 6, wherein the step of applying the conductive paste is performed by screen printing. After alkali washing the silicon wafer (11) and before etching the surface of the silicon wafer (11) using the etching solution, the preparation method of the battery piece (1) comprises: water washing the silicon wafer (11).

8. The method of claim 1-7, wherein, The etching solution performs anisotropic etching on the surface of the silicon wafer (11), the etching solution comprising a second sodium hydroxide solution, a second deionized water and an additive, the concentration Q2 of the second sodium hydroxide solution satisfying: 10wt%≤Q2≤60wt%, the amount C1 of the second sodium hydroxide solution satisfying: 2L≤C1≤10.5L, the amount C2 of the additive satisfying: 1L≤C2≤4.5L, and the amount C3 of the second deionized water satisfying: 680L≤C3≤710L; the etching temperature T2 satisfies: 75℃≤T2≤90℃, and the etching time S2 satisfies: 200s≤S2≤600s.

9. The method of claim 1-7, wherein, After texturing the surface of the silicon wafer (11), the preparation method of the battery piece (1) comprises: water washing the silicon wafer (11); post-cleaning the silicon wafer (11); water washing the silicon wafer (11); acid washing the silicon wafer (11); water washing the silicon wafer (11); slowly pulling the silicon wafer (11); drying the silicon wafer (11).

10. A battery sheet, characterized by The battery wafer (1) is prepared by the preparation method of the battery wafer (1) in any one of claims 1-9. The battery wafer (1) comprises a textured surface, and the textured surface comprises a plurality of pyramid structures (114), a base side length L of the pyramid structures (114) satisfies 1um≤L≤2.5um, and a height F of the pyramid structures (114) satisfies 0.5um≤F≤2um.

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