Memory access request statistics method, memory tracking circuit and system

Abstract

Provided are a memory access request statistics method, a memory tracking circuit and system, comprising: in each iteration period, the memory tracking circuit updates a first statistics counter in response to a first memory access request sent from a processing unit, wherein the first memory access request indicates accessing data in a first memory range, the first memory range is associated with the first statistics counter, and the first statistics counter indicates the access frequency of the data in the first memory range; and providing first information in the first statistics counter to a memory management component, the first information indicating that the first memory range is a high access memory range. Through the memory tracking circuit, the high access memory range can be quickly counted and identified.

Description

[0001] This application is a divisional application. The original application has the application number 202280092125.4 and the original application date is February 23, 2022. The entire contents of the original application are incorporated herein by reference. Technical Field

[0002] This application relates to the field of computers, and more particularly to a memory access request statistics method, memory tracking circuit, and system. Background Technology

[0003] The present invention relates to a computerized apparatus, and more specifically, but not exclusively, to a computerized apparatus having one or more memory components.

[0004] For the sake of brevity, the term "system" will hereafter be used to refer to a computerized system, and these terms are used interchangeably.

[0005] Numerous metrics are used to measure the performance of computerized systems, such as throughput, which is the amount of tasks executed within a defined time interval, and latency, which is the amount of time a task is delayed before execution. Improving system performance, such as by increasing throughput and / or reducing latency, depends, among other factors, on the amount of available computing resources in the system and how well the various components of the system work together. For example, reducing latency when accessing memory and / or increasing memory access throughput can improve system performance.

[0006] Memory components with relatively high performance access characteristics, such as low-latency memory components or high-throughput memory components, such as static RAM (SRAM), are generally more expensive than memory components with lower performance access characteristics, such as dynamic RAM (DRAM). It is common practice to design system memory using more than one type of memory component to balance system cost and performance. Some common system designs organize multiple memory components in multiple memory layers, where smaller, faster layers sit above larger and slower layers, acting as caches for the larger layers. In some designs, there is a hierarchical structure of layers where only the largest layer is available to the software program, meaning it can be addressed using the application's memory address, and the other layers in the hierarchy serve as tiered caches.

[0007] Some other system designs allow all memory layers to be addressed using the application memory addresses of the software program. In such systems, system performance is affected by the distribution of the software program's application memory across multiple memory layers (i.e., across one or more memory components of the system). When the software program's application memory comprises multiple application memory regions, performance can be improved by storing frequently accessed application memory regions in one or more high-performance memory components, while lower-performance memory components are used to store less frequently accessed application memory regions.

[0008] The term non-uniform memory access (NUMA) refers to a computerized system with more than one memory component, where some characteristics of memory access from the processing unit to the memory component (such as latency and / or throughput) depend on the system topology, such as the location of the memory component relative to the processing unit. Similar to the system described above, in a system with NUMA, the system's performance can be affected by the distribution of application memory for a software program across one or more memory components. Summary of the Invention

[0009] This invention includes a method for counting memory access requests, memory tracking circuitry, and a system. In some embodiments described herein, one or more memory tracking circuits are used to update at least one of a plurality of statistical counters in response to receiving a memory access command from a processing unit. Furthermore, in these embodiments, one or more memory tracking circuits are used to provide one or more of the plurality of statistical counters to a memory management component to map the application memory of a software program to a plurality of memory components connected to the processing unit. Updating at least one statistical counter using one or more memory tracking circuits reduces the processing overhead required for the processing unit to track memory accesses and manage the allocation of application memory of a software program to multiple memory components, thereby improving the performance of the apparatus.

[0010] The above and other objectives are achieved through the features of the independent claim. Other implementations will be apparent from the dependent claims, the description, and the drawings.

[0011] According to a first aspect, an apparatus for executing a software program is provided, the apparatus comprising: a processing unit; at least one memory component, each memory component being connected to the processing unit and mapped to at least one of a plurality of memory address ranges of the processing unit; and at least one memory tracking circuit connected to the processing unit and the at least one memory component, configured to: in each iteration of a plurality of iterations, in response to receiving a memory access command from the processing unit, update at least one of a plurality of statistical counters; and provide one or more of the plurality of statistical counters to a memory management component to map the application memory of the software program to the at least one memory component.

[0012] According to a second aspect, a method is provided for managing memory in an apparatus for executing one or more software programs, the method comprising: in each of a plurality of iterations, in response to receiving a memory access command from a processing unit, updating at least one of a plurality of statistical counters connected to the processing unit and at least one memory component, the at least one memory component being connected to the processing unit, wherein each of the at least one memory component is mapped to at least one of a plurality of memory address ranges of the processing unit; and providing one or more of the plurality of statistical counters to a memory management component to map application memory of the software program to the at least one memory component.

[0013] According to a third aspect, a software program product for memory management is provided, the software program product comprising: a non-transitory computer-readable storage medium; and program instructions for: in each of one or more management iterations, receiving one or more of a plurality of statistical counters from at least one memory tracking circuit connected to a processing unit and at least one memory component, such that the application memory of the software program is mapped to the at least one memory component connected to the processing unit, wherein each of the at least one memory component is mapped to at least one of a plurality of memory address ranges of the processing unit. According to the third aspect, the program instructions are executed from the non-transitory computer-readable storage medium by at least one computerized processor.

[0014] According to a fourth aspect, a method for a memory management component is provided, the method comprising: in each of one or more management iterations, receiving one or more of a plurality of statistical counters from at least one memory tracking circuit connected to a processing unit and at least one memory component, for mapping application memory of a software program to at least one of the memory components, the at least one memory component being connected to the processing unit, wherein each of the at least one memory component is mapped to at least one of a plurality of memory address ranges of the processing unit.

[0015] According to a fifth aspect, a memory tracking circuit is provided, including a plurality of statistical counters, the plurality of statistical counters including: a high access counter; a low access counter; and a plurality of range access counters. According to the fifth aspect, the memory tracking circuit is configured, when connected to a processing unit and at least one memory component, each memory component being connected to the processing unit and mapped to at least one of a plurality of memory address ranges of the processing unit, and when each of the plurality of range access counters is associated with one of the plurality of memory address ranges: in each of a plurality of iterations, in response to receiving a memory access command from the processing unit: identifying a memory address in the memory access command; identifying a memory address range among the plurality of memory address ranges, wherein the memory address range includes the memory address; incrementing the corresponding range access counter associated with the memory address range; incrementing the high access counter when the corresponding range access counter exceeds a high access threshold; and providing one or more of the plurality of statistical counters to a memory management component to map the application memory of the software program to the at least one memory component.

[0016] In one implementation of the first and second aspects, the plurality of statistical counters includes at least one of the following: at least one watermark counter selected from a group consisting of high access counters and low access counters; and a plurality of range access counters, each range access counter associated with one of the plurality of memory address ranges. In addition to the plurality of range access counters, using at least one watermark counter helps reduce the number of accesses to the plurality of range access counters, reducing the amount of computational resources required for memory management compared to accessing all of the plurality of range access counters. Optionally, at least one other statistical counter among the plurality of statistical counters is implemented in the at least one memory tracking circuit. Implementing the statistical counters in the memory tracking circuit reduces the amount of computational resources required to track one or more memory accesses compared to implementing the statistical counters in the page tables of an operating system executed by a processing unit executing a software program. Optionally, at least one other statistical counter among the plurality of statistical counters is implemented in a cache memory component connected to one or more of the at least one memory component. Optionally, at least one additional other statistical counter among the plurality of statistical counters is implemented in one of the at least one memory component.

[0017] In another implementation of the first and second aspects, updating the at least one statistical counter includes: identifying a memory address in the memory access command; identifying a memory address range among the plurality of memory address ranges, wherein the memory address range includes the memory address; incrementing a corresponding range access counter; and incrementing a high access counter when the corresponding range access counter exceeds a high access threshold. Increasing the high access counter when the corresponding range access counter associated with a memory address range exceeds the high access threshold helps reduce the number of accesses to the plurality of range access counters, reducing the amount of computational resources required for memory management compared to accessing all of the plurality of range access counters. Optionally, providing the one or more statistical counters to the memory management component includes: providing the at least one watermark counter; and providing at least one of the plurality of range access counters in response to a request from the memory management component. Optionally, the memory management component is configured to: perform another analysis including the at least one watermark counter; and, based on another result of the other analysis, send a request to the at least one memory tracking circuit to provide the at least one range access counter. In one or more steps, while performing another analysis, one or more statistical counters are provided from at least one memory tracking circuit to the memory management component. This reduces the number of accesses to multiple range access counters, reducing the amount of computational resources required for memory management compared to methods that access all multiple range access counters. This includes reducing processing time, processing complexity, and the number of accesses to at least one memory tracking circuit. Optionally, the memory management component is further configured to configure at least one of the low access threshold and the high access threshold in the at least one memory tracking circuit. Optionally, based on a further result of a further analysis including the one or more statistical counters, the memory management component configures at least one of the low access threshold and the high access threshold in the at least one memory tracking circuit. Configuring the low access threshold and / or the high access threshold improves the accuracy of the high access counter and the low access counter, and improves the accuracy of the memory mapping calculated based on the one or more statistical counters.

[0018] In another implementation of the first and second aspects, the at least one memory tracking circuit is used to update the at least one statistical counter and to provide one or more of the plurality of statistical counters when the processing unit executes the software program. Updating the at least one statistical counter and providing one or more statistical counters when the processing unit executes the software program facilitates runtime modifications to the memory mapping of the application memory of the software program, thereby improving system performance during software program execution.

[0019] In another implementation of the first and second aspects, the at least one memory tracking circuit includes a plurality of local tracking circuits. Optionally, each of the plurality of local tracking circuits is connected to the processing unit and one or more of the at least one memory component; each of the plurality of local tracking circuits updates the at least one statistical counter in response to receiving the memory access command when at least one memory address range associated with the one or more memory components connected to the local tracking circuit includes a local memory address as a memory address in a memory address command. Using a plurality of local tracking circuits improves the availability of the method described herein in systems where at least one memory component is topologically distant from each other.

[0020] In another implementation of the first and second aspects, the application memory of the software program includes a plurality of application memory regions, each application memory region being stored in one of the at least one memory component; the mapping of the application memory by the memory management component includes: performing an analysis including the one or more statistical counters; and, in response to the result of the analysis, moving at least one of the plurality of application memory regions from one of the at least one memory component to another. Optionally, the memory mapping component maps the application memory while the processing unit executes the software program. Moving application memory regions from one memory component to another while the processing unit executes the software program helps reduce the total latency of multiple memory accesses performed during software program execution and / or increases the total bandwidth of multiple memory accesses, thereby improving the performance of the device executing the software program. Performing an analysis including one or more statistical counters increases the accuracy of the analysis results, making the movement of at least one application memory region based on the analysis results improve the performance of the device executing the software program compared to other methods, such as methods using static analysis of the software program, which select memory regions not included in one or more statistical counters collected while the processing unit executes the software program.

[0021] In another implementation of the first and second aspects, the at least one memory tracking circuit is further configured to: in each of one or more management iterations, execute the plurality of iterations, including updating the at least one statistical counter; provide the one or more statistical counters to the memory management component; and reset one or more other statistical counters among the plurality of statistical counters.

[0022] In another implementation of the first and second aspects, the memory management component includes a software object executed by the processing unit. Optionally, the memory management component includes memory management circuitry connected to the at least one memory tracking circuit and the at least one memory component. Using memory management circuitry reduces the amount of computational resources required by the processing unit for memory management and reduces the impact of memory management on the performance of the device executing the software program.

[0023] In another implementation of the first and second aspects, the processing unit is used to execute an operating system. Optionally, the operating system uses a plurality of operating system memory pages to address the at least one memory component, each operating system memory page having a page size from an identified set of page sizes; at least one identified memory address range of the plurality of memory address ranges has a range size that is not equal to any page size in the set of page sizes. Tracking memory address ranges whose range size is not equal to any page size in the operating system's set of page sizes improves the accuracy of the analysis of one or more statistical counters, thereby improving the performance of the device executing the software program.

[0024] In one implementation of the fourth aspect, the plurality of statistical counters includes at least one of a high access counter, a low access counter, and a plurality of range access counters, each range access counter being associated with one of the plurality of memory address ranges. Optionally, receiving the one or more statistical counters includes receiving at least one of the high access counter and the low access counter. Optionally, the method further includes: performing an analysis including at least one of the low access counter and the high access counter; and, based on the result of the other analysis, sending a request to the at least one memory tracking circuit to provide the at least one range access counter.

[0025] Other systems, methods, features, and advantages of the present invention will be apparent to those skilled in the art upon review of the accompanying drawings and detailed description below. It is intended that all such other systems, methods, features, and advantages be included in this specification, within the scope of the invention, and protected by the appended claims.

[0026] Unless otherwise defined, all technical and / or scientific terms used herein have the same meaning as known to one of ordinary skill in the art to which the implementation pertains. While similar or equivalent methods and materials to those described herein may be used in the practice or testing of the implementation, exemplary methods and / or materials are described below. In case of any conflict, this patent specification (including the definitions) shall prevail. Furthermore, these materials, methods, and examples are illustrative only and are not necessarily limiting. Attached Figure Description

[0027] This document describes some embodiments by way of example and in conjunction with the accompanying drawings. The detailed description below, with specific reference to the accompanying drawings, emphasizes that the details shown are merely illustrative and for the purpose of discussing the embodiments. Thus, based on the accompanying drawings, those skilled in the art can readily understand how to practice the embodiments.

[0028] In the attached diagram:

[0029] Figure 1 These are schematic block diagrams of exemplary devices provided in some embodiments;

[0030] Figure 2 This is a schematic block diagram of another exemplary device provided in some embodiments;

[0031] Figure 3 These are schematic block diagrams illustrating exemplary address mappings provided in some embodiments;

[0032] Figure 4 These are flowcharts illustrating optional operational flows for memory management, provided in some embodiments.

[0033] Figure 5 These are flowcharts illustrating optional operational procedures for updating a statistical counter, provided by some embodiments.

[0034] Figure 6 These are flowcharts illustrating optional operational flows for memory management, provided in some embodiments.

[0035] Figure 7 These are sequence diagrams of optional operation flows provided in some embodiments;

[0036] Figure 8 These are schematic block diagrams illustrating exemplary memory mappings provided in some embodiments;

[0037] Figure 9 This is a schematic block diagram of another exemplary memory mapping provided in some embodiments. Detailed Implementation

[0038] As used herein, the term "processing unit" refers to any type of programmable or non-programmable circuit used to perform the operations described below. A processing unit may include hardware and software. For example, a processing unit may include one or more processors and transient or non-transient memory carrying a program that, when executed by one or more processors, causes the processing unit to perform the corresponding operations.

[0039] Furthermore, as used herein, the term "physical address" refers to the address used by the processing unit to access a memory component in a memory access request. Additionally, the term "application address" as used herein refers to an address used in an application. An application address can be a virtual address, in which case it needs to be translated into a physical address to access one or more memory components. The term "memory mapping" as used herein refers to mapping the application memory address of a software program to a physical address in a memory access request sent by the processing unit. This mapping can be used to translate application addresses into physical addresses that identify the location in a memory component where application data or instructions are stored.

[0040] Furthermore, the terms "memory access request" and "memory access command" used herein both refer to a request to access a memory component for the purpose of reading from and / or writing to the memory component, and these terms are used interchangeably. A memory access request can be generated when computer instructions, including memory access computer instructions, are executed in a software program.

[0041] Furthermore, the terms “range of memory addresses” and “memory address range” used in this article are used to refer to the range of memory addresses and are used interchangeably.

[0042] To improve system performance by allocating each of multiple application memory regions to one or more memory components connected to the processing unit, some systems track accesses to one or more memory components. Some existing tracking methods maintain access counters in page tables used to map application addresses to physical addresses. This approach requires updating the counters in the page tables every time memory is accessed. Furthermore, analyzing multiple counters in the page tables requires merging the counters of multiple virtual pages mapped to a common physical page. Additionally, some methods require sorting multiple counters to categorize page table entries, for example, to identify page table entries describing frequently accessed application memory regions. This approach degrades system performance because it requires computational resources from the processing unit.

[0043] In some other methods of tracking memory accesses, the processing unit maintains multiple counters stored in one or more memory components. In systems that implement this approach, each memory access request from the processing unit requires the unit to access the memory twice: once to update the counters and once to access the data in memory, thus reducing the effective throughput of memory (i.e., access to application memory regions).

[0044] To reduce the amount of computer resources required for a processing unit to track multiple memory accesses, in some embodiments described herein, the inventors propose using one or more memory management circuits connected to the processing unit and one or more memory components to update at least one of a plurality of statistical counters in response to receiving a memory access command from the processing unit. Optionally, the statistical counter indicates the plurality of memory access commands. For example, when the processing unit has a plurality of memory address ranges, and each of the one or more memory components maps to one or more of the plurality of memory address ranges, the statistical counter may be a range access counter associated with a memory address range, indicating the number of times the memory address range is accessed in the plurality of memory access commands. Optionally, the statistical counter indicates the amount of range access counters that satisfy an identified criterion. For example, the statistical counter may be a watermark counter indicating the amount of range access counters exceeding a high access threshold, wherein the high access threshold indicates the amount of access to a memory address range considered high. Alternatively, the watermark counter may indicate the amount of range access counters less than a low access threshold, wherein the low access threshold indicates another amount of access to a memory address range considered low. Optionally, the statistical counter indicates the amount of memory access commands received from the processing unit. Optionally, one or more processing circuits receive memory access commands in each of the multiple iterations and update at least one of the multiple statistical counters in each of the multiple iterations. Using one or more processing circuits to update at least one statistical counter reduces the amount of resources the processing unit uses to track multiple memory accesses, for example, reducing the number of memory accesses performed by the processing unit and / or reducing the number of processor cycles used by the processing unit to compute memory maps. Reducing the amount of computational resources used by the processing unit improves system performance when executing software programs, for example, by increasing throughput and / or reducing latency when executing one or more tasks of the software program.

[0045] Optionally, at least one of the multiple statistical counters is implemented in one or more memory tracking circuits to further reduce access to one or more memory components, thereby improving system performance.

[0046] Furthermore, in some embodiments, the present invention proposes that one or more memory tracking circuits provide one or more of a plurality of statistical counters to a memory management component to map the application memory of a software program to one or more memory components. Optionally, the memory management component analyzes one or more statistical counters to map application memory. Optionally, the memory management component includes software objects executed by a processing unit. Optionally, the memory management component includes other circuitry optionally connected to one or more memory tracking circuits and one or more memory components. Providing one or more statistical counters to the memory management component helps improve system performance by moving one or more application memory regions of a software program from one of one or more memory components to another. For example, a range access counter for a memory address range exceeding a high access threshold can indicate that the memory address range is frequently accessed, and the application memory region referenced by that memory address range in multiple application memory regions should be stored in a memory component with high performance access characteristics (e.g., low latency and / or high throughput). Similarly, an access counter for another range of memory addresses below a low access threshold can indicate that another memory address range is rarely accessed, and that another application memory region referenced by that other memory address range should be stored in another memory component with relatively low performance access characteristics (e.g., higher latency and / or lower throughput than a memory component with relatively high performance access characteristics). Optionally, the memory mapping component maps application memory while the processing unit executes the software program, and optionally moves one or more application memory regions while the processing unit executes the software program.

[0047] In some embodiments described herein, at least one memory component is a plurality of memory components, including at least two memory components. Optionally, one or more memory tracking circuits include a plurality of local tracking circuits, such that each of the plurality of local tracking circuits is connected to one or more of the plurality of memory components. Optionally, each local tracking circuit is connected to a subset of the plurality of memory components, such that the local tracking circuit is not connected to at least one of the plurality of memory components. Optionally, when at least one of a plurality of memory address ranges associated with the one or more memory components connected to the local tracking circuit includes a local memory address in a memory address command, each local tracking circuit updates at least one statistical counter according to the one or more memory components to which it is connected. When the processing unit is connected to at least one memory component via a host memory controller, the local tracking circuit connected to the at least one memory component may optionally be additionally connected to the host memory controller.

[0048] Optionally, when one or more memory tracking circuits provide one or more statistical counters to the memory management component, these statistical counters may include one or more watermark counters. Optionally, the memory management component performs further analysis on the one or more watermark counters, and based on the result of this further analysis, the memory management component may optionally send a request to one or more memory tracking circuits to provide at least one range access counter. For example, the memory management component may request at least one range access counter only if the result of the further analysis indicates that a high watermark counter exceeds an identified threshold. In this example, as long as the amount of ranges experiencing high access is below the threshold, it may not be necessary to move memory regions. This requires fewer computational resources compared to some other methods that require reading all multiple range access counters to identify memory regions that do not need to be moved. In another example, the memory management component may request one or more range access counters until it receives an amount of range access counters exceeding or equal to a high watermark threshold. In this example, identifying all memory regions experiencing high access rates can be achieved without reading all multiple memory counters, which requires fewer computational resources compared to some other methods that do not use watermark counters.

[0049] When the processing unit executes the operating system, the operating system can address multiple memory components using multiple operating system memory pages. A common practice is to avoid using arbitrary page sizes for the multiple operating system memory pages; that is, each of the multiple operating system memory pages has a page size from an identified set of page sizes. When memory access tracing is performed using the operating system's page tables, the granularity of the memory access tracing is based on the corresponding page size of each of the multiple operating system memory pages. In some embodiments described herein, at least one identified memory address range among the multiple memory address ranges has a range size that is not equal to any of the page size sets. Using one or more memory tracing circuits to trace multiple memory access commands based on multiple memory address ranges supports tracing multiple memory access commands at a granularity different from the operating system's page size. This improves the accuracy of memory mapping calculated based on multiple statistical counters compared to memory mapping calculated when tracing based on the operating system's page size, thereby improving the accuracy of allocating multiple application memory regions to one or more memory components and improving system performance.

[0050] Before detailing at least one embodiment, it should be understood that the embodiments are not necessarily limited to the details of the construction and setup of the components and / or methods illustrated in the following description and / or drawings and / or examples. The implementations described herein support other embodiments, or can be practiced or performed in various ways.

[0051] An embodiment may be a system, method, and / or computer program product. The computer program product may include one or more computer-readable storage media having computer-readable program instructions that cause a processor to perform various aspects of the embodiment.

[0052] The computer-readable storage medium can be a tangible device capable of retaining and storing instructions for use by an instruction execution device. The computer-readable storage medium can be, but is not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes: portable computer floppy disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, and any suitable combination of the foregoing. The computer-readable storage medium as used herein should not be construed as a transient signal itself, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0053] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a suitable computing / processing device, or downloaded to an external computer or external storage device via a network such as the Internet, local area network, wide area network, and / or wireless network. The network may include copper transmission cables, optical fiber transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives and forwards the computer-readable program instructions from the network for storage in a computer-readable storage medium within the suitable computing / processing device.

[0054] Computer-readable program instructions used to perform the operations of the embodiments may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code, compiled locally or just-in-time (JIT), written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, Java, object-oriented Fortran, etc., interpreted programming languages ​​such as JavaScript, Python, etc., and traditional procedural programming languages ​​such as the "C" programming language, Fortran, or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, or as a standalone software package partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including local area networks (LANs) or wide area networks (WANs), and may also be connected to external computers (e.g., via the Internet provided by an Internet service provider). In some embodiments, electronic circuits including programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs) can execute computer-readable program instructions to customize the electronic circuits by using state information of computer-readable program instructions, thereby performing various aspects of the embodiments.

[0055] This document describes aspects of the embodiments in conjunction with flowcharts and / or block diagrams of the methods, apparatus (systems), and computer program products provided in the embodiments. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0056] These computer-readable program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to generate a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create modules for implementing the functions / actions specified in one or more blocks of a flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that can instruct a computer, programmable data processing apparatus, and / or other device to operate in a particular manner, such that the computer-readable storage medium storing the instructions includes an article of art containing instructions for implementing aspects of the functions / actions specified in one or more blocks of a flowchart and / or block diagram.

[0057] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus or other equipment to cause a series of operational steps to be performed on the computer, other programmable apparatus or other equipment, thereby producing a computer-implemented process, such that the instructions executed on the computer, other programmable apparatus or other equipment perform the functions / actions specified in one or more blocks of a flowchart and / or block diagram.

[0058] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products provided in various embodiments. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing one or more specified logical functions. In some alternative implementations, the functions described in the blocks may not be implemented in the order shown in the figures. For example, in fact, two blocks shown consecutively may be executed almost simultaneously, or sometimes in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by systems based on dedicated hardware that perform specific functions or actions, or by combinations of dedicated hardware and computer instructions.

[0059] Now for reference Figure 1 The diagram illustrates a schematic block diagram of an exemplary device 100 provided in some embodiments. In these embodiments, a processing unit 101 is connected to at least one memory component 120.

[0060] For the sake of brevity, the term "memory component 120" will hereafter be used to refer to "at least one memory component 120," and these terms are used interchangeably. Optionally, memory component 120 may include one memory component, such as memory component 120C. Optionally, memory component 120 may include more than one memory component, such as memory component 120A, memory component 120B, and memory component 120C. The memory component may be a random access memory (RAM) component, such as an SRAM component or a DRAM component. Other examples of memory components include read-only memory (ROM) components, electrically erasable programmable ROM (EEPROM), and non-volatile RAM (NVRAM). Optionally, one or more of the memory components 120 may be electrically coupled to the processing unit 101. Optionally, one or more of the memory components 120 may be connected to the processing unit 101 via a host memory controller (not shown).

[0061] Optionally, one or more of the memory components 120 are cache memory components of the processing unit 101. Optionally, one or more of the memory components 120 are connected to another cache memory component (not shown), which is additionally connected to the processing unit 101.

[0062] Optionally, one or more memory tracking circuits 130 are connected to the processing unit 101 and the memory component 120.

[0063] Still referencing Figure 2 This illustration shows a schematic block diagram of another exemplary device 200 provided in some embodiments. In these embodiments, one or more memory tracking circuits 130 include a plurality of local tracking circuits 201, such as local tracking circuit 201A and local tracking circuit 201B. Optionally, each of the plurality of local tracking circuits 201 is connected to one or more of memory components 120. Optionally, each of the plurality of local tracking circuits is connected to a subset of memory components 120 such that each of the plurality of local tracking circuits 201 is not connected to at least one of memory components 120. In this example, local tracking circuit 201A is connected to memory components 120A and 120B, but not to memory component 120C. Furthermore, in this example, local tracking circuit 201B is connected to memory component 120C, but not to memory components 120A and 120B. Optionally, each of the plurality of local tracking circuits 201 is connected to one of the memory components 120.

[0064] Now refer to it again Figure 1Optionally, each of the memory components 120 is mapped to at least one of the plurality of memory address ranges of the processing unit 101.

[0065] Still referencing Figure 3 The diagram illustrates a schematic block diagram of an exemplary address mapping 300 provided in some embodiments. In this example, memory component 120A is mapped to memory address ranges 301A, 301B, and 301C, which are among a plurality of memory address ranges 301. Therefore, when processing unit 101 accesses one of the memory addresses in memory address ranges 301A, 301B, and 301C, processing unit 101 accesses the memory component.

[0066] Similarly, memory component 120B is mapped to memory address range 301D in the plurality of memory address ranges 301, and memory component 120C is mapped to memory address ranges 301E and 301F in the plurality of memory address ranges 301.

[0067] Optionally, the processing unit 101 executes an operating system that uses multiple operating system memory pages to address memory components 120. Optionally, each of the multiple operating system memory pages has a page size that is one of an identified set of page sizes. Optionally, the size of at least one of the multiple memory address ranges 301 is not a member of the identified set of page sizes.

[0068] Now refer to it again Figure 1 Optionally, one or more memory tracking circuits 130 are connected to the memory management component 110. Optionally, the memory management component 110 includes a software object executed by the processing unit 101. Optionally, the memory management component 110 includes memory management circuitry additionally connected to the processing unit 101 and the memory component 120.

[0069] According to some embodiments, the following optional methods may be implemented by system 100 or system 200 in order to track memory access commands and manage memory.

[0070] Still referencing Figure 4The diagram illustrates a flowchart of an optional operational flow 400 for managing memory, as provided in some embodiments. In these embodiments, at 401, one or more memory tracking circuits 130 receive a memory access command including a memory address from processing unit 101. Optionally, the memory address is in one of a plurality of memory address ranges 301. For example, when the memory address is in memory address range 301E, the memory address is a local memory address of memory component 120C. In this example, memory address range 301E includes the local memory address of memory component 120C, which is the memory address in the memory access command. Optionally, processing unit 101 sends the memory access command while executing a software program, optionally for accessing the application memory of the software program.

[0071] In 410, one or more memory tracking circuits 130 optionally update at least one of a plurality of statistical counters. Optionally, the plurality of statistical counters include a plurality of range access counters, each range access counter associated with one of a plurality of memory address ranges 301. Optionally, the plurality of statistical counters include one or more watermark counters, each watermark counter associated with the frequency of access to a memory component. The watermark counter can indicate the amount of memory access range accessed at the frequency associated with the watermark counter. The watermark counter can be a high access counter, indicating the amount of range access counters among the plurality of range access counters exceeding a high access threshold, thereby indicating frequent access to the corresponding memory component associated with the range access counter exceeding the high access threshold. For example, a range access counter for memory address range 301F exceeding a high access threshold can indicate frequent access to memory component 120C associated with memory address range 301F. Another example of a watermark counter is a low access counter, indicating the amount of range access counters among the plurality of range access counters exceeding a low access threshold. There can be more than two watermark counters, each watermark counter associated with one of a plurality of access frequencies of a memory component. Each of two or more watermark counters can be associated with an access threshold that indicates the frequency of access thereby, i.e., the amount of range access counters that exceed the threshold associated with the watermark counter among multiple range access counters.

[0072] Optionally, at least one of the plurality of statistical counters is implemented in one or more memory tracking circuits 130. Optionally, at least one other statistical counter is implemented in one of the memory components 120. Optionally, the memory component implementing at least one other statistical counter is a cache memory component of the processing unit 101. Optionally, at least one other statistical counter is implemented in another cache memory component connected to one or more of the memory components 120.

[0073] Still referencing Figure 5 The diagram illustrates a flowchart of an optional operational flow 500 for updating a statistical counter, as provided in some embodiments. In these embodiments, at 501, one or more memory tracking circuits 130 identify a memory address in a memory access command received at 401. At 502, one or more memory tracking circuits 130 optionally identify a memory address range within a plurality of memory address ranges 301, wherein the memory address range includes a memory address. For example, a memory command may include a memory address within a memory address range 301F. In this example, one or more memory tracking circuits 130 identify a memory address range 301F. Optionally, at 510, one or more memory tracking circuits 130 increment a corresponding range access counter among a plurality of range access counters associated with memory address range 301F. When one or more memory tracking circuits 130 include a plurality of local tracking circuits 201, each of the plurality of local tracking circuits 201 updates at least one statistical counter when at least one memory address range among the plurality of memory address ranges 301 associated with one or more memory components connected to the local tracking circuits includes the memory address of the memory access command. For example, when the local trace circuit 201B identifies that the memory address of a memory access command is within the memory address range 301F associated with the memory component 120C connected to the local trace circuit 201B, the local trace circuit 201B may update one or more statistical counters.

[0074] In step 520, one or more memory tracking circuits 130 optionally determine whether a corresponding range access counter associated with the memory address range 301F exceeds a low access threshold, and in step 521, if it is determined that the corresponding range access counter associated with the memory address range 301F exceeds the low access threshold, one or more memory tracking circuits 130 optionally decrease the low access counter. In step 530, one or more memory tracking circuits 130 optionally determine whether a corresponding range access counter associated with the range of memory address 301F exceeds a high access threshold, and in step 531, if it is determined that the corresponding range access counter associated with the memory address range 301F exceeds the high access threshold, one or more memory tracking circuits 130 optionally increase the high access counter. When one or more watermark counters include two or more watermark counters, one or more tracking circuits 130 may optionally determine for each of the two or more watermark counters whether the corresponding range access counter associated with the memory address range 301F exceeds the threshold associated with the watermark counter, and if it is determined that the corresponding range access counter associated with the memory address range 301F exceeds the threshold associated with the watermark counter, one or more memory tracking circuits 130 may optionally increment the watermark counter.

[0075] Now refer to it again Figure 4 Optionally, while the processing unit 101 executes the software program, one or more memory tracking circuits 130 execute steps 401 and 410. Optionally, the one or more memory tracking circuits 130 repeat steps 401 and 410 in each of a plurality of iterations.

[0076] In 420, one or more memory tracking circuits 130 optionally provide one or more of a plurality of statistical counters to memory management component 110, optionally for mapping application memory of a software program to memory component 120. Optionally, while processing unit 101 executes the software program, one or more memory tracking circuits 130 provide one or more statistical counters. Optionally, while processing unit 101 executes the software program, memory mapping component 110 maps application memory to memory component 120.

[0077] Now refer to it again Figure 6 The document illustrates optional operational flows 600 for memory management provided in some embodiments. In these embodiments, at 601, the memory management component 110 performs analysis of one or more statistical counters. The following are exemplary, non-mandatory methods for performing the analysis.

[0078] Still referencing Figure 7The diagram illustrates a sequence of optional operational flows 700 provided in some embodiments. In these embodiments, at 701, one or more memory tracking circuits 130 provide one or more watermark counters to the memory management component 110. Optionally, the one or more memory tracking circuits 130 provide a subset of the one or more watermark counters in 701, such as only one of the one or more watermark counters. Optionally, the one or more watermark counters include a high access counter. Optionally, the one or more watermark counters include a low access counter. In 702, the one or more memory tracking circuits 130 perform another analysis including the one or more watermark counters. Based on the result of the other analysis, in 710, the memory management component 110 optionally sends a request to the one or more memory tracking circuits 130 in 710 to provide at least one of a plurality of range access counters. For example, when the result of the other analysis indicates that a watermark counter exceeds a frequency threshold, the memory mapping component may request at least one range access counter to identify which of a plurality of memory address ranges is frequently accessed. On the other hand, when the result of another analysis indicates that the watermark counter does not exceed the frequency threshold, the memory mapping component 110 may refuse to perform the other analysis and refuse to modify the application memory mapping of the software program. The other analysis may use one of one or more watermark counters, for example, when only one watermark counter is implemented. The other analysis may use more than one of one or more watermark counters. When one or more watermark counters include at least one of a low access counter and a high access counter, the other analysis may optionally include at least one of the low access counter and the high access counter.

[0079] In response to receiving a request from memory management component 110, in step 711, one or more memory tracking circuits 130 optionally send at least one range access counter to memory management component 110. Optionally, steps 710 and 711 are repeated in multiple read iterations. Optionally, in step 711, one or more memory tracking circuits 130 send a range access counter to memory management component 110, such that memory management component 110 accesses one or more range access counters at a time. Optionally, in each execution of step 711, one or more memory tracking circuits 130 send a subset of multiple range access counters to memory management component 110. Optionally, management component 110 refuses to execute step 710 if a stopping condition is identified, for example, by receiving a range access counter amount exceeding a threshold equal to the value of the watermark counter provided in step 701.

[0080] Now refer to it again Figure 6 Based on the results of the analysis performed in 601, memory management component 110 may optionally perform one or more memory management tasks, such as mapping application memory for software programs. Another example of a memory management task is configuring one or more memory tracking circuits 130.

[0081] Still referencing Figure 8 The diagram illustrates a schematic block diagram of an example memory map 800 provided in some embodiments. Optionally, the application memory of a software program includes multiple application memory regions 801, such as memory application region 801A, memory application region 801B, and memory application region 801C. Optionally, each of the multiple memory application regions is stored in one of the memory components 120. For example, application memory region 801A may be stored in memory component 120A, application memory region 801B may be stored in memory component 120B, and application memory region 801C may be stored in memory component 120C.

[0082] Now refer to it again Figure 6 In 610, in response to the analysis performed in 601 (e.g., using method 700), memory management component 110 can move one or more application memory regions of a plurality of application memory regions 801 from one of memory components 120 to another of memory components 120.

[0083] Still referencing Figure 9 This illustrates a schematic block diagram of another exemplary memory mapping 900 provided in some embodiments. In this example, the result of the analysis may be, for example, that when memory component 120C has higher performance access characteristics than memory component 120A and the analysis results indicate high-frequency access to application memory region 801A, memory management component 110 moves application memory region 801A from memory component 120A to memory component 120C. Optionally, memory management component 110 updates the mapping between application memory and one or more of a plurality of memory address ranges 301, for example, in the page tables of the operating system executed by processing unit 101.

[0084] Now refer to it again Figure 7 In 721, the memory management component 110 may optionally configure one or more watermark thresholds, such as a high watermark threshold or a low watermark threshold, in one or more memory tracking circuits 130. Optionally, in 720, the memory management component 110 performs another analysis of one or more statistical counters and performs 721 based on another result of the further analysis. For example, when a memory component with high-performance access characteristics is not fully utilized, the memory management component 110 may lower the high watermark threshold. Similarly, when a memory component with high-performance access characteristics is overused, the memory management component 110 may raise the high watermark threshold.

[0085] Now refer to it again Figure 4In 430, one or more memory tracking circuits 130 may optionally reset one or more other counters among a plurality of statistical counters. For example, in 420, one or more memory tracking circuits 130 may reset the statistical counters after they have been provided to the memory management component 110. Resetting a counter may involve setting the counter to 0. Resetting a counter may involve setting the counter to an initial value. For example, a low access counter may start with a value equal to the amount of memory in memory component 120 and decrease in 521 for each range of access counters exceeding a low watermark threshold.

[0086] Optionally, one or more memory tracking circuits 130 repeatedly execute multiple iterations including 401 and 410, provide one or more statistical counters in 420, and reset one or more other counters in each of the multiple management iterations.

[0087] The descriptions of various embodiments are for illustrative purposes only and are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology chosen herein is best suited to explain the principles, practical application, or technological advancement of the embodiments, or to enable others skilled in the art to understand the embodiments disclosed herein, compared to technologies available on the market.

[0088] It is anticipated that many related memory tracking circuits will be developed during the expiry date of this patent application, and the scope of the term memory tracking circuit is intended to a priori include all of these new technologies.

[0089] The term "about" as used in this article refers to ±10%.

[0090] The terms “including,” “having,” and their variations mean “including but not limited to.” This term includes the terms “consisting of” and “substantially consisting of.”

[0091] The phrase “consistently of” indicates that a composition or method may include additional components and / or steps, provided that the additional components and / or steps do not substantially alter the fundamental and novel characteristics of the claimed composition or method.

[0092] Unless the context clearly indicates otherwise, the singular forms “a” and “the” used herein include the plural meaning. For example, the terms “a complex” or “at least one complex” can include multiple complexes, including mixtures thereof.

[0093] As used herein, the term "exemplary" means "as an example, instance, or illustration." Any embodiment described as "exemplary" is not necessarily to be construed as being more preferred or advantageous than other embodiments, and / or as excluding combinations of features of other embodiments.

[0094] As used herein, the term "optionally" means "provided in some embodiments and not provided in others." Any particular embodiment may include multiple "optional" features unless these features conflict.

[0095] In this application, various embodiments are presented in a range format. It should be understood that the range format is used merely for convenience and brevity and should not be construed as a fixed limitation on the scope of the embodiments. Therefore, the description of a range should be considered as specifically disclosing all possible subranges and individual numerical values ​​within said ranges. For example, a description of a range, such as from 1 to 6, should be considered as specifically disclosing subranges from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., and individual numbers within that range, such as 1, 2, 3, 4, 5, and 6. This applies regardless of how broad the range may be.

[0096] When this document indicates a range of numbers, it means that any of the listed numbers (fractions or integers) within the indicated range are included. The phrases “range between the first and second indicated numbers” and “range from the first to the second indicated number” are used interchangeably in this document to mean that all fractions and integers in between are included, including the first and second indicated numbers.

[0097] It should be understood that certain features of embodiments described in the context of a single embodiment for the sake of brevity may also be provided in combination in a single embodiment. Conversely, various features of embodiments described in the context of a single embodiment for the sake of brevity may also be provided individually or in any suitable sub-combination or appropriate in any other described embodiment. Certain features described in the context of various embodiments are not considered essential features of these embodiments unless the embodiment is inoperable without these elements.

[0098] While embodiments have been described in conjunction with their specific examples, it will be apparent to those skilled in the art that many alternatives, modifications, and variations will be readily apparent. Therefore, it is intended to cover all such alternatives, modifications, and variations that fall within the spirit and broad scope of the appended claims.

[0099] The applicant's purpose is that all publications, patents, and patent applications mentioned in this specification are incorporated herein by reference in their entirety, as if each individual publication, patent, or patent application were specifically and individually identified when referred to as being incorporated herein by reference. Furthermore, any reference or designation to any document in this application should not be construed as allowing such reference to take precedence over the present invention in the prior art. Section headings should not be construed as necessary limitations with respect to their use. Additionally, the entire contents of any one or more priority documents of this application are incorporated herein by reference.

Claims

1. A method for counting memory access requests, characterized in that, The method is executed iteratively by a memory tracking circuit, which is connected to a processing unit and at least one memory component, including: Within each iteration cycle: In response to a first memory access request sent by the processing unit, a first statistical counter is updated, wherein the first memory access request indicates access to data within a first memory range, the first memory range is associated with the first statistical counter, the first statistical counter indicates the access frequency of data in the first memory range, and the data in the first memory range is located in the at least one memory component; Provide first information to the memory management component, the first information indicating that the first memory range is a high-access memory range.

2. The method according to claim 1, characterized in that, The method further includes: When the value of the first statistical counter exceeds the high access threshold, the first memory range is determined to be a high access memory range.

3. The method according to claim 2, characterized in that, Providing the first information to the memory management component includes: After determining that the first memory range is a high-access memory range, the first information is provided to the memory management component.

4. The method according to claim 1, characterized in that, The method further includes: In response to a second memory access request sent by the processing unit, a second statistical counter is updated, wherein the second memory access request indicates access to data within a second memory range, the second memory range being associated with the second statistical counter, and the data within the second memory range being located in the at least one memory component.

5. The method according to claim 1, characterized in that, The memory tracking circuit includes multiple statistical counters, including the first statistical counter.

6. The method according to claim 1, characterized in that, The method further includes: After providing the first information to the memory management component, the first counter is reset.

7. The method according to claim 2, characterized in that, The high access threshold is configured by the memory management component.

8. A memory tracking circuit, characterized in that, The memory tracking circuit performs the method of any one of claims 1-7.

9. A computer system, characterized in that, It includes a memory management component, a memory tracking circuit, and at least one memory component, wherein the memory tracking circuit is connected to the at least one memory management component, and the memory management component is used to manage the at least one memory management component, and the memory tracking circuit is the memory tracking circuit as described in claim 8.

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