Display device

Abstract

A display device includes: a panel including a pixel, the pixel including: an LED; a capacitor between the first voltage line and the node; a first transistor between the first voltage line and a first electrode of the LED; a second transistor between the data line and the source of the first transistor; a third transistor between the node and the drain of the first transistor; a fourth transistor between the node and a second voltage line; a fifth transistor between the first voltage line and a source of the first transistor; a sixth transistor between the first electrode of the LED and the drain of the first transistor; and a seventh transistor between the second voltage line and the first electrode of the LED, each of the third and fourth transistors including: an active region including a metal oxide; a first gate and a second gate over the active region; and a pattern under the active region.

Description

[0001] This application is a divisional application of patent application No. 202010412439.0, filed on May 15, 2020, entitled "Display Device". Technical Field

[0002] This invention relates to a display device. More specifically, this invention relates to a display device having two types of transistors. Background Technology

[0003] A display device is an output device used to present information in a visual form. A display device includes multiple pixels and driving circuitry for controlling the pixels. The driving circuitry includes, for example, scan driving circuitry and data driving circuitry. Each pixel includes a display element and pixel driving circuitry for controlling the display element. The pixel driving circuitry includes multiple transistors.

[0004] The scan drive circuit and / or data drive circuit are formed using the same process as the pixel. Therefore, the drive circuit also includes multiple transistors. Summary of the Invention

[0005] An exemplary embodiment of the present invention provides a display device, comprising: a display panel including a plurality of pixels, wherein a first pixel includes: a light-emitting diode; a capacitor connected between a first voltage line and a reference node; a first transistor connected between the first voltage line and a first electrode of the light-emitting diode; a second transistor connected between a data line and the source of the first transistor; a third transistor connected between the reference node and the drain of the first transistor; a fourth transistor connected between the reference node and a second voltage line; a fifth transistor connected between the first voltage line and the source of the first transistor; a sixth transistor connected between the first electrode of the light-emitting diode and the drain of the first transistor; and a seventh transistor connected between the second voltage line and the first electrode of the light-emitting diode, each of the third and fourth transistors including: an active region comprising a metal oxide; a first gate and a second gate disposed on a first side of the active region and overlapping the active region; and a pattern disposed on a second side of the active region and overlapping the active region.

[0006] Each of the first, second, fifth, and sixth transistors is a P-type transistor, and each of the third and fourth transistors is an N-type transistor.

[0007] The active region of each of the first, second, fifth, and sixth transistors comprises polysilicon.

[0008] The source of the first transistor extends from the active region of the first transistor.

[0009] The pattern of each of the third transistor and the fourth transistor includes a metal.

[0010] The pattern of each of the third transistor and the fourth transistor includes polysilicon.

[0011] The pattern of each of the third transistor and the fourth transistor includes a conductive material, and the source of the third transistor is electrically connected to the pattern of the third transistor or the source of the fourth transistor is electrically connected to the pattern of the fourth transistor.

[0012] The pattern of each of the third transistor and the fourth transistor includes a conductive material, and the first gate and the second gate of the third transistor are electrically connected to the pattern of the third transistor or the first gate and the second gate of the fourth transistor are electrically connected to the pattern of the fourth transistor.

[0013] The display device further includes a semiconductor pattern disposed below the pattern of each of the third transistor and the fourth transistor and overlapping the active region of the third transistor.

[0014] The active region of the first transistor includes polysilicon, and the semiconductor pattern extends from the active region of the first transistor.

[0015] The seventh transistor includes an active region including a metal oxide, a gate disposed on a first side of the active region of the seventh transistor and overlapping the active region of the seventh transistor, and a pattern disposed on a second side of the active region of the seventh transistor and overlapping the active region of the seventh transistor.

[0016] Each of the first transistor, the second transistor, the fifth transistor, and the sixth transistor is a P-type transistor, and each of the third transistor, the fourth transistor, and the seventh transistor is an N-type transistor.

[0017] The second voltage line and the pattern of each of the third transistor and the fourth transistor are disposed on the same layer and include the same material.

[0018] An exemplary embodiment of the inventive concept provides a display apparatus including a display panel including a pixel, the pixel including: a light emitting diode; a capacitor connected between a first voltage line and a reference node; a first transistor connected between the first voltage line and a first electrode of the light emitting diode; a second transistor connected between a data line and a source of the first transistor; a third transistor connected between the reference node and a drain of the first transistor; a fourth transistor connected between the reference node and a second voltage line; a fifth transistor connected between the first voltage line and the source of the first transistor; a sixth transistor connected between the first electrode of the light emitting diode and the drain of the first transistor; and a seventh transistor connected between the second voltage line and the first electrode of the light emitting diode, each of the third transistor and the fourth transistor including: an active region including a metal oxide; a gate disposed above the active region; and a first pattern including poly-silicon disposed below the active region and overlapping the active region when viewed in a plan view, wherein the first pattern of the fourth transistor extends from the first pattern of the third transistor.

[0019] The first pattern of the third transistor extends from the active region of the first transistor.

[0020] The active region of the fourth transistor extends from the active region of the third transistor.

[0021] Each of the third transistor and the fourth transistor further includes a second pattern disposed between the active region thereof and the first pattern thereof.

[0022] The second voltage line and the second pattern are disposed on a same layer and include a same metal.

[0023] The second pattern of the third transistor at least overlaps the first pattern of the third transistor when viewed in a plan view.

[0024] Each of the first transistor, the second transistor, the fifth transistor, and the sixth transistor is a P-type transistor, and each of the third transistor and the fourth transistor is an N-type transistor.

[0025] An exemplary embodiment of the inventive concept provides a display apparatus including a display panel including a pixel, the pixel including: a light emitting diode; a capacitor connected between a first voltage line receiving a first power voltage and a reference node; a first transistor connected between the first voltage line and a first electrode of the light emitting diode; a second transistor connected between a data line and a source of the first transistor; a third transistor connected between the reference node and a drain of the first transistor; a fourth transistor connected between the reference node and a second voltage line receiving an initialization voltage; a fifth transistor connected between the first voltage line and the source of the first transistor; a sixth transistor connected between the first electrode of the light emitting diode and the drain of the first transistor; and a seventh transistor connected between the second voltage line and the first electrode of the light emitting diode, each of the third transistor and the fourth transistor including: an active layer including a metal oxide; a gate disposed above the active layer; and a pattern disposed below the active layer and overlapping the active layer when viewed in a plan view, the first transistor including: an active layer including poly-silicon; and a gate disposed above the active layer of the first transistor, wherein the active layer of the first transistor is disposed lower than the active layer of each of the third transistor and the fourth transistor. BRIEF DESCRIPTION OF DRAWINGS

[0026] The above and other features of the inventive concept will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:

[0027] Figure 1 is a block diagram illustrating a display apparatus according to an exemplary embodiment of the inventive concept;

[0028] Figure 2 is an equivalent circuit diagram illustrating a pixel according to an exemplary embodiment of the inventive concept;

[0029] Figure 3 is a plan view illustrating a third transistor according to an exemplary embodiment of the inventive concept; Figure 2 is a waveform diagram illustrating driving signals for driving the pixel illustrated in FIG. 1A;

[0030] Figure 4A and Figure 4B are cross-sectional views illustrating a display panel corresponding to the pixel according to an exemplary embodiment of the inventive concept;

[0031] Figure 5A is a plan view illustrating a third transistor according to an exemplary embodiment of the inventive concept;

[0032] Figure 5B , Figure 5C and Figure 5D are cross-sectional views illustrating the third transistor illustrated in FIG. 2A, taken along line I-I' of FIG. 2A; Figure 5A Figure 5A Figure 5A ​

[0033] Figure 6A is a cross-sectional view illustrating a fourth transistor according to an exemplary embodiment of the inventive concept;

[0034] Figure 6B is a cross-sectional view illustrating a fourth transistor according to an exemplary embodiment of the inventive concept;

[0035] Figure 7A is a cross-sectional view illustrating a fourth transistor according to an exemplary embodiment of the inventive concept;

[0036] Figure 7B is a cross-sectional view illustrating a fourth transistor according to an exemplary embodiment of the inventive concept;

[0037] Figure 8A is a cross-sectional view illustrating a fourth transistor according to an exemplary embodiment of the inventive concept;

[0038] Figure 8B is a cross-sectional view illustrating a seventh transistor according to an exemplary embodiment of the inventive concept;

[0039] Figure 9 is a plan view illustrating a pixel according to an exemplary embodiment of the inventive concept;

[0040] Figure 10A 、 Figure 10B 、 Figure 10C 、 Figure 10D 、 Figure 10E 、 Figure 10F 、 Figure 10G 、 Figure 10H 、 Figure 10I 、 Figure 10J and Figure 10K is a plan view illustrating a pattern of a pixel according to an exemplary embodiment of the inventive concept; and

[0041] Figure 11 is a cross-sectional view illustrating a display panel corresponding to a first transistor and a third transistor according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0042] In this specification, when it is referred to that an element or a layer is "on" or "connected to" or "coupled to" another element or layer, it can be directly on or connected or coupled to the other element or layer, or an intervening element or layer can be present.

[0043] Throughout the drawings, like reference numerals can refer to like elements. In the drawings, the thickness of layers, films, and regions can be exaggerated for clarity.

[0044] As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0045] Hereinafter, exemplary embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0046] Figure 1 is a block diagram illustrating a display apparatus DD according to an exemplary embodiment of the inventive concept. The display apparatus DD includes a timing controller TC, a scan driving circuit SDC, a data driving circuit DDC, and a display panel DP. In the present exemplary embodiment, the display panel DP will be described as a light emitting type display panel. The light emitting type display panel can include an organic light emitting display panel or a quantum dot light emitting display panel.

[0047] The timing controller TC receives an input image signal, converts a data format of the input image signal into a data format suitable for an interface between the timing controller TC and the data driving circuit DDC, and generates image data D-RGB. The timing controller TC outputs the image data D-RGB as well as various control signals DCS and SCS.

[0048] The scan driving circuit SDC receives a scan control signal SCS from the timing controller TC. The scan control signal SCS includes a vertical start signal for starting an operation of the scan driving circuit SDC and a clock signal for determining an output timing of a signal output from the scan driving circuit SDC. The scan driving circuit SDC generates a plurality of scan signals and sequentially outputs the scan signals to corresponding signal lines SL1 to SLn and GL1 to GLn. In addition, the scan driving circuit SDC generates a plurality of light emitting control signals in response to the scan control signal SCS and outputs the light emitting control signals to corresponding signal lines EL1 to ELn.

[0049] In Figure 1 , the scan signals and the light emitting control signals are output from one scan driving circuit SDC, but the inventive concept is not limited thereto. For example, a plurality of scan driving circuits can generate and output the scan signals after dividing the scan signals, and can generate and output the light emitting control signals after dividing the light emitting control signals. In addition, in the exemplary embodiment of the inventive concept, the scan driving circuit that generates and outputs the scan signals can be provided separately from the scan driving circuit that generates and outputs the light emitting control signals.

[0050] The data driving circuit DDC receives the data control signal DCS and the image data D-RGB from the timing controller TC. The data driving circuit DDC converts the image data D-RGB into a data signal and outputs the data signal to a plurality of data lines DL1 to DLm. The data signal is an analog voltage corresponding to a gray value of the image data D-RGB.

[0051] The light emitting display panel DP includes a first group of scan lines SL1 to SLn, a second group of scan lines GL1 to GLn, a third group of scan lines HL1 to HLn, light emitting lines EL1 to ELn, data lines DL1 to DLm, a first voltage line PL, a second voltage line RL, and a plurality of pixels PX. The first group of scan lines SL1 to SLn, the second group of scan lines GL1 to GLn, the third group of scan lines HL1 to HLn, and the light emitting lines EL1 to ELn extend in a first direction DR1 and are arranged in a second direction DR2.

[0052] The data lines DL1 to DLm are insulated from and cross the first group of scan lines SL1 to SLn, the second group of scan lines GL1 to GLn, the third group of scan lines HL1 to HLn, and the light emitting lines EL1 to ELn. Each of the pixels PX is connected to a corresponding one of the signal lines. The connection relationship between the pixels PX and the signal lines can vary depending on the configuration of the pixel driving circuit of the pixels PX.

[0053] The first voltage line PL receives a first power voltage ELVDD. The second voltage line RL receives an initialization voltage Vint. The initialization voltage Vint has a level lower than that of the first power voltage ELVDD. The display panel DP receives a second power voltage ELVSS. The second power voltage ELVSS has a level lower than that of the first power voltage ELVDD.

[0054] In the above description, reference is made to Figure 1 A display device DD according to the present embodiment is described, but the display device DD is not limited thereto. For example, depending on the configuration of the pixel driving circuit, signal lines can be added or omitted. In addition, the connection relationship between one pixel PX and the signal lines can vary.

[0055] The pixel PX can include a plurality of groups that generate light of different colors from each other. For example, the pixel PX can include a red pixel for generating red light, a green pixel for generating green light, and a blue pixel for generating blue light. The light emitting diode of the red pixel, the light emitting diode of the green pixel, and the light emitting diode of the blue pixel can include a light emitting layer including materials different from each other.

[0056] The pixel driving circuit can include a plurality of transistors and a capacitor electrically connected to the transistors. At least one of the scan driving circuit SDC and the data driving circuit DDC can include a plurality of transistors formed by the same process as the pixel driving circuit.

[0057] The signal lines, the pixels PX, the scan driving circuit SDC, and the data driving circuit DDC described above can be formed on the base substrate through a plurality of photolithography processes. The plurality of insulating layers can be formed on the base substrate through a plurality of deposition processes or coating processes. The insulating layers can be thin layers corresponding to the pixels PX, and a portion of the insulating layers can include insulating patterns overlapping only specific conductive patterns. The insulating layers can include organic layers and / or inorganic layers.

[0058] Figure 2 is an equivalent circuit diagram illustrating a pixel PXij according to an exemplary embodiment of the present inventive concept. Figure 3 is a waveform diagram illustrating driving signals for driving the pixel PXij illustrated in Figure 2

[0059] As a representative example, Figure 2 illustrates a pixel PXij connected to an i-th scan line SLi among a first group of scan lines SL1 to SLn and connected to a j-th data line DLj among data lines DL1 to DLm.

[0060] In the present exemplary embodiment, the pixel driving circuit can include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, and a capacitor Cst. In the present exemplary embodiment, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are P-type transistors, and the third transistor T3 and the fourth transistor T4 are N-type transistors. However, the first to seventh transistors T1 to T7 are not limited thereto, and the first to seventh transistors T1 to T7 can be implemented as one of P-type transistors and N-type transistors. In addition, in the present exemplary embodiment, at least one of the first to seventh transistors T1 to T7 can be omitted.

[0061] In the present exemplary embodiment, the first transistor T1 can be a driving transistor, and the second transistor T2 can be a switching transistor. The capacitor Cst is connected between a first voltage line PL receiving a first power voltage ELVDD and a reference node RD. The capacitor Cst includes a first electrode Cst1 connected to the reference node RD and a second electrode Cst2 connected to the first voltage line PL.

[0062] ​The first transistor T1 is connected between the first voltage line PL and a first electrode (e.g., an anode) of the light emitting diode OLED. The source S1 of the first transistor T1 is electrically connected to the first voltage line PL. In the following description, the expression "a transistor is electrically connected to a signal line" can mean that a source, a drain, or a gate of the transistor is integrally provided with or connected to the signal line through a connection electrode. Also, the expression "a transistor is electrically connected to another transistor" can mean that a source, a drain, or a gate of one transistor is integrally provided with or connected to a source, a drain, or a gate of the other transistor through a connection electrode. Another transistor can be provided or omitted between the source S1 of the first transistor T1 and the first voltage line PL.

[0063] The drain D1 of the first transistor T1 is electrically connected to the anode of the light emitting diode OLED. Another transistor can be provided or omitted between the drain D1 of the first transistor T1 and the anode of the light emitting diode OLED. The gate G1 of the first transistor T1 is electrically connected to the reference node RD.

[0064] The second transistor T2 is connected between the jth data line DLj and the source S1 of the first transistor T1. The source S2 of the second transistor T2 is electrically connected to the jth data line DLj, and the drain D2 of the second transistor T2 is electrically connected to the source S1 of the first transistor T1. In the present exemplary embodiment, the gate G2 of the second transistor T2 can be electrically connected to the ith scan line SLi in the first group.

[0065] The third transistor T3 is connected between the reference node RD and the drain D1 of the first transistor T1. The drain D3 of the third transistor T3 is electrically connected to the drain D1 of the first transistor T1, and the source S3 of the third transistor T3 is electrically connected to the reference node RD. The third transistor T3 can include a plurality of gates G3. In the present exemplary embodiment, two gates G3-1 and G3-2 of the third transistor T3 can be electrically connected to the ith scan line GLi in the second group. In another exemplary embodiment of the present inventive concept, the third transistor T3 can include a single gate.

[0066] The fourth transistor T4 is connected between the reference node RD and the second voltage line RL. The drain D4 of the fourth transistor T4 is electrically connected to the reference node RD, and the source S4 of the fourth transistor T4 is electrically connected to the second voltage line RL. The fourth transistor T4 can include a plurality of gates G4. In another exemplary embodiment of the present inventive concept, the fourth transistor T4 can include a single gate.

[0067] In the present exemplary embodiment, the two gates G4-1 and G4-2 of the fourth transistor T4 can be electrically connected to the i-th scan line HLi in the third group. Since the third transistor T3 and the fourth transistor T4 include a plurality of gates, the leakage current of the pixel PXij can be reduced.

[0068] The fifth transistor T5 is connected between the first voltage line PL and the source S1 of the first transistor T1. The source S5 of the fifth transistor T5 is electrically connected to the first voltage line PL, and the drain D5 of the fifth transistor T5 is electrically connected to the source S1 of the first transistor T1. The gate G5 of the fifth transistor T5 can be electrically connected to the i-th light-emitting line ELi.

[0069] The sixth transistor T6 is connected between the drain D1 of the first transistor T1 and the light-emitting diode OLED. The source S6 of the sixth transistor T6 is electrically connected to the drain D1 of the first transistor T1, and the drain D6 of the sixth transistor T6 is electrically connected to the anode of the light-emitting diode OLED. The gate G6 of the sixth transistor T6 can be electrically connected to the i-th light-emitting line ELi. In the exemplary embodiment of the present inventive concept, the gate G6 of the sixth transistor T6 can be connected to a signal line different from the signal line to which the gate G5 of the fifth transistor T5 is connected.

[0070] The seventh transistor T7 is connected between the drain D6 of the sixth transistor T6 and the second voltage line RL. The source S7 of the seventh transistor T7 is electrically connected to the drain D6 of the sixth transistor T6, and the drain D7 of the seventh transistor T7 is electrically connected to the second voltage line RL. The gate G7 of the seventh transistor T7 can be electrically connected to the i+1-th scan line SLi+1 in the first group.

[0071] The operation of the pixel PXij will be described in more detail with reference to Figure 2 and Figure 3 The operation of the pixel PXij will be described in more detail with reference to Figure 1 The display device DD (refer to FIG. 1) displays an image every frame period. During each frame period, the signal lines of each of the first group of scan lines SL1 to SLn, the second group of scan lines GL1 to GLn, the third group of scan lines HL1 to HLn, and the light-emitting lines EL1 to ELn are sequentially scanned. Figure 3 A portion of one frame period is shown.

[0072] With reference to Figure 3 , each of the signals Ei, GIi, GWPi, GWNi, and GWPi+1 can have a high level V-HIGH for a portion of the period and a low level V-LOW for another portion of the period. When the corresponding signal has the high level V-HIGH, the N-type transistor is turned on, and when the corresponding signal has the low level V-LOW, the P-type transistor is turned on.

[0073] When the light-emitting control signal Ei has a high level V-HIGH, the fifth transistor T5 and the sixth transistor T6 are turned off. When the fifth transistor T5 and the sixth transistor T6 are turned off, no current path is formed between the first voltage line PL and the light-emitting diode OLED. Therefore, the period during which no current path is formed can be a non-light-emitting period.

[0074] When the first scan signal GIi applied to the i-th scan line HLi in the third group has a high level V-HIGH, the fourth transistor T4 is turned on. When the fourth transistor T4 is turned on, the reference node RD is initialized by the initialization voltage Vint.

[0075] When the second scan signal GWPi applied to the i-th scan line SLi in the first group has a low level V-LOW and the third scan signal GWNi applied to the i-th scan line GLi in the second group has a high level V-HIGH, the second transistor T2 and the third transistor T3 are turned on.

[0076] Since the reference node RD is initialized to the initialization voltage Vint, the first transistor T1 is in the on state. When the first transistor T1 is on, it is in the same state as the data signal Dj (reference). Figure 2 The voltage corresponding to the data signal Dj is applied to the reference node RD. In this case, the capacitor Cst is charged with the voltage corresponding to the data signal Dj.

[0077] When the fourth scan signal GWPi+1 applied to the (i+1)th scan line SL1+1 in the first group has a low level V-LOW, the seventh transistor T7 is turned on. When the seventh transistor T7 is turned on, the anode of the light-emitting diode (OLED) is initialized to the initialization voltage Vint. The parasitic capacitance of the OLED can then be discharged.

[0078] When the light emission control signal Ei is at a low level (V-LOW), the fifth transistor T5 and the sixth transistor T6 are turned on. When the fifth transistor T5 is turned on, the first power supply voltage ELVDD is applied to the first transistor T1. When the sixth transistor T6 is turned on, the first transistor T1 and the light-emitting diode (OLED) are electrically connected to each other. The OLED produces light with a brightness corresponding to the amount of current applied to it.

[0079] Figure 4A and Figure 4B This is a cross-sectional view of a display panel DP corresponding to pixels of an exemplary embodiment of the present invention. Figure 4A and Figure 4B It shows the relationship with Figure 2 The cross-sections of the portions corresponding to the first transistor T1 and the third transistor T3 shown in the figure.

[0080] refer to Figure 4A andFigure 4B The display panel DP can include a base layer BL, and a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE disposed on the base layer BL in a third direction DR3. The display panel DP can further include functional layers such as an anti-reflection layer and a refractive index control layer. The circuit element layer DP-CL includes at least circuit elements and a plurality of insulating layers. Hereinafter, the insulating layers can include organic layers and / or inorganic layers.

[0081] The insulating layers, the semiconductor layer, and the conductive layer are formed through a coating and deposition process. Then, the insulating layers, the semiconductor layer, and the conductive layer are selectively patterned through a photolithography process. At least one of the semiconductor pattern, the conductive pattern, and the signal line is formed through the above-described method.

[0082] The base layer BL can include a synthetic resin film. The synthetic resin film can include a thermosetting resin. Specifically, the synthetic resin film (or synthetic resin layer) can be a polyimide-based resin layer, but is not limited thereto. The synthetic resin layer can include at least one of an acrylic resin, a methacrylic resin, a polyisoprene, a vinyl-based resin, an epoxy-based resin, a polyurethane-based resin, a cellulose-based resin, a siloxane-based resin, a polyamide-based resin, and a perylene-based resin. In addition, the base layer BL can include a glass substrate, a metal substrate, or an organic / inorganic composite substrate.

[0083] At least one inorganic layer is formed on an upper surface of the base layer BL. The inorganic layer can include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer can be provided in a plurality. The inorganic layer can form a barrier layer BRL and / or a buffer layer BFL. The barrier layer BRL and the buffer layer BFL can be selectively disposed. For example, the barrier layer BRL can be disposed between the buffer layer BFL and the base layer BL.

[0084] The barrier layer BRL can prevent foreign substances from entering from the outside. The barrier layer BRL can include a silicon oxide layer and a silicon nitride layer. Each of the silicon oxide layer and the silicon nitride layer can be provided in a plurality, and the silicon oxide layer and the silicon nitride layer can be alternately stacked with each other.

[0085] The buffer layer BFL can be disposed on the barrier layer BRL. The buffer layer BFL can increase a coupling force between the base layer BL and the semiconductor pattern and / or the conductive pattern. The buffer layer BFL can include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer can be alternately stacked with each other.

[0086] A semiconductor pattern is disposed on the buffer layer BFL. The semiconductor pattern disposed directly on the buffer layer BFL can be a first semiconductor pattern. The first semiconductor pattern can include a silicon semiconductor. The first semiconductor pattern can include polysilicon, but is not limited thereto. The first semiconductor pattern can include amorphous silicon.

[0087] Figure 4A and Figure 4B Only a portion of the first semiconductor pattern is shown, and the first semiconductor pattern can be further disposed in another region of the pixel PXij (refer to Figure 2 ). The first semiconductor pattern can have different electrical properties according to whether it is doped. The first semiconductor pattern can include a doped region and an undoped region. In other words, the first semiconductor pattern can include a first region and a second region. The doped region can be doped with an N-type dopant or a P-type dopant. A P-type transistor includes a doped region doped with a P-type dopant. An N-type transistor includes a doped region doped with an N-type dopant.

[0088] The doped region has a higher electrical conductivity than the electrical conductivity of the undoped region, and functions as an electrode or a signal line. The undoped region corresponds to an active region (or a channel) of a transistor. In other words, a first portion of the first semiconductor pattern can be an active region of a transistor, a second portion of the first semiconductor pattern can be a source or a drain of a transistor, and a third portion of the first semiconductor pattern can be a connection signal line (or a connection electrode).

[0089] As shown in Figure 4A and Figure 4B , a source S1, an active region A1, and a drain D1 of the first transistor T1 are formed of the first semiconductor pattern. The source S1 and the drain D1 of the first transistor T1 extend from the active region A1 in opposite directions with respect to each other.

[0090] Figure 4A and Figure 4B A portion of a connection signal line SCL formed of a semiconductor pattern is shown. When viewed in a plan view, the connection signal line SCL can be connected to a drain D6 of the sixth transistor T6 (refer to Figure 2 ).

[0091] A first insulating layer 10 is disposed on the buffer layer BFL. The first insulating layer 10 is commonly disposed with each pixel PX (refer to Figure 1The first insulating layer 10 overlaps and covers the first semiconductor pattern. The first insulating layer 10 may include an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In this exemplary embodiment, the first insulating layer 10 may be a silicon oxide layer with a single-layer structure. The insulating layer of the circuit element layer DP-CL, described later, may include an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure as well as the first insulating layer 10. The inorganic layer may include at least one of the materials described above.

[0092] The gate G1 of the first transistor T1 is disposed on the first insulating layer 10. The gate G1 may be part of a metal pattern. The gate G1 of the first transistor T1 overlaps with the active region A1 of the first transistor T1. In the doping process of the first semiconductor pattern, the gate G1 of the first transistor T1 is used as a mask.

[0093] A second insulating layer 20 is disposed on the first insulating layer 10 to cover the gate G1. The second insulating layer 20 is commonly grounded with each pixel PX (reference). Figure 1 The second insulating layer 20 may include inorganic and / or organic layers, and may have a single-layer or multi-layer structure. In this exemplary embodiment, the second insulating layer 20 may be a silicon oxide layer with a single-layer structure.

[0094] The upper electrode UE can be disposed on the second insulating layer 20. The upper electrode UE can overlap with the gate G1. The upper electrode UE can be part of a metal pattern or part of a doped semiconductor pattern. A portion of the gate G1 and the upper electrode UE overlapping this portion of the gate G1 can be a capacitor Cst (refer to...). Figure 2 In an exemplary embodiment of the present invention, the upper electrode UE may be omitted.

[0095] In an exemplary embodiment of the present invention, the second insulating layer 20 may be replaced by an insulating pattern. An upper electrode UE is disposed on the insulating pattern. The upper electrode UE may be used as a mask for forming the insulating pattern from the second insulating layer 20.

[0096] The first electrode Cst1 and the second electrode Cst2 of capacitor Cst (reference) Figure 2 The first electrode Cst1 can be formed with the gate G1 and the upper electrode UE using the same process. The first electrode Cst1 can be disposed on the first insulating layer 10. The first electrode Cst1 can be electrically connected to the gate G1. The first electrode Cst1 can be provided integrally with the gate G1.

[0097] The second electrode Cst2 can be disposed on the second insulating layer 20. The second electrode Cst2 can be electrically connected to the upper electrode UE. The second electrode Cst2 can be provided integrally with the upper electrode UE.

[0098] A third insulating layer 30 is provided on the second insulating layer 20 to cover the upper electrode UE. In the present exemplary embodiment, the third insulating layer 30 can be a silicon oxide layer having a single layer structure. The source S2, S5, S6, and S7 (refer to Figure 2 ), the drain D2, D5, D6, and D7 (refer to Figure 2 ), and the gate G2, G5, G6, and G7 (refer to Figure 2 ) of the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 (refer to Figure 2 ) can be formed by the same process as the source S1, the drain D1, and the gate G1 of the first transistor T1, respectively.

[0099] A semiconductor pattern is provided on the third insulating layer 30. Hereinafter, the semiconductor pattern provided directly on the third insulating layer 30 is referred to as a "second semiconductor pattern". The second semiconductor pattern can include a metal oxide. The oxide semiconductor can include a crystalline oxide semiconductor or an amorphous oxide semiconductor. For example, the oxide semiconductor can include a metal oxide of zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti), or a mixture of a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti) and an oxide thereof. The oxide semiconductor can include indium tin oxide (ITO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (IZO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium zinc tin oxide (IZTO), or zinc tin oxide (ZTO).

[0100] Figure 4A and Figure 4B Only a part of the second semiconductor pattern is shown, and the second semiconductor pattern can be further provided in another region of the pixel PXij (refer to Figure 2 ). The second semiconductor pattern can include a plurality of regions that are distinguished from each other depending on whether a metal oxide is reduced. A region in which a metal oxide is reduced (hereinafter referred to as a "reduced region") has a higher electrical conductivity than a region in which a metal oxide is not reduced (hereinafter referred to as an "unreduced region"). The reduced region functions as an electrode or a signal line. The unreduced region corresponds to an active region (or a channel) of a transistor. In other words, a first part of the second semiconductor pattern can be an active region of a transistor, a second part of the second semiconductor pattern can be a source or a drain of a transistor, and a third part of the second semiconductor pattern can be a connection electrode or a connection signal line.

[0101] As Figure 4A and Figure 4BAs shown in FIG. 2, the source S3, the active region A3, and the drain D3 of the third transistor T3 are formed of the second semiconductor pattern. The source S3 and the drain D3 of the third transistor T3 include a metal reduced from a metal oxide semiconductor. The source S3 and the drain D3 can include a metal layer having a predetermined thickness from an upper surface of the second semiconductor pattern and including the reduced metal.

[0102] The fourth insulating layer 40 is disposed on the third insulating layer 30 to cover the second semiconductor pattern. In the present exemplary embodiment, the fourth insulating layer 40 can be a silicon oxide layer having a single layer structure. The gate G3 of the third transistor T3 is disposed on the fourth insulating layer 40. The gate G3 can be a part of a metal pattern. The gate G3 of the third transistor T3 overlaps the active region A3 of the third transistor T3.

[0103] In the exemplary embodiment of the present inventive concept, the fourth insulating layer 40 can be replaced with an insulating pattern. The gate G3 of the third transistor T3 is disposed on the insulating pattern. In the present exemplary embodiment, the gate G3 can have substantially the same shape as the insulating pattern when viewed in a plan view. In the present exemplary embodiment, one gate G3 is shown for convenience of explanation, but the third transistor T3 can include two gates G3-1 and G3-2 as shown in FIG. 3. Figure 2

[0104] The fifth insulating layer 50 is disposed on the fourth insulating layer 40 to cover the gate G3. In the present exemplary embodiment, the fifth insulating layer 50 can include a silicon oxide layer and a silicon nitride layer. The fifth insulating layer 50 can include a silicon oxide layer and a silicon nitride layer alternately stacked with the silicon oxide layer.

[0105] The source S4 (reference numeral 54), the drain D4 (reference numeral 44), and the gate G4 (reference numeral 64) of the fourth transistor T4 (reference numeral 40) can be formed by the same process as the source S3, the drain D3, and the gate G3 of the third transistor T3, respectively. Figure 2 Figure 2 Figure 2 Figure 2

[0106] ​​​​​At least one insulating layer is further disposed on the fifth insulating layer 50. In the present exemplary embodiment, a sixth insulating layer 60 and a seventh insulating layer 70 can be disposed on the fifth insulating layer 50. The sixth insulating layer 60 and the seventh insulating layer 70 can be organic layers and can have a single layer or a multi-layer structure. The sixth insulating layer 60 and the seventh insulating layer 70 can be polyimide-based resin layers having a single layer structure, but they are not limited thereto. The sixth insulating layer 60 and the seventh insulating layer 70 can include at least one of an acrylic-based resin, a methacrylic-based resin, a polyisoprene, a vinyl-based resin, an epoxy-based resin, a polyurethane-based resin, a cellulose-based resin, a siloxane-based resin, a polyamide-based resin, and a perylene-based resin.

[0107] As shown in Figure 4A , a first connection electrode CNE1 can be disposed on the sixth insulating layer 60. The first connection electrode CNE1 can be connected to the connection signal line SCL (or a connection electrode) through a first contact hole CH1 passing through the first to sixth insulating layers 10 to 60. An organic light emitting diode OLED is disposed on the seventh insulating layer 70. An anode AE of the organic light emitting diode OLED is disposed on the seventh insulating layer 70. A pixel definition layer PDL is disposed on the seventh insulating layer 70. The anode AE is connected to the first connection electrode CNE1 through a contact hole CH-70 passing through the seventh insulating layer 70.

[0108] In Figure 4A , the first connection electrode CNE1 is directly connected to the connection signal line SCL, but is not limited thereto. Referring to Figure 4B , a first connection electrode CNE10 can be disposed on the fifth insulating layer 50. The first connection electrode CNE10 can be connected to the connection signal line SCL through a first contact hole CH1 passing through the first to fifth insulating layers 10 to 50, and a second connection electrode CNE20 can be connected to the first connection electrode CNE10 through a contact hole CH-60 passing through the sixth insulating layer 60. In the exemplary embodiment of the present inventive concept, at least one of the fifth insulating layer 50 and the sixth insulating layer 60 can be omitted.

[0109] At least a portion of the anode AE is exposed through an opening OP of the pixel definition layer PDL. The opening OP of the pixel definition layer PDL can define a light emitting area PXA. For example, the pixel PX (referring to Figure 1 ) can be regularly arranged on a plane of the display panel DP (referring to Figure 1 ). An area in which the pixels PX are arranged can be referred to as a pixel area, and one pixel area can include the light emitting area PXA and a non-light emitting area NPXA adjacent to the light emitting area PXA. The non-light emitting area NPXA can surround the light emitting area PXA.

[0110] The hole control layer HCL can be commonly disposed in the light emitting area PXA and the non-light emitting area NPXA. A common layer such as the hole control layer HCL can be commonly formed in the respective pixels PX. The hole control layer HCL can include a hole transport layer, and can further include a hole injection layer.

[0111] The light emitting layer EML can be disposed on the hole control layer HCL. The light emitting layer EML can be disposed in an area corresponding to the opening OP. The light emitting layer EML can be formed in each of the respective pixels PX after being divided into a plurality of portions.

[0112] In the present exemplary embodiment, the patterned light emitting layer EML is illustrated as a representative example, but the light emitting layer EML can be commonly disposed in the respective pixels PX. In this case, the light emitting layer EML can generate white light or blue light. In addition, the light emitting layer EML can have a multi-layer structure.

[0113] The electron control layer ECL can be disposed on the light emitting layer EML. The electron control layer ECL can include an electron transport layer and an electron injection layer. The cathode CE can be disposed on the electron control layer ECL. The electron control layer ECL and the cathode CE can be commonly disposed in the respective pixels PX.

[0114] The thin film encapsulation layer TFE is disposed on the cathode CE. The thin film encapsulation layer TFE is commonly disposed in the respective pixels PX. In the present exemplary embodiment, the thin film encapsulation layer TFE directly covers the cathode CE. In the exemplary embodiment of the present inventive concept, a cap layer directly covering the cathode CE can be further provided. In the exemplary embodiment of the present inventive concept, the stack structure of the organic light emitting diode OLED can have a structure that is vertically inverted (e.g., upside down) compared to the structure illustrated in Figure 4A and Figure 4B

[0115] The thin film encapsulation layer TFE includes at least an inorganic layer or an organic layer. In the exemplary embodiment of the present inventive concept, the thin film encapsulation layer TFE can include two inorganic layers and an organic layer disposed between the two inorganic layers. In the exemplary embodiment of the present inventive concept, the thin film encapsulation layer TFE can include a plurality of inorganic layers and a plurality of organic layers alternately stacked with the inorganic layers.

[0116] The inorganic layer of the thin film encapsulation layer TFE protects the organic light emitting diode OLED from moisture and oxygen, and the organic layer of the thin film encapsulation layer TFE protects the organic light emitting diode OLED from foreign substances such as dust particles. The inorganic layer of the thin film encapsulation layer TFE can include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer, but is not limited thereto. The organic layer of the thin film encapsulation layer TFE can include an acrylic organic layer, but is not limited thereto. ​

[0117] Figure 5A is a plan view showing a third transistor T3 according to an example embodiment of the present inventive concept. Figure 5B to Figure 5D is a cross-sectional view taken along line I-I' in Figure 5A Figure 5A Figure 1 to Figure 4B Detailed descriptions of elements identical with those described with reference to

[0118] With reference to Figure 5A to Figure 5D , the third transistor T3 can further include a pattern LSP. The pattern LSP can include a material having a high light absorption rate or a material having a high light reflection rate. The pattern LSP is disposed under the second semiconductor pattern SCP2 to block light incident from the outside to the second semiconductor pattern SCP2 (particularly, the active region A3 of the third transistor T3). In other words, the pattern LSP can be a light blocking pattern. For example, the pattern LSP can prevent the external light from changing the voltage-current characteristic of the active region A3 of the third transistor T3 and from causing a leakage current.

[0119] With reference to Figure 5A , the source S3, the active region A3, and the drain D3 of the third transistor T3 correspond to portions different from each other of the second semiconductor pattern SCP2. The gate G3 of the third transistor T3 corresponds to a portion of the i-th scan line GLi in the second group.

[0120] As shown in Figure 5B , the pattern LSP can be disposed on the buffer layer BFL. The pattern LSP can include the same material as the source S1 and the drain D1 of the first transistor T1 (with reference to Figure 4A ). The pattern LSP includes a metal.

[0121] The pattern LSP and the source S1 and the drain D1 of the first transistor T1 (with reference to Figure 4A ) can be formed of the first semiconductor pattern. For example, the pattern LSP can include doped polysilicon. In other words, the pattern LSP can be a semiconductor pattern different from the active region A3 of the third transistor T3. The pattern LSP includes at least polysilicon.

[0122] As shown in Figure 5A and Figure 5B ​​The third transistor T3 can include a first gate G3-1 and a second gate G3-2, and a first active region A3-1 and a second active region A3-2 corresponding to the first gate G3-1 and the second gate G3-2, respectively, as shown in FIG. 1B. For example, the first gate G3-1 can overlap the first active region A3-1, and the second gate G3-2 can overlap the second active region A3-2. A region between the first active region A3-1 and the second active region A3-2 corresponds to the drain / source DS3 of the second semiconductor pattern SCP2. In Figure 5A The drain / source DS3 is shown as having an elliptical shape, but is not limited thereto. Figure 5A and Figure 5B The third transistor T3 shown in FIG. 1B has a circuit configuration in which two transistors are connected in series in an equivalent circuit.

[0123] As shown in FIG. 1B, the pattern LSP can be disposed on the first insulating layer 10. The pattern LSP can include the same material as the gate G1 of the first transistor T1 (refer to FIG. 1A). Figure 5C As shown in FIG. 1B, the pattern LSP can be disposed on the second insulating layer 20. The pattern LSP can include the same material as the upper electrode UE. Some signal lines such as the second voltage line RL (refer to FIG. 1A) can be disposed on the same layer as the upper electrode UE. Figure 4A Figure 5D Figure 2

[0124] In FIG. 1B, the pattern LSP can correspond to a floating electrode. The pattern LSP is electrically isolated without being electrically connected to other electrodes and other signal lines. However, the inventive concept is not limited thereto. For example, the pattern LSP can be electrically connected to a gate or a source of a corresponding transistor. Figure 5A to Figure 5D

[0125] Figure 6A is an equivalent circuit diagram illustrating a pixel PXij according to an exemplary embodiment of the inventive concept. Figure 6B is a cross-sectional view illustrating a fourth transistor T4 according to an exemplary embodiment of the inventive concept. Figure 7A is an equivalent circuit diagram illustrating a pixel PXij according to an exemplary embodiment of the inventive concept. Figure 7B is a cross-sectional view illustrating a fourth transistor T4 according to an exemplary embodiment of the inventive concept. Hereinafter, detailed descriptions of elements identical to those described with reference to Figure 1 to Figure 5B may be omitted.

[0126] Reference is made to Figure 6A and Figure 6B ​​​​The pattern LSP can include a conductive material, and the source S4 of the fourth transistor T4 can be electrically connected to the pattern LSP. In this case, the pattern LSP can correspond to a gate electrode provided below the fourth transistor T4. When the initialization voltage Vint is applied to the lower gate (e.g., the pattern LSP), the fourth transistor T4 has the same voltage-current characteristics as a dual-gate transistor in which a bias voltage is applied to the lower gate thereof. The fourth transistor T4 corresponds to a single-channel transistor which is turned on in response to a voltage applied to the upper gate. The voltage-current characteristics of the fourth transistor T4 can be controlled by adjusting the level of the initialization voltage Vint.

[0127] The source S4 of the fourth transistor T4 and the pattern LSP can be connected to each other through the connection electrode CNE. The connection electrode CNE is provided on the sixth insulating layer 60, connected to the source S4 of the fourth transistor T4 through the contact hole CH100 which passes through the fourth to sixth insulating layers 40 to 60, and connected to the pattern LSP through the contact hole CH200 which passes through the first to sixth insulating layers 10 to 60.

[0128] The cross-sectional structure of the third transistor T3 can correspond to that of the fourth transistor T4. The gate G3 of the third transistor T3 can be provided on the same layer as the gate G4 of the fourth transistor T4, and the source S3 and the drain D3 of the third transistor T3 can be provided on the same layer as the source S4 and the drain D4 of the fourth transistor T4. The pattern LSP of the third transistor T3 can be provided on the same layer as the pattern LSP of the fourth transistor T4.

[0129] In the present exemplary embodiment, the pattern LSP is applied to each of the third transistor T3 and the fourth transistor T4, but is not limited thereto. For example, the pattern LSP can be applied to only one transistor.

[0130] In Figure 6A and Figure 6B , DS4 can correspond to the drain / source of the fourth transistor T4, G4-1 and G4-2 can correspond to the first gate and the second gate of the fourth transistor T4, and A3-1 and A3-2 can correspond to the first active region and the second active region of the fourth transistor T4.

[0131] Referring to Figure 7A and Figure 7BThe pattern LSP can include a conductive material, and at least one of the gate G3 of the third transistor T3 and the gate G4 of the fourth transistor T4 can be electrically connected to the corresponding pattern LSP. In this case, the pattern LSP can correspond to a gate provided under the third transistor T3 and the fourth transistor T4. When a first scan signal GIi is applied to the lower gate of the fourth transistor T4 and a third scan signal GWNi is applied to the lower gate of the third transistor T3, a double channel can be formed in the third transistor T3 and the fourth transistor T4, respectively, in an on state. The third transistor T3 and the fourth transistor T4 can each correspond to two transistors.

[0132] Figure 7B A cross section of the fourth transistor T4 is shown as a representative example. The gate G4 of the fourth transistor T4 and the pattern LSP can be connected to each other through a connection electrode CNE. The connection electrode CNE is provided on the sixth insulating layer 60, connected to the gates G4-1, G4-2 of the fourth transistor T4 through contact holes CH101 passing through the fifth and sixth insulating layers 50, 60, and connected to the pattern LSP through a contact hole CH200 passing through the first to sixth insulating layers 10 to 60. Figure 7B In the example of FIG. 10, the contact hole CH101 is provided with a plurality of. In the example of FIG. 11, the contact hole CH101 overlaps the first and second active areas A4-1, A4-2, but this is merely exemplary. When viewed in a plan view, the contact hole CH101 can not overlap the first and second active areas A4-1, A4-2. Figure 7B

[0133] Figure 8A is an equivalent circuit diagram showing a pixel PXij according to an exemplary embodiment of the inventive concept. Figure 8B is a cross-sectional view showing a seventh transistor T7 according to an exemplary embodiment of the inventive concept. Hereinafter, a detailed description of elements identical to those described with reference to Figure 1 to Figure 7B may be omitted.

[0134] As shown in Figure 8A and Figure 8B , the seventh transistor T7 can be an N-type transistor. The active area A7 of the seventh transistor T7 can include a metal oxide semiconductor. The seventh transistor T7 can include two gates G7-1 and G7-2. In addition, the seventh transistor T7 can include two active areas A7-1 and A7-2 corresponding to the two gates G7-1 and G7-2, respectively, and a drain / source DS7. The seventh transistor T7 can include a pattern LSP.

[0135] Figure 8B is shown as a representative example. The gate G4 of the fourth transistor T4 and the pattern LSP can be connected to each other through a connection electrode CNE. The connection electrode CNE is provided on the sixth insulating layer 60, connected to the gates G4-1, G4-2 of the fourth transistor T4 through contact holes CH101 passing through the fifth and sixth insulating layers 50, 60, and connected to the pattern LSP through a contact hole CH200 passing through the first to sixth insulating layers 10 to 60. Figure 5B ​The seventh transistor T7 has the same structure as that of the third transistor T3 illustrated in FIG. 7, but the structure of the seventh transistor T7 is not limited thereto. The seventh transistor T7 can be modified to have Figure 5C and Figure 5D the structure of the third transistor T3 illustrated in FIG. 7, or Figure 6A to Figure 7B the structure of the fourth transistor T4 illustrated in FIG. 8.

[0136] In the embodiments of the inventive concept described with reference to Figure 5A to Figure 8B , the third transistor T3, the fourth transistor T4, and the seventh transistor T7 include an active region of a metal oxide semiconductor, but they are not limited thereto. Some of the first to seventh transistors T1 to T7 can include an active region of a metal oxide semiconductor, and other of the first to seventh transistors T1 to T7 can include an active region of polysilicon. Among the first to seventh transistors T1 to T7, the transistors having an active region of a metal oxide semiconductor can include the pattern LSP described with reference to Figure 5A to Figure 7B .

[0137] Figure 9 is a plan view illustrating a pixel PXij according to an exemplary embodiment of the inventive concept. Figure 10A to Figure 10K is a plan view illustrating a stacking order of a pattern of a pixel PXij according to an exemplary embodiment of the inventive concept. Hereinafter, detailed descriptions of elements identical to those described with reference to Figure 1 to Figure 8B may be omitted.

[0138] Figure 9 is a plan view illustrating a pixel PXij having an equivalent circuit of Figure 2 . With reference to Figure 9 , the first to seventh transistors T1 to T7 of the pixel PXij are illustrated. In addition, the i-th scan line SLi in the first group, the i+1-th scan line SLi+1 in the first group, the i-th scan line GLi in the second group, the i-th scan line HLi in the third group, and the i-th light emitting line ELi are illustrated. Unlike the equivalent circuit of Figure 2 , each of the third transistor T3 and the fourth transistor T4 includes one gate, e.g., G3 and G4.

[0139] With reference to Figure 10A , a first semiconductor pattern SCP1 is disposed on a base layer BL (with reference to Figure 4A ). The first semiconductor pattern SCP1 can include a plurality of regions having different doping concentrations. The first semiconductor pattern SCP1 can include the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 (with reference to Figure 9source electrodes S1, S2, S5, S6, and S7, active regions A1, A2, A5, A6, and A7, and drain electrodes D1, D2, D5, D6, and D7 of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5. The first semiconductor pattern SCP1 can include a connection signal line SCL.

[0140] The portions of the first semiconductor pattern SCP1 can be patterns LSP-3P and LSP-4P of the transistors. The first portion of the first semiconductor pattern SCP1 can be the pattern LSP-3P of the third transistor T3, and the second portion of the first semiconductor pattern SCP1 can be the pattern LSP-4P of the fourth transistor T4. The first and second portions corresponding to the patterns LSP-3P and LSP-4P can overlap the patterns LSP-3 and LSP-4 shown in FIG. 6B. Figure 10D Figure 10A The patterns LSP-3P and LSP-4P of the first semiconductor pattern SCP1 and the patterns LSP-3 and LSP-4 shown in FIG. 6B correspond to double patterns. Figure 10D

[0141] The patterns LSP-3P and LSP-4P of the third transistor T3 and the fourth transistor T4 have areas larger than areas of the active regions A2, A5, A6, and A7 of the transistors T2, T5, T6, and T7 other than the first transistor T1. Figure 10A The reason why the patterns LSP-3P and LSP-4P in the first semiconductor pattern SCP1 have such areas is to cover the active regions A3 and A4 of the third transistor T3 and the fourth transistor T4 shown in FIG. 6B. Figure 10D Figure 10F The reason why the patterns LSP-3P and LSP-4P in the first semiconductor pattern SCP1 have such areas is to cover the active regions A3 and A4 of the third transistor T3 and the fourth transistor T4 shown in FIG. 6B.

[0142] Referring again to FIG. 6A, Figure 10A One pattern LSP-4P or LSP-3P can extend from the other pattern LSP-3P or LSP-4P. The pattern LSP-3P extends from the active region Al of the first transistor Tl. In the present exemplary embodiment, the first semiconductor pattern SCP1 corresponding to the pixel PXij has an overall shape, but is not limited thereto. The pattern LSP-4P and the pattern LSP-3P can be separated from each other, and the pattern LSP-3P can be separated from the active region Al of the first transistor Tl.

[0143] Figure 10B A plan view of a first semiconductor pattern SCP1 according to another exemplary embodiment of the present inventive concept is illustrated. As shown in FIG. 6A, Figure 10B Figure 10A ​​​​The portions of the pattern LSP-3P and LSP-4P of the first semiconductor pattern SCP1 in FIG. 1A corresponding to the pattern LSP-3 and LSP-4 shown in FIG. 1B can be omitted.

[0144] Figure 10C The pattern based on Figure 10A is shown. Referring to Figure 10C , the first metal pattern MP1 is disposed on the first insulating layer 10 (refer to Figure 4A ). The first metal pattern MP1 can include the gate G1 of the first transistor T1, the i-th scan line SLi in the first group, the i+1-th scan line SLi+1 in the first group, and the i-th emission line ELi. A portion of the i-th scan line SLi in the first group can be the gate G2 of the second transistor T2, and a portion of the i+1-th scan line SLi+1 in the first group can be the gate G7 of the seventh transistor T7. A portion of the i-th emission line ELi can be the gate G5 of the fifth transistor T5, and another portion of the i-th emission line ELi can be the gate G6 of the sixth transistor T6.

[0145] Referring to Figure 10D , the second metal pattern MP2 is disposed on the second insulating layer 20 (refer to Figure 4A ). The second metal pattern MP2 can include the upper electrode UE, the second voltage line RL, and dummy lines DL-H and DL-G. The upper electrode UE, the second voltage line RL, and the dummy lines DL-H and DL-G can include the same metal and the same layer structure as each other. The upper electrode UE can be provided with an opening UE-OP therethrough.

[0146] The first dummy line DL-H overlaps the i-th scan line HLi in the third group described later. The second dummy line DL-G overlaps the i-th scan line GLi in the second group described later. A portion of the first dummy line DL-H can be the pattern LSP-4 of the fourth transistor T4, and a portion of the second dummy line DL-G can be the pattern LSP-3 of the third transistor T3.

[0147] Figure 10D The patterns LSP-3 and LSP-4 shown in FIG. 1A overlap the patterns LSP-3P and LSP-4P to form the pattern LSP-3P+LSP-3 and LSP-4P+LSP-4 shown in FIG. 1B. Figure 10AThe double pattern is described. In the case where the double pattern is formed, the area of the patterns LSP-3 and LSP-4 of the second metal pattern MP2 can be adjusted. The area of the patterns LSP-3 and LSP-4 of the second metal pattern MP2 can be smaller than the area of the patterns LSP-3P and LSP-4P of the first semiconductor pattern SCP1. The area of the patterns LSP-3 and LSP-4 of the second metal pattern MP2 can at least overlap the patterns LSP-3P and LSP-4P of the first semiconductor pattern SCP1. The patterns LSP-3 and LSP-4 of the second metal pattern MP2 can have a width corresponding to the width of the line portion DL-HL to reduce the parasitic capacitance between the patterns LSP-3 and LSP-4 of the second metal pattern MP2 and the patterns LSP-3P and LSP-4P of the first semiconductor pattern SCP1. In an exemplary embodiment of the present inventive concept, the dummy lines DL-H and DL-G can be omitted and only the patterns LSP-3 and LSP-4 of the second metal pattern MP2 can be provided. In an exemplary embodiment of the present inventive concept, Figure 10A the patterns LSP-3P and LSP-4P shown in FIG. 11A can be omitted and the patterns LSP-3 and LSP-4 shown in FIG. 11B or Figure 10D the dummy lines DL-H and DL-G shown in FIG. 11C can be provided. Figure 10D

[0148] In an exemplary embodiment of the present inventive concept, the dummy lines DL-H and DL-G can be omitted. This structure is shown in Figure 10E In this case, the portion of the first semiconductor pattern SCP1 corresponding to the patterns LSP-3P and LSP-4P can be the light-blocking patterns of the third transistor T3 and the fourth transistor T4.

[0149] Referring to Figure 10F , the second semiconductor pattern SCP2 is disposed on the third insulating layer 30 (refer to FIG. 10A). The second semiconductor pattern SCP2 can include regions distinguished from each other depending on whether metal oxide is reduced. The second semiconductor pattern SCP2 can include the source S3 and S4, the active region A3 and A4, and the drain D3 and D4 of the third transistor T3 and the fourth transistor T4 (refer to FIG. 10B). Figure 4A Figure 9 The active region A4 of the fourth transistor T4 extends from the active region A3 of the third transistor T3. The second semiconductor pattern SCP2 includes a connection signal line SCL.

[0150] One connection signal line SCL extends from the source S3 of the third transistor T3 and / or the drain D4 of the fourth transistor T4. The connection signal line SCL is connected to the gate G1 of the first transistor T1 through a contact hole CH10. Referring to Figure 4A , Figure 4B , Figure 5A and​​Figure 5B The contact hole CH10 passes through the second insulating layer 20 and the third insulating layer 30.

[0151] Referring to Figure 10A and Figure 10F The drain D3 of the third transistor T3 is connected to the connection signal line SCL of the first semiconductor pattern SCP1 through the contact hole CH20. Referring to Figure 10A and Figure 10F The drain D3 of the third transistor T3 is connected to the source S6 of the sixth transistor T6. Referring to Figure 10D and Figure 10F The source S4 of the fourth transistor T4 is connected to the second voltage line RL through the contact hole CH30. The connection signal line SCL extending from the source S4 of the fourth transistor T4 can overlap the contact hole CH30.

[0152] Referring to Figure 10G The third metal pattern MP3 is disposed on the fourth insulating layer 40 (refer to Figure 4A ). The third metal pattern MP3 can include an i-th scan line GLi of the second group and an i-th scan line HLi of the third group. A portion of the i-th scan line GLi of the second group can be the gate G3 of the third transistor T3, and a portion of the i-th scan line HLi of the third group can be the gate G4 of the fourth transistor T4.

[0153] Referring to Figure 10H The fourth metal pattern MP4 is disposed on the sixth insulating layer 60 (refer to Figure 4A ). The fourth metal pattern MP4 can include a first connection electrode CNE1, a second connection electrode CNE2, a data line DLj, and a first voltage line PL. Figure 10H A portion of the data line DLj and a portion of the first voltage line PL are shown. Referring to Figure 10A and Figure 10H The first connection electrode CNE1 is connected to the connection signal line SCL through the contact hole CH1. The first connection electrode CNE1 can be the first connection electrode CNE1 shown in Figure 4A The second connection electrode CNE2 connects the drain D7 of the seventh transistor T7 to the second voltage line RL through the contact holes CH2 and CH3. The data line DLj is connected to the source S2 of the second transistor T2 through the contact hole CH4. The first voltage line PL is connected to the source S5 of the fifth transistor T5 through the contact hole CH5.

[0154] In addition, Figure 10HThe structure in which one pixel overlaps with one data line DLj is shown, but the inventive concept is not limited thereto. For example, one pixel can overlap with two data lines. Among the two data lines, one data line can be connected to pixels arranged in one pixel row, and the other data line can be connected to pixels arranged in a pixel row adjacent to the one pixel row. The one pixel row can be an odd-numbered pixel row or an even-numbered pixel row.

[0155] Figure 10I to Figure 10K A plan view of a pixel PXij according to another exemplary embodiment of the inventive concept is shown, which is different from the plan view of the pixel PXij shown in FIG. 1. Figure 10A to Figure 10H Figure 10I Corresponding to Figure 10F , the contact hole CH10, the contact hole CH20, and the contact hole CH30 are not formed. In other words, the second semiconductor pattern SCP2 can not be directly connected to Figure 10I , the first semiconductor pattern SCP1, the first metal pattern MP1, or the second metal pattern MP2 shown in FIG. 1. In addition, referring to Figure 10F , the connection signal line SCL overlapping with the first transistor T1 is omitted, unlike FIG. 1. Figure 10A to Figure 10E Figure 10I Figure 10F

[0156] According to the present exemplary embodiment, the fourth metal pattern MP4 and the fifth metal pattern MP5 are provided on the third metal pattern MP3, unlike the pixel PXij shown in FIG. 1. Figure 10A to Figure 10H The fourth metal pattern MP4 is shown, and Figure 10J The fifth metal pattern MP5 is shown. Figure 10K

[0157] Referring to Figure 10J , the third metal pattern MP3 described with reference to FIG. 1 is additionally provided. The third metal pattern MP3 can include the i-th scan line GLi of the second group, the i-th scan line HLi of the third group, and the i+1-th scan line HLi+1 of the third group. Figure 10G

[0158] Referring to Figure 10J ​​​​​​The third, fourth, fifth, sixth, and seventh connection electrodes CNE3, CNE4, CNE5, CNE6, and CNE7 formed of the fourth metal pattern MP4, and the connection electrodes CNE3 to CNE7 are shown through the second, third, fourth, fifth, sixth, seventh, eighth, and ninth contact holes CH2, CH3, CH4, CH5, CH6, CH7, CH8, and CH9 by which they are connected to the first semiconductor pattern SCP1, the first metal pattern MP1, or the second metal pattern MP2. The third connection electrode CNE3 connects the second voltage line RL to the seventh transistor T7 through the third and fourth contact holes CH3 and CH4. The fourth connection electrode CNE4 connects the third transistor T3 to the sixth transistor T6 through the fifth and sixth contact holes CH5 and CH6. The fifth connection electrode CNE5 connects the third transistor T3 to the first transistor T1 and the fourth transistor T4 to the first transistor T1 through the seventh and eighth contact holes CH7 and CH8. The sixth connection electrode CNE6 is connected to the second transistor T2 through the ninth contact hole CH9. The seventh connection electrode CNE7 is connected to the fifth transistor T5 through the second contact hole CH2. The first connection electrode CNE10 is electrically connected to the sixth transistor T6 through the first contact hole CH1.

[0159] Reference Figure 10K The connection electrode CNE20, the data lines DLj-E and DLj-O, and the first voltage line PL formed of the fifth metal pattern MP5 are shown. In addition, the connection electrode CNE20, the data lines DLj-E and DLj-O, and the first voltage line PL are shown through the contact holes CH-60, CH40, and CH50 by which they are connected to the fourth metal pattern MP4. The connection electrode CNE20 is connected to the connection electrode CNE10 through the contact hole CH-60. The first voltage line PL is connected to the seventh connection electrode CNE7 through the contact hole CH40, and the first voltage line PL is electrically connected to the fifth transistor T5. The data line DLj-O is connected to the sixth connection electrode CNE6 through the contact hole CH50, and the data line DLj-O is electrically connected to the second transistor T2. Two data lines DLj-E and DLj-O overlap one pixel, but one data line DLj-O is connected to one pixel, and the other data line DLj-E is connected to a pixel adjacent to the one pixel. When one data line DLj-O is connected to an odd-numbered pixel row, the other data line DLj-E is connected to an even-numbered pixel row.

[0160] Figure 11 is a cross-sectional view showing a display panel corresponding to the first and third transistors T1 and T3 according to an exemplary embodiment of the present inventive concept. Hereinafter, detailed descriptions of elements identical to those described with reference to Figure 1 to Figure 10K to those described with reference to

[0161] Figure 11 The third transistor T3 is shown to have two gates G3-1 and G3-2. In addition, the third transistor T3 has a double pattern structure. The first pattern LSP-3P extends from the active area A1 of the first transistor T1. The second pattern LSP-3 is disposed on the same layer as the upper electrode UE.

[0162] Reference Figure 10D The area on the plane of the first pattern LSP-3P and the area on the plane of the second pattern LSP-3 can be compared to each other. The second pattern LSP-3 has a smaller area than the first pattern LSP-3P, and is disposed inside the first pattern LSP-3P. The second pattern LSP-3 at least overlaps the first pattern LSP-3P.

[0163] According to the above-described embodiments of the inventive concept, the display apparatus includes two types of transistors, and thus, a leakage current of a pixel can be reduced, and a response speed of a light emitting diode can be improved. The leakage current of the pixel can be reduced by a transistor including a metal oxide semiconductor, and the response speed of the light emitting diode can be improved by a transistor including a polysilicon semiconductor. The leakage current of the pixel can be reduced using a transistor including a plurality of gates.

[0164] The pattern formed under the metal oxide semiconductor blocks external light from traveling to the metal oxide semiconductor. Thus, it is possible to prevent a current-voltage characteristic of the metal oxide semiconductor from being shifted due to the external light. The pattern can be used as another gate. The characteristic of the transistor including the metal oxide semiconductor can be controlled according to a voltage applied to the pattern.

[0165] While the inventive concept has been described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the inventive concept as set forth in the following claims.

Claims

1. A display apparatus comprising: a display panel including a plurality of pixels, a first pixel of the pixels including: a light emitting diode; a capacitor connected between a first voltage line and a reference node; a first transistor connected between the first voltage line and a first electrode of the light emitting diode, the first transistor including a gate and a first semiconductor pattern, the first semiconductor pattern including an active region, a source, and a drain; a second transistor connected between a data line and the source of the first transistor; a third transistor connected between the reference node and the drain of the first transistor; a fourth transistor connected between the reference node and a second voltage line; a fifth transistor connected between the first voltage line and the source of the first transistor; and a sixth transistor connected between the first electrode of the light emitting diode and the drain of the first transistor, each of the third transistor and the fourth transistor including: an active region including a metal oxide; a first gate and a second gate disposed on a first side of the active region and overlapping the active region; and a pattern disposed on a second side of the active region and overlapping the active region, wherein the pattern of the third transistor is disposed on a same layer as the first semiconductor pattern, the pattern of the third transistor and the first semiconductor pattern have an integrated shape in a plan view, and the pattern of the third transistor and the first semiconductor pattern include a silicon semiconductor.

2. The display device of claim 1, wherein, Each of the first transistor, the second transistor, the fifth transistor, and the sixth transistor is a P-type transistor, and each of the third transistor and the fourth transistor is an N-type transistor.

3. The display device of claim 1, wherein, The active region of the first transistor includes polysilicon. 4.The display apparatus of claim 3, wherein the source of the first transistor extends from the active region of the first transistor. 5.The display apparatus of claim 1, wherein the second transistor includes a second semiconductor pattern, the second semiconductor pattern including an active region, a source, and a drain. 6.The display apparatus of claim 5, wherein the first semiconductor pattern and the second semiconductor pattern are disposed on a same layer, and the first semiconductor pattern and the second semiconductor pattern have an integrated shape in a plan view. 7.The display apparatus of claim 1, wherein each of the third transistor and the fourth transistor further includes another pattern, the another pattern including a conductive material.

8. The display device of claim 1, wherein, The pattern of the third transistor and the source of the first semiconductor pattern have a same material.

9. The display device of claim 1, wherein, The pattern of the third transistor and the first semiconductor pattern include polysilicon.

10. The display device of claim 1, wherein, The display panel further includes a seventh transistor connected to the first electrode of the light emitting diode, wherein the seventh transistor includes: an active region including a metal oxide; a gate disposed on a first side of the active region of the seventh transistor and overlapping the active region of the seventh transistor; and a pattern disposed on a second side of the active region of the seventh transistor and overlapping the active region of the seventh transistor. a pattern disposed on a second side of the active region of the seventh transistor and overlapping the active region of the seventh transistor.

11. The display device of claim 10, wherein, Each of the first transistor, the second transistor, the fifth transistor, and the sixth transistor is a P-type transistor, and each of the third transistor, the fourth transistor, and the seventh transistor is an N-type transistor.

12. The display device of claim 1, wherein, The pattern of the third transistor extends from the pattern of the fourth transistor.

13. A display device comprising: a display panel comprising pixels, the pixels comprising: a light emitting diode; a capacitor connected between a first voltage line and a reference node; a first transistor connected between the first voltage line and a first electrode of the light emitting diode; a second transistor connected between a data line and a source of the first transistor; a third transistor connected between the reference node and a drain of the first transistor; a fourth transistor connected between the reference node and a second voltage line; a fifth transistor connected between the first voltage line and the source of the first transistor; and a sixth transistor connected between the first electrode of the light emitting diode and the drain of the first transistor, Each of the third transistor and the fourth transistor comprises: an active region comprising a metal oxide; a gate disposed above the active region; and a first pattern comprising polysilicon disposed below the active region and overlapping the active region when viewed in a plan view, wherein the first pattern of the fourth transistor extends from the first pattern of the third transistor.

14. The display device of claim 13, wherein the first pattern of the third transistor extends from an active region of the first transistor.

15. The display device of claim 13, wherein the active region of the fourth transistor extends from the active region of the third transistor. Each of the third transistor and the fourth transistor further comprises a second pattern disposed between its active region and its first pattern.

16. The display device of claim 13, wherein, The second voltage line and the second pattern are disposed on a same layer and comprise a same metal.

17. The display device of claim 16, wherein, The second pattern of the third transistor at least overlaps the first pattern of the third transistor when viewed in the plan view.

18. The display device of claim 16, wherein, Each of the first transistor, the second transistor, the fifth transistor, and the sixth transistor is a P-type transistor, and each of the third transistor and the fourth transistor is an N-type transistor.

19. The display device of claim 13, wherein, ​

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