Display panel, driving method thereof, driving device and display device

Abstract

The embodiment of the invention provides a display panel, a driving method thereof, a driving device and a display device, and relates to the technical field of display, the display panel comprises a light emitting device, a driving sub-circuit and a reset sub-circuit, the driving sub-circuit is electrically connected with a first node and a second node, the first node is electrically connected with a first voltage end, and the second node is electrically connected with a second voltage end. The second node is electrically connected with the light-emitting device; the reset sub-circuit is electrically connected with a reset voltage end and a reset control end, the reset sub-circuit is further electrically connected with the first node and / or the second node, and the reset sub-circuit is configured to reset the first node and / or the second node under the control of the reset control end. Resetting the driving sub-circuit for multiple times according to the reset voltage of the reset voltage end; the multiple resets comprise the Nth reset and the (N + 1) th reset, and the duration time of the Nth reset is different from the duration time of the (N + 1) th reset.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a driving method, a driving device and a display device. BACKGROUND

[0002] Organic Light Emitting Diode (OLED) display technology is considered as the most potential new display technology of the next generation. Compared with liquid crystal display technology, OLED display technology has the advantages of low energy consumption, low cost, self-luminous, wide viewing angle and fast response speed.

[0003] In the preparation process of a traditional OLED display panel, a fine metal mask (FMM) is usually used to realize the patterning of a light-emitting pixel. The FMM technology is mature and has rich experience in mass production. However, the FMM technology also has the problems of limited precision and high cost. The fine metal mask-free technology eliminates the limitations of the traditional OLED process on the size, resolution and other performance of the display screen, and has the advantages of high performance, full-size and agile delivery. The contents described in patent documents CN118251982A, 202311324257.8, 202310731471.9, 202311686416.9, 202310707183.X, 202310479495.X, 202310445544.8, CN117580403A, CN116669477B and CN116936581B are for reference.

[0004] However, the display panel is prone to flicker during use. SUMMARY

[0005] In order to overcome the technical problems mentioned in the above technical background, the embodiments of the present application provide a display panel and a driving method, a driving device and a display device.

[0006] In one aspect, the present application provides a display panel, which comprises a light-emitting device, a driving sub-circuit and a reset sub-circuit. The driving sub-circuit is electrically connected with a first node and a second node respectively. The first node is electrically connected with a first voltage terminal. The second node is electrically connected with the light-emitting device. The reset sub-circuit is electrically connected with a reset voltage terminal and a reset control terminal respectively. The reset sub-circuit is also electrically connected with the first node and / or the second node. The reset sub-circuit is configured to reset the driving sub-circuit multiple times according to a reset voltage of the reset voltage terminal under the control of the reset control terminal. The multiple times of reset include the Nth reset and the N+1th reset. The duration of the Nth reset is different from the duration of the N+1th reset.

[0007] In the display panel provided by the embodiments of this application, the threshold offset of the driving transistor before the Nth reset may be different from the threshold offset of the driving transistor before the (N+1)th reset. If the duration of the Nth reset is the same as the duration of the (N+1)th reset, the state of the driving transistor after the Nth reset will be different from the state after the (N+1)th reset, resulting in a difference in the brightness of the light-emitting device after the Nth reset compared to the brightness after the (N+1)th reset, thus causing flickering. Therefore, in the embodiments of this application, the duration of the Nth reset is different from the duration of the (N+1)th reset. This allows for flexible adjustment of the duration of the Nth and (N+1)th resets based on the threshold offset of the driving transistor before the Nth reset and the threshold offset of the driving transistor before the (N+1)th reset, ensuring that the state of the driving transistor after the Nth reset is the same as or similar to the state after the (N+1)th reset, thereby improving the flickering phenomenon of the display panel.

[0008] In some embodiments, the multiple resets further include an (N-1)th reset, the interval between the (N-1)th reset and the Nth reset is greater than the interval between the Nth reset and the (N+1)th reset, and the duration of the Nth reset is greater than the duration of the (N+1)th reset.

[0009] The longer interval between the (N-1)th and Nth resets results in a longer operating time for the driving transistor before the Nth reset, leading to a larger threshold offset. Conversely, the shorter interval between the Nth and (N+1)th resets results in a longer operating time for the driving transistor before the (N+1)th reset, leading to a smaller threshold offset. Therefore, the duration of the Nth reset is longer than that of the (N+1)th reset, ensuring that the state of the driving transistor after the Nth reset is the same as or similar to that after the (N+1)th reset, thus improving the flickering effect of the display panel.

[0010] In some embodiments, the multiple resets further include an (N-1)th reset, the light-emitting time of the light-emitting device during the interval between the (N-1)th reset and the Nth reset is a first time, the light-emitting time of the light-emitting device during the interval between the Nth reset and the (N+1)th reset is a second time, the first time is greater than the second time, and the duration of the Nth reset is greater than the duration of the (N+1)th reset.

[0011] The threshold offset of the driving transistor is positively correlated with its operating time. When the first time interval is longer than the second time interval, the threshold offset of the driving transistor before the Nth reset is greater than that before the (N-1)th reset. Therefore, the duration of the Nth reset is longer than that of the (N+1)th reset, making the state of the driving transistor after the Nth reset the same as or similar to that after the (N+1)th reset, thus improving the flickering phenomenon of the display panel.

[0012] In some implementations, the duration of the (N+1)th reset is positively correlated with the second time.

[0013] The threshold offset of the driving transistor is positively correlated with the operating time of the driving transistor. Therefore, the duration of the N+1th reset is positively correlated with the second time, which can make the state of the driving transistor after each reset tend to be consistent.

[0014] In some implementations, the duration of the Nth reset is The duration of the (N+1)th reset is The first time is The second time is ,but .

[0015] It is assumed that the duration of the reset is linearly related to the amount of correction of the threshold voltage offset, which facilitates calculation.

[0016] In some implementations, the Nth reset occurs in the Mth display frame, and the (N+1)th reset occurs in the (M+1)th display frame.

[0017] The inconsistency in the operating time of the driving transistors before reset usually occurs between the last reset of the previous display frame and the first reset of the next display frame. Therefore, the Nth reset and the N+1th reset are not in the same display frame.

[0018] In some embodiments, the display panel further includes a gate driving circuit configured to provide a reset control signal to the reset control terminal. The reset control signal includes a plurality of reset pulses, and the reset sub-circuit is configured to reset the driving sub-circuit during the duration of the reset pulses. The plurality of reset pulses include a first pulse and a second pulse. The first pulse is configured to control the reset sub-circuit to perform the Nth reset on the driving sub-circuit, and the second pulse is configured to control the reset sub-circuit to perform the (N+1)th reset on the driving sub-circuit. The duration of the first pulse is different from the duration of the second pulse.

[0019] The threshold offset of the driving transistor before the Nth reset may be different from that before the (N+1)th reset, and the duration of the first pulse may be different from that of the second pulse. This allows for flexible adjustment of the duration of the first and second pulses based on the threshold offsets of the driving transistor before the Nth and (N+1)th resets, so that the state of the driving transistor after the Nth reset is the same as or similar to that after the (N+1)th reset, thereby improving the flickering phenomenon of the display panel.

[0020] In some embodiments, the plurality of reset pulses further includes a third pulse, which is configured to control the reset sub-circuit to perform the (N-1)th reset on the drive sub-circuit, wherein the time between the third pulse and the first pulse is greater than the time between the second pulse and the first pulse, and the duration of the first pulse is greater than the duration of the second pulse.

[0021] The longer interval between the (N-1)th and Nth resets results in a longer operating time for the driving transistor before the Nth reset, leading to a larger threshold offset. Conversely, the shorter interval between the Nth and N+1th resets results in a longer operating time for the driving transistor before the N+1th reset, leading to a smaller threshold offset. Therefore, the duration of the first pulse is longer than the duration of the second pulse, ensuring that the state of the driving transistor after the Nth reset is the same as or similar to that after the N+1th reset, thus improving the flickering phenomenon of the display panel.

[0022] In some embodiments, the plurality of reset pulses further includes a third pulse, which is configured to control the reset sub-circuit to perform an N-1th reset on the drive sub-circuit. The light-emitting device emits light for a first time during the interval between the third pulse and the first pulse, and emits light for a second time during the interval between the first pulse and the second pulse. The first time is longer than the second time, and the duration of the first pulse is longer than the duration of the second pulse.

[0023] The threshold offset of the driving transistor is positively correlated with its operating time. When the first time is longer than the second time, the threshold offset of the driving transistor before the Nth reset is greater than that before the (N-1)th reset. Therefore, the duration of the first pulse is longer than the duration of the second pulse, making the state of the driving transistor after the Nth reset the same as or similar to that after the (N+1)th reset, thus improving the flickering phenomenon of the display panel.

[0024] On the other hand, this application also provides a driving method for driving a display panel, the display panel including a light-emitting device, a driving sub-circuit, and a reset sub-circuit. The driving sub-circuit is electrically connected to a first node and a second node, the first node being electrically connected to a first voltage terminal, and the second node being electrically connected to the light-emitting device. The reset sub-circuit is electrically connected to a reset voltage terminal and a reset control terminal, and is also electrically connected to the first node and / or the second node. The reset sub-circuit is configured to reset the driving sub-circuit multiple times according to the reset voltage of the reset voltage terminal under the control of the reset control terminal. The driving method includes: The reset sub-circuit is controlled to perform the Nth reset on the drive sub-circuit. The reset sub-circuit is controlled to perform the (N+1)th reset on the drive sub-circuit. The duration of the Nth reset is different from the duration of the (N+1)th reset.

[0025] The display panel driving method provided in the embodiments of this application may have different threshold offsets for the driving transistor before the Nth reset and before the (N+1)th reset. If the duration of the Nth reset is the same as the duration of the (N+1)th reset, the state of the driving transistor after the Nth reset will be different from that after the (N+1)th reset, resulting in a difference in brightness between the light-emitting device after the Nth reset and the (N+1)th reset, thus causing flickering. Therefore, in the embodiments of this application, the duration of the Nth reset is different from the duration of the (N+1)th reset. This allows for flexible adjustment of the duration of the Nth and (N+1)th resets based on the threshold offsets of the driving transistor before the Nth and (N+1)th resets, ensuring that the state of the driving transistor after the Nth reset is the same as or similar to that after the (N+1)th reset, thereby improving the flickering phenomenon of the display panel.

[0026] In some embodiments, the display panel further includes a gate driving circuit configured to provide a reset control signal to the reset control terminal, the reset control signal including a plurality of reset pulses, and the reset sub-circuit configured to reset the driving sub-circuit during the duration of the reset pulses; The control of the reset sub-circuit to perform the (N+1)th reset of the drive sub-circuit includes: The gate drive circuit is controlled to generate a second pulse; the second pulse is one of the plurality of reset pulses. The reset sub-circuit is controlled to perform the (N+1)th reset on the drive sub-circuit according to the second pulse.

[0027] In some embodiments, controlling the gate drive circuit to generate the second pulse includes: The first time, the second time, and the duration of the Nth reset are obtained; the light-emitting time of the light-emitting device during the interval between the (N-1)th reset and the Nth reset is the first time, and the light-emitting time of the light-emitting device during the interval between the Nth reset and the (N+1)th reset is the second time; The duration of the (N+1)th reset is determined based on the first time, the second time, and the duration of the Nth reset; The second pulse is generated based on the duration of the (N+1)th reset.

[0028] In some implementations, the first time is longer than the second time, and the duration of the Nth reset is longer than the duration of the (N+1)th reset.

[0029] On the other hand, this application also provides a driving device for driving a display panel, the driving device being used to execute the driving method described above.

[0030] In another aspect, this application also provides a display device, which includes the aforementioned display panel.

[0031] In the display device provided in the embodiments of this application, the threshold offset of the driving transistor before the Nth reset may be different from the threshold offset of the driving transistor before the (N+1)th reset. If the duration of the Nth reset is the same as the duration of the (N+1)th reset, the state of the driving transistor after the Nth reset will be different from the state after the (N+1)th reset, resulting in a difference in the brightness of the light-emitting device after the Nth reset compared to the brightness after the (N+1)th reset, thus causing flickering. Therefore, in the embodiments of this application, the duration of the Nth reset is different from the duration of the (N+1)th reset. This allows for flexible adjustment of the duration of the Nth and (N+1)th resets based on the threshold offset of the driving transistor before the Nth reset and the threshold offset of the driving transistor before the (N+1)th reset, ensuring that the state of the driving transistor after the Nth reset is the same as or similar to the state after the (N+1)th reset, thereby improving the flickering phenomenon of the display panel. Attached Figure Description

[0032] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a front view structure of a display device provided in some embodiments of this application; Figure 2 This is a simplified structural diagram of a display module provided in some embodiments of this application; Figure 3 These are schematic diagrams of the display panel structure provided in some embodiments of this application; Figure 4 yes Figure 3 A partial cross-sectional view of the membrane layers of BB in the image; Figure 5 This is a partial cross-sectional view of the film layers of the display panel in some embodiments of this application; Figure 6 This is a partial top view of the display panel structure in some embodiments of this application; Figure 7 This is a partial cross-sectional view of the film layers of the display panel in some embodiments of this application; Figure 8 These are schematic diagrams of the light-emitting structures in some embodiments of this application; Figure 9 This is a partial cross-sectional view of the film layers of the display panel in some embodiments of this application; Figure 10 These are step flowcharts of a method for manufacturing a display panel according to some embodiments of this application; Figure 11 These are simplified structural diagrams of pixel circuits in some embodiments of this application; Figure 12 These are simplified structural diagrams of pixel circuits in some embodiments of this application; Figure 13 These are simplified structural diagrams of pixel circuits in some embodiments of this application; Figure 14 These are circuit schematics of pixel circuits in some embodiments of this application; Figure 15 This is a partial signal timing diagram of the pixel circuit; Figure 16 This is a partial signal timing diagram of the pixel circuit; Figure 17 This is a flowchart illustrating the steps of a driving method provided in some embodiments of this application. Detailed Implementation To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0034] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0035] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. It should be noted that, unless otherwise specified, different features in the embodiments of this application can be combined with each other.

[0036] For ease of understanding, the accompanying diagram shows the mutually orthogonal X-axis, Y-axis, and Z-axis. The direction along the X-axis is called the X-direction, the direction along the Y-axis is called the Y-direction, and the direction along the Z-axis is called the Z-direction. The Z-direction is the normal direction relative to the plane containing the X and Y directions. Furthermore, a view where various elements are observed parallel to the plane containing the X and Y directions is called a top view. Alternatively, the planes in the X and Y directions can be planes parallel to the display surface of the display panel, and the Z-direction can be a direction parallel to the thickness direction of the display panel.

[0037] For certain elements, terms like "above" or "overhead" are sometimes used when describing the position of an element in the Z direction, and "below" or "under" are used when describing the position of an element in the opposite direction. Furthermore, when using terms like "above," "overhead," "below," "under," or "relative" to define the positional relationship between two elements, this includes not only the state where the two elements are directly adjacent, but also the state where the two elements are separated by gaps or other elements. Additionally, terms like "first," "second," and "third" are used only for distinguishing descriptions and should not be interpreted as indicating or implying relative importance.

[0038] Some embodiments of this application provide a display device that can display images. The displayed images can be moving images (e.g., videos), still images (e.g., pictures), text images, or images combining text, pictures, and videos. The content displayed is not limited. Depending on the application scenario, display devices can be categorized into several types. For example, a display device can be a mobile phone, wireless device, personal data assistant (PDA), handheld or portable computer, GPS receiver / navigator, camera, MP4 video player, camcorder, game console, watch, wristband, clock, calculator, television monitor, flat panel display, computer monitor, automotive display (e.g., odometer display, center console display, etc.), navigator, cockpit controller and / or display, camera view display (e.g., display of a rearview camera in a vehicle), electronic photo album, electronic billboard or sign, projector, architectural structure, packaging and aesthetic structure (e.g., a display of an image of a piece of jewelry), etc. Figure 1 This is a front view structure of a display device provided in some embodiments of this application. Figure 1 The display device 100 is illustrated using a mobile phone as an example.

[0039] Continue to refer to Figure 1 The display device 100 includes a housing 110 and a display module 120 connected to the housing 110. The housing 110 serves as the skeleton of the display device 100, supporting and connecting other components within the display device 100. The display module 120 is used to display images. In addition to the housing 110 and the display module 120, the display device 100 may also include other components, the types and quantities of which vary depending on the type of display device 100. For example, when the display device 100 is a mobile phone, it may also include a battery, a motherboard, and a system-on-a-chip (SoC).

[0040] Figure 2 This is a simplified structural diagram of a display module provided in some embodiments of this application. For example... Figure 2 As shown, the display module 120 includes a display panel 10 and a control board 20. The control board 20 is used to generate drive signals, and the display panel 10 is used to display images under the drive signals. Exemplarily, the display module 120 also includes a flexible printed circuit board (FPC) 30. One end of the flexible printed circuit board 30 is electrically connected to the display panel 10, and the other end is electrically connected to the control board 20. The flexible printed circuit board 30 is used to realize the electrical connection between the display panel 10 and the control board 20.

[0041] The display panel 10 can be a liquid crystal display (LCD), an electroluminescent display panel, or a photoluminescent display panel. When the display panel 10 is a liquid crystal display panel, it can be a twisted nematic (TN) type display panel, an in-plane switching (IPS) type display panel, or a vertical alignment (VA) type display panel. When the display panel 10 is an electroluminescent display panel, it can be an organic light-emitting diode (OLED) display panel or a quantum dot light-emitting diode (QLED) display panel. When the display panel 10 is a photoluminescent display panel, it can be a quantum dot photoluminescent display panel. Some embodiments of this application are described using an organic light-emitting diode display panel as an example.

[0042] Figure 3 These are schematic diagrams illustrating the structure of a display panel provided in some embodiments of this application. For example... Figure 3 As shown, the display panel 10 may have a display area AA and a non-display area NA connected to the display area AA. The non-display area NA may be located on one, two, or three sides of the display area AA, or it may surround the display area AA. The shape of the display area AA may be rectangular, square, circular, elliptical, or other shapes.

[0043] Continue to refer to Figure 3 The display area AA includes multiple pixels PX arranged in the X and Y directions. Each pixel PX includes multiple sub-pixels SPX displaying different colors. In some embodiments, a pixel PX includes a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. For example, the first sub-pixel SPX1 is a blue sub-pixel, the second sub-pixel SPX2 is a green sub-pixel SPX2, and the third sub-pixel SPX3 is a red sub-pixel SPX3. In some embodiments, in addition to sub-pixels SPX1, SPX2, and SPX3, a pixel PX also includes sub-pixels SPX that emit white or other colors of light.

[0044] A sub-pixel (SPX) includes a pixel circuit and a light-emitting device driven by the pixel circuit to emit light of the corresponding color. The first sub-pixel (SPX1) includes a first light-emitting device, the second sub-pixel (SPX2) includes a second light-emitting device, and the third sub-pixel (SPX3) includes a third light-emitting device. One pixel circuit drives at least one light-emitting device to emit light. For example, the display area AA includes a normal display area and a light-transmitting display area. The light-transmitting display area is a display area set according to a corresponding sensor and has light-transmitting properties, while the normal display area is a display area not set according to a corresponding sensor. In the normal display area, one pixel circuit drives one light-emitting device to emit light, and in the light-transmitting display area, one pixel circuit drives one or more light-emitting devices to emit light.

[0045] Figure 4 yes Figure 3 A partial cross-sectional view of the BB membrane. (See image below.) Figure 4 As shown, in one embodiment, the display panel 10 includes an array substrate 11, an isolation structure 12, and a plurality of light-emitting devices 13.

[0046] Figure 5 These are partial film layer cross-sectional views of the display panel in some embodiments of this application. For example... Figure 5 As shown, the array substrate 11 includes a pixel circuit layer and a planarization layer 19. The pixel circuit layer includes pixel circuits for driving the light-emitting device 13 to emit light. Figure 5 A transistor 18 in a pixel circuit is shown. A via is provided in the planarization layer 19, and a first electrode 131 is electrically connected to the transistor 18 in the pixel circuit layer through the via. Furthermore, the pixel circuit layer includes at least one insulating layer, which may include at least one of an inorganic layer and an organic layer. Additionally, the array substrate 11 includes scan lines providing the scan signal Scan and data lines providing the data signal Data to the pixel circuit.

[0047] Figure 6 This is a partial top view of the display panel structure in some embodiments of this application. For example... Figure 6As shown, the isolation structure 12 is located on one side of the array substrate 11 and encloses a plurality of isolation openings 12a. The plurality of isolation openings 12a include a plurality of first isolation openings 12a1, a plurality of second isolation openings 12a2, and a plurality of third isolation openings 12a3. A plurality of light-emitting devices 13 are located on one side of the array substrate 11, and the plurality of light-emitting devices 13 include a plurality of first light-emitting devices 13a, a plurality of second light-emitting devices 13b, and a plurality of third light-emitting devices 13c. The first light-emitting devices 13a are disposed corresponding to the first isolation opening 12a1, the second light-emitting devices 13b are disposed corresponding to the second isolation opening 12a2, and the third light-emitting devices 13c are disposed corresponding to the third isolation opening 12a3. In one embodiment, one light-emitting device 13 is disposed corresponding to one isolation opening 12a. For example, the first light-emitting devices 13a are disposed one-to-one with the first isolation opening 12a1, the second light-emitting devices 13b are disposed one-to-one with the second isolation opening 12a2, and the third light-emitting devices 13c are disposed one-to-one with the third isolation opening 12a3. At least a portion of the first light-emitting device 13a is disposed within a corresponding first isolation opening 12a1, at least a portion of the second light-emitting device 13b is disposed within a corresponding second isolation opening 12a2, and at least a portion of the third light-emitting device 13c is disposed within a corresponding third isolation opening 12a3. In another embodiment, multiple light-emitting devices 13 are correspondingly disposed with one isolation opening 12a; for example, multiple light-emitting devices with the same emission color are corresponding to one isolation opening 12a.

[0048] In one example, the isolation structure 12 includes an isolation portion 122 and a blocking portion 121 stacked along a direction away from the array substrate 11 (i.e., the Z direction), with the width of the blocking portion 121 being greater than the width of the isolation portion 122. Thus, the two ends of the blocking portion 121 protrude compared to the sides of the isolation portion 122, and this shape of the isolation structure 12 is also referred to as a pendant shape. The isolation portion 122 and the blocking portion 121 are made of different materials, and the etching rate of the blocking portion 121 is lower than that of the isolation portion 122. The material of the isolation portion 122 includes a conductive material, specifically including at least one of aluminum (Al), aluminum alloys, and aluminum alloys including at least one of aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY), or aluminum-silicon alloy (AlSi). The blocking portion 121 can be a single-layer structure or a multi-layer structure. If the blocking portion 121 is a single-layer structure, the material of the blocking portion 121 can include at least one of titanium, titanium nitride, molybdenum, tungsten, molybdenum-tungsten alloy, or molybdenum-niobium alloy. When the blocking part 121 has a multi-layer structure, one layer of the blocking part 121 is made of at least one of titanium, titanium nitride, molybdenum, tungsten, molybdenum-tungsten alloy or molybdenum-niobium alloy, and the other layer of the blocking part 121 may be made of conductive oxide or inorganic insulating material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0049] Figure 7 These are partial film layer cross-sectional views of the display panel in some embodiments of this application. For example... Figure 7 As shown, in some embodiments, the isolation structure 12 may further include a base 123 located on the side of the isolation portion 122 near the array substrate 11. The base 123 protrudes relative to the isolation portion 122 in the direction toward the isolation opening 12a, and the orthographic projection of the isolation portion 122 on the array substrate 11 lies within the orthographic projection of the base 123 on the array substrate 11. The material of the base 123 may include at least one of molybdenum (Mo), titanium (Ti), titanium nitride (TiN), molybdenum-tungsten alloy (MoW), or molybdenum-niobium alloy (MoNb).

[0050] In one embodiment, the display panel 100 may further include a pixel defining layer 17, on which an isolation structure 12 is disposed. The pixel defining layer 17 has pixel openings communicating with isolation openings 12a. Specifically, the pixel defining layer 17 has a first pixel opening communicating with a first isolation opening 12a1, a second pixel opening communicating with a second isolation opening 12a2, and a third pixel opening communicating with a third isolation opening 12a3. The areas of the orthographic projections of the first, second, and third pixel openings onto the array substrate 11 may be the same or different. The shapes of the orthographic projections of the pixel openings and the corresponding isolation openings 12a onto the array substrate 11 may be the same or different. Generally, the area of ​​the orthographic projection of the isolation opening 12a onto the array substrate 11 is larger than the area of ​​the orthographic projection of the pixel opening communicating with the isolation opening 12a onto the array substrate 11. The orthographic projections of the pixel openings of the light-emitting device 13 onto the array substrate 11 overlap with the orthographic projections of the isolation openings 12a onto the array substrate 11. The pixel defining layer 17 is made of an inorganic material, such as an inorganic insulating material formed by using at least one of silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiON).

[0051] In another embodiment, the isolation structure 12 is disposed within the recess of the pixel limiting layer 17. Alternatively, the pixel limiting layer 17 may not be provided in the display panel 100, and the isolation structure 12 may be disposed on one side of the array substrate 11, with the isolation structure 12 in contact with one side of the array substrate 11.

[0052] The first light-emitting device 13a, the second light-emitting device 13b, and the third light-emitting device 13c emit light of different colors. Each of the three devices includes a first electrode 131, a light-emitting structure 132, and a second electrode 133 stacked together. The first electrode 131 is disposed on the array substrate 11, and a pixel defining layer 17 covers the end of the first electrode 131. A pixel opening is provided on the pixel defining layer 17, through which the first electrode 131 is exposed. The light-emitting structure 132 of the first light-emitting device 13a, the second light-emitting device 13b, and the third light-emitting device 13c covers the sidewall of the pixel opening of the pixel defining layer 17 and the side of the pixel defining layer 17 facing away from the array substrate 11. Each light-emitting structure 132 is located within the pixel opening and is in contact with the first electrode 131.

[0053] The second electrodes 133 of the first light-emitting device 13a, the second light-emitting device 13b, and the third light-emitting device 13c respectively cover the corresponding light-emitting structure 132. The second electrodes 133 are electrically connected to the isolation structure 12. For example, the second electrodes 133 are connected to the isolation portion 122 of the isolation structure 12, and / or the second electrodes 133 are connected to the base portion 123 of the isolation structure 12.

[0054] The first electrode 131 can be an anode, and the second electrode 133 can be a cathode. The first electrode 131 of each light-emitting device 13 can be connected to the pixel circuit through a via, so that the pixel circuit drives the light-emitting device 13 to emit light.

[0055] The first electrode 131 may include a multilayer structure, such as a reflective layer and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer, respectively. The reflective layer can be formed, for example, using silver, a metallic material with excellent light reflectivity. Each conductive oxide layer can be formed, for example, from a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide). The second electrode 133 is formed, for example, from a metallic material such as an alloy of magnesium and silver (MgAg).

[0056] Figure 8 These are schematic diagrams of the light-emitting structures in some embodiments of this application. For example... Figure 8As shown, the light-emitting structure 132 of at least one of the first light-emitting device 13a, the second light-emitting device 13b, and the third light-emitting device 13c includes a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL, a light-emitting material layer EML, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL stacked along a direction away from the array substrate 11 (i.e., the Z direction). The light-emitting structure 132 may include a single light-emitting material layer EML, or a stacked light-emitting structure including multiple light-emitting material layers EML.

[0057] In order for the light-emitting structure 132 to emit light, a pixel voltage is provided to the first electrode 131 and a common voltage is provided to the second electrode 133, forming a potential difference between the first electrode 131 and the second electrode 133, so that the light-emitting structure 132 disposed between the first electrode 131 and the second electrode 133 emits light. In one embodiment, if a potential difference is formed between the first electrode 131 and the second electrode 133 of the first light-emitting device 13a, the light-emitting material layer EML of the light-emitting structure 132 emits blue light; if a potential difference is formed between the first electrode 131 and the second electrode 133 of the second light-emitting device 13b, the light-emitting material layer EML of the light-emitting structure 132 emits green light; and if a potential difference is formed between the first electrode 131 and the second electrode 133 of the third light-emitting device 13c, the light-emitting material layer EML of the light-emitting structure 132 emits red light.

[0058] In this configuration, the pixel voltage of the first electrode 131 is provided by the pixel circuit 1, and the common voltage of the second electrode 133 is provided by the isolation structure 12. Specifically, the second electrode 133 is electrically connected to the isolation structure 12, and the common voltage is supplied to the second electrode 133 by providing the isolation structure 12. That is, the isolation structure 12 has the function of supplying a common voltage to the second electrode 133.

[0059] Figure 9 These are partial film layer cross-sectional views of the display panel in some embodiments of this application. For example... Figure 9As shown, the display panel 10 also includes a first encapsulation layer, which includes a plurality of encapsulation portions 14. The encapsulation portions 14 are located on the side of the second electrode 133 facing away from the array substrate 11, and extend through the sidewall of the isolation structure 12 to the side of the isolation structure 12 facing away from the array substrate 11. The plurality of encapsulation portions 14 include a plurality of first encapsulation portions 14a corresponding to a plurality of first light-emitting devices 13a, a plurality of second encapsulation portions 14b corresponding to a plurality of second light-emitting devices 13b, and a plurality of third encapsulation portions 14c corresponding to a plurality of third light-emitting devices 13c. The first encapsulation portions 14a are disposed on the side of the corresponding first light-emitting device 13a facing away from the array substrate 11, the second encapsulation portions 14b are disposed on the side of the corresponding second light-emitting device 13b facing away from the array substrate 11, and the third encapsulation portions 14c are disposed on the side of the corresponding third light-emitting device 13c facing away from the array substrate 11.

[0060] Continue to refer to Figure 9 The display panel 10 further includes a second encapsulation layer 15 and a third encapsulation layer 16. The second encapsulation layer 15 covers the isolation structure 12 and the encapsulation portion 14, and the third encapsulation layer 16 covers the second encapsulation layer 15. Both the first encapsulation layer and the third encapsulation layer 16 are inorganic materials, and the materials of the first encapsulation layer and the third encapsulation layer 16 include at least one of silicon nitride (SiN), silicon oxide (SiO), and silicon oxynitride (SiON). The second encapsulation layer 15 is an organic insulating material, such as epoxy resin, acrylic resin, or other resin materials. The second encapsulation layer 15 and the third encapsulation layer 16 are continuously disposed at least over the entire display area AA, with a portion of them also disposed in the bezel area NA.

[0061] The display panel 10 may also include at least one film layer such as a touch layer, a polarizer, a color filter substrate, and a protective cover. This film layer may also be bonded to the display panel via an adhesive layer such as OCA (Optical Clear Adhesive).

[0062] Figure 10 These are flowcharts illustrating the steps of a method for manufacturing a display panel according to some embodiments of this application. The following is a summary of the steps. Figure 11 The manufacturing method of the display panel 10 will be described.

[0063] like Figure 11 As shown, the manufacturing method of the display panel includes the following steps: Step S11: Provide an array substrate.

[0064] Step S12: An isolation structure is formed on one side of the array substrate. The isolation structure has multiple isolation openings, including multiple first isolation openings, multiple second isolation openings, and multiple third isolation openings.

[0065] Step S13: Fabricate the film layer of the first light-emitting device, which includes the light-emitting structure layer and the second electrode layer of the first light-emitting device.

[0066] Step S14: Fabricate the first encapsulation layer of the first light-emitting device. Since the film layer and the first encapsulation layer of the first light-emitting device are both fabricated as a single layer, the film layer and the first encapsulation layer of the first light-emitting device are present at the locations of the multiple first isolation openings, the multiple second isolation openings, and the multiple third isolation openings.

[0067] Step S15: Etch away the film layer and the first encapsulation layer of the first light-emitting device at the locations of the multiple second isolation openings and the multiple third isolation openings, thereby forming the light-emitting structure and the second electrode of the first light-emitting device, as well as the first encapsulation portion of the first light-emitting device, only at the locations of the multiple first isolation openings.

[0068] Based on the above steps S13 to S15, the light-emitting structure 132 and the second electrode 133 of the second light-emitting device 13b and the first encapsulation part 14b of the second light-emitting device 13b are respectively provided at the positions of the multiple second isolation openings 12a2, and the light-emitting structure 132 and the second electrode 133 of the third light-emitting device 13c and the first encapsulation part 14c of the third light-emitting device 13c are respectively provided at the positions of the multiple third isolation openings 12a3.

[0069] Figure 11 These are simplified structural diagrams of pixel circuits in some embodiments of this application. For example... Figure 11 As shown, the pixel circuit includes a driving sub-circuit 1 and a reset sub-circuit 2. The driving sub-circuit 1 is electrically connected to the first node N1 and the second node N2, respectively. The first node N1 is electrically connected to the first voltage terminal VDD, and the second node N2 is electrically connected to the light-emitting device 13. The reset sub-circuit 2 is electrically connected to the reset voltage terminal, the reset control terminal, and the first node N1, respectively.

[0070] Figure 12 These are simplified structural diagrams of pixel circuits in some embodiments of this application. For example... Figure 12 As shown, the pixel circuit includes a driving sub-circuit 1 and a reset sub-circuit 2. The driving sub-circuit 1 is electrically connected to the first node N1 and the second node N2, respectively. The first node N1 is electrically connected to the first voltage terminal VDD, and the second node N2 is electrically connected to the light-emitting device 13. The reset sub-circuit 2 is electrically connected to the reset voltage terminal, the reset control terminal, and the second node N2, respectively.

[0071] Figure 13 These are simplified structural diagrams of pixel circuits in some embodiments of this application. For example... Figure 13As shown, the pixel circuit includes a driving sub-circuit 1 and two reset sub-circuits 2. The driving sub-circuit 1 is electrically connected to a first node N1 and a second node N2, respectively. The first node N1 is electrically connected to a first voltage terminal VDD, and the second node N2 is electrically connected to the light-emitting device 13. One of the reset sub-circuits 2 is electrically connected to a reset voltage terminal, a reset control terminal, and the first node N1, respectively. The other reset sub-circuit 2 is electrically connected to the reset voltage terminal, the reset control terminal, and the second node N2, respectively.

[0072] Figure 14 These are circuit schematics of pixel circuits in some embodiments of this application. Figure 14 The diagram shows a pixel circuit consisting of only one reset sub-circuit 2, which is electrically connected to the first node N1. Figure 14 The specific structure of a pixel circuit is introduced using an example.

[0073] For example, such as Figure 14 As shown, the driving sub-circuit 1 includes a driving transistor T1, the source of which is connected to the first node N1, and the drain of which is connected to the second node N2. The first node N1 is electrically connected to the first voltage terminal VDD. The reset sub-circuit 2 includes a reset transistor T3, the source of which is electrically connected to the reset voltage terminal Reset, the drain of which is electrically connected to the first node N1, and the gate of which is electrically connected to the reset control terminal G.

[0074] Continue to refer to Figure 14 The pixel circuit may also include a data transistor T2 and a storage capacitor C1. The source of the data transistor T2 is connected to the data line that provides the data signal Data, the gate of the data transistor T2 is connected to the scan line that provides the scan signal Scan, the drain of the data transistor T2 is connected to the gate of the driving transistor T1, and the two ends of the storage capacitor C1 are respectively connected to the gate and the source of the driving transistor T1.

[0075] Continue to refer to Figure 14 The pixel circuit may also include a light-emitting control transistor T4, the source of which is electrically connected to the second node N2, the drain of which is electrically connected to the anode of the light-emitting device 13, the cathode of which is electrically connected to the second voltage terminal VSS, and the gate of which is electrically connected to the light-emitting control terminal EM.

[0076] Within a display frame, the operation of a sub-pixel includes multiple lighting stages and multiple extinguishing stages. During the lighting stage, the light-emitting device 13 emits light, and during the extinguishing stage, the light-emitting device 13 does not emit light. Figure 15 This is a partial signal timing diagram of the pixel circuit. For example, as shown... Figure 15As shown, in the signal of the light-emitting control terminal EM, a high level corresponds to the off stage. When the signal of the light-emitting control terminal EM is high, the light-emitting control transistor T4 is turned off, and the light-emitting device 13 does not emit light. In the signal of the light-emitting control terminal EM, a low level corresponds to the lighting stage. When the signal of the light-emitting control terminal EM is low, the light-emitting control transistor T4 is turned on, and the light-emitting device 13 emits light.

[0077] Within a display frame, as the operating time of the driving transistor T1 increases, the threshold voltage of the driving transistor T1 shifts, causing a change in the brightness of the light-emitting device 13. The reset sub-circuit 2 is configured to reset the driving sub-circuit 1 multiple times according to the reset voltage of the reset voltage terminal Reset, under the control of the reset control terminal G. For example, the reset sub-circuit 2 is turned on under the control of the reset control terminal G, and the reset voltage of the reset voltage terminal Reset is written to the first node N1 and / or the second node N2, thereby resetting the driving sub-circuit 1. The reset of the driving sub-circuit 1 occurs during the off-state phase.

[0078] For example, continue to refer to Figure 15 When the reset control terminal G is low, the reset transistor T3 is turned on, and the signal at the reset voltage terminal G is written to the first node N1, thereby resetting the driving transistor T1. When the reset control terminal G is high, the reset transistor T3 is turned off, the signal at the reset voltage terminal Reset cannot be written to the first node N1, and the driving transistor T1 cannot be reset. The duration of the low-level signal is equal to the reset time of the driving transistor T1.

[0079] Continue to refer to Figure 15 Within one display frame, the signal at the reset control terminal G includes multiple low-level signals. Therefore, within one display frame, the reset sub-circuit 2 resets the drive sub-circuit 1 multiple times. However, the display panel 10 equipped with the reset sub-circuit 2 will exhibit flickering during image display.

[0080] The inventors discovered through analysis that the flickering phenomenon was caused by the inconsistency between the threshold voltage of the driving transistor T1 after the previous reset and the threshold voltage of the driving transistor T1 after the next reset. The following is a combination of... Figure 15 This section details the causes of flickering.

[0081] Figure 15 Taking a display frame time consisting of three lighting pulses and two reset pulses as an example. Figure 15As shown, in the previous display frame, when the signal of the light-emitting control terminal EM first goes high, the signal of the reset control terminal G goes low, resetting the driving transistor T1. After the reset is complete, after two lighting stages, the signal of the reset control terminal G goes low again, resetting the driving transistor T1 again. In the next display frame, when the signal of the light-emitting control terminal EM first goes high, the signal of the reset control terminal G goes low, resetting the driving transistor T1.

[0082] After the first reset of driver transistor T1, it undergoes two lighting stages followed by a second reset. After the second reset, it undergoes one lighting stage followed by a third reset. The threshold voltage offset of driver transistor T1 is positively correlated with its operating time; the longer the operating time, the larger the threshold voltage offset, and vice versa. The threshold voltage offset of driver transistor T1 after two lighting stages is greater than that after one lighting stage.

[0083] After resetting the driving transistor T1, the correction amount of its threshold voltage offset is positively correlated with the reset time. A longer reset time results in a larger correction amount, and a shorter reset time results in a smaller correction amount. Since the duration of each reset pulse is the same in related technologies, the correction amount of the threshold voltage offset is the same for each reset. Before the second reset, the threshold voltage offset of the driving transistor T1 is greater than before the third reset, while the correction amount during the second reset is the same as that during the third reset. Therefore, the threshold voltage offset after the second reset is different from that after the third reset, leading to a difference in the brightness of the light-emitting device 13 after the second reset and the third reset, resulting in flickering.

[0084] The multiple resets of driver sub-circuit 1 include the Nth reset and the (N+1)th reset. The Nth reset can be any reset, and the (N+1)th reset is the reset following the Nth reset, and the (N+1)th reset is adjacent to the Nth reset. For example, if the Nth reset is the first reset, the (N+1)th reset is the second reset. Or, if the Nth reset is the second reset, then the (N+1)th reset is the third reset.

[0085] The Nth reset and the (N+1)th reset can occur within the same display frame. Alternatively, they can occur within different display frame times. For example, the Nth reset might occur in the previous display frame, and the (N+1)th reset in the next display frame.

[0086] The threshold offset of the driving transistor T1 before the Nth reset may be different from that before the N+1th reset. If the duration of the Nth reset is the same as that of the N+1th reset, the state of the driving transistor T1 after the Nth reset will be different from that after the N+1th reset, resulting in a difference between the brightness of the light-emitting device 13 after the Nth reset and the brightness of the light-emitting device 13 after the N+1th reset, thus causing flickering.

[0087] Therefore, in this embodiment, the duration of the Nth reset is different from the duration of the (N+1)th reset. This allows for flexible adjustment of the duration of the Nth and (N+1)th resets based on the threshold offset of the driving transistor T1 before the Nth reset and the threshold offset of the driving transistor T1 before the (N+1)th reset. This ensures that the state of the driving transistor T1 after the Nth reset is the same as or similar to the state of the driving transistor T1 after the (N+1)th reset, thereby improving the flickering phenomenon of the display panel 10.

[0088] For example, if the threshold offset of the driving transistor T1 before the Nth reset is greater than the threshold offset of the driving transistor T1 before the (N+1)th reset, then the duration of the Nth reset can be greater than the duration of the (N+1)th reset; if the threshold offset of the driving transistor T1 before the Nth reset is less than the threshold offset of the driving transistor T1 before the (N+1)th reset, then the duration of the Nth reset can be less than the duration of the (N+1)th reset.

[0089] In some implementations, multiple resets also include an (N-1)th reset, where the interval between the (N-1)th reset and the Nth reset is greater than the interval between the Nth reset and the (N+1)th reset, and the duration of the Nth reset is greater than the duration of the (N+1)th reset.

[0090] The (N-1)th reset is a reset preceding the Nth reset, and it is adjacent to the Nth reset. The relatively large interval between the (N-1)th and Nth resets results in a longer operating time for the driving transistor T1 before the Nth reset, leading to a larger threshold offset for T1. Conversely, the relatively small interval between the Nth and (N+1)th resets results in a longer operating time for T1 before the (N+1)th reset, leading to a smaller threshold offset for T1. Therefore, the duration of the Nth reset is longer than that of the (N+1)th reset, ensuring that the state of the driving transistor T1 after the Nth reset is the same as or similar to that after the (N+1)th reset, thus improving the flickering phenomenon of the display panel 10.

[0091] In some embodiments, multiple resets also include an N-1th reset. The light-emitting time of the light-emitting device 13 during the interval between the N-1th reset and the Nth reset is a first time, and the light-emitting time of the light-emitting device 13 during the interval between the Nth reset and the N+1th reset is a second time. The first time is greater than the second time, and the duration of the Nth reset is greater than the duration of the N+1th reset.

[0092] The threshold offset of driving transistor T1 is positively correlated with the operating time of driving transistor T1. When the first time is longer than the second time, the threshold offset of driving transistor T1 before the Nth reset is greater than the threshold offset of driving transistor T1 before the (N-1)th reset. Therefore, the duration of the Nth reset is longer than the duration of the N+1th reset, making the state of driving transistor T1 after the Nth reset the same as or similar to the state of driving transistor T1 after the N+1th reset, thus improving the flickering phenomenon of display panel 10.

[0093] In some implementations, the duration of the (N+1)th reset is positively correlated with the second time. Specifically, the duration of the (N+1)th reset can be directly proportional to the second time; for example, if the second time increases by 50%, the duration of the (N+1)th reset increases by 50%; if the second time increases by 60%, the duration of the (N+1)th reset increases by 60%. Of course, the duration of the (N+1)th reset can also be non-proportional to the second time; for example, if the second time increases by 50%, the duration of the (N+1)th reset increases by 60%.

[0094] The threshold offset of the driving transistor T1 is positively correlated with the operating time of the driving transistor T1. Therefore, the duration of the N+1th reset is positively correlated with the second time, which can make the state of the driving transistor T1 after each reset tend to be consistent.

[0095] For example, in some implementations, the duration of the Nth reset is The duration of the (N+1)th reset is The first thing is The second time is ,but We assume that the duration of the reset is linearly related to the amount of correction of the threshold voltage offset for ease of calculation.

[0096] In some implementations, the Nth reset occurs in the Mth display frame, and the (N+1)th reset occurs in the (M+1)th display frame. The inconsistent operating time of the driving transistor T1 before the reset typically occurs between the last reset of the previous display frame and the first reset of the next display frame; therefore, the Nth and (N+1)th resets are not within the same display frame.

[0097] For example, the Mth display frame is the previous display frame, and the (M+1)th display frame is the next display frame.

[0098] For example, a display frame includes three light-up pulses, three light-down pulses, and two reset pulses. During the duration of the previous display frame, a first reset occurs during the first light-down pulse, and a second reset occurs during the third light-down pulse. During the duration of the next display frame, a third reset occurs during the first light-down pulse, and a fourth reset occurs during the third light-down pulse. There are two light-up pulses between the first and second resets, and only one light-up pulse between the second and third resets. Therefore, the duration of the third reset is shorter than the duration of the second reset.

[0099] In some embodiments, the display panel 10 further includes a gate driving circuit (not shown in the figures), which is configured to provide a reset control signal to a reset control terminal. The reset control signal includes a plurality of reset pulses, and the reset sub-circuit 2 is configured to reset the drive sub-circuit 1 during the duration of the reset pulses.

[0100] Figure 16 This is a partial timing diagram of the pixel circuit. For example... Figure 16 As shown, the multiple reset pulses include a first pulse and a second pulse. The first pulse is configured to control the reset sub-circuit 2 to perform the Nth reset on the drive sub-circuit 1, and the second pulse is configured to control the reset sub-circuit 2 to perform the N+1th reset on the drive sub-circuit 1. The duration of the first pulse is different from the duration of the second pulse.

[0101] The threshold offset of the driving transistor T1 before the Nth reset may be different from that before the (N+1)th reset, and the duration of the first pulse may be different from that of the second pulse. In this way, the duration of the first pulse and the duration of the second pulse can be flexibly adjusted according to the threshold offset of the driving transistor T1 before the Nth reset and the threshold offset of the driving transistor T1 before the (N+1)th reset, so that the state of the driving transistor T1 after the Nth reset is the same as or similar to that after the (N+1)th reset, thereby improving the flickering phenomenon of the display panel 10.

[0102] Continue to refer to Figure 16 In some embodiments, the multiple reset pulses also include a third pulse, which is configured to control the reset sub-circuit 2 to perform the (N-1)th reset on the drive sub-circuit 1. The time between the third pulse and the first pulse is greater than the time between the second pulse and the first pulse, and the duration of the first pulse is greater than the duration of the second pulse.

[0103] The longer interval between the (N-1)th and Nth resets results in a longer operating time for the driving transistor T1 before the Nth reset, leading to a larger threshold offset for T1. Conversely, the shorter interval between the Nth and N+1th resets results in a longer operating time for the driving transistor T1 before the N+1th reset, leading to a smaller threshold offset for T1. Therefore, the duration of the first pulse is longer than the duration of the second pulse, ensuring that the state of the driving transistor T1 after the Nth reset is the same as or similar to that after the N+1th reset, thus improving the flickering phenomenon of the display panel 10.

[0104] Continue to refer to Figure 16 In some embodiments, the multiple reset pulses also include a third pulse, which is configured to control the reset sub-circuit 2 to perform the (N-1)th reset on the drive sub-circuit 1. The light emission time of the light-emitting device 13 during the interval between the third pulse and the first pulse is the first time, and the light emission time of the light-emitting device 13 during the interval between the first pulse and the second pulse is the second time. The first time is greater than the second time, and the duration of the first pulse is greater than the duration of the second pulse.

[0105] The threshold offset of driving transistor T1 is positively correlated with the operating time of driving transistor T1. When the first time is longer than the second time, the threshold offset of driving transistor T1 before the Nth reset is greater than the threshold offset of driving transistor T1 before the (N-1)th reset. Therefore, the duration of the first pulse is longer than the duration of the second pulse, making the state of driving transistor T1 after the Nth reset the same as or similar to the state of driving transistor T1 after the (N+1)th reset, thus improving the flickering phenomenon of display panel 10.

[0106] This application also provides a driving method for driving the display panel 10. Figure 17 This is a flowchart illustrating the steps of a driving method provided in some embodiments of this application. For example... Figure 17 As shown, the driving method includes the following steps.

[0107] S100: Controls the reset sub-circuit to perform the Nth reset on the drive sub-circuit.

[0108] S200: Controls the reset sub-circuit to perform the N+1th reset on the drive sub-circuit.

[0109] The duration of the Nth reset is different from the duration of the (N+1)th reset.

[0110] In the driving method provided by the embodiments of this application, the threshold offset of the driving transistor T1 before the Nth reset may be different from the threshold offset of the driving transistor T1 before the (N+1)th reset. If the duration of the Nth reset is the same as the duration of the (N+1)th reset, the state of the driving transistor T1 after the Nth reset will be different from the state of the driving transistor T1 after the (N+1)th reset, resulting in a difference in the brightness of the light-emitting device 13 after the Nth reset compared to the brightness of the light-emitting device 13 after the (N+1)th reset, thus causing flickering. Therefore, in the embodiments of this application, the duration of the Nth reset is different from the duration of the (N+1)th reset. This allows for flexible adjustment of the duration of the Nth and (N+1)th resets based on the threshold offset of the driving transistor T1 before the Nth reset and the threshold offset of the driving transistor T1 before the (N+1)th reset, ensuring that the state of the driving transistor T1 after the Nth reset is the same as or similar to the state of the driving transistor T1 after the (N+1)th reset, thereby improving the flickering phenomenon of the display panel 10.

[0111] In some implementations, step S200, which controls the reset sub-circuit 2 to perform the (N+1)th reset on the drive sub-circuit 1, includes the following sub-steps.

[0112] S210: Controls the gate drive circuit to generate a second pulse; S220: The control reset sub-circuit performs the N+1th reset on the drive sub-circuit according to the second pulse.

[0113] The gate drive circuit generates a reset control signal, which includes multiple reset pulses, with the second pulse being one of these pulses. During the duration of the second pulse, the reset sub-circuit 2 performs the (N+1)th reset on the drive sub-circuit 1.

[0114] Specifically, a second pulse can be generated based on the threshold voltage offset state of the driving transistor T1 before the (N+1)th reset. When the threshold voltage offset of the driving transistor T1 before the (N+1)th reset is large, the duration of the second pulse is longer; when the threshold voltage offset of the driving transistor T1 before the (N+1)th reset is small, the duration of the second pulse is shorter.

[0115] In some implementations, the control gate drive circuit generates a second pulse in sub-step S210, including the following sub-steps.

[0116] S211: Obtain the duration of the first time, the second time, and the Nth reset; S212: Determine the duration of the (N+1)th reset based on the first time, the second time, and the duration of the Nth reset; S213: Generate a second pulse based on the duration of the (N+1)th reset.

[0117] The light-emitting time of the light-emitting device 13 during the interval between the (N-1)th reset and the Nth reset is the first time, and the light-emitting time of the light-emitting device 13 during the interval between the Nth reset and the N+1th reset is the second time.

[0118] For example, the duration of the Nth reset is The duration of the second pulse is The first thing is The second time is ,but .

[0119] In some implementations, the control board is configured to execute a driving method. For example, a timing controller or display driver chip on the control board is configured to execute a driving method.

[0120] Some embodiments of this application also provide a driving device for driving a display panel, the driving device being used to execute the driving method described above.

[0121] In practical applications, the driver chip (DDIC) can preset multiple reset control signals, each of which is different. The reset control signal that matches the specific display panel can be selected from the multiple reset control signals according to the specific situation of the display panel.

[0122] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0123] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A display panel, characterized in that, The display panel includes: Light-emitting devices; A driving sub-circuit, wherein the driving sub-circuit is electrically connected to a first node and a second node respectively, the first node is electrically connected to a first voltage terminal, and the second node is electrically connected to the light-emitting device; A reset sub-circuit is electrically connected to a reset voltage terminal and a reset control terminal, and is also electrically connected to the first node and / or the second node. The reset sub-circuit is configured to perform multiple resets on the drive sub-circuit according to the reset voltage of the reset voltage terminal under the control of the reset control terminal. The multiple resets include an Nth reset and an (N+1)th reset, and the duration of the Nth reset is different from the duration of the (N+1)th reset.

2. The display panel according to claim 1, characterized in that, The multiple resets also include the (N-1)th reset, the interval between the (N-1)th reset and the Nth reset is greater than the interval between the Nth reset and the (N+1)th reset, and the duration of the Nth reset is greater than the duration of the (N+1)th reset.

3. The display panel according to claim 1, characterized in that, The multiple resets also include the (N-1)th reset. The light-emitting time of the light-emitting device during the interval between the (N-1)th reset and the Nth reset is a first time, and the light-emitting time of the light-emitting device during the interval between the Nth reset and the (N+1)th reset is a second time. The first time is greater than the second time, and the duration of the Nth reset is greater than the duration of the (N+1)th reset.

4. The display panel according to claim 3, characterized in that, The duration of the (N+1)th reset is positively correlated with the second time.

5. The display panel according to claim 4, characterized in that, The duration of the Nth reset is The duration of the (N+1)th reset is The first time is The second time is ,but .

6. The display panel according to claim 1, characterized in that, The Nth reset occurs in the Mth display frame, and the (N+1)th reset occurs in the (M+1)th display frame.

7. The display panel according to claim 1, characterized in that, The display panel further includes a gate driving circuit, which is configured to provide a reset control signal to the reset control terminal. The reset control signal includes a plurality of reset pulses, and the reset sub-circuit is configured to reset the driving sub-circuit during the duration of the reset pulses. The plurality of reset pulses include a first pulse and a second pulse. The first pulse is configured to control the reset sub-circuit to perform the Nth reset on the drive sub-circuit, and the second pulse is configured to control the reset sub-circuit to perform the (N+1)th reset on the drive sub-circuit. The duration of the first pulse is different from the duration of the second pulse.

8. The display panel according to claim 7, characterized in that, The plurality of reset pulses also includes a third pulse, which is configured to control the reset sub-circuit to perform the (N-1)th reset on the drive sub-circuit. The time between the third pulse and the first pulse is greater than the time between the second pulse and the first pulse, and the duration of the first pulse is greater than the duration of the second pulse.

9. The display panel according to claim 7, characterized in that, The plurality of reset pulses also include a third pulse, which is configured to control the reset sub-circuit to perform the (N-1)th reset on the drive sub-circuit. The light-emitting device emits light for a first time during the interval between the third pulse and the first pulse, and emits light for a second time during the interval between the first pulse and the second pulse. The first time is longer than the second time, and the duration of the first pulse is longer than the duration of the second pulse.

10. A driving method for driving a display panel, characterized in that, The display panel includes a light-emitting device, a driving sub-circuit, and a reset sub-circuit. The driving sub-circuit is electrically connected to a first node and a second node, respectively. The first node is electrically connected to a first voltage terminal, and the second node is electrically connected to the light-emitting device. The reset sub-circuit is electrically connected to a reset voltage terminal and a reset control terminal, respectively. The reset sub-circuit is also electrically connected to the first node and / or the second node. The reset sub-circuit is configured to reset the driving sub-circuit multiple times according to the reset voltage of the reset voltage terminal under the control of the reset control terminal. The driving method includes: The reset sub-circuit is controlled to perform the Nth reset on the drive sub-circuit. The reset sub-circuit is controlled to perform the (N+1)th reset on the drive sub-circuit. The duration of the Nth reset is different from the duration of the (N+1)th reset.

11. The driving method according to claim 10, characterized in that, The display panel further includes a gate driving circuit, which is configured to provide a reset control signal to the reset control terminal. The reset control signal includes a plurality of reset pulses, and the reset sub-circuit is configured to reset the driving sub-circuit during the duration of the reset pulses. The control of the reset sub-circuit to perform the (N+1)th reset of the drive sub-circuit includes: The gate drive circuit is controlled to generate a second pulse; the second pulse is one of the plurality of reset pulses. The reset sub-circuit is controlled to perform the (N+1)th reset on the drive sub-circuit according to the second pulse.

12. The driving method according to claim 11, characterized in that, The step of controlling the gate drive circuit to generate the second pulse includes: The first time, the second time, and the duration of the Nth reset are obtained; the light-emitting time of the light-emitting device during the interval between the (N-1)th reset and the Nth reset is the first time, and the light-emitting time of the light-emitting device during the interval between the Nth reset and the (N+1)th reset is the second time; The duration of the (N+1)th reset is determined based on the first time, the second time, and the duration of the Nth reset; The second pulse is generated based on the duration of the (N+1)th reset.

13. The driving method according to claim 12, characterized in that, The first time is greater than the second time, and the duration of the Nth reset is greater than the duration of the (N+1)th reset.

14. A driving device for driving a display panel, characterized in that, The driving device is used to perform the driving method as described in any one of claims 10 to 13.

15. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 9.

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