Display panel

Abstract

The embodiment of the invention provides a display panel. The display panel comprises a multiplexing circuit and an error-proof charging circuit. The multiplexing circuit comprises a multiplexing unit, and the multiplexing unit comprises a first selection transistor and a second selection transistor; the misplacement charging circuit comprises an anti-phase control unit; the inverting control unit includes a first inverting transistor and a second inverting transistor. The multiplexing unit is used for communicating the data input line with the first data line and the second data line in a time-sharing manner in response to that the first selection signal and the second selection signal are sequentially at effective levels. The anti-phase control unit is used for controlling the first anti-phase transistor to be conducted to pull back or maintain the level of the control electrode of the second selection transistor at an ineffective level when the first selection signal is in an effective level; when the second selection signal is in the effective level, the second inverting transistor is controlled to be switched on so as to pull back the level of the control electrode of the first selection transistor or maintain the level at the ineffective level, so that the display abnormity that the data signal is transmitted mistakenly due to the selection signal delay is prevented.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel. BACKGROUND

[0002] In the field of display technology, mux multiplexing technology is usually used to realize time-sharing transmission of data signals to corresponding pixel columns through different data lines by switching, so as to reduce the number of source driving chips (Source IC, hereinafter referred to as Source) used, thereby reducing cost and power consumption. However, due to the design of large size, high resolution and narrow frame, the RC load of the signal transmission line increases, which makes the delay of the selection signal transmitted by the line heavier, thereby causing some data signals to be incorrectly provided to unrelated pixel columns, thereby causing display abnormalities. SUMMARY

[0003] The embodiment of the present application provides a display panel, which realizes effective provision of data signals of a plurality of pixel columns through the design of a multiplexing circuit and an error prevention charging circuit, avoids signal interference and incorrect transmission, and improves the display performance of the display panel.

[0004] In one aspect, the display panel provided by the embodiment of the present application comprises a display area and a non-display area, the display area comprises a plurality of pixel columns, each pixel column is connected with at least one data line and comprises a plurality of pixel units, the non-display area comprises a multiplexing circuit and an error-proof charging circuit, the multiplexing circuit comprises at least one multiplexing unit, the multiplexing unit comprises a first selection transistor and a second selection transistor, the source and the drain of the first selection transistor are connected between a data input line and a first data line, the control electrode of the first selection transistor is connected with a first selection control line, the source and the drain of the second selection transistor are connected between the data input line and a second data line, the control electrode of the second selection transistor is connected with a second selection control line, the error-proof charging circuit comprises an inverse control unit corresponding to the multiplexing unit, the inverse control unit comprises a first inverse control group and a second inverse control group, the first inverse control group comprises a first inverse transistor, the second inverse control group comprises a second inverse transistor, the source and the drain of the first inverse transistor are connected between the second selection control line and a low-level power supply line, the control electrode of the first inverse transistor is connected with the first selection control line, the source and the drain of the second inverse transistor are connected between the first selection control line and the low-level power supply line, and the control electrode of the second inverse transistor is connected with the second selection control line, the multiplexing unit is used to make the first selection transistor and the second selection transistor conductive in sequence to connect the data input line with the first data line and the second data line in time division to provide a data signal for the corresponding pixel unit in response to the first selection signal transmitted by the first selection control line and the second selection signal transmitted by the second selection control line being in an effective level in sequence, and the inverse control unit is used to control the first inverse transistor to conduct in response to the first selection signal being in the effective level to pull or maintain the level of the control electrode of the second selection transistor at an ineffective level, and control the second inverse transistor to conduct in response to the second selection signal being in the effective level to pull or maintain the level of the control electrode of the first selection transistor at the ineffective level.

[0005] The display panel provided by the embodiment of the present application first controls the selection signal in time division through the multiplexing circuit to effectively provide the multiplexed data signal, avoids signal interference, reduces the number of source driving chips, reduces power consumption and saves cost. Furthermore, when the second selection signal is in the effective level, the level of the control electrode of the first selection transistor is pulled back or maintained at the ineffective level through the design of the error-proof charging circuit, which avoids the abnormality of the display panel caused by the pixel units in the pixel column corresponding to the first selection transistor due to the provision of the error data signal, thereby improving the display performance of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0006] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0007] In order to more completely understand the present application and its beneficial effects, the following will be described in conjunction with the drawings, wherein the same reference numerals in the following description represent the same parts.

[0008] Figure 1 An exemplary structural schematic diagram of the arrangement of pixel units in the display panel provided by the embodiments of the present application is shown.

[0009] Figure 2 An exemplary structural block diagram of the display panel in the related art provided by the embodiments of the present application is shown.

[0010] Figure 3 An exemplary structural block diagram of the display panel provided by the embodiments of the present application is shown. Figure 1 An exemplary schematic diagram of the ideal control timing of the display panel is shown.

[0011] Figure 4 An exemplary schematic diagram of the actual control timing of the display panel is shown. Figure 1

[0012] An exemplary structural block diagram of the display panel provided by the embodiments of the present application is shown. Figure 5

[0013] An exemplary schematic diagram of the control timing of the display panel is shown. Figure 6 Figure 5 An exemplary structural block diagram of the display panel provided by the embodiments of the present application is shown.

[0014] Figure 7 An exemplary schematic diagram of the control timing of the display panel is shown.

[0015] Figure 8 Figure 7 An exemplary structural block diagram of the display panel provided by the embodiments of the present application is shown.

[0016] Figure 9 An exemplary structural block diagram of the display panel provided by the embodiments of the present application is shown.

[0017] Figure 10 An exemplary schematic diagram of the control timing of the display panel is shown. Figure 9

[0018] Figure 11 ​​​Another exemplary structural block diagram of a display panel with mux2:4 provided in embodiments of the present application.

[0019] Figure 12 An exemplary structural block diagram of a display panel with mux2:6 provided in embodiments of the present application. DETAILED DESCRIPTION

[0020] The technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by a person skilled in the art without creative labor fall within the scope of protection of the present application.

[0021] The terms "first", "second", and the like in the present application are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or modules is not limited to the listed steps or modules, but can optionally include steps or modules not listed, or can optionally include other steps or modules inherent to the process, method, product, or device.

[0022] Reference to "embodiments" herein means that the specific features, structures, or characteristics described in connection with the embodiments can be included in at least one embodiment of the present application. The phrase appears at various places in the specification does not necessarily all refer to the same embodiments, nor is it necessarily mutually exclusive of other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0023] In the field of display technology, the display panel may, for example, be an Organic Light Emitting Diode (OLED) display panel, a liquid crystal display panel, and of course, the display panel can also be a Mini-LED display panel or a Micro-LED display panel. Exemplarily as shown in Figure 1 The display panel 100 can include a plurality of pixel units PX arranged in an array, a plurality of gate lines G1-Gn, and a plurality of data lines D1-Dm. Among them, the pixel units PX arranged along the first direction (exemplarily as shown in Figure 1 The pixel units PX arranged along the first direction (exemplarily as shown in Figure 1The pixel units PX arranged in the vertical direction as shown can be defined as a pixel column. The pixel units PX can include red (R) pixel units, green (G) pixel units, and blue (B) pixel units. An exemplary arrangement of the red pixel units, the green pixel units, and the blue pixel units can be that the pixel units PX in the same pixel row have the same color, the pixel units in the same pixel column have different colors, and the pixel units of different colors are arranged alternately along the second direction. Another exemplary arrangement of the red pixel units, the green pixel units, and the blue pixel units can be that the pixel units PX in the same pixel column have the same color, the pixel units in the same pixel row have different colors, and the pixel units of different colors are arranged alternately along the first direction.

[0024] As shown in Figure 1 The plurality of gate lines can exemplarily include gate lines G1, G2, …, Gn arranged along the second direction, and each of the gate lines is connected with the pixel units in a pixel row for transmitting a scanning signal. The plurality of data lines can exemplarily include data lines D1, D2, …, Dm arranged along the first direction, and each of the data lines is connected with the pixel units in at least one pixel column for transmitting a data signal. The data signal and the scanning signal can be used to turn on the corresponding pixel units.

[0025] At present, in order to reduce the number of source driving chips for providing data signals, the mux multiplexing technology can effectively reduce the number of input channels of the data signals. Exemplarily, referring to Figure 2 the display panel as shown and Figure 3The ideal control timing is shown. The display panel 100 includes two multiplexing units, and each multiplexing unit adopts mux1:2 multiplexing. The first multiplexing unit can include a first selection transistor K1 and a second selection transistor K2, which are controlled by the selection signals transmitted by the selection control lines Demux A and Demux B respectively, and the selection signals transmitted by the selection control lines Demux A and Demux B are in turn at the active level, so as to control the first selection transistor K1 and the second selection transistor K2 to be turned on at different times, so as to transmit the data signal provided by Source1 to the pixel units in the corresponding pixel column through the data line D1 and the data line D3 at different times. The second multiplexing unit can include a third selection transistor K3 and a fourth selection transistor K4, which are also controlled by the selection signals transmitted by the selection control lines Demux A and Demux B respectively, and the selection signals transmitted by the selection control lines Demux A and Demux B are in turn at the active level, so as to control the third selection transistor K3 and the fourth selection transistor K4 to be turned on at different times, so as to transmit the data signal provided by Source2 to the pixel units in the corresponding pixel column through the data line D4 and the data line D2 at different times. It should be noted that, Figure 2 The symbols "+" and "-" in the above formula represent the polarity of the pixel unit. The box R represents a red pixel unit; the box G represents a green pixel unit; and the box B represents a blue pixel unit. Source1 and Source2 represent two data input lines (or channels) for providing data signals, which can be included in one source driving chip (Source IC) or in different Source ICs. For example, Source1 and Source2 can be different pins in one source driving chip (Source IC) or pins of different Source ICs. In this application and the drawings, the drawings of the pixel units are the same as those represented by the above formula, and will not be described in detail hereinafter. Figure 2

[0026] In this way, through the above design, the pixel units in at least four pixel columns can be transmitted by two sources, which can reduce the number of Source ICs, save power consumption and cost. However, in actual use, with the development of display panels towards large size, high resolution and narrow frame (such as vehicle control screen, folding mobile phone, etc.), the RC load of the signal transmission line increases, which makes the delay of the selection signal transmitted by the signal transmission line more serious, so that the data signal is incorrectly provided to the unrelated pixel units, thereby causing the abnormality of the display picture. For example, as Figure 4 shown in FIG. 6, due to the increase of the RC load of the signal transmission line, the falling edge of the selection signal transmitted by the selection control line Demux A is delayed (the selection signal transmitted by the selection control line Demux B is not delayed, which is not shown in the figure), so that the selection signal transmitted by the selection control line Demux A is not transmitted to the selection transistor K1 in time, and the selection signal transmitted by the selection control line Demux B is not transmitted to the selection transistor K2 in time, so that the data signal provided by Source1 is incorrectly transmitted to the pixel units in the pixel column corresponding to the selection control line Demux B through the data line D3, and the data signal provided by Source2 is incorrectly transmitted to the pixel units in the pixel column corresponding to the selection control line Demux A through the data line D4. Figure 4 ​As shown by the number 1, when the selection signal transmitted by the selection control line Demux B is converted from the invalid level to the valid level, the selection signal transmitted by the selection control line Demux A does not drop to the invalid level, at this time, the selection transistor K1 is still in the on state, at this time, the data signal to be provided to the pixel unit connected with the data line D3 will also be provided to the pixel unit connected with the data line D1, in this case, the data signal written to the pixel unit connected with the data line D1 when the selection signal transmitted by the selection control line Demux A is in the valid level is covered by the newly written data signal (the data signal transmitted when the selection signal transmitted by the selection control line Demux B is in the valid level), which will cause the data signal written to the pixel unit connected with the data line D1 to be different from the originally designed one, thereby causing display abnormalities. The analysis of the remaining selection signals and selection transistors can be referred to the foregoing understanding, and will not be described in detail. As shown in the following figure, the selection signals transmitted by the selection control lines Demux A and Demux B are in the invalid level, and the selection signals transmitted by the selection control lines Demux C and Demux D are in the valid level. Figure 3 or Figure 4 As shown, the valid level can refer to the state that the selection signal is in the high level. The invalid level can refer to the state that the selection signal is in the low level. It should be noted that the valid level and the invalid level are relative, which is related to the type of the selection transistors K1-K4, which is not limited in the present application. It should be understood that, Figure 2 As shown, the data lines D1-D4 are only marked for the convenience of description, and are not used to limit the present application. The same is true for the following figures, and the following will not be declared.

[0027] Based on this, the embodiment of the present application provides a display panel, by designing a multiplexing circuit and an error-proof charging circuit, by adding a direct current signal in the invalid level, the inverse output of different split selection signals can be realized, so as to prevent the data signal from being incorrectly provided to the irrelevant pixel unit and causing the display picture abnormal, thereby realizing the effective provision of the data signal of the plurality of pixel columns, avoiding signal interference and mis-transmission, and improving the display performance of the display panel.

[0028] Specifically, in order to understand the present application, the following embodiments will be described in detail.

[0029] Embodiment one Mux1:2 As shown in the following figure, the selection signals transmitted by the selection control lines Demux A and Demux B are in the invalid level, and the selection signals transmitted by the selection control lines Demux C and Demux D are in the valid level. Figure 5As shown, the display panel 100 can include a display area 10 and a non-display area 20, the display area 10 includes a plurality of pixel columns; each pixel column is connected with at least one data line and includes a plurality of pixel units PX; the non-display area 20 includes a multiplexing circuit 101 and an error-proof charging circuit 102. Wherein; the multiplexing circuit 101 can include at least one multiplexing unit 1011, the multiplexing unit 1011 includes a first selection transistor (such as K11 and K21) and a second selection transistor (such as K12 and K22), wherein; the source and drain of the first selection transistor (such as K11 and K21) are connected between a data input line (such as source1 or source2) and a first data line (such as D1 or D4), the control electrode of the first selection transistor (such as K11 or K21) is connected with a first selection control line (such as DemuxR1); the source and drain of the second selection transistor (such as K12 or K22) are connected between the data input line and a second data line (such as D3 or D2), the control electrode of the second selection transistor (such as K12 or K22) is connected with a second selection control line (such as DemuxG1).

[0030] The error-proof charging circuit 102 comprises an inverting control unit 1021 corresponding to the multiplexing unit, and the inverting control unit 1021 comprises a first inverting control group and a second inverting control group. The first inverting control group comprises a first inverting transistor (such as TR1), and the second inverting control group comprises a second inverting transistor (such as TG1). The source and drain of the first inverting transistor (such as TR1) are connected between the second selection control line (such as DemuxG1) and a low-level power supply line VGL, and the control electrode of the first inverting transistor (such as TR1) is connected with the first selection control line (such as DemuxR1). The source and drain of the second inverting transistor (such as TG1) are connected between the first selection control line (such as DemuxR1) and the low-level power supply line VGL, and the control electrode of the second inverting transistor (such as TG1) is connected with the second selection control line (such as DemuxG1). The multiplexing unit 101 is configured to, in response to the first selection signal transmitted by the first selection control line DemuxR1 and the second selection signal transmitted by the second selection control line (such as DemuxG1) being in an effective level in sequence, make the first selection transistor (such as K11 or K21) and the second selection transistor (such as K12 or K22) conductive in sequence to connect the data input line with the first data line (such as D1 or D4) and the second data line (such as D3 or D2) in time sharing mode, and provide a data signal for a corresponding pixel unit. The inverting control unit 1021 is configured to, in response to the first selection signal being in the effective level, control the first inverting transistor (such as TR1) to conduct to pull or maintain the level of the control electrode of the second selection transistor (such as K12 and K22) to an ineffective level; and in response to the second selection signal being in the effective level, control the second inverting transistor (such as TG1) to conduct to pull or maintain the level of the control electrode of the first selection transistor (such as K11 and K21) to an ineffective level.

[0031] It should be noted that, referring to Figure 5 An exemplary structural schematic diagram of a display panel of mux1:2 provided by an embodiment of the present application is shown. In Figure 5 which shows two groups of multiplexing units, each group of multiplexing units is connected with one data input line (such as Source1 or Source2), and a plurality of data input lines are provided by one or more source driving chips. That is, the plurality of data input lines are contained in one or more source driving chips. Since one multiplexing unit can provide data signals for at least two data lines, the number of source driving chips can be saved in actual use. Each multiplexing unit comprises a first selection transistor and a second selection transistor, wherein, as shown in Figure 5As shown, the selection transistor K11 and the selection transistor K21 are the first selection transistors in different multiplexing units, and the selection transistor K12 and the selection transistor K22 are the second selection transistors in different multiplexing units.

[0032] wherein, Figure 5 The control timing of the display panel shown is as follows Figure 6 As shown, for the working principle of the multiplexing unit, for example, the multiplexing unit composed of the selection transistor K11 and the selection transistor K12 is sequentially turned on in response to the first selection signal transmitted by the selection control line Demux R1 (as the first selection control line) and the second selection signal transmitted by the selection control line Demux G1 (as the second selection control line) being at the effective level, so that the selection transistor K11 (as the first selection transistor) and the selection transistor K12 (as the second selection transistor) are turned on, respectively, to time-divisionally connect the data input line Source1 with the first data line D1 and the second data line D3, and provide the data signal for the corresponding pixel unit. The working principle of the multiplexing unit composed of the selection transistor K21 and the selection transistor K22 is similar, and will not be described here.

[0033] For the working principle of the error-proof charging circuit, as shown in Figure 6 As shown, the first inverting transistor (such as TR1) of the first inverting control group in the inverting control unit 1021 is turned on in response to the first selection signal being at the effective level, to pull or maintain the level of the control electrode of the second selection transistor (such as K12 and K22) at the ineffective level (as shown in the position pointed by the number 2 in the middle), to turn off the connection between the data input line (at this time, source1) corresponding to the second data line (at this time, D3) and stop providing the data signal for the second data line (at this time, D3), and turn off the connection between the data input line (at this time, source2) corresponding to the second data line (at this time, D2) and stop providing the data signal for the second data line (at this time, D2). The second inverting transistor (such as TG1) of the second inverting control group in the inverting control unit 1021 is turned on in response to the second selection signal being at the effective level, to pull or maintain the level of the control electrode of the first selection transistor (such as K11 and K21) at the ineffective level (as shown in the position pointed by the number 3 in the middle), to turn off the connection between the data input line (at this time, source1) corresponding to the first data line (at this time, D1) and stop providing the data signal for the first data line (at this time, D1), and turn off the connection between the data input line (at this time, source2) corresponding to the first data line (at this time, D4) and stop providing the data signal for the first data line (at this time, D4). Wherein, the power signal transmitted by the low potential power line VGL can be a direct current signal at the low level. Figure 6 ​​

[0034] The transistors in the multiplexing unit 101 and the transistors in the inverting control unit can be the same type of transistors. For example, the transistors in the multiplexing unit 101 and the transistors in the inverting control unit can be N-type thin film transistors, and the N-type thin film transistors can include high mobility oxide semiconductor material. The high mobility oxide semiconductor material can be indium gallium zinc oxide semiconductor material, indium zinc oxide semiconductor material, or indium gallium zinc tin oxide semiconductor material. The transistors used in the following embodiments are the same as those in Embodiment One, and will not be described again.

[0035] Embodiment Two Mux1:3 The embodiments of the present application also provide a display panel with mux1:3, which is specifically shown in Figure 7 and Figure 8 In this embodiment two, as shown in Figure 7As shown, the multiplexing unit 101 further comprises a third selection transistor (such as K13 or K23), the source and drain of the third selection transistor (such as K13 or K23) are connected between the data input line and a third data line (such as D3 or D6), the control electrode of the third selection transistor (such as K13 or K23) is connected with a third selection control line (such as DemuxB1); the first inverting control group further comprises a third inverting transistor (such as TR2), the source and drain of the third inverting transistor (such as TR2) are connected between the third selection control line (such as DemuxB1) and the low-level power supply line VGL, the control electrode of the third inverting transistor (such as TR2) is connected with the first selection control line (such as DemuxR1); the second inverting control group further comprises a fourth inverting transistor (such as TG2), the source and drain of the fourth inverting transistor (such as TG2) are connected between the third selection control line (such as DemuxB1) and the low-level power supply line VGL, the control electrode of the fourth inverting transistor (such as TG2) is connected with the second selection control line (such as DemuxG1); the inverting control unit 102 further comprises a third inverting control group, the third inverting control group comprises a fifth inverting transistor (such as TB1) and a sixth inverting transistor (such as TB2), wherein the source and drain of the fifth inverting transistor (such as TB1) are connected between the first selection control line Demux R1 and the low-level power supply line VGL, the control electrode of the fifth inverting transistor (such as TB1) is connected with the third selection control line (such as Demux B1); the source and drain of the sixth inverting transistor (such as TB2) are connected between the second selection control line (such as DemuxG1) and the low-level power supply line VGL, the control electrode of the sixth inverting transistor (such as TB2) is connected with the third selection control line. Figure 7 The control timing of the display panel shown can refer to Figure 8 As shown, and the positions pointed by the number 4, the number 5 and the number 6 are the schematic diagrams of the working of each inverting control transistor in the error-proof charging circuit, which pulls back or maintains the corresponding selection transistor at the invalid level, and the specific analysis can refer to the analysis of the foregoing Figure 6 , which will not be described here again.

[0036] Embodiment three Mux1:4 The embodiment of the present application further provides a display panel of mux1:4, which can refer to Figure 9 and Figure 10As shown in the figure. In this embodiment three, the multiplexing unit 101 also includes a fourth selection transistor (such as K14), the source and drain of the fourth selection transistor (such as K14) are connected between the data input line (such as source1) and the fourth data line (at this time D4), the control electrode of the fourth selection transistor (such as K14) is connected with the fourth selection control line (such as DemuxD); the first inversion control group further includes a seventh inversion transistor (such as TR3), the source and drain of the seventh inversion transistor (such as TR3) are connected between the fourth selection control line (such as DemuxD) and the low voltage power supply line VGL, the control electrode of the seventh inversion transistor (such as TR3) is connected with the first selection control line (such as DemuxR1); the second inversion control group further includes an eighth inversion transistor (such as TG3), the source and drain of the eighth inversion transistor (such as TG3) are connected between the fourth selection control line (such as DemuxD) and the low voltage power supply line VGL, the control electrode of the eighth inversion transistor (such as TG3) is connected with the second selection control line (such as DemuxG1); the third inversion control group further includes a ninth inversion transistor (such as TB3), the source and drain of the ninth inversion transistor (such as TB3) are connected between the fourth selection control line (such as DemuxD) and the low voltage power supply line VGL, the control electrode of the ninth inversion transistor (such as TB3) is connected with the third selection control line (such as DemuxB1); the inversion control unit 102 further includes: a fourth inversion control group; the fourth inversion control group includes a tenth inversion transistor (such as TD1), an eleventh inversion transistor (such as TD2) and a twelfth inversion transistor (such as TD3); wherein the control electrodes of the tenth inversion transistor (such as TD1), the eleventh inversion transistor (such as TD2) and the twelfth inversion transistor (such as TD3) are connected with the fourth selection control line (such as DemuxD), the source and drain of the tenth inversion transistor (such as TD1) are connected between the first selection control line (such as DemuxR1) and the low voltage power supply line VGL; the source and drain of the eleventh inversion transistor (such as TD2) are connected between the second selection control line (such as DemuxG1) and the low voltage power supply line VGL; the source and drain of the twelfth inversion transistor (such as TD3) are connected between the third selection control line (such as DemuxB1) and the low voltage power supply line VGL. Figure 9 The control timing of the display panel shown as Figure 10 As shown in the figure, the positions pointed by the digital 7, the digital 8, the digital 9 and the digital 10 are the schematic of the corresponding selection transistor being pulled back or maintained at the invalid level by each inversion control transistor in the error-proof charging circuit during working, and the specific analysis can be referred to the foregoing description of the embodiment one.Figure 6 The analysis is not repeated here.

[0037] In some embodiments, the selection control lines connected with one of the multiplexing units 101 can define a selection control line group; wherein each of the at least one multiplexing unit 101 is connected with the selection control lines in the same selection control line group, and the error-proof charging circuit 102 includes one inverting control unit. For example, as shown in Figure 5 The multiplexing unit composed of the selection transistor K11 and the selection transistor K12 and the multiplexing unit composed of the selection transistor K21 and the selection transistor K22 are connected with the selection control lines in the same selection control group, and the error-proof charging circuit 102 includes one inverting control unit 1021.

[0038] In other embodiments, the at least one multiplexing unit is connected with the selection control lines in multiple different selection control line groups, and the error-proof charging circuit includes multiple inverting control units, and the number of the inverting control units is equal to the number of the selection control line groups. For example, the fourth embodiment and the fifth embodiment.

[0039] For the fourth embodiment and the fifth embodiment, the details are as follows: Embodiment Four Mux2:4 The present application also provides a display panel with mux2:4, which is specifically shown in Figure 11 In the fourth embodiment, the multiplexing circuit 101 can include a multiplexing unit (referred to as multiplexing unit 1) composed of the selection transistor K11 and the selection transistor K12 and a multiplexing unit (referred to as multiplexing unit 2) composed of the selection transistor K21 and the selection transistor K22, wherein the selection control line groups connected with the multiplexing unit 1 and the multiplexing unit 2 are different: the selection transistor K11 and the selection transistor K12 in the multiplexing unit 1 are connected with the selection control line DemuxR1 and the selection control line DemuxG1 (referred to as selection control line group 1), and the selection transistor K21 and the selection transistor K22 in the multiplexing unit 2 are connected with the selection control line DemuxR2 and the selection control line DemuxG2 (referred to as selection control line group 2). At this time, the error-proof charging circuit 102 includes two inverting control units 1021, as shown in Figure 11As shown, the inversion control unit 1021 includes: an inversion control transistor TR1 of the first inversion control group and an inversion control transistor TG1 of the second inversion control group. The inversion control unit 1021-2 includes: an inversion control transistor TR2 of the first inversion control group and an inversion control transistor TG2 of the second inversion control group. That is, the number of the selection control line groups is the same as the number of the inversion control units. The control timing of the embodiment four is similar to the control timing of the embodiment one, which can be understood by referring to the embodiment one.

[0040] Embodiment five Mux2:6 The embodiment of the present application also provides a display panel of mux2:6, which can be specifically referred to Figure 12 As shown, the multiplexing circuit 101 can include a multiplexing unit (referred to as multiplexing unit 1) composed of a selection transistor K11, a selection transistor K12 and a selection transistor K13, and a multiplexing unit (referred to as multiplexing unit 2) composed of a selection transistor K21, a selection transistor K22 and a selection transistor K23. The selection control line groups connected by the multiplexing unit 1 and the multiplexing unit 2 are different: the selection transistor K11, the selection transistor K12 and the selection transistor K23 in the multiplexing unit 1 are connected with the selection control line DemuxR1, the selection control line DemuxG1 and the selection control line DemuxB1 (referred to as selection control line group 1) respectively, while the selection transistor K21, the selection transistor K22 and the selection transistor K23 in the multiplexing unit 2 are connected with the selection control line DemuxR2, the selection control line DemuxG2 and the selection control line DemuxB2 (referred to as selection control line group 2) respectively. At this time, the error-proof charging circuit 102 includes two inversion control units 1021, as shown in Figure 11 As shown, the inversion control unit 1021 includes: an inversion control transistor TR1 of the first inversion control group and an inversion control transistor TG1 of the second inversion control group. The inversion control unit 1021-2 includes: an inversion control transistor TR2 of the first inversion control group and an inversion control transistor TG2 of the second inversion control group. That is, the number of the selection control line groups is the same as the number of the inversion control units. The control timing of the embodiment four is similar to the control timing of the embodiment one, which can be understood by referring to the embodiment one.

[0041] It should be noted that the multiplexing circuit provided by the embodiments of the present application is not limited to the above-mentioned embodiments, and can also be applied to higher division multiplexing circuits.

[0042] The display panel provided by the embodiments of the present application is described in detail above, and the principles and implementation manners of the present application are described by using specific examples. The above description of the embodiments is only used to help understand the technical solutions of the present application and the core ideas thereof. It should be understood by those skilled in the art that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features thereof can be replaced by equivalents; and the modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized by, The display panel comprises a display area and a non-display area, the display area comprises a plurality of pixel columns, each pixel column is connected with at least one data line and comprises a plurality of pixel units, and the non-display area comprises a multiplexing circuit and an error prevention charging circuit. The multiplexing circuit comprises at least one multiplexing unit, and the multiplexing unit comprises a first selection transistor and a second selection transistor. The source and drain of the first selection transistor are connected between a data input line and a first data line, the control electrode of the first selection transistor is connected with a first selection control line, the source and drain of the second selection transistor are connected between the data input line and a second data line, and the control electrode of the second selection transistor is connected with a second selection control line. The error prevention charging circuit comprises an inverse control unit corresponding to the multiplexing unit, the inverse control unit comprises a first inverse control group and a second inverse control group, the first inverse control group comprises a first inverse transistor, the second inverse control group comprises a second inverse transistor, the source and drain of the first inverse transistor are connected between the second selection control line and a low-level power supply line, the control electrode of the first inverse transistor is connected with the first selection control line, the source and drain of the second inverse transistor are connected between the first selection control line and the low-level power supply line, and the control electrode of the second inverse transistor is connected with the second selection control line. The multiplexing unit is used for making the first selection transistor and the second selection transistor conductive in sequence to connect the data input line with the first data line and the second data line in time sharing mode to provide a data signal for the corresponding pixel unit in response to the first selection signal transmitted by the first selection control line and the second selection signal transmitted by the second selection control line being in an effective level in sequence. The inverse control unit is used for controlling the first inverse transistor to conductive in response to the first selection signal being in the effective level to pull or maintain the level of the control electrode of the second selection transistor to an ineffective level, and controlling the second inverse transistor to conductive in response to the second selection signal being in the effective level to pull or maintain the level of the control electrode of the first selection transistor to the ineffective level. The multiplexing unit further comprises a third selection transistor, the source and drain of the third selection transistor are connected between the data input line and a third data line, and the control electrode of the third selection transistor is connected with a third selection control line.

2. The display panel of claim 1, wherein, The first inverse control group further comprises a third inverse transistor, the source and drain of the third inverse transistor are connected between the third selection control line and the low-level power supply line, and the control electrode of the third inverse transistor is connected with the first selection control line. The second inverse control group further comprises a fourth inverse transistor, the source and drain of the fourth inverse transistor are connected between the third selection control line and the low-level power supply line, and the control electrode of the fourth inverse transistor is connected with the second selection control line. ​ The inverting control unit further comprises a third inverting control group, the third inverting control group comprises a fifth inverting transistor and a sixth inverting transistor, wherein the source and drain of the fifth inverting transistor are connected between the first selection control line and the low-level power supply line, and the control electrode of the fifth inverting transistor is connected with the third selection control line; the source and drain of the sixth inverting transistor are connected between the second selection control line and the low-level power supply line, and the control electrode of the sixth inverting transistor is connected with the third selection control line.

3. The display panel of claim 2, wherein, The multiplexing unit further comprises a fourth selection transistor, the source and drain of the fourth selection transistor are connected between the data input line and a fourth data line, and the control electrode of the fourth selection transistor is connected with a fourth selection control line; The first inverting control group further comprises a seventh inverting transistor, the source and drain of the seventh inverting transistor are connected between the fourth selection control line and the low-level power supply line, and the control electrode of the seventh inverting transistor is connected with the first selection control line; The second inverting control group further comprises an eighth inverting transistor, the source and drain of the eighth inverting transistor are connected between the fourth selection control line and the low-level power supply line, and the control electrode of the eighth inverting transistor is connected with the second selection control line; The third inverting control group further comprises a ninth inverting transistor, the source and drain of the ninth inverting transistor are connected between the fourth selection control line and the low-level power supply line, and the control electrode of the ninth inverting transistor is connected with the third selection control line; The inverting control unit further comprises a fourth inverting control group, the fourth inverting control group comprises a tenth inverting transistor, an eleventh inverting transistor and a twelfth inverting transistor, wherein the control electrodes of the tenth, eleventh and twelfth inverting transistors are connected with the fourth selection control line, the source and drain of the tenth inverting transistor are connected between the first selection control line and the low-level power supply line, the source and drain of the eleventh inverting transistor are connected between the second selection control line and the low-level power supply line, and the source and drain of the twelfth inverting transistor are connected between the third selection control line and the low-level power supply line.

4. The display panel of any one of claims 1 to 3, wherein, When the at least one multiplexing unit comprises a plurality of multiplexing units, the plurality of multiplexing units are respectively connected with one data input line, and the plurality of data input lines are provided by one or more source driving chips.

5. The display panel of any one of claims 1 to 3, wherein, The selection control lines connected with one multiplexing unit are defined as one selection control line group. Each multiplexing unit in the at least one multiplexing unit is connected with the selection control lines in the same selection control line group, and the error prevention charging circuit comprises one inverting control unit.

6. The display panel of claim 5, wherein, The at least one multiplexing unit is connected with the selection control lines in a plurality of different selection control line groups, and the error prevention charging circuit comprises a plurality of inverting control units, the number of the inverting control units is equal to the number of the selection control line groups.

7. The display panel of any one of claims 1 to 3, wherein, The transistor in the multiplexing unit and the transistor in the inverting control unit are the same type of transistor.

8. The display panel of claim 7, wherein, The transistor in the multiplexing unit and the transistor in the inverting control unit are N-type thin film transistors respectively; the N-type thin film transistor comprises a high mobility oxide semiconductor material; the high mobility oxide semiconductor material is an indium gallium zinc oxide semiconductor material, an indium zinc oxide semiconductor material or an indium gallium zinc tin oxide semiconductor material.

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