Display substrate and display device

Abstract

The invention discloses a display substrate and a display device. The display substrate comprises a first display area and a second display area, the first display area is located on the periphery of the second display area, the first display area comprises a first light-emitting element, a first pixel circuit, a second pixel circuit and a third pixel circuit, and the first pixel circuit is connected with the first light-emitting element; the second display area comprises a second light-emitting element, the second pixel circuit is connected with the second light-emitting element, and the third pixel circuit is a dummy pixel circuit. The display substrate further comprises a first data line and a second data line, the first data line is configured to be connected with the first pixel circuit, and the second data line is configured to be at least connected with the second pixel circuit. In the direction perpendicular to the substrate, at least part of the third pixel circuit overlapped with the second data line is insulated from the second data line. Load is reduced by reducing the number of the pixel circuits connected with the second data lines, and the phenomenon that dark vertical stripes appear in the second display area can be relieved.

Description

[0001] This application is a divisional application of Chinese Patent Application No. 202180001035.5 entitled "Display Substrate and Display Device", which entered the Chinese national phase on May 6, 2021. Chinese Patent Application No. 202180001035.5 is a patent application that entered the Chinese national phase on April 30, 2021, under PCT Application No. PCT / CN2021 / 091475. Technical Field

[0002] At least one embodiment of this disclosure relates to a display substrate and a display device. Background Technology

[0003] As people increasingly pursue better visual effects in display products, narrow bezels and even full-screen displays have become a new trend in the development of OLED display products. The front-facing camera is key to the design of a full-screen display. To achieve a higher screen-to-body ratio, display products with notch screens, punch-hole screens, and other designs have emerged. These full-screen forms increase the screen-to-body ratio by sacrificing the phone's appearance. Therefore, an under-display camera design can both maintain the phone's appearance and improve the screen-to-body ratio. Summary of the Invention

[0004] At least one embodiment of this disclosure provides a display substrate and a display device.

[0005] At least one embodiment of this disclosure provides a display substrate, including a substrate and a plurality of data lines located on the substrate. The display substrate includes a first display area and a second display area, the first display area being located around the periphery of the second display area. The first display area includes a plurality of first light-emitting elements, a plurality of first pixel circuits, a plurality of second pixel circuits, and a plurality of third pixel circuits. The plurality of first pixel circuits are connected one-to-one with the plurality of first light-emitting elements. The second display area includes a plurality of second light-emitting elements, the plurality of second pixel circuits being connected one-to-one with the plurality of second light-emitting elements, and the third pixel circuits are dummy pixel circuits. The plurality of data lines do not pass through the second display area, wherein the plurality of data lines include a plurality of first data lines and a plurality of second data lines. Each first data line is configured to be connected to a first pixel circuit, and each second data line is configured to be at least connected to a second pixel circuit. Along a direction perpendicular to the substrate, portions of the plurality of third pixel circuits overlap with the plurality of second data lines, and at least a portion of the third pixel circuits overlapping with the second data lines is insulated from the second data lines.

[0006] For example, according to an embodiment of this disclosure, each of the third pixel circuits overlapping the second data line is insulated from the second data line.

[0007] For example, according to an embodiment of this disclosure, each of the first data lines extends along a first direction, and the first data lines whose extensions do not pass through the second display area are configured to transmit data signals to M first pixel circuits, and each of the second data lines is configured to transmit signals to N pixel circuits, where M ≥ N, and the N pixel circuits include at least the second pixel circuits.

[0008] For example, according to an embodiment of this disclosure, the second data line includes a first sub-data line and a second sub-data line extending along the first direction, and an adapter cable connecting the first sub-data line and the second sub-data line; the first sub-data line, the second sub-data line and the first data line are disposed on the same layer, the first sub-data line is configured to be connected to the first pixel circuit, and the second sub-data line is configured to be connected to the second pixel circuit.

[0009] For example, according to an embodiment of this disclosure, the display substrate further includes: a plurality of traces extending along the first direction and not passing through the second display area. The plurality of traces are disposed on the same layer as the plurality of first data lines, and at least one data line is disposed between two adjacent traces; along a direction perpendicular to the substrate, each trace overlaps only with the third pixel circuit.

[0010] For example, according to an embodiment of this disclosure, the plurality of traces includes a plurality of first traces, the number of which is the same as the number of second sub-data lines. At least a portion of one first trace and one second sub-data line are substantially on the same straight line and are spaced apart. A transition area includes the plurality of transition lines. The transition area includes a first transition area located on one side of the second display area in the first direction. The transition lines in the first transition area extend along a second direction intersecting the first direction and are located on a different layer from the first data lines. The gap is located on the side of the first transition area away from the second display area. The first traces and at least a portion of the third pixel circuit overlap.

[0011] For example, according to embodiments of this disclosure, the first trace and the second sub-data line are configured to transmit different electrical signals.

[0012] For example, according to an embodiment of this disclosure, the first trace is configured to transmit a power supply voltage signal.

[0013] For example, according to an embodiment of this disclosure, the transition area further includes a second transition area located on the other side of the second display area in the first direction, the second transition area being located in a non-display area outside the first display area and the second display area.

[0014] For example, according to an embodiment of the present disclosure, each of the adapter wires in the second adapter area includes a first adapter wire and a second adapter wire that are connected to each other and disposed on different layers, wherein one of the first adapter wire and the second adapter wire is connected to the second sub-data line and is located on a different layer from the second sub-data line.

[0015] For example, according to an embodiment of this disclosure, in each of the second data lines, two first sub-data lines are connected to the same second sub-data line, the two first sub-data lines are respectively located on both sides of the second display area in the first direction, and at least a portion of the two first sub-data lines are substantially on the same straight line.

[0016] For example, according to an embodiment of this disclosure, a second sub-data line extends along the first direction and overlaps with the orthographic projection of a said trace onto a straight line extending along the first direction.

[0017] For example, according to an embodiment of this disclosure, the adapter cable is located in a non-display area outside the first display area and the second display area.

[0018] For example, according to embodiments of this disclosure, each of the adapter cables includes a first adapter cable and a second adapter cable that are connected to each other and disposed on different layers, wherein one of the first adapter cable and the second adapter cable is connected to the second sub-data line and is located on a different layer from the second sub-data line.

[0019] For example, according to an embodiment of this disclosure, the length of the second sub-data line is not less than the length of the first data line whose extension does not pass through the second display area among the plurality of first data lines.

[0020] For example, according to an embodiment of this disclosure, the first sub-data line and a first data line are respectively located on both sides of the second display area in the first direction and are substantially on the same straight line, and each of the first sub-data lines and the first data line substantially on the same straight line is configured to transmit the same data signal.

[0021] For example, according to an embodiment of this disclosure, the other of the first adapter cable and the second adapter cable extends along a second direction intersecting the first direction and is located on the same layer as the second sub-data cable.

[0022] For example, according to an embodiment of this disclosure, the second data line extends along the first direction, and the second data line is configured to connect only to the second pixel circuit.

[0023] For example, according to an embodiment of this disclosure, the first display area includes a plurality of pixel circuits arranged in an array along the first direction and the second direction, and the plurality of second pixel circuits are located on both sides of the second display area in the second direction.

[0024] For example, according to an embodiment of this disclosure, the pixel circuit column containing the second pixel circuit arranged along the first direction includes the third pixel circuit, and the third pixel circuit in the pixel circuit column overlaps with the second data line.

[0025] For example, according to an embodiment of the present disclosure, the plurality of third pixel circuits include a plurality of third pixel circuit columns extending along the first direction and arranged along the second direction, at least a portion of the plurality of third pixel circuit columns being located on at least one side of the second display area in the first direction.

[0026] For example, according to embodiments of this disclosure, the plurality of third pixel circuit columns further include portions located on both sides of the second display area in the second direction.

[0027] For example, according to an embodiment of this disclosure, the pixel circuit includes a data writing transistor, the data writing transistor including a first electrode, a second electrode, and a gate, an insulating layer is disposed between the film layer where the first electrode of the data writing transistor is located and the film layer where the data line is located, the first electrode of the data writing transistor in the first pixel circuit and the second pixel circuit is connected to the data line through a via located in the insulating layer, and the first electrode of the data writing transistor in at least a portion of the third pixel circuit overlapping with the second data line is insulated from the second data line by the insulating layer.

[0028] At least one embodiment of this disclosure provides a display substrate, including a substrate, a plurality of pixel circuits located on the substrate, and a plurality of data lines. The plurality of pixel circuits include a plurality of first-type pixel circuits and a plurality of second-type pixel circuits, wherein the first-type pixel circuits are electrically connected to the data lines, and the second-type pixel circuits are insulated from the data lines.

[0029] For example, according to an embodiment of this disclosure, the first type of pixel circuit and the data line overlapping therewith are electrically connected, and the second type of pixel circuit and the data line overlapping therewith are insulated.

[0030] For example, according to an embodiment of the present disclosure, at least a portion of the first type of pixel circuit is configured to drive a light-emitting element connected thereto to emit light, and the second type of pixel circuit is a first dummy pixel circuit.

[0031] For example, according to an embodiment of this disclosure, the first type of pixel circuit includes a first pixel circuit and a second pixel circuit, wherein the first pixel circuit and the light-emitting element connected thereto overlap in a direction perpendicular to the substrate, and the second pixel circuit and the light-emitting element connected thereto do not overlap in a direction perpendicular to the substrate; the first type of pixel circuit further includes a second dummy pixel circuit.

[0032] For example, according to an embodiment of this disclosure, the second type of pixel circuit and a portion of the first type of pixel circuit are located in the same column.

[0033] For example, according to an embodiment of this disclosure, the second type of pixel circuit and the second pixel circuit are located in the same column.

[0034] For example, according to an embodiment of this disclosure, the pixel circuit includes a data writing transistor, the data writing transistor including a first electrode, a second electrode, and a gate, an insulating layer is disposed between the film layer where the first electrode of the data writing transistor is located and the film layer where the data line is located, the first electrode of the data writing transistor of the first type of pixel circuit is connected to the corresponding data line through a via located in the insulating layer; the first electrode of the data writing transistor of the second type of pixel circuit and the data line are insulated by the insulating layer.

[0035] This disclosure provides at least one embodiment of a display device, including any of the above-described display substrates. Attached Figure Description

[0036] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0037] Figure 1 This is a schematic diagram of a partial planar structure of a display substrate in a display device with an under-display camera;

[0038] Figure 2 This is a partial planar structure schematic diagram of a display substrate provided according to an example of an embodiment of the present disclosure;

[0039] Figure 3 for Figure 2 A partially enlarged structural schematic diagram of the display substrate shown;

[0040] Figure 4 This is a partial planar structure schematic diagram of a display substrate provided according to another example of an embodiment of the present disclosure;

[0041] Figure 5 for Figure 4 A partially enlarged structural schematic diagram of the display substrate shown;

[0042] Figure 6 This is a partial planar structure schematic diagram of a display substrate provided according to another example of an embodiment of the present disclosure;

[0043] Figure 7 for Figures 2 to 6 The diagram shown is an equivalent diagram of the pixel circuits in the display substrate.

[0044] Figure 8 This is a partial planar structural schematic diagram of the stacked structure of the active semiconductor layer, the first conductive layer, and the source / drain metal layer of the second pixel circuit provided according to an embodiment of the present disclosure;

[0045] Figure 9 This is a partial planar structural schematic diagram of the stacked structure of the active semiconductor layer, the first conductive layer, the source / drain metal layer and the second conductive layer of the second pixel circuit provided according to an embodiment of the present disclosure.

[0046] Figure 10 for Figure 8 A schematic diagram of the cross-sectional structure of the pixel circuit shown, cut along AA'.

[0047] Figure 11 This is a partial planar structural schematic diagram of the stacked structure of the active semiconductor layer, the first conductive layer, and the source / drain metal layer of the third pixel circuit provided according to an embodiment of the present disclosure.

[0048] Figure 12 for Figure 11 A schematic diagram of the cross-sectional structure of the pixel circuit along BB' shown;

[0049] Figure 13 for Figure 2 A schematic diagram of the display area and a second data line on the display substrate shown;

[0050] Figure 14 for Figure 13 An enlarged view of region E1 shown;

[0051] Figure 15 for Figure 13 An enlarged view of region E2 shown;

[0052] Figure 16 for Figure 13 An enlarged view of region E3 shown;

[0053] Figure 17 for Figure 13 An enlarged view of region E4 shown;

[0054] Figure 18 For including Figure 16 The enlarged view shows a portion of the structure; and

[0055] Figure 19 For including Figure 17 The enlarged view shown is a partial view of the structure. Detailed Implementation

[0056] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the described embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0057] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects.

[0058] An under-display camera (FDC) refers to a front-facing camera located below the screen without affecting the screen's display functionality. When the front-facing camera is not in use, the screen above the camera can still display images normally. Visually, an under-display camera has no camera hole, truly achieving a full-screen display effect.

[0059] Figure 1 This is a schematic diagram of a partial planar structure of a display substrate in a display device with an under-display camera. Figure 1 As shown, the display substrate includes a substrate 10, and includes a first display area 11 for normal display and a second display area 12 for mounting a camera. The first display area 11 may be located on at least one side of the second display area 12. For example, the first display area 11 surrounds the second display area 12, the second display area 12 is a light-transmitting display area, and the first display area 11 is an opaque display area used only for display.

[0060] Figure 1The first display area 11 in the shown display substrate includes a first light-emitting element and a first pixel circuit that drives the first light-emitting element to emit light. The second display area 12 includes a second light-emitting element. The second pixel circuit that drives the second light-emitting element in the second display area 12 to emit light is located in the first display area to improve the light transmittance of the second display area 12. That is, the light transmittance of the second display area 12 is improved by separating the light-emitting element and the pixel circuit. For example, multiple second pixel circuits can be distributed at intervals between multiple first pixel circuits. For example, the second light-emitting element can be connected to the second pixel circuit through transparent traces. For example, the second display area 12 can be an aperture area in the entire display area without pixel circuits. For example, the density of the light-emitting elements in the first display area 11 and the second display area 12 can be the same or different.

[0061] like Figure 1 As shown, the display substrate includes multiple data lines 20 located on the substrate 10. In a display device with an under-display camera, the multiple data lines can be arranged in two ways: winding within the second display area and winding outside the second display area. Due to the limitation of the space size of the second display area, Figure 1 The display substrate shown is designed according to a fully compressed pixel circuit scheme, using a data line winding method outside the second display area 12. In this display substrate, the first display area includes multiple first pixel circuit columns and multiple second pixel circuit columns. The second pixel circuit column containing the second pixel circuits includes not only the second pixel circuits but also dummy pixel circuits that are not connected to any light-emitting element. The first display area also includes multiple dummy pixel circuit columns, with at least one first pixel circuit column positioned between two adjacent dummy pixel circuit columns. The aforementioned fully compressed pixel circuit refers to compressing multiple pixel circuit columns in the overall display area in the X direction (e.g., reducing the size of each pixel circuit along the X direction) to increase the number of pixel circuits arranged along the X direction without reducing the pixel density of the overall display area (including the first and second display areas). The newly added pixel circuit columns include second pixel circuit columns for connection to the second light-emitting element of the second display area, and dummy pixel circuit columns that are not connected to any light-emitting element.

[0062] like Figure 1As shown, the multiple data lines 20 include a data line 21 connected only to the first pixel circuit and a data line 22 connected to at least the second pixel circuit. The data line 21 extends along the Y direction. For example, each data line 20 can be driven in a single path, with some data lines 20 disconnected at the edge of the second display area 12. That is, some data lines 20 include two data lines 22-1 located on the upper and lower sides of the second display area 12. Both data lines 22-1 are connected to the first pixel circuit, and these two data lines 22-1 can be electrically connected via an adapter cable 22-3 and a data line 22-2 connected to the second pixel circuit, so that the two data lines 22-1 transmit the same data signal. Thus, the data line 22, for example, includes five parts, which are, in sequence, data line 22-1, adapter cable 22-3, data line 22-2, adapter cable 22-3, and data line 22-1. The number of first pixel circuits connected to the two data lines 22-1 are a1 and a3 respectively, and the number of second pixel circuits and dummy pixel circuits connected to the data line 22-2 are a2 and (a4+a5) respectively. That is, the number of pixel circuits connected to the data line 22 is b, where b = a1+a2+a3+a4+a5. a1 to a5 represent the number of pixel circuits connected to the data lines at the corresponding positions in the figure.

[0063] In their research, the inventors of this application discovered that the extension line of data line 21 does not pass through the second display area 12, and the number of pixel circuits connected to data line 21 is a (a = a1 + a2 + a3). To reduce the data loading of data line 22-2 connected to the second pixel circuit, the metal wire containing data line 22-2 is broken into two parts on the side of adapter 22-3 away from the second display area 12. This metal wire includes data line 22-2 and trace 30, with a gap 23 between data line 22-2 and trace 30 to achieve insulation between them. Trace 30 is connected to a dummy pixel circuit. To avoid the floating of trace 30, trace 30 can be connected to a power supply voltage signal (VDD). However, the number b of pixel circuits connected to the aforementioned data line 22 is greater than the number a of pixel circuits connected to data line 21, which will cause the load on data line 22 to be too large. For example, when all data lines simultaneously input the same signal (ET light), dark vertical stripes are likely to appear at the second display area, affecting the display quality of the display device.

[0064] Embodiments of this disclosure provide a display substrate and a display device. The display substrate includes a substrate and a plurality of data lines located on the substrate. The display substrate includes a first display area and a second display area, the first display area being located around the second display area. The first display area includes a plurality of first light-emitting elements, a plurality of first pixel circuits, a plurality of second pixel circuits, and a plurality of third pixel circuits. The plurality of first pixel circuits are connected to the plurality of first light-emitting elements in a one-to-one correspondence. The second display area includes a plurality of second light-emitting elements, the plurality of second pixel circuits are connected to the plurality of second light-emitting elements in a one-to-one correspondence, and the third pixel circuits are dummy pixel circuits. The plurality of data lines do not pass through the second display area. The plurality of data lines include a plurality of first data lines and a plurality of second data lines. Each first data line is configured to be connected only to a first pixel circuit, and each second data line is configured to be connected to at least a second pixel circuit. Along a direction perpendicular to the substrate, portions of the plurality of third pixel circuits overlap with the plurality of second data lines, and at least a portion of the third pixel circuits overlapping with the second data lines are insulated from the second data lines. In the display substrate provided in this embodiment, by setting at least a portion of the third pixel circuit that overlaps with the second data line to be unconnected to the second data line, the number of pixel circuits connected to the second data line can be reduced to lower the load, thereby alleviating the phenomenon of dark vertical stripes appearing in the second display area and improving the display quality of the display substrate.

[0065] The display substrate and display device provided in the embodiments of this disclosure are described below with reference to the accompanying drawings.

[0066] Figure 2 This is a partial planar structure schematic diagram of a display substrate provided according to an example of an embodiment of the present disclosure. Figure 3 for Figure 2 The diagram shows a partially enlarged structural schematic of the display substrate. Figure 2 and Figure 3 As shown, the display substrate includes a substrate 100 and multiple data lines 200 located on the substrate 100. The display substrate includes a first display area 111 and a second display area 112, with the first display area 111 located around the second display area 112. For example, the first display area 111 surrounds the second display area 112, meaning the second display area 112 can be surrounded by the first display area 111. Of course, the embodiments disclosed herein are not limited to this; the second display area 112 can also be disposed in other locations. The location of the second display area 112 can be determined as needed. For example, the second display area 112 can be located at the top center of the overall display area (including the first and second display areas), or at the upper left or upper right corner of the overall display area. Figure 2The diagram schematically shows that the first display area 111 is rectangular and the second display area 112 is circular, but it is not limited to these. The shape of the second display area 112 can also be a regular shape or an irregular shape such as a rectangle or an ellipse, and the shape of the first display area 111 can also be a regular shape or an irregular shape such as a circle or a hexagon.

[0067] like Figure 2 and Figure 3 As shown, the first display area 110 includes multiple first light-emitting elements 111, multiple first pixel circuits 112, multiple second pixel circuits 113, and multiple third pixel circuits 114. Each of the multiple first pixel circuits 112 is connected to one of the multiple first light-emitting elements 111 to drive the multiple first light-emitting elements 111 to emit light. The second display area 120 includes multiple second light-emitting elements 121, and each of the multiple second pixel circuits 113 is connected to one of the multiple second light-emitting elements 121 to drive the multiple second light-emitting elements 121 to emit light. The third pixel circuits 114 are dummy pixel circuits. The aforementioned dummy pixel circuits refer to pixel circuits that are not connected to any light-emitting element. The second display area only has transparent second light-emitting elements and no non-transparent pixel circuits. This second display area can serve as an under-screen camera area, possessing both high light transmittance for camera functionality and the ability to emit light through connection with pixel circuits in other areas, without affecting the screen's display function.

[0068] For example, along a direction perpendicular to the substrate 100, at least a portion of the first pixel circuit 112 and the first light-emitting element 111 connected thereto overlap; the second pixel circuit 113 and the second light-emitting element 121 connected thereto do not overlap. Alternatively, for example, along a direction perpendicular to the substrate 100, the average distance between the first pixel circuit 112 and the first light-emitting element 111 connected thereto is less than the average distance between the second pixel circuit 113 and the second light-emitting element 121 connected thereto. The average distance is, for example, the average distance between the driving transistors of a row of pixel circuits and the center of the light-emitting element connected thereto. For example, the second pixel circuit 113 can be connected to the corresponding second light-emitting element 121 via a transparent trace 400; neither the second pixel circuit 113 nor the third pixel circuit 114 overlaps with the light-emitting elements. For example, the second pixel circuit 113 may only be located on both sides of the second display area 120 along the X direction, and the first pixel circuit 112 includes portions located on both sides of the second display area 120 along the X direction and portions located on both sides of the second display area 120 along the Y direction.

[0069] For example, the pixel circuit column containing the second pixel circuit 113 arranged along the first direction includes a third pixel circuit 114, and the third pixel circuit 114 in this pixel circuit column overlaps with or is electrically connected to the second data line 220. For example, the pixel circuit column containing the second pixel circuit 113 (e.g., multiple pixel circuits arranged along the Y direction constitute one pixel circuit column) includes the third pixel circuit 114 in addition to the second pixel circuit 113. For example, to ensure the uniformity of the pixel circuits, the number of pixel circuits included in the pixel circuit column containing the second pixel circuit 113 can be approximately the same as the number of pixel circuits included in the pixel circuit column containing the first pixel circuit 112 (excluding pixel circuit columns whose data lines pass through the second display area 120). However, the pixel circuit column containing the first pixel circuit 112 only includes the first pixel circuit 112, while the pixel circuit column containing the second pixel circuit 113 includes both the second pixel circuit 113 and the third pixel circuit 114. For example, at least one first pixel circuit column can be provided between two adjacent pixel circuit columns containing second pixel circuits.

[0070] For example, the first display area 110 includes a plurality of pixel circuits arranged in an array along a first direction and a second direction, and a plurality of second pixel circuits 113 are located on both sides of the second display area 120 in the second direction.

[0071] For example, the display substrate also includes multiple third pixel circuit columns ( Figure 2 and Figure 3 (Not shown, each third pixel circuit column includes only third pixel circuits), at least one first pixel circuit column is disposed between adjacent third pixel circuit columns. For example, the third pixel circuit column includes portions distributed on both sides of the second display area 120 along the X direction, and the third pixel circuit column may also be distributed on another portion of the second display area 120 along the Y direction.

[0072] like Figure 2 and Figure 3 As shown, the multiple data lines 200 do not pass through the second display area 120 to prevent affecting the light transmittance of the second display area 120. In display devices with under-display cameras, the multiple data lines can be arranged in two ways: winding within the second display area and winding outside the second display area. Due to the limitation of the space size of the second display area, the display substrate provided in this embodiment is designed according to a fully compressed pixel circuit scheme, and the data lines are arranged by winding outside the second display area 120. The multiple data lines 200 include multiple first data lines 210 and multiple second data lines 220. Each first data line 210 is configured to be connected only to the first pixel circuit 112, and each second data line 220 is configured to be connected to at least the second pixel circuit 113.

[0073] For example, such as Figure 2 and Figure 3 As shown, among the multiple second data lines 220 located on both sides of the second display area 120 in the X direction, multiple first data lines 210 can be set between adjacent second data lines 220. For example, 2 to 10 lines ( Figure 3 (Two first data lines are schematically shown.) This embodiment of the present disclosure is not limited in this respect and can be configured according to the actual product needs. For example, multiple second data lines 220 located on both sides of the second display area 120 in the X direction can be evenly distributed, but are not limited thereto. For example, depending on the wiring requirements, the second data lines can be non-uniformly distributed, and the number of first data lines arranged between adjacent second data lines can be different.

[0074] like Figure 2 and Figure 3 As shown, along a direction perpendicular to the substrate 100, portions of a plurality of third pixel circuits 114 overlap with a plurality of second data lines 220 (for example, third pixel circuits that overlap with and are connected to the second data lines can be electrically connected through vias in the vertical substrate). At least a portion of the third pixel circuits 114 that overlap with the second data lines 220 are insulated from the second data lines 220 (for example, compared to normal pixel circuits, at least a portion of the vias used for electrical connection with the data lines in the pixel circuits are not provided with vias, but are isolated by an insulating layer, so that the pixel circuits cannot be electrically connected to the data lines to realize the function of the pixel circuits). Figure 3 If a black dot is set between the data line 200 and the pixel circuit that overlaps with it, it indicates that the two are connected. If no black dot is set between the data line 200 and the pixel circuit that overlaps with it, it indicates that the two are insulated and that they are not connected.

[0075] In the display substrate provided in this embodiment, by configuring at least a portion of the third pixel circuit overlapping with the second data line to be insulated from the second data line, the number of pixel circuits connected to the second data line can be reduced to lower the load. Therefore, when all data lines simultaneously input the same signal (ET lamp activation), the phenomenon of dark vertical stripes appearing in the second display area can be alleviated, improving the display quality of the display substrate. Furthermore, reducing the number of pixel circuits connected to the second data line to lower the load also reduces the burden on the driver IC when each data line inputs a corresponding data signal (module lamp activation).

[0076] For example, such as Figure 2 and Figure 3 As shown, each third pixel circuit 114 overlapping with the second data line 220 is insulated from the second data line 220. That is, all third pixel circuits 114 overlapping with the second data line 220 are not connected to the second data line 220. Therefore, the pixel circuits connected to the second data line 220 are all configured to drive the light-emitting element to emit light, thereby greatly reducing the number of pixel circuits connected to the second data line and thus reducing the load on the second data line.

[0077] For example, such as Figure 2 and Figure 3 As shown, each first data line 210 extends along a first direction, for example, the first direction is schematically shown as the Y direction, but it is not limited to this and can also be the X direction shown in the figure. The first data line 210 whose extension does not pass through the second display area 120 is configured to transmit data signals to M first pixel circuits 112. For example, the first data line 210 can pass through the first display area 110. Each second data line 220 is configured to transmit signals to N pixel circuits, where M ≥ N, and the N pixel circuits include at least second pixel circuits. Here, the N pixel circuits refer to the pixel circuits connected to the second data line 220, including the second pixel circuits connected to the second sub-data lines and the first pixel circuits connected to the first sub-data lines, as described later, or only including second pixel circuits.

[0078] For example, in Figure 2 and Figure 3 In the example shown, the first data line 210 only includes data lines located on both sides of the second display area 120 in the X direction. Therefore, when the second data line 220 is not connected to the dummy pixel circuits, the number N of pixel circuits connected to the second data line 220 is no greater than the number M of pixel circuits connected to the first data line 210. For example, the number N of pixel circuits connected to the second data line 220 is equal to the number M of first pixel circuits 111 connected to the first data line 210.

[0079] For example, such as Figure 2 and Figure 3 As shown, each second data line 220 includes a first sub-data line 221 and a second sub-data line 222 extending along a first direction, and an adapter cable 223 connecting the first sub-data line 221 and the second sub-data line 222.

[0080] For example, such as Figure 2 and Figure 3 As shown, the first sub-data line 221, the second sub-data line 222, and the first data line 210 are arranged on the same layer. The first sub-data line 221 is configured to be connected to the first pixel circuit 112, and the second sub-data line 222 is configured to be connected to the second pixel circuit 113.

[0081] For example, the second data line 220 includes a first sub-data line 221 that extends to the edge of the second display area 120. Figure 2 and Figure 3In the example shown, the data line 200 connected to the first pixel circuit 112 located on both sides of the second display area 120 in the X direction is the first data line 210, the data line 200 connected to the first pixel circuit 112 located on both sides of the second display area 120 in the Y direction is the first sub-data line 221 of the second data line 220, and the data line 200 connected to the second pixel circuit 113 is the second sub-data line 222 of the second data line 220.

[0082] For example, Figure 2 and Figure 3 The schematic diagram shows that the first sub-data line 221 of each second data line 220 includes two parts distributed on both sides of the second display area 120 in the Y direction, but it is not limited to this. The first sub-data line included in each second data line may also be located only on one side of the second display area. For example, the first pixel circuit and the first sub-data line are not provided above the second display area (with the direction of the arrow in the Y direction being upward).

[0083] For example, such as Figure 2 and Figure 3 As shown, the display substrate includes a transition area 2230, and multiple transition lines 223 are disposed in the transition area 2230. The transition area 2230 includes a first transition area 2231 located on one side of the second display area 120 in the first direction, and the transition area 2230 also includes a second transition area 2232 located on the other side of the second display area 120 in the first direction.

[0084] For example, such as Figure 2 and Figure 3 As shown, the adapter line 223 in the first adapter area 2231 extends along a second direction intersecting the first direction. The second direction is schematically shown as the X direction, but it is not limited to this, and the first and second directions can be interchanged. Figure 2 and Figure 3 The diagram illustrates that the first and second directions are perpendicular, but it is not limited to this; the first and second directions may not be perpendicular.

[0085] For example, such as Figure 2 and Figure 3 As shown, the adapter line 223 in the first adapter area 2231 and the first sub-data line 221 are located on different layers. For example, the adapter line 223 may be located on the side of the first sub-data line 221 away from the substrate 100.

[0086] For example, such as Figure 2 and Figure 3As shown, the adapter cable 223 in the second adapter area 2232 may include a first adapter cable 223-1 and a second adapter cable 223-2 that are connected to each other and disposed on different layers. One of the first adapter cable 223-1 and the second adapter cable 223-2 is connected to the second sub-data line 222 and is located on a different layer from the second sub-data line 222.

[0087] For example, such as Figure 3 As shown, each adapter cable 223 includes two second adapter cables 223-2 and a first adapter cable 223-1 connecting the two second adapter cables 223-2. One of the two second adapter cables 223-2 is connected to a second sub-data line 222, and the other of the two second adapter cables 223-2 is connected to a first sub-data line 221. For example, the first adapter cable 223-1 extends in a second direction, and the second adapter cables 223-2 extend in a first direction. For example, the first adapter cable 223-1 may be substantially parallel to the adapter cable 223 located in the first adapter area 2231.

[0088] For example, the second adapter cable 223-2 and the second sub-data cable 222 are located on different layers. For example, the first adapter cable 223-1 can be located on the same layer as the second sub-data cable 222. Of course, the embodiments of this disclosure are not limited to this; the first adapter cable can be on a different layer than the second sub-data cable, and the second adapter cable can be on the same layer as the second sub-data cable.

[0089] For example, such as Figure 2 and Figure 3 As shown, the second data line 220 includes five parts connected in sequence, such as a first sub-data line 221, an adapter cable 223, a second sub-data line 222, an adapter cable 223, and the first sub-data line 221. For example, the two first sub-data lines 221 are respectively connected to the same continuous second sub-data line 222 through two parts of the adapter cable 223. These two first sub-data lines 221 are located on both sides of the second display area 120 in the first direction, and the two first sub-data lines 221 are located on the same straight line. In this embodiment of the present disclosure, the two data lines being located on the same straight line means that the two data lines are approximately on the same straight line, for example, more than 50% of the two data lines are on the same straight line, or the maximum offset distance between the two data lines in the second direction is less than 5 micrometers, or 3 micrometers, etc.

[0090] For example, a data signal is loaded onto the first data lines 210 located on the left and right sides of the second display area 120 via a circuit board (not shown) located below the first display area 110, and provided to the M first pixel circuits 112 connected to the first data lines 210; the data signal is loaded onto the first sub-data line 221 located below the second display area 120 via the circuit board located below the first display area 110, and provided to the first pixel circuits 112 connected to the first sub-data line 221; the data signal loaded onto the first sub-data line 221 located below the second display area 120 is transmitted to the second sub-data line 222 via a first adapter cable 223, and then the data signal is transmitted to the first sub-data line 221 located above the second display area 120 via the second adapter cable 223, and provided to the first pixel circuit 112. Thus, the first sub-data lines located on both sides of the second display area and the second sub-data lines connected to these two first sub-data lines all transmit the same data signal. This data signal transmission method can be called single-channel drive.

[0091] like Figure 2 As shown, the number of first pixel circuits 112 connected to the two first sub-data lines 221 are a1 and a3 respectively, and the number of second pixel circuits 113 connected to the second sub-data line 222 is a2. Then, the number N of pixel circuits connected to the second data line 220 is equal to a1+a2+a3, and the number M of first pixel circuits 111 connected to the first data line 210 is also equal to a1+a2+a3, so M=N. Figure 2 The data lines in the display substrate shown are single-path driven. By reducing the number of third pixel circuits connected to the second data lines, the number of pixel circuits connected in series on the second data lines can be reduced, making M=N. This reduces the load on the second data lines to some extent, and thus alleviates the phenomenon of dark vertical stripes appearing in the second display area when all data lines simultaneously input the same signal (ET LED illumination). Furthermore, reducing the number of pixel circuits connected to the second data lines to reduce the load also reduces the burden on the driver IC when each data line inputs a corresponding data signal (module LED illumination).

[0092] Since the second display area has first pixel circuits on both sides of the first direction, the second display area also has first sub-data lines connected to the first pixel circuits on both sides of the first direction. In single-channel driving, the two parts of the first sub-data lines need to be electrically connected through the second sub-data lines and the two parts of the adapter lines. Therefore, the adapter area includes the first adapter area and the second adapter area located on both sides of the second display area.

[0093] For example, the second transition area 2232 is located in a non-display area outside the first display area 110 and the second display area 112, so as to prevent the transition lines in the second transition area from affecting the display effect of the display substrate.

[0094] For example, the distance between two adjacent first transition lines 223-1 in the second transition area 2232 can be less than the distance between two adjacent transition lines 223 in the first transition area 2231, so as to minimize the size of the border and achieve a narrow border.

[0095] For example, such as Figure 2 and Figure 3 As shown, the third pixel circuit 114 includes two parts located on both sides of each second pixel circuit column extending along the first direction, that is, in the pixel circuit column where the second pixel circuit 113 is located, the third pixel circuit 114 includes two parts distributed on both sides of the second pixel circuit 113.

[0096] Of course, this embodiment is not limited to this. When the second display area is located at the top of the overall display area, the third pixel circuit may only be located on the lower side of each column of second pixel circuits, that is, no third pixel circuit is provided on the upper side of the second pixel circuits. The upper and lower sides are, for example, two sides along the long side of the entire display area, and the top position is, for example, the end away from the driver IC. At this time, when the shape of the first display area is rectangular and the shape of the second display area is circular, some first pixel circuits will also be provided on the upper edge of the second display area, and the transition area will also include, for example, Figure 2 The diagram shows a first transition area and a second transition area. When both the first and second display areas are rectangular, the upper edge of the first display area can be flush with the upper edge of the second display area. In this case, the first pixel circuit is no longer provided on the upper side of the second display area, and the transition area only includes... Figure 2 The first transition area shown omits the second transition area, which allows for a narrower bezel.

[0097] For example, such as Figure 2 and Figure 3 As shown, the display substrate also includes multiple traces 300 extending along a first direction. These traces 300 do not pass through the second display area 120. The multiple traces 300 are disposed on the same layer as multiple data lines 200, and at least one data line 200 is disposed between adjacent traces 300. Along a direction perpendicular to the substrate 100, each trace 300 overlaps only with the third pixel circuit 114. For example, each trace 300 is connected to the third pixel circuit 114 it overlaps with. In this embodiment, the traces are traces that only overlap with dummy pixel circuits.

[0098] For example, trace 300 includes first traces 310, the number of which is the same as the number of second sub-data lines 222. Each first trace 310 and a second sub-data line 222 are generally on the same line and are separated by a gap 230. This same line is, for example, a straight line extending generally in a second direction, and may have some bends at certain locations, but the main body, for example, more than 50% of which is on the same straight line. For example, each first trace 310 and at least a portion of a second sub-data line 222 are on the same line and are separated by a gap 230. For example, a second sub-data line 222 and the first trace 310 on the same line can be two parts broken by a single metal wire. In this case, the length of the second sub-data line 222 is less than the length of the first data line 210, which can reduce the load on the second sub-data line 222.

[0099] For example, such as Figure 2 and Figure 3 As shown, the gap 230 between the second sub-data line 222 and the first trace 310 is located on the side of the first transition area 2231 away from the second display area 120, so the first trace 310 does not affect the data signal transmitted on the second sub-data line 222.

[0100] For example, such as Figure 2 and Figure 3 As shown, each first trace 310 is connected to the third sub-pixel 114 that overlaps with it, and is configured to transmit electrical signals. In this embodiment of the present disclosure, by connecting the first trace and the third pixel circuit that overlaps with the first trace, and transmitting electrical signals on the first trace, the floating of the first trace can be avoided.

[0101] For example, the second sub-data line 222 is configured to transmit a data signal, and the electrical signal transmitted on the first trace 310 is different from the signal transmitted on the second sub-data line 222.

[0102] For example, the first trace 310 is configured to transmit a power supply voltage signal. For example, it can be a constant positive voltage VDD, but it is not limited to this; it can also be other electrical signals, such as a reset voltage signal.

[0103] For example, such as Figure 2As shown, the trace 300 also includes a second trace 320 extending along the first direction. The second trace 320 includes portions located on both sides of the second display area 120 in the X direction and a portion located on at least one side of the second display area 120 in the Y direction. For example, in the second traces 320 located on both sides of the second display area 120 in the X direction, multiple first data lines 210 are provided between adjacent two second traces 320, or multiple second sub-data lines 222 are provided between adjacent two second traces 320. In the second traces 320 located on at least one side of the second display area 120 in the Y direction, multiple first sub-data lines 221 are provided between adjacent two second traces 320. For example, in the second traces 320 located on both sides of the second display area 120 in the Y direction, multiple first sub-data lines 221 are provided between adjacent two second traces 320 on either side of the second trace 320. Figure 2 The second traces located on both sides of the second display area 120 in the Y direction are not shown.

[0104] For example, each second trace 320 can transmit a power supply voltage signal. For example, multiple second traces 320 can be connected to a connecting line extending along the X direction. However, this is not the only possibility; second traces located on one side of the second display area may not transmit electrical signals, i.e., they may be floating.

[0105] Figure 4 This is a partial planar structure schematic diagram of a display substrate provided according to another example of an embodiment of the present disclosure. Figure 5 for Figure 4 The diagram shows a partially enlarged structural schematic of the display substrate. Figure 4 and Figure 5 As shown, Figure 4 and Figure 5 The example shown is the same as Figure 2 and Figure 3 The difference in the example shown is that the first pixel circuit 112 located on at least one side of the second display area 120 in the first direction is connected to the first data line 210, and the first data line 210 is not connected to the second sub-data line 222.

[0106] For example, such as Figure 4 and Figure 5 As shown, each second sub-data line 222 extends along a first direction and overlaps with the orthographic projection of each trace 300 onto a straight line extending along the first direction. In this example, each second sub-data line 222 is essentially a data line 200 that passes through the first display area 110. Each second sub-data line 222 is not on the same straight line as any trace 300, that is, the trace 300 only includes the portion that passes through the first display area 110 and another portion that extends to the edge of the second display area 120.

[0107] For example, such as Figure 4 and Figure 5 As shown, the first data line 210 is connected to the first pixel circuit 112 located on one side of the second display area 120 in the Y direction and the first pixel circuits 112 located on both sides of the second display area 120 in the X direction.

[0108] For example, such as Figure 4 and Figure 5 As shown, each first sub-data line 221 and a first data line 210 are located on both sides of the second display area 120 in the first direction and are on the same straight line. Each first sub-data line 211 and the first data line 210 on the same straight line are configured to transmit the same data signal.

[0109] For example, such as Figure 4 and Figure 5 As shown, the number of first pixel circuits 112 connected to each of the first data lines 210 located on both sides of the second display area 120 in the X direction is M, and the number of first pixel circuits 112 connected to the first data lines 210 located on one side of the second display area 120 in the Y direction is a1.

[0110] For example, such as Figure 4 and Figure 5 As shown, each second data line 220 includes a first sub-data line 221, a second sub-data line 222, and an adapter cable 223 connecting the first sub-data line 221 and the second sub-data line 222. For example, the adapter cable 223 is located in a non-display area outside the first display area 110 and the second display area 120. The second data line 220 includes three parts connected in sequence, such as the second sub-data line 222, the adapter cable 223, and the first sub-data line 221.

[0111] For example, such as Figure 4 and Figure 5 As shown, the number of second pixel circuits 113 connected to the second sub-data line 222 is a2, and the number of first pixel circuits 112 connected to the first sub-data line 221 is a3.

[0112] For example, data signals are loaded onto first data lines 210 located on the left and right sides of the second display area 120 via a circuit board (not shown) located below the first display area 110, so as to provide data to M first pixel circuits 112 connected to the first data lines 210; data signals are loaded onto first sub-data lines 221 located below the second display area 120 via the circuit board located below the first display area 110, so as to provide data to a1 first pixel circuits 112 connected to the first sub-data lines 221; data signals are loaded onto first pixel circuits 112 located on the left and right sides of the second display area 120 via the circuit board located below the first display area 110. The data signal is provided to the a2 second pixel circuits 113 connected to the second sub-data line 222 on both sides of the left and right sides of the second sub-data line 0. Then, the data signal is transmitted through the adapter cable 223 to the first sub-data line 221 located on the upper side of the second display area 120 to the a3 first pixel circuits 112 connected to the first sub-data line 221. The first data line 210 located on the lower side of the second display area 120 and the first sub-data line 221 located on the same straight line as the first data line 210 are configured to transmit the same data signal. This data signal transmission method can be called dual-path drive.

[0113] In this dual-path driving mode, the number M of first pixel circuits connected to the first data lines whose extensions do not pass through the second display area is (a1+a2+a3), the number a1 of first pixel circuits connected to the first data lines whose extensions pass through the second display area is less than M, and the number N of pixel circuits connected to the second data lines is (a2+a3), where N is less than M. Figure 4 The data lines in the display substrate shown are driven by dual circuits. By reducing the number of third pixel circuits connected to the second data lines, the number of pixel circuits connected in series on the second data lines can be reduced, making M greater than or equal to N. This reduces the load on the second data lines to some extent, and thus alleviates the phenomenon of dark vertical stripes appearing in the second display area when all data lines simultaneously input the same signal (ET LED illumination). In addition, reducing the number of pixel circuits connected to the second data lines to reduce the load can also reduce the burden on the driver IC when each data line inputs a corresponding data signal (module LED illumination).

[0114] For example, such as Figure 4 and 5 As shown, the length of each second sub-data line 222 is not less than the length of the first data line 210 whose extension does not pass through the second display area 120. For example, the second sub-data line 222, part of the first data line 120, and part of the trace 300 all pass through the first display area 110.

[0115] Since the second sub-data line is the same length as the first data line whose extension line does not pass through the second display area, and the second sub-data line with this length is only connected to the second pixel circuit and not to any dummy pixel circuit, and since the second sub-data line is not connected to the first sub-data line through an adapter cable, the capacitance generated by the second sub-data line can be reduced.

[0116] For example, such as Figure 4 and Figure 5 As shown, each adapter cable 223 includes a first adapter cable 223-1 and a second adapter cable 223-2 that are connected to each other and disposed on different layers. One of the first adapter cable 223-1 and the second adapter cable 223-2 is connected to the second sub-data line 222 and is located on a different layer from the second sub-data line 222.

[0117] For example, such as Figure 4 and Figure 5 As shown, the other of the first adapter cable 223-1 and the second adapter cable 223-2 extends along a second direction that intersects with the first direction and is located on the same layer as the second sub-data cable 212.

[0118] Figure 6 This is a partial planar structure schematic diagram of a display substrate provided according to another example of an embodiment of the present disclosure. For example... Figure 6 As shown, Figure 6 The example shown is the same as Figure 5 The difference in the example shown is that each second data line 220 extends along the first direction, and each second data line 220 is configured to connect only to the second pixel circuit 113. For example... Figure 6 As shown, the second display area 120 and the first display area 110 have the same shape, and one side edge (e.g., the upper edge) of the second display area 120 is flush with one side edge (e.g., the upper edge) of the first display area 110, so that the first pixel circuit 112 is only distributed on three sides of the second display area 120.

[0119] For example, such as Figure 6 As shown, the second display area 120 has a first pixel circuit 112 on one side of the Y direction and no first pixel circuit 112 on the other side of the Y direction. Therefore, the second data line 220 is only configured to provide data signals to the second pixel circuit 113 and does not need to provide data signals to the first pixel circuit.

[0120] For example, such as Figure 6 As shown, all third pixel circuits 114 that overlap with the second data line 220 can be insulated from the second data line 220, but this is not the only possibility. In the third pixel circuits that overlap with the second data line, some third pixel circuits can be connected to the second data line, while others can be insulated from the second data line.

[0121] For example, Figure 7 for Figures 2 to 6 The diagram shown is an equivalent diagram of the pixel circuitry in the display substrate. Figure 7 The pixel circuit shown is the second pixel circuit 113, which is configured to drive the second light-emitting element 121 to emit light. Other pixel circuits, such as the first pixel circuit and the third pixel circuit, have the same structure as the second pixel circuit, but the third pixel circuit is not connected to the light-emitting element. For example, the display substrate also includes a reset power signal line, a scan signal line, a power signal line, a reset control signal line, and a light emission control signal line located on the substrate.

[0122] For example, such as Figure 7 As shown, the second pixel circuit 113 includes a data writing transistor T4, a driving transistor T3, a threshold compensation transistor T2, and a first reset control transistor T7. The first terminal of the threshold compensation transistor T2 is connected to the first terminal of the driving transistor T3, and the second terminal of the threshold compensation transistor T2 is connected to the gate of the driving transistor T3. The first terminal of the first reset control transistor T7 is connected to the reset power supply signal line to receive the reset signal Vinit, and the second terminal of the first reset control transistor T7 is connected to the second light-emitting element 121. The first terminal of the data writing transistor T4 is connected to the second terminal of the driving transistor T3. For example, as... Figure 7As shown, the second pixel circuit 113 further includes a storage capacitor C, a first light-emitting control transistor T6, a second light-emitting control transistor T5, and a second reset transistor T1. The gate of the data writing transistor T4 is electrically connected to the scan signal line to receive the scan signal Gate; the first terminal of the storage capacitor C is electrically connected to the power supply signal line, and the second terminal of the storage capacitor C is electrically connected to the gate of the driving transistor T3; the gate of the threshold compensation transistor T2 is electrically connected to the scan signal line to receive the compensation control signal; the gate of the first reset transistor T7 is electrically connected to the reset control signal line to receive the reset control signal Reset(N+1); the first terminal of the second reset transistor T1 is electrically connected to the reset power supply signal line to receive the reset signal Vinit, and the second terminal of the second reset transistor T1 is electrically connected to the gate of the driving transistor T3. The gate of the second reset transistor T1 is electrically connected to the reset control signal line to receive the reset control signal Reset(N); the gate of the first light-emitting control transistor T6 is electrically connected to the light-emitting control signal line to receive the light-emitting control signal EM; the first electrode of the second light-emitting control transistor T5 is electrically connected to the power supply signal line to receive the power supply voltage signal VDD, the second electrode of the second light-emitting control transistor T5 is electrically connected to the second electrode of the driving transistor T3, and the gate of the second light-emitting control transistor T5 is electrically connected to the light-emitting control signal line to receive the light-emitting control signal EM; the first electrode of the second light-emitting element 121 is connected to the voltage terminal to receive the signal VSS. The aforementioned power supply signal line refers to the signal line that outputs the power supply voltage signal VDD, and can be connected to a voltage source to output a constant voltage signal, such as a positive voltage signal.

[0123] For example, the scan signal and the compensation control signal can be the same; that is, the gate of the data writing transistor T3 and the gate of the threshold compensation transistor T2 can be electrically connected to the same signal line to receive the same signal, reducing the number of signal lines. Alternatively, the gate of the data writing transistor T3 and the gate of the threshold compensation transistor T2 can be electrically connected to different signal lines; that is, the gate of the data writing transistor T3 is electrically connected to the first scan signal line, and the gate of the threshold compensation transistor T2 is electrically connected to the second scan signal line. The signals transmitted by the first scan signal line and the second scan signal line can be the same or different, thus allowing the gate of the data writing transistor T3 and the threshold compensation transistor T2 to be controlled separately, increasing the flexibility of the pixel circuit control.

[0124] For example, the first light-emitting control transistor T6 and the second light-emitting control transistor T5 can receive the same light-emitting control signal. That is, the gate of the first light-emitting control transistor T6 and the gate of the second light-emitting control transistor T5 can be electrically connected to the same signal line to receive the same signal, reducing the number of signal lines. Alternatively, the gate of the first light-emitting control transistor T6 and the gate of the second light-emitting control transistor T5 can be electrically connected to different light-emitting control signal lines, and the signals transmitted by the different light-emitting control signal lines can be the same or different.

[0125] For example, the reset control signals input to the first reset transistor T7 and the second reset transistor T1 can be the same; that is, the gates of the first reset transistor T7 and the second reset transistor T1 can be electrically connected to the same signal line to receive the same signal, reducing the number of signal lines. Alternatively, the gates of the first reset transistor T7 and the second reset transistor T1 can be electrically connected to different reset control signal lines, in which case the signals on the different reset control signal lines can be the same or different.

[0126] For example, such as Figure 7 As shown, when the display substrate is working, in the first stage of screen display, the second reset transistor T1 is turned on to initialize the voltage of node N1; in the second stage of screen display, data is stored in node N1 through data writing transistor T4, driving transistor T3 and threshold compensation transistor T2; in the third stage of light emission, the second light emission control transistor T5, driving transistor T3 and the first light emission control transistor T6 are all turned on, and the light emission element is forward-biased to emit light.

[0127] It should be noted that, in the embodiments of this disclosure, the pixel circuit can, in addition to being able to... Figure 7 In addition to the 7T1C (i.e., seven transistors and one capacitor) structure shown, other structures including other numbers of transistors are also possible, such as 7T2C, 6T1C, 6T2C, 8T1C, or 9T2C structures. This disclosure does not limit the specific number of transistors in the embodiments.

[0128] Figure 8 This is a partial planar structural diagram of the stacked structure of the active semiconductor layer, the first conductive layer, and the source / drain metal layer of the second pixel circuit provided according to an embodiment of this disclosure. Figure 8As shown, the active semiconductor layer 3100 can be formed by patterning semiconductor material. The active semiconductor layer 3100 can be used to fabricate the active layers of the aforementioned second reset transistor T1, threshold compensation transistor T2, driving transistor T3, data writing transistor T4, second light-emitting control transistor T5, first light-emitting control transistor T6, and first reset control transistor T7. The active semiconductor layer 3100 includes active layer patterns (channel regions) and doped region patterns (source and drain doped regions) for each transistor.

[0129] For example, the active layer may include an integrally formed low-temperature polycrystalline silicon layer, and the source and drain regions may be conductiveized through doping to achieve electrical connection between the structures. For example, the active semiconductor layer of each transistor is an integral pattern formed of p-silicon, and each transistor in the same pixel circuit includes a doped region pattern (i.e., source and drain regions) and an active layer pattern, with the active layers of different transistors separated by doped structures.

[0130] For example, the active semiconductor layer 3100 can be fabricated using amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the aforementioned source and drain regions can be regions doped with n-type or p-type impurities.

[0131] Figure 10 for Figure 8 The diagram shows a cross-sectional view of the pixel circuit along AA'. Figure 8 and Figure 10 As shown, a gate insulating layer 71 is disposed on the side of the active semiconductor layer 3100 away from the substrate 100, and a first conductive layer 3200 (i.e., gate metal layer) is disposed on the side of the gate insulating layer 71 away from the active semiconductor layer 3100. The first conductive layer 3200 may include the second terminal CC2 of capacitor C, a scan signal line 52 extending along the X direction, a reset control signal line 51, a light emission control signal line 53, and the gates of a second reset transistor T1, a threshold compensation transistor T2, a driving transistor T3, a data writing transistor T4, a second light emission control transistor T5, a first light emission control transistor T6, and a first reset control transistor T7.

[0132] For example, such as Figure 8 and Figure 10As shown, the gate of the data writing transistor T3 can be the portion where the scan signal line 52 overlaps with the active semiconductor layer 3100; the gate of the first light-emitting control transistor T6 can be the first portion where the light-emitting control signal line 53 overlaps with the active semiconductor layer 3100, and the gate of the second light-emitting control transistor T5 can be the second portion where the light-emitting control signal line 53 overlaps with the active semiconductor layer 3100. The gate of the second reset transistor T1 is the first portion where the reset control signal line 51 overlaps with the active semiconductor layer 3100, and the gate of the first reset control transistor T7 is the second portion where the reset control signal line 51 overlaps with the active semiconductor layer 3100. The threshold compensation transistor T2 can be a thin-film transistor with a dual-gate structure. Figure 8 As shown, the gate of the driving transistor T1 can be the second terminal CC2 of the capacitor C.

[0133] It should be noted that, Figure 8 The dashed rectangles in the diagram illustrate the overlapping portions of the active semiconductor layer 3100 and the first conductive layer 3200, i.e., the channel regions. As the channel regions of each transistor, the active semiconductor layers on both sides of each channel region are conductiveized through processes such as ion doping, serving as the first and second electrodes of each transistor. The source and drain electrodes of a transistor can be structurally symmetrical, so their physical structures can be indistinguishable. In the embodiments of this disclosure, to distinguish transistors, except for the gate electrode which serves as the control electrode, one electrode is directly described as the first electrode and the other as the second electrode. Therefore, in the embodiments of this disclosure, the first and second electrodes of all or some transistors can be interchanged as needed.

[0134] For example, such as Figure 8 As shown, the scan signal line 52, reset control signal line 51, and light emission control signal line 53 are arranged along the Y direction. The scan signal line 52 is located between the reset control signal line 51 and the light emission control signal line 53. For example, the second terminal CC2 of capacitor C (i.e., the gate of driving transistor T1) is located between the scan signal line 52 and the light emission control signal line 53.

[0135] For example, such as Figure 8 As shown, a source / drain metal layer 3300 is disposed on the side of the first conductive layer 3200 away from the substrate. The source / drain metal layer 3300 includes a data line 200 extending along the Y direction and a power signal line 54. The source / drain metal layer 3300 also includes a first connection portion 55, a second connection portion 56, a third connection portion 57, and a fourth connection portion 58.

[0136] Figure 9 This is a partial planar structural diagram of the stacked structure of the active semiconductor layer, the first conductive layer, the source / drain metal layer, and the second conductive layer of the second pixel circuit provided according to an embodiment of this disclosure. Figure 9 and Figure 10As shown, a first insulating layer 72 is disposed on the side of the first conductive layer 3200 away from the substrate 100, a second conductive layer 3400 is disposed on the side of the second insulating layer 72 away from the substrate 100, a second insulating layer 73 is disposed on the side of the second conductive layer 3400 away from the substrate 100, and a source / drain metal layer 3300 is disposed on the side of the second insulating layer 73 away from the substrate 100.

[0137] For example, such as Figure 9 As shown, the second conductive layer 3400 includes a first terminal CC1 of capacitor C and a second reset power signal line 82 along the first reset power signal line 81. The first terminal CC1 of capacitor C and the second terminal CC2 of capacitor C at least partially overlap to form capacitor C.

[0138] For example, the second conductive layer 3400 also includes a plurality of cover portions S, and each threshold compensation transistor T2 includes two gates and an active semiconductor layer located between the orthogonal projections of the two gates onto the active semiconductor layer 3100. Along a direction perpendicular to the substrate, the cover portions S overlap with the active semiconductor layer 3100 between the two gates.

[0139] For example, such as Figures 8 to 10 As shown, the second sub-data line 222 is electrically connected to the second pole of the data writing transistor T2 in the second pixel circuit through a via H1 that passes through the gate insulating layer 71, the first insulating layer 72 and the second insulating layer 73, so as to realize that the second sub-data line 222 is the input data signal for the second pixel circuit.

[0140] For example, such as Figure 8 and Figure 9 As shown, the power signal line 54 is electrically connected to the first terminal of the second light-emitting control transistor T5 through a via penetrating the gate insulating layer, the first insulating layer, and the second insulating layer. The power signal line 54 and the data line 200 are alternately arranged along the X direction. The power signal line 54 is electrically connected to the first terminal CC1 of the capacitor C through a via penetrating the second insulating layer. For example, the second insulating layer is an interlayer insulating layer.

[0141] For example, a dual-gate threshold compensation transistor can reduce leakage current. For instance, the active semiconductor layer between the two channels of the dual-gate threshold compensation transistor T2 is in a floating state when T2 is off, making it susceptible to fluctuations due to surrounding line voltages. This fluctuations affect the leakage current of T2 and consequently its luminous brightness. To maintain a stable voltage in the active semiconductor layer between the two channels of T2, a capacitive capacitor is formed between the capacitive portion S and the active semiconductor layer. The capacitive portion S can be connected to the power signal line 54 to obtain a constant voltage, thus ensuring a stable voltage for the floating active semiconductor layer. The overlap between the capacitive portion S and the active semiconductor layer between the two channels of T2 also prevents the active semiconductor layer between the two gates from being altered by illumination, such as preventing voltage changes in this portion of the active semiconductor layer and thus preventing crosstalk.

[0142] For example, such as Figure 8 and Figure 9 As shown, the second terminal of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3 through the first connection portion 55. The first end of the first connection portion 55 is connected to the second terminal of the threshold compensation transistor T2 through a via penetrating the gate insulating layer, the first insulating layer, and the second insulating layer. The second end of the first connection portion 55 is connected to the gate of the driving transistor T3 through a via penetrating the first insulating layer and the second insulating layer. For example, the first connection portion 55 overlaps with the first terminal CC1 of the capacitor C. The first terminal of the second reset transistor T1 is electrically connected to the first reset power supply signal line 81 through the second connection portion 56. One end of the second connection portion 56 is connected to the first terminal of the second reset transistor T1 through a via penetrating the gate insulating layer, the first insulating layer, and the second insulating layer. The other end of the second connection portion 56 is connected to the first reset power supply signal line 81 through a via penetrating the second insulating layer. The first electrode of the first reset transistor T7 is electrically connected to the second reset power signal line 82 through the third connection portion 57. One end of the third connection portion 57 is connected to the first electrode of the first reset transistor T7 through a via penetrating the gate insulating layer, the first insulating layer, and the second insulating layer. The other end of the third connection portion 57 is connected to the second reset power signal line 82 through a via penetrating the second insulating layer. Because the second display area has a large ITO capacitance (i.e., the capacitance generated by the transparent traces connecting the second light-emitting element and the second pixel circuit, and the overlapping conductive layers, source / drain metal layers, etc.), the anode voltage rise process of the second light-emitting element becomes very slow. For low grayscale, the turn-on time of the second light-emitting element is greatly delayed. In this embodiment, the first reset power signal line and the second reset power signal line are connected to the first reset transistor and the second reset transistor respectively. Appropriately increasing the first reset power signal voltage can improve the uneven grayscale brightness of the low second display area.

[0143] For example, such as Figure 8 and Figure 9 As shown, the fourth connection portion 58 is connected to the second electrode of the first light-emitting control transistor T6 through a via penetrating the gate insulating layer, the first insulating layer, and the second insulating layer.

[0144] It should be noted that the first pixel circuit and the second pixel circuit have the same structure, and the positional and connection relationships between the first pixel circuit and the data lines, scan lines, reset control signal lines, light emission control signal lines, and power signal lines are the same as those between the second pixel circuit and the corresponding signal lines. Therefore, they will not be repeated here. Similarly, the third pixel circuit has the same structure as the second pixel circuit, and the positional and connection relationships between the third pixel circuit and the traces, scan lines, reset control signal lines, light emission control signal lines, and power signal lines are the same as those between the second pixel circuit and the corresponding signal lines. Therefore, they will not be repeated here.

[0145] For example, Figure 11 This is a partial planar structural diagram of the stacked structure of the active semiconductor layer, the first conductive layer, and the source / drain metal layer of the third pixel circuit provided according to an embodiment of this disclosure. Figure 11 As shown, the third pixel circuit overlaps with the second sub-data line 222, and the third pixel circuit overlapping with the second sub-data line 222 is... Figure 8 The difference between the second pixel circuit shown overlapping with the second sub-data line 222 is that the third pixel circuit overlapping with the second sub-data line 222 is insulated from the second sub-data line 222.

[0146] Figure 12 for Figure 11 The diagram shows a cross-sectional view of the pixel circuit along BB'. Figure 11 and Figure 12 As shown, the gate insulating layer 71, the first insulating layer 72 and the second insulating layer 73 disposed between the second sub-data line 222 and the second electrode of the data writing transistor T2 in the third pixel circuit are not provided with vias, thereby making the second sub-data line 222 and the second electrode of the data writing transistor T2 located directly below it insulated.

[0147] Therefore, an insulating layer (including a gate insulating layer, a first insulating layer, and a second insulating layer) is provided between the film layer where the first electrode of the data writing transistor is located and the film layer where the data line is located. The first electrode of the data writing transistor in the first pixel circuit and the second pixel circuit is connected to the data line through a via located in the insulating layer. The first electrode of the data writing transistor in at least a portion of the third pixel circuit that overlaps with the second data line is insulated from the second data line by the insulating layer.

[0148] For example, at least one insulating layer between the third pixel circuit and the second data line may not have any vias in the region corresponding to the third pixel circuit. Alternatively, all insulating layers between the third pixel circuit and the second data line may not have any vias in the region corresponding to the third pixel circuit.

[0149] For example, Figure 13 for Figure 2 The diagram shown illustrates the display area of ​​the display substrate and a second data line. Figure 14 for Figure 13 An enlarged view of region E1 shown. Figure 15 for Figure 13 The enlarged view of region E2 shown. Figure 16 for Figure 13 The enlarged view of region E3 shown. Figure 17 for Figure 13 An enlarged view of region E4 is shown. Figures 14 to 16 A schematic planar diagram illustrating the stacked structure of the source / drain metal layers and the third conductive layer is shown. Figures 13 to 16 As shown, the display substrate also includes a third conductive layer located on the side of the source / drain metal layer away from the substrate. The third conductive layer includes a transition line 223 located in the display area, a shielding electrode SE, a fifth connection portion 59, and a second transition line 223-2 located outside the display area.

[0150] For example, the shielding electrode SE is connected to the power signal line 54, thereby stabilizing the voltage on the shielding electrode SE and providing a shielding effect. This prevents the transparent traces connecting the second light-emitting element and the second pixel circuit from affecting the gate of the driving transistor and the potential of the first connection portion. The orthographic projection of the first connection portion on the substrate falls within the orthographic projection of the shielding electrode SE on the substrate.

[0151] For example, such as Figures 13 to 17 As shown, a third insulating layer can be provided between the third conductive layer and the source / drain metal layer. The fifth connection portion 59 can be connected to the fourth connection portion 58 through a via in the third insulating layer to achieve connection with the second electrode of the first light-emitting control transistor T6.

[0152] For example, each light-emitting element includes a first electrode, a light-emitting layer, and a second electrode (not shown) stacked together. The first electrode is located on the side of the light-emitting layer facing the substrate. The first electrode is connected to the second electrode of the first light-emitting control transistor T6 through the fifth connection portion and the fourth connection portion.

[0153] For example, such as Figure 14 and Figure 15 As shown, the adapter cable 223 connected to a first sub-data line 221 can overlap with the second connection portion 56 and the third connection portion 57. For example, in the direction perpendicular to the substrate, the adapter cable 223 can overlap with a reset control signal line.

[0154] For example, such as Figure 16 and Figure 17 As shown, the first adapter line 223-1 can be patterned from the source / drain metal layer to save on the number of film layers, and the second adapter line 223-2 is patterned from the third conductive layer. The second adapter line 223-1 is connected to the first sub-data line 221 and the first adapter line 223-1 respectively through two vias H2 in the third insulating layer. This embodiment is not limited to this; the second adapter line can be disposed on the same layer as the first sub-data line (or the second sub-data line) and be the same signal line, while the first adapter line is disposed on a different layer from the first sub-data line.

[0155] For example, such as Figure 16 and Figure 17 As shown, the third insulating layer also includes multiple vias H3 to make the third insulating layer etched more uniformly.

[0156] For example, Figure 18 For including Figure 16 The enlarged view shown is a partial view of the structure. Figure 19 For including Figure 17 The enlarged view shown is a partial structural representation. For example, as... Figures 16 to 19 As shown, seven first data lines 210 can be set between two adjacent second sub-data lines 222, and seven first sub-data lines 221 can be set between two adjacent traces 300. For example, the first sub-data lines 221 located on the upper side of the second display area are all connected to the second sub-data lines 222 located on the left and right sides of the second display area through the first adapter cable 223-1 and the second adapter cable 223-2.

[0157] This disclosure provides at least one embodiment of a display substrate, such as... Figures 2 to 19 As shown, the display substrate includes a substrate 100, a plurality of pixel circuits 1000 located on the substrate 100, and a plurality of data lines 200. The plurality of pixel circuits 1000 includes a plurality of first-type pixel circuits 1001 and a plurality of second-type pixel circuits 1002. The first-type pixel circuits 1001 are electrically connected to the data lines 200, and the second-type pixel circuits 1002 are insulated from the data lines 200. In the display substrate provided in this embodiment, by insulating the second-type pixel circuits from the data lines, the number of pixel circuits connected to the data lines can be reduced to lower the load, thereby alleviating the phenomenon of dark vertical stripes in the display area and improving the display quality of the display substrate.

[0158] For example, such as Figures 2 to 19 As shown, the first type of pixel circuit 1001 and the data line 200 overlapping therewith are electrically connected, and the second type of pixel circuit 1002 and the data line 200 overlapping therewith are insulated.

[0159] For example, such as Figures 2 to 19 As shown, at least a portion of the first type pixel circuit 1001 is configured to drive a light-emitting element (e.g., a first light-emitting element 111 or a second light-emitting element 121) connected thereto to emit light, and the second type pixel circuit 1002 is a first dummy pixel circuit. The first dummy pixel circuit is a pixel circuit that is not connected to any light-emitting element.

[0160] For example, such as Figures 2 to 19 As shown, the first type of pixel circuit 1001 includes a first pixel circuit 112 and a second pixel circuit 113. The first pixel circuit 112 and the light-emitting element (first light-emitting element 111) connected thereto overlap in a direction perpendicular to the substrate 100. The second pixel circuit 113 and the light-emitting element (second light-emitting element 121) connected thereto do not overlap in a direction perpendicular to the substrate 100. The first type of pixel circuit 1001 also includes a second dummy pixel circuit 1003. The second dummy pixel circuit 1003 is a pixel circuit that is not connected to any light-emitting element.

[0161] For example, such as Figures 2 to 19 As shown, the second type of pixel circuit 1002 and a portion of the first type of pixel circuit 1002 are located in the same column.

[0162] For example, such as Figures 2 to 19 As shown, the second type pixel circuit 1002 and the second pixel circuit 113 are located in the same column.

[0163] For example, such as Figures 2 to 19 As shown, the pixel circuit 1000 includes a data writing transistor T4, which includes a first electrode, a second electrode, and a gate. An insulating layer is disposed between the film layer containing the first electrode of the data writing transistor T4 and the film layer containing the data line 200. The first electrode of the data writing transistor T4 of the first type pixel circuit 1001 is connected to the corresponding data line 200 through a via H1 located in the insulating layer (e.g., gate insulating layer 71, first insulating layer 72, and second insulating layer 73). The first electrode of the data writing transistor T4 of the second type pixel circuit 1002 is insulated from the data line 200 by the insulating layer (e.g., gate insulating layer 71, first insulating layer 72, and second insulating layer 73).

[0164] The first type of pixel circuit in this embodiment includes the first pixel circuit, the second pixel circuit, and a portion of the third pixel circuit (the third pixel circuit connected to the wiring) in the above embodiments. The second type of pixel circuit includes another portion of the third pixel circuit (the pixel circuit not connected to the wiring or data line). The structures of the substrate, data line, pixel circuit, and light-emitting element in this embodiment have the same features as those in the above embodiments, and will not be described again here.

[0165] Another embodiment of this disclosure provides a display device, which includes any of the above-described display substrates.

[0166] For example, the display device provided in the embodiments of this disclosure can be an organic light-emitting diode display device.

[0167] For example, in the display device provided in the embodiments of this disclosure, by setting at least a portion of the third pixel circuit that overlaps with the second data line to be unconnected to the second data line, the number of pixel circuits connected to the second data line can be reduced to reduce the load, thereby alleviating the phenomenon of dark vertical stripes appearing in the second display area and improving the display quality of the display device.

[0168] For example, the display device may also include a cover plate located on the display side of the display substrate. For example, the display device may also include a functional component located on the side of the substrate away from the light-emitting element, the functional component being directly opposite the second display area.

[0169] For example, the functional components include at least one of a camera module (e.g., a front-facing camera module), a 3D structured light module (e.g., a 3D structured light sensor), a time-of-flight 3D imaging module (e.g., a time-of-flight sensor), and an infrared sensing module (e.g., an infrared sensing sensor).

[0170] For example, a front-facing camera module is typically activated when a user takes a selfie or makes a video call. The pixel display area of ​​the display device shows the image taken during the selfie for the user to view. A front-facing camera module typically includes a lens, an image sensor, and an image processing chip. The optical image of the scene, generated by the lens, is projected onto the surface of the image sensor (image sensors can be either CCD or CMOS), converted into an electrical signal, and then converted into a digital image signal by the image processing chip. This digital signal is then processed by the processor and output as an image of the scene on the display screen.

[0171] For example, 3D structured light sensors and time-of-flight (ToF) sensors can be used for facial recognition to unlock display devices.

[0172] For example, functional component 20 may only include a camera module to enable selfie or video call functions; for example, functional component 20 may further include a 3D structured light module or a time-of-flight 3D imaging module to enable face recognition unlocking, etc., and this embodiment includes, but is not limited to, these.

[0173] For example, the display device can be any product or component with display function, such as a mobile phone, tablet computer, laptop computer, or navigator with an under-display camera; this embodiment is not limited to this.

[0174] The following points need to be explained:

[0175] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure, and other structures can be referred to the general design.

[0176] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure may be combined with each other.

[0177] The above description is merely an exemplary embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure, which is determined by the appended claims.

Claims

1. A display substrate, comprising: Substrate; Multiple pixel circuits are located on the substrate. Multiple data lines are located on the substrate. The plurality of pixel circuits include a plurality of first-type pixel circuits and a plurality of second-type pixel circuits. The first-type pixel circuits are electrically connected to the data line, and the second-type pixel circuits are insulated from the data line.

2. The display substrate according to claim 1, wherein, The first type of pixel circuit and the overlapping data line are electrically connected, while the second type of pixel circuit and the overlapping data line are insulated.

3. The display substrate according to claim 1, wherein, At least a portion of the first type of pixel circuit is configured to drive a light-emitting element connected thereto to emit light, and the second type of pixel circuit is a first dummy pixel circuit.

4. The display substrate according to claim 3, wherein, The first type of pixel circuit includes a first pixel circuit and a second pixel circuit. The first pixel circuit and the light-emitting element connected thereto overlap in a direction perpendicular to the substrate, while the second pixel circuit and the light-emitting element connected thereto do not overlap in a direction perpendicular to the substrate. The first type of pixel circuit also includes a second dummy pixel circuit.

5. The display substrate according to claim 4, wherein, The second type of pixel circuit and a portion of the first type of pixel circuit are located in the same column.

6. The display substrate according to claim 5, wherein, The second type of pixel circuit and the second pixel circuit are located in the same column.

7. The display substrate according to any one of claims 1, wherein, The pixel circuit includes a data writing transistor, which includes a first electrode, a second electrode, and a gate. An insulating layer is disposed between the film layer containing the first electrode of the data writing transistor and the film layer containing the data line. In the first type of pixel circuit, the first terminal of the data writing transistor is connected to the corresponding data line through a via located in the insulating layer; in the second type of pixel circuit, the first terminal of the data writing transistor and the data line are insulated from each other by the insulating layer.

8. The display substrate according to any one of claims 1, wherein, The substrate includes a first display area and a second display area. The first display area is located around the second display area. The first display area includes a plurality of first light-emitting elements. The second display area includes a plurality of second light-emitting elements. The first type of pixel circuit includes a plurality of first pixel circuits and a plurality of second pixel circuits located in the first display area. The plurality of first pixel circuits are connected one-to-one with the plurality of first light-emitting elements, and the plurality of second pixel circuits are connected one-to-one with the plurality of second light-emitting elements; the first display area further includes a dummy pixel circuit, the first type of pixel circuit includes a part of the dummy pixel circuit, and the second type of pixel circuit includes another part of the dummy pixel circuit; The plurality of data lines do not pass through the second display area. The plurality of data lines include a plurality of first data lines and a plurality of second data lines. Each first data line is configured to be connected to the first pixel circuit, and each second data line is configured to be connected to at least the second pixel circuit. At least a portion of the third pixel circuit that overlaps with the second data line along a direction perpendicular to the substrate is insulated from the second data line.

9. The display substrate according to claim 8, wherein, Each of the first data lines extends along a first direction. The first data lines whose extensions do not pass through the second display area are configured to transmit data signals to M first pixel circuits. Each of the second data lines is configured to transmit signals to N pixel circuits, and M≥N. The N pixel circuits include at least the second pixel circuits. The second data line includes a first sub-data line and a second sub-data line extending along the first direction, and an adapter cable connecting the first sub-data line and the second sub-data line; the first sub-data line, the second sub-data line and the first data line are arranged on the same layer, the first sub-data line is configured to be connected to the first pixel circuit, and the second sub-data line is configured to be connected to the second pixel circuit.

10. The display substrate according to claim 9, further comprising: Multiple traces extend along the first direction but do not pass through the second display area. The plurality of traces are arranged on the same layer as the plurality of first data lines, and at least one data line is arranged between two adjacent traces; Along a direction perpendicular to the substrate, the trace only overlaps with the third pixel circuit.

11. The display substrate according to claim 10, wherein the plurality of traces includes a plurality of first traces, the number of first traces being the same as the number of second sub-data lines, and at least a portion of one first trace and one second sub-data line being substantially on the same straight line and having a gap between them; The transfer area includes the aforementioned multiple transfer cables. in, The transition area includes a first transition area located on one side of the second display area in the first direction, the transition line in the first transition area extends along a second direction intersecting the first direction and is located on a different layer from the first data line, the interval is located on the side of the first transition area away from the second display area, and the first trace and at least part of the dummy pixel circuit overlap.

12. The display substrate according to claim 11, wherein, The first data line and the second sub-data line are configured to transmit different electrical signals; The first trace is configured to transmit a power supply voltage signal.

13. The display substrate according to claim 12, wherein, The other of the first and second adapter cables extends along a second direction intersecting the first direction and is located on the same layer as the second sub-data cable.

14. The display substrate according to claim 9, wherein, The second data line extends along the first direction and is configured to connect only to the second pixel circuit.

15. The display substrate according to claim 9, wherein, The first display area includes a plurality of pixel circuits arranged in an array along the first direction and a second direction intersecting the first direction, and the plurality of second pixel circuits are located on both sides of the second display area in the second direction.

16. The display substrate according to claim 15, wherein, The pixel circuit column containing the second pixel circuit arranged along the first direction includes the dummy pixel circuit, and the dummy pixel circuit in the pixel circuit column overlaps with the second data line.

17. The display substrate according to claim 10, wherein, The plurality of dummy pixel circuits include a plurality of third pixel circuit columns extending along the first direction and arranged along the second direction, at least a portion of the plurality of third pixel circuit columns being located on at least one side of the second display area in the first direction.

18. The display substrate according to claim 17, wherein, The plurality of third pixel circuit columns also include portions located on both sides of the second display area in the second direction.

19. The display substrate according to claim 8, wherein, The pixel circuit includes a data writing transistor, which includes a first electrode, a second electrode, and a gate. An insulating layer is disposed between the film layer containing the first electrode of the data writing transistor and the film layer containing the data line. The first electrode of the data writing transistor in the first pixel circuit and the second pixel circuit is connected to the data line through a via located in the insulating layer. In at least a portion of the third pixel circuit that overlaps with the second data line, the first electrode of the data writing transistor and the second data line are insulated by the insulating layer.

20. A display device comprising the display substrate according to any one of claims 1-19.

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