Display panel and display device

Abstract

The invention provides a display panel and a display device. The display panel comprises a gate drive circuit arranged in a non-display area and a pixel drive circuit arranged in a display area, the gate drive circuit comprises a plurality of cascaded gate drive units arranged in a first direction, and the pixel drive circuit comprises a compensation transistor and a first reset transistor which are connected. The gate driving unit comprises a first gate circuit and a second gate circuit which are arranged in the first direction, the output end of the first gate circuit is connected with the compensation transistor, and the second gate circuit is connected with the first reset transistor; the first gate circuit connected with the compensation transistor and the second gate circuit connected with the first reset transistor are arranged along the first direction, so that the arrangement of the first gate circuit and the second gate circuit is changed from transverse arrangement to longitudinal arrangement, the transverse frame width of the product is reduced, and the narrow frame design of the product is further realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] In the related art, the pixel driving circuit of an OLED (Organic Light-Emitting Diode) display panel is usually composed of multiple transistors, and the increase in the number of transistors results in the need to set a gate driving circuit outputting different control signals in the non-display area, and such a gate driving circuit occupies a large space in the frame. Currently, a CMOS (Complementary Metal Oxide Semiconductor) gate driving circuit (GOA) is proposed to achieve a narrow-frame design.

[0003] The current gate driving circuit has two CMOS GOA circuits to output different Nscan signals to different transistors in the pixel driving circuit, and the two CMOS GOA circuits are usually arranged horizontally in the non-display area, occupying a large space in the frame, which prevents the frame of the display device from being further reduced. SUMMARY

[0004] Embodiments of the present application provide a display panel and a display device to solve the technical problem of a large frame width of the existing display panel.

[0005] Embodiments of the present application provide a display panel, which includes a display area and a non-display area; wherein the display panel includes:

[0006] a gate driving circuit arranged in the non-display area, the gate driving circuit including a plurality of cascaded gate driving units arranged along a first direction;

[0007] a pixel driving circuit arranged in the display area, the pixel driving circuit including a compensation transistor and a first reset transistor connected in series;

[0008] wherein the gate driving unit includes a first gate circuit and a second gate circuit arranged along the first direction, an output end of the first gate circuit is connected to the compensation transistor, and an output end of the second gate circuit is connected to the first reset transistor.

[0009] Meanwhile, embodiments of the present application provide a display device including the above display panel.

[0010] Other features and advantages of the present application will be described in detail in the following specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0011] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0013] FIG. 1 This is a first structural diagram of the display panel of this application.

[0014] FIG. 2 This is a structural diagram of the pixel driving circuit in the display panel of this application.

[0015] FIG. 3 This is a second structural diagram of the display panel in this application.

[0016] FIG. 4 This is a structural diagram of the gate driving circuit in the display panel of this application.

[0017] FIG. 5 This is a diagram of the film structure in the display panel of this application.

[0018] FIG. 6 This is a film stacking diagram of the first gate circuit or the second gate circuit in the gate drive circuit of this application;

[0019] FIG. 7 for FIG. 6 The pattern of the first gate layer of the signal generation module.

[0020] FIG. 8 for FIG. 6 The pattern of the first gate layer of the first output module.

[0021] FIG. 9 for FIG. 6 The pattern of the first gate layer of the second output module.

[0022] FIG. 10 for FIG. 6 The pattern of the first active layer of the signal generation module.

[0023] FIG. 11 for FIG. 6 The pattern of the first active layer of the first output module.

[0024] FIG. 12 for FIG. 6 The pattern of the first active layer of the second output module.

[0025] FIG. 13 The pattern of the second gate layer of the signal generation module. FIG. 6

[0026] FIG. 14 The pattern of the second gate layer of the signal generation module. FIG. 6

[0027] The pattern of the second gate layer of the signal generation module. FIG. 15 FIG. 6 The pattern of the second gate layer of the signal generation module.

[0028] FIG. 16 FIG. 6 The pattern of the second gate layer of the signal generation module.

[0029] FIG. 17 The pattern of the second gate layer of the signal generation module. FIG. 6

[0030] The pattern of the second gate layer of the signal generation module. FIG. 18 FIG. 6 The pattern of the second gate layer of the signal generation module.

[0031] FIG. 19 FIG. 6 The pattern of the second gate layer of the signal generation module.

[0032] FIG. 20 The pattern of the second gate layer of the signal generation module. FIG. 6

[0033] The pattern of the second gate layer of the signal generation module. FIG. 21 FIG. 6 The pattern of the second gate layer of the signal generation module.

[0034] FIG. 22 FIG. 6 The pattern of the second gate layer of the signal generation module.

[0035] FIG. 23 The pattern of the second gate layer of the signal generation module. FIG. 6

[0036] The pattern of the second gate layer of the signal generation module. FIG. 24 FIG. 6 The pattern of the second gate layer of the signal generation module.

[0037] FIG. 25 FIG. 6 The pattern of the second gate layer of the signal generation module. ​​​​​​​​​

[0038] FIG. 26 for FIG. 6 a pattern of the first source-drain layer of the second output module.

[0039] FIG. 27 for FIG. 6 a stack pattern of the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source-drain layer of the signal generation module.

[0040] FIG. 28 for FIG. 6 a stack pattern of the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source-drain layer of the first output module.

[0041] FIG. 29 for FIG. 6 a stack pattern of the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source-drain layer of the second output module.

[0042] FIG. 30 for FIG. 6 a pattern of the second source-drain layer of the signal generation module.

[0043] FIG. 31 for FIG. 6 a pattern of the second source-drain layer of the first output module.

[0044] FIG. 32 for FIG. 6 a pattern of the second source-drain layer of the second output module.

[0045] FIG. 33 for FIG. 6 a stack pattern of the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source-drain layer, and the second source-drain layer of the signal generation module.

[0046] FIG. 34 for FIG. 6 a stack pattern of the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source-drain layer, and the second source-drain layer of the first output module.

[0047] FIG. 35 for FIG. 1 to FIG. 35 a stack pattern of the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source-drain layer, and the second source-drain layer of the second output module. DETAILED DESCRIPTION

[0048] With reference to the drawings of the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative effort belong to the protection scope of the present application.

[0049] With reference to FIG. 1 The present application provides a display panel 100, comprising a display area AA and a non-display area NA, the display panel 100 comprising a gate drive circuit 300 and a pixel drive circuit PC, the gate drive circuit 300 being arranged in the non-display area NA, and the pixel drive circuit PC being arranged in the display area AA.

[0050] In the embodiment, the gate drive circuit 300 comprises a plurality of cascaded gate drive units 300a arranged along a first direction X, and the pixel drive circuit PC comprises a compensation transistor T3A and a first reset transistor T4A connected in series.

[0051] In the embodiment, the gate drive unit 300a comprises a first gate circuit 210 and a second gate circuit 220 arranged along the first direction X, the output terminal of the first gate circuit 210 being connected to the compensation transistor T3A, and the second gate circuit 220 being connected to the first reset transistor T4A.

[0052] The present application arranges the first gate circuit 210 connected to the compensation transistor T3A and the second gate circuit 220 connected to the first reset transistor T4A along the first direction X, so that the first gate circuit 210 and the second gate circuit 220 are changed from horizontal arrangement to vertical arrangement, the width of the frame of the product in the horizontal direction is reduced, and the narrow frame design of the product is further realized.

[0053] The technical solutions of the present application will be described in combination with specific embodiments.

[0054] With reference to FIG. 1 The display panel 100 comprises a display area AA and a non-display area NA arranged adjacent to the display area AA, and a plurality of rows of sub-pixels PL are arranged in the display area AA. Optionally, the non-display area NA surrounds the display area AA, so that the display area AA is surrounded by the non-display area NA. The display area AA is an area in the display panel 100 for displaying, and a plurality of display units for displaying are arranged in the display area AA. The non-display area NA can be a frame area of the display panel 100, and functional components for assisting the display units in the display area AA to display can be arranged in the non-display area NA.

[0055] With reference to FIG. 2The lower side of the display area AA is provided with a binding terminal 400, which can be connected with an external circuit, and the binding terminal 400 transmits the signal input by the external circuit to the data wire, so as to drive the display panel 100 to display a picture. For example, the binding terminal 400 can be connected with a chip or a chip on film, etc., and is used to provide power supply and driving signal for the display panel 100.

[0056] In the embodiment, a plurality of light emitting devices LED and pixel driving circuits PC driving the light emitting devices LED can be arranged in an array in the display area AA. The pixel driving circuit PC can be a 7T1C, 7T2C, 8T2C, 8T3C, 8T4C, etc. The present application does not make specific limitation, and the following will be described by taking the 8T2C pixel driving circuit PC as an example.

[0057] Please refer to FIG. 2 The pixel driving circuit PC can include a switch transistor T2A, a driving transistor T1A, a compensation transistor T3A, a first reset transistor T4A, a second reset transistor T7A, a third reset transistor T8A, a first light emitting transistor T5A, a second light emitting transistor T6A, a boost capacitor Cboost and a control capacitor Csta.

[0058] Please refer to FIG. 3The first electrode of the switch transistor T2A is connected to the data signal line Data, the second electrode of the switch transistor T2A is connected to the control node Aa, and the gate of the switch transistor T2A receives the switch control signal PscanA; the first electrode of the drive transistor T1A is connected to the control node Aa, the second electrode of the drive transistor T1A is connected to the control node Ba, and the gate of the drive transistor T1A is connected to the control node Qa; the first electrode of the compensation transistor T3A is connected to the control node Qa, the second electrode of the compensation transistor T3A is connected to the control node Ba, and the gate of the compensation transistor T3A receives the compensation control signal NscanA; the first electrode of the first reset transistor T4A receives the first reset signal Vi1, the second electrode of the first reset transistor T4A is connected to the control node Qa, and the gate of the first reset transistor T4A receives the first reset control signal NscanB; the first electrode of the second reset transistor T7A receives the second reset signal Vi2, the second electrode of the second reset transistor T7A is connected to the anode of the light emitting device, and the gate of the second reset transistor T7A receives the second reset control signal PscanB; the first electrode of the third reset transistor T8A receives the third reset signal Vi3, the second electrode of the third reset transistor T8A is connected to the control node Aa, and the gate of the third reset transistor T8A receives the third reset control signal Vi3; the first electrode of the first light emitting transistor T5A is connected to the high level source VDD, the second electrode of the first light emitting transistor T5A is connected to the control node Aa, and the gate of the first light emitting transistor T5A receives the light emitting control signal EM; the first electrode of the second light emitting transistor T6A is connected to the second node Ba, the second electrode of the second light emitting transistor T6A is connected to the anode of the light emitting device, and the gate of the second light emitting transistor T6A receives the light emitting control signal EM; one end of the boost capacitor Cboost is connected to the control node Qa, and the other end of the boost capacitor Cboost is connected to the gate of the switch transistor T2A; one end of the control capacitor Csta is connected to the control node Qa, and the other end of the control capacitor Csta is connected to the high level source VDD; and the cathode of the light emitting device is connected to the low level source VSS.

[0059] In the embodiment, the high level source VDD is used to provide a constant voltage high level to the pixel driving circuit PC, and the low level source VSS is used to provide a constant voltage low level to the pixel driving circuit PC.

[0060] In the embodiment, the switch transistor T2A, the drive transistor T1A, the second reset transistor T7A, the third reset transistor T8A, the first light-emitting transistor T5A, and the second light-emitting transistor T6A can be one of a P-type transistor and an N-type transistor, and the compensation transistor T3A and the first reset transistor T4A can be the other one of the P-type transistor and the N-type transistor. In the embodiment, the switch transistor T2A, the drive transistor T1A, the second reset transistor T7A, the third reset transistor T8A, the first light-emitting transistor T5A, and the second light-emitting transistor T6A are P-type transistors, and the compensation transistor T3A and the first reset transistor T4A are N-type transistors.

[0061] In the embodiment, the capacitance of the boost capacitor Cboost is smaller than the capacitance of the control capacitor Csta. In the embodiment, the control capacitor Csta is mainly used to maintain the stability of the potential of the third node Qa, and thus the control capacitor Csta has a relatively large capacitance.

[0062] In the embodiment, the first electrode can be one of a source electrode and a drain electrode, and the second electrode can be the other one of the source electrode and the drain electrode.

[0063] In the embodiment, the second direction Y is parallel to the scan lines of the display panel 100, and the included angle between the first direction X and the second direction Y is greater than 0° and less than or equal to 90°.

[0064] Referring to FIG. 3 , the gate drive circuit 300 is arranged in the non-display area NA, and the gate drive circuit 300 can be arranged on both sides of the display area AA. The gate drive circuit 300 can include N gate drive units 300a connected in cascade, and the plurality of gate drive units 300a can be arranged along the first direction X. The structure of the gate drive unit 300a can be various, for example, in the structure of FIG. 3 , the non-display area NA can include a plurality of first gate circuits 210 arranged along the first direction X and connected in cascade, a plurality of second gate circuits 220 arranged along the first direction X and connected in cascade, a plurality of third gate circuits 230 arranged along the first direction X and connected in cascade, and a plurality of fourth gate circuits 240 arranged along the first direction X and connected in cascade.

[0065] Referring to FIG. 3 , the first gate circuit 210 is arranged on one side of the display area AA, and the first gate circuit 210 is used to transmit the compensation control signal NscanA and the switch control signal PscanA to a row of sub-pixels PL.

[0066] Referring to FIG. 3The second gate circuit 220 is arranged at one side of the display area AA, and the first gate circuit 210 and the second gate circuit 220 are arranged alternately along the first direction X. One second gate circuit 220 is used for transmitting the first reset control signal NscanB and the switch control signal PscanA to one row of sub-pixels PL.

[0067] Please refer to FIG. 3 The third gate circuit 230 is arranged at one side of the second gate circuit 220 away from the display area AA. One third gate circuit 230 is used for transmitting the second reset control signal PscanB to two rows of sub-pixels PL, that is, two rows of pixel driving circuits PC need one third gate circuit 230.

[0068] Please refer to FIG. 4 The fourth gate circuit 240 is arranged at one side of the first gate circuit 210 away from the display area AA. The fourth gate circuit 240 is used for transmitting the emission control signal EM to two rows of sub-pixels PL, that is, two rows of pixel driving circuits PC need one fourth gate circuit 240. The fourth gate circuit 240 and the third gate circuit 230 are arranged alternately along the first direction X, that is, the third gate circuit 230 and the second gate circuit 220 can be located in the same row, and the fourth gate circuit 240 and the first gate circuit 210 can be located in the same row.

[0069] It should be noted that the first reset signal Vi1, the second reset signal Vi2 and the third reset signal Vi3 are all constant voltage, and do not need to be controlled by the corresponding gate driving circuit 300, but can be directly connected to the corresponding constant voltage source.

[0070] In the embodiment, the pixel driving circuit PC further includes a first emission transistor T5A and a second reset transistor T7A connected in series. The fourth gate circuit 240 is connected to one of the first emission transistor T5A and the second reset transistor T7A, and the third gate circuit 230 is connected to the other one of the first emission transistor T5A and the second reset transistor T7A. For example, the fourth gate circuit 240 of the present application can be connected to the gate of the first emission transistor T5A, and the third gate circuit 230 can be connected to the gate of the second reset transistor T7A.

[0071] It should be noted that the fourth gate circuit 240 can be connected to the gate of the second emission transistor T6A.

[0072] In the embodiment, the first gate circuit 210, the second gate circuit 220, the third gate circuit 230 and the fourth gate circuit 240 of the present application can be mTnC gate circuits.

[0073] It should be noted that the circuit structures of the first gate circuit 210 and the second gate circuit 220 of the present application can be the same, and only the received control signals are different.

[0074] For example, refer to FIG. 4 , the first gate circuit 210 and the second gate circuit can each include a signal generation module 310 connected, a second output module 320 and a first output module 330, the signal generation module 310 is connected with the first type clock line NCK, the first output module 330 is connected with the signal generation module 310, the second output module 320 is connected with the second type clock line PCK and the signal generation module 310, the first output module 330 is configured to output the first gate control signal according to the signal output by the signal generation module 310, the effective level of the first gate control signal is high, the second output module 320 is configured to output the second gate control signal according to the second type clock line PCK and the signal output by the signal generation module 310, the effective level of the second gate control signal is low.

[0075] In the embodiment, the first output module 330 and the second output module 320 are arranged on both sides of the signal generation module 310 along the second direction Y, and the second output module 320 is arranged close to the display area AA of the display panel 100.

[0076] For example, refer to FIG. 6 , FIG. 33 and FIG. 4 , the signal generation module 310 includes a signal level transmission module 310a, a first frequency division unit 316a and a second frequency division unit 316b, the first frequency division unit 316a and the second frequency division unit 316b are arranged on both sides of the signal level transmission module 310a along the second direction Y.

[0077] In the embodiment, the first frequency division unit 316a is arranged adjacent to the first output module 330, the second frequency division unit 316b is arranged adjacent to the second output module 320, and the first frequency division unit 316a is connected with the internal node of the first output module 330, the second frequency division unit 316b is connected with the internal node of the second output module 320.

[0078] In the embodiment, the first frequency division unit 316a, the signal level transmission module 310a and the second frequency division unit 316b can be arranged along the second direction Y, replacing the original arrangement of the first frequency division unit 316a and the second frequency division unit 316b along the first direction X, that is, by changing the original longitudinal arrangement of the first frequency division unit 316a and the second frequency division unit 316b to transverse interval arrangement, the size of the signal generation module 310 in the first direction X is reduced, and the size of the signal generation module 310 in the second direction Y is increased, and the first gate circuit 210 and the second gate circuit 220 are arranged along the first direction X, that is, by increasing the size of the first gate circuit 210 and the second gate circuit 220 in the transverse direction, and compressing the size in the longitudinal direction, the original longitudinal space can be arranged with two gate circuits.

[0079] In the embodiment, the first frequency division unit 316a is arranged close to the first output module 330, which reduces the path of the frequency division signal transmitted from the first frequency division unit 316a to the first output module 330, and improves the accuracy of the frequency division signal received by the first output module 330; the second frequency division unit 316b is arranged close to the second output module 320, which reduces the path of the frequency division signal transmitted from the second frequency division unit 316b to the second output module 320, and improves the accuracy of the frequency division signal received by the second output module 320.

[0080] In the embodiment, the first frequency division unit 316a and the second frequency division unit 316b are arranged on both sides of the signal stage transmission module 310a, which increases the spacing of the first frequency division unit 316a and the second frequency division unit 316b, and avoids the problem of interference of the frequency division signals transmitted by the first frequency division unit 316a and the second frequency division unit 316b.

[0081] In the embodiment, although the size of the first gate circuit 210 and the second gate circuit 220 in the lateral direction increases, the increased size is much smaller than the size of the existing first gate circuit 210 or the second gate circuit 220 in the lateral direction; for example, in the prior art, the first gate circuit 210 and the second gate circuit 220 are each provided with a high potential line, a low potential line, a first frequency division signal line NLF, a control signal line CTL, a second frequency division signal line PLF, and a start signal line STV, which extend along the first direction X and are arranged along the second direction Y.

[0082] In the present application, the first gate circuit 210 and the second gate circuit 220 are changed from the original arrangement along the second direction Y to the arrangement along the first direction X, i.e. from the lateral arrangement to the longitudinal arrangement, so that the first gate circuit 210 and the second gate circuit 220 can share the high potential line, the low potential line, the first frequency division signal line NLF, the control signal line CTL, the second frequency division signal line PLF, and the start signal line STV, i.e. the number of the high potential line, the low potential line, the first frequency division signal line NLF, the control signal line CTL, the second frequency division signal line PLF, and the start signal line STV is reduced. By arranging the first gate circuit 210 and the second gate circuit 220 along the first direction X, the narrow frame design of the product is realized.

[0083] Therefore, by adjusting the structure of the first gate circuit 210 and the second gate circuit 220, the first gate circuit 210 and the second gate circuit 220 are arranged along the first direction X, and the narrow frame design of the product is realized; for example, the size of the first gate circuit 210 or the second gate circuit 220 in the second direction Y is reduced by 200 microns compared with the sum of the sizes of the existing first gate circuit 210 and the second gate circuit 220 in the second direction Y.

[0084] Please refer to FIG. 6 , FIG. 33 and FIG. 6 , the signal stage transmission module 310a includes a first control unit 311, a second control unit 312, an output control unit 313, a third control unit 314, a fourth control unit 315, a frequency division module 316, and a reset unit 317, the frequency division module 316 includes a first frequency division unit 316a and a second frequency division unit 316b.

[0085] Please refer to FIG. 33 and FIG. 6 , the first control unit 311 and the second control unit 312 are arranged along the first direction X and are both arranged adjacent to the first frequency division unit 316a, that is, the first control unit 311 is arranged along the second direction Y with the first frequency division unit 316a, and the second control unit 312 is arranged along the second direction Y with the first frequency division unit 316a.

[0086] Please refer to FIG. 33 and FIG. 6 , the third control unit 314, the output control unit 313, and the fourth control unit 315 are arranged along the second direction Y, the third control unit 314 is arranged close to the second control unit 312, the fourth control unit 315 is arranged close to the first type clock line NCK, and the reset unit 317 is arranged between the first type clock line NCK and the first control unit 311.

[0087] In this embodiment, due to the transmission line connection of the seventeenth transistor T17 and the transmission node W, the transmission line connection of the fourth transistor T4 and the transmission node K, and the transmission line connection of the twenty-first transistor T21 and the transmission node M, in order to avoid the overlapping of the transmission line of the transmission node W, the transmission line of the transmission node M, and the transmission line of the transmission node K, the third control unit 314, the output control unit 313, and the fourth control unit 315 are arranged along the second direction Y in sequence.

[0088] Please refer to FIG. 33 and FIG. 6 , the first type clock line NCK includes a plurality of control clock lines arranged along the second direction Y, the second type clock line PCK includes a plurality of output clock lines arranged along the second direction Y, the plurality of clock control lines are arranged between the signal stage transmission module 310a and the second frequency division unit 316b, and the plurality of output control lines are arranged between the second frequency division unit 316b and the first output module 330.

[0089] Please refer to FIG. 33 and FIG. 4The first type clock line NCK includes the first control clock line NCK1, the second control clock line NCK2, the third control clock line NCK3, and the fourth control clock line NCK4 arranged at intervals, the second type clock line PCK includes the first output clock line PCK1, the second output clock line PCK2, the third output clock line PCK3, and the fourth output clock line PCK4 arranged at intervals, and the first type clock line NCK and the signal generation module 310 are not arranged in overlap, and the second type clock line PCK and the signal generation module 310 are not arranged in overlap, so that the parasitic capacitance of the first type clock line NCK and the second type clock line PCK is reduced, and the voltage stability transmitted by the first type clock line NCK and the second type clock line PCK is improved.

[0090] In the following embodiment, the first gate circuit 210 and the second gate circuit 220 are taken as an example of the 22T3C to describe the structure of the gate drive unit 300a.

[0091] Please refer to FIG. 4 The first control unit 311 includes the thirteenth transistor T13, the twelfth transistor T12, and the second transistor T2. The gate of the thirteenth transistor T13 (including the first gate T13Ga of the thirteenth transistor T13 and the second gate T13Gb of the thirteenth transistor T13) and the gate T12G of the twelfth transistor T12 are connected with the start signal line STV. The drain of the thirteenth transistor T13 is connected with the second low potential signal line NVGL. The drain of the twelfth transistor T12 is connected with the first high potential signal line PVGH. The source of the thirteenth transistor T13 and the source of the twelfth transistor T12 are connected with the drain of the second transistor T2 at the second node O. The gate T2G of the second transistor T2 is connected with the first type clock line NCK. The source of the second transistor T2 is connected with the first node K.

[0092] Please refer to FIG. 4 The second control unit 312 includes the first transistor T1 and the third transistor T3. The gate of the first transistor T1 (including the first gate T1Ga of the first transistor T1 and the second gate T1Gb of the first transistor T1) and the gate T3G of the third transistor T3 are connected with the first node K. The drain T1D of the first transistor T1 is connected with the first low potential signal line PVGL. The drain of the third transistor T3 is connected with the first high potential signal line PVGH. The source of the first transistor T1 and the source of the third transistor T3 are connected with the internal node P(n).

[0093] Please refer to FIG. 4The first output module 330 includes a sixth transistor T6, a seventh transistor T7, a first capacitor C1 and a first output signal line Pout(n), the signal generation module 310 further includes an output control transistor T8, a gate electrode T8G of the output control transistor T8 is connected with the internal node P(n-2) of the upper two-stage gate driving unit 300a, a drain electrode of the output control transistor T8 is electrically connected with the first node K, a source electrode of the output control transistor T8, a first plate C1a of the first capacitor C1 and a gate electrode T6G of the sixth transistor T6 are connected to a third node Q1, a drain electrode of the sixth transistor T6 is connected with the second type clock line PCK, a source electrode of the sixth transistor T6, a source electrode of the seventh transistor T7, a second plate C1b of the first capacitor C1 and the first output signal line Pout(n) are connected, a gate electrode T7G of the seventh transistor T7 is connected with the internal node P(n) of the current-stage gate driving unit 300a, and a drain electrode of the seventh transistor T7 is connected with the first high potential signal line PVGH.

[0094] Please refer to FIG. 4 The output control unit 313 includes a fourth transistor T4, a fifth transistor T5 and a fourteenth transistor T14, a gate electrode (including a first gate electrode T4Ga and a second gate electrode T4Gb of the fourth transistor T4) of the fourth transistor T4 is connected with the first type clock line NCK, a drain electrode of the fourth transistor T4 is connected with the first node K, a source electrode of the fourth transistor T4 is connected with a source electrode of the fifth transistor T5, a gate electrode T5G of the fifth transistor T5 is connected with the internal node P(n), a drain electrode of the fifth transistor T5 is connected with the first high potential signal line PVGH, a gate electrode (including a first gate electrode T14Ga and a second gate electrode T14Gb of the fourteenth transistor T14) of the fourteenth transistor T14 is connected with the internal node P(n), a drain electrode of the fourteenth transistor T14 is connected with the second low potential signal line NVGL, and a source electrode of the fourteenth transistor T14 is connected with the first node K.

[0095] Please refer to FIG. 4 The third control unit 314 includes a seventeenth transistor T17 and an eighteenth transistor T18, a gate electrode (including a first gate electrode T17Ga and a second gate electrode T17Gb of the seventeenth transistor T17) of the seventeenth transistor T17 is connected with the first type clock line NCK, a drain electrode of the seventeenth transistor T17 is electrically connected with the first node K, a source electrode of the seventeenth transistor T17 is connected with a source electrode of the eighteenth transistor T18, a gate electrode T18G of the eighteenth transistor T18 is connected with the internal node P(n), and a drain electrode of the eighteenth transistor T18 is connected with the first high potential signal line PVGH.

[0096] Please refer to FIG. 4The fourth control unit 315 includes a twenty-first transistor T21 and a twenty-second transistor T22. The gate of the twenty-first transistor T21 (including a first gate T21Ga and a second gate T21Gb of the twenty-first transistor T21) is connected with the first type clock line NCK, the drain of the twenty-first transistor T21 is electrically connected with the first node K, the source of the twenty-first transistor T21 is connected with the source of the twenty-second transistor T22, the gate T22G of the twenty-second transistor T22 is connected with the internal node P(n), and the drain of the twenty-second transistor T22 is connected with the first high potential signal line PVGH.

[0097] Referring to FIG. 4 The second output module 320 includes a tenth transistor T10, a ninth transistor T9 and a second output signal line Nout(n). The gate of the tenth transistor T10 (including a first gate T10Ga and a second gate T10Gb of the tenth transistor T10) is connected with the first node K, the drain of the tenth transistor T10 is connected with the second low potential signal line NVGL, the source of the tenth transistor T10, the source of the ninth transistor T9 and the third output signal line Nout(n) are connected, the gate T9G of the ninth transistor T9 is electrically connected with the first node K, and the drain of the ninth transistor T9 is connected with the second high potential signal line NVGH.

[0098] Referring to FIG. 4 The frequency division module 316 includes a first frequency division unit 316a and a second frequency division unit 316b. The first frequency division unit 316a includes a sixteenth transistor T16, an eleventh transistor T11 and a second capacitor C2. The gate T16G of the sixteenth transistor T16 is connected with the internal node P(n) of the gate drive unit 300a of the current stage, the drain of the sixteenth transistor T16 is connected with the first frequency division signal line NLF, the source of the sixteenth transistor T16, the first plate C2a of the second capacitor C2 and the gate T11G of the eleventh transistor T11 are connected, the drain of the eleventh transistor T11 is connected with the first node K, and the source of the eleventh transistor T11 is connected with the second plate C2b of the second capacitor C2 at the fifth node W.

[0099] Referring to FIG. 4The second frequency division unit 316b comprises a twentieth transistor T20, a nineteenth transistor T19 and a third capacitor C3, the gate electrode T20G of the twentieth transistor T20 is connected to the internal node P(n) of the gate drive unit 300a of the current stage, the drain electrode of the twentieth transistor T20 is connected to the second frequency division signal line PLF, the source electrode of the twentieth transistor T20, the gate electrode T19G of the nineteenth transistor T19 and the first plate C3a of the third capacitor C3 are connected, the drain electrode of the nineteenth transistor T19 is connected to the first node K, and the source electrode of the nineteenth transistor T19 is connected to the second plate of the third capacitor C3.

[0100] Please refer to FIG. 4 The reset unit 317 comprises a fifteenth transistor T15, the gate electrode T15G of the fifteenth transistor T15 is connected to the control signal line CTL, the drain electrode of the fifteenth transistor T15 is connected to the first high potential signal line PVGH, and the source electrode of the fifteenth transistor T15 is connected to the first node K.

[0101] Specifically, the twelfth transistor T12, the second transistor T2, the third transistor T3, the eighteenth transistor T18, the twenty-second transistor T22, the sixth transistor T6, the seventh transistor T7, the ninth transistor T9, the output control transistor T8, the fifth transistor T5, the sixteenth transistor T16, the eleventh transistor T11, the twentieth transistor T20, the nineteenth transistor T19 and the fifteenth transistor T15 are P-type transistors; the thirteenth transistor T13, the first transistor T1, the seventeenth transistor T17, the twenty-first transistor T21, the fourth transistor T4, the fourteenth transistor T14 and the tenth transistor T10 are N-type transistors.

[0102] Specifically, the twelfth transistor T12, the second transistor T2, the third transistor T3, the eighteenth transistor T18, the twenty-second transistor T22, the sixth transistor T6, the seventh transistor T7, the ninth transistor T9, the output control transistor T8, the fifth transistor T5, the sixteenth transistor T16, the eleventh transistor T11, the twentieth transistor T20, the nineteenth transistor T19 and the fifteenth transistor T15 are silicon semiconductor transistors; the thirteenth transistor T13, the first transistor T1, the seventeenth transistor T17, the twenty-first transistor T21, the fourth transistor T4, the fourteenth transistor T14 and the tenth transistor T10 are oxide semiconductor transistors.

[0103] Specifically, the oxide semiconductor transistor can be a metal oxide transistor, and the silicon semiconductor transistor can be a low-temperature polysilicon transistor.

[0104] In the embodiment, the first type of clock line NCK can be one of the first control clock line NCK1, the second control clock line NCK2, the third control clock line NCK3, and the fourth control clock line NCK4, and the second type of output clock line PCK can be one of the first output clock line PCK1, the second output clock line PCK2, the third output clock line PCK3, and the fourth output clock line PCK4. For example, refer to FIG. 5 , the first type of clock line NCK can be the first control clock line NCK1, and the second type of output clock line PCK can be the first output clock line PCK1; or the first type of clock line NCK can be the second control clock line NCK2, and the second type of output clock line PCK can be the second output clock line PCK2; or the first type of clock line NCK can be the third control clock line NCK3, and the second type of output clock line PCK can be the third output clock line PCK3; or the first type of clock line NCK can be the fourth control clock line NCK4, and the second type of output clock line PCK can be the fourth output clock line PCK4.

[0105] It should be noted that some of the transistors in the present application are designed with a single gate, and some are designed with a double gate. For the transistors designed with a single gate, the gate is the only gate. For the transistors designed with a double gate, the gate refers to the bottom gate and the top gate. For example, the thirteenth transistor is designed with a double gate, and the gate of the thirteenth transistor refers to the first gate and the second gate of the thirteenth transistor. Similarly, the gate of other transistors can be described by referring to the description of the above transistors, which will not be described again in the following embodiments.

[0106] The following describes the film layers of the display panel 100 according to the structure of FIG. 5 .

[0107] Please refer to FIG. 5 , the display area AA and the non-display area NA of the display panel 100 can be provided with a substrate 110 and an array driving layer 120 disposed on the substrate 110. In the display area AA, the display panel 100 can further be provided with a pixel definition layer disposed on the array driving layer 120, a light emitting device layer disposed in the same layer as the pixel definition layer, and an encapsulation layer disposed on the pixel definition layer. The following mainly describes the film layer structure in the non-display area NA.

[0108] In the embodiment, the substrate 110 supports each layer disposed on the substrate 110. When the display panel 100 is a bottom emission light emitting display device or a double-sided emission light emitting display device, a transparent substrate is used. When the display panel 100 is a top emission light emitting display device, a semi-transparent or opaque substrate and a transparent substrate can be used.

[0109] In the present embodiment, the substrate 110 is used to support various film layers provided on the substrate 110, and the substrate 110 can be made of an insulating material such as glass, quartz, or a polymer resin. The substrate 110 can be a rigid substrate or a flexible substrate that can be bent, folded, rolled, or the like. Examples of a flexible material for the flexible substrate include polyimide (PI), but are not limited to polyimide (PI).

[0110] In the present embodiment, the substrate 110 can include a first flexible base 111, a first barrier layer 112, a second flexible base 113, and a second barrier layer 114, which are stacked, the first and second flexible bases 111 and 113 can be formed of the same material such as polyimide, and the first and second barrier layers 112 and 114 can be formed of an inorganic material including at least one of SiOx and SiNx, for example.

[0111] In the present embodiment, the first flexible base 111 is formed by coating a polymer material on a support base (not shown) and then curing the polymer material, the second flexible base 113 is formed by coating the same material as that of the first flexible base 111 and curing the material, and the second flexible base 113 is formed by the same method as that of forming the first flexible base 111. Each of the first and second flexible bases 111 and 113 can be formed to have a thickness of about 8 μm to about 12 μm. In addition, when the substrate 110 is formed of the first and second flexible bases 111 and 113, small holes, cracks, or the like formed during the manufacturing of the first flexible base 111 are covered by the second flexible base 113, so that the above-described defects can be removed.

[0112] Referring to FIG. 1, FIG. 2 The array driving layer 120 can include a plurality of thin film transistors, which can be of an etch barrier type, a back channel etch type, or divided into a bottom gate thin film transistor, a top gate thin film transistor, or the like according to the position of a gate and an active layer, or divided into an N-type thin film transistor, a P-type thin film transistor according to the performance of the thin film transistor; wherein, FIG. 5 The thin film transistor in FIG. 1 does not represent a structure diagram of any transistor in FIG. 1, but is only a schematic diagram of each film layer of the display panel 100 of the present application. FIG. 5

[0113] Referring to FIG. 1, FIG. 5 ​The array driving layer 120 may include a light-shielding layer 121 disposed on the substrate 110, a buffer layer 122 disposed on the light-shielding layer 121, a first active layer 123 disposed on the buffer layer 122, a first gate insulating layer 124 disposed on the first active layer 123, a first gate layer 125 disposed on the first gate insulating layer 124, a second gate insulating layer 126 disposed on the first gate layer 125, a second gate layer 127 disposed on the second gate insulating layer 126, and a third gate insulating layer 128 disposed on the second gate layer 127. The third active layer 129 is disposed on the third gate insulating layer 128, the fourth gate insulating layer 130 is disposed on the second active layer 129, the third gate layer 131 is disposed on the fourth gate insulating layer 130, the first inter-insulating layer 132 is disposed on the third gate layer 131, the first source-drain layer 133 is disposed on the first inter-insulating layer 132, the second inter-insulating layer 134 is disposed on the first source-drain layer 133, the second source-drain layer 135 is disposed on the second inter-insulating layer 134, and the planarization layer 136 is disposed on the second source-drain layer 135.

[0114] Please see FIG. 5 The light-shielding layer 121 is disposed on the second barrier layer 114. The light-shielding layer 121 is used to block external light from entering the thin film transistor from the bottom. The material of the light-shielding layer 121 can be made of black light-shielding material, such as black light-shielding metal or black organic material.

[0115] Please see FIG. 5 A buffer layer 122 is disposed on the light-shielding layer 121. The buffer layer 122 is used to isolate the light-shielding layer 121 from the upper metal material. The material of the buffer layer 122 may be composed of a compound consisting of nitrogen, silicon and oxygen elements, such as a single layer of silicon oxide film or a stacked structure of silicon oxide and silicon nitride.

[0116] Please see FIG. 5 The first active layer 123 is disposed on the buffer layer 122, and the second active layer 129 can be disposed on the third gate insulating layer 128. The materials of the first active layer 123 and the second active layer 129 can be indium gallium zinc oxide semiconductor, amorphous silicon or low temperature polycrystalline silicon. For example, in this application, the material of the first active layer 123 can be low temperature polycrystalline silicon, and the material of the second active layer 129 can be indium gallium zinc oxide semiconductor.

[0117] Please see FIG. 5The first gate insulating layer 124, the second gate insulating layer 126, the third gate insulating layer 128, the fourth gate insulating layer 130, the first interlayer insulating layer 132 and the second interlayer insulating layer 134 are respectively arranged on the corresponding metal layer or semiconductor layer, and are arranged in different layers of metal layer or semiconductor layer; the materials of the first gate insulating layer 124, the second gate insulating layer 126, the first interlayer insulating layer 132, the third gate insulating layer 128, the fourth gate insulating layer 130 and the second interlayer insulating layer 134 can be inorganic materials combined with silicon and oxygen or organic materials with flatness.

[0118] Referring to FIG. 5 The first gate layer 125, the second gate layer 127 and the third gate layer 131 are respectively arranged on the corresponding insulating layer, and the materials of the first gate layer 125, the second gate layer 127 and the third gate layer 131 can be conductive materials such as copper, molybdenum or molybdenum-titanium alloy.

[0119] Referring to FIG. 7 to FIG. 9 The first source-drain layer 133 is arranged on the first interlayer insulating layer 132, and the second source-drain layer 135 is arranged on the second interlayer insulating layer 134; the materials of the first source-drain layer 133 and the second source-drain layer 135 can be conductive materials such as titanium-aluminum-titanium, copper, molybdenum or molybdenum-titanium alloy.

[0120] Referring to FIG. 7 to FIG. 9 The planarization layer 136 is arranged in a whole layer to ensure the flatness of the film layer of the array driving layer 120; the material of the planarization layer 136 can be inorganic materials combined with silicon and oxygen or organic materials with flatness.

[0121] Referring to FIG. 7 to FIG. 9 The first gate layer 125 includes the gate T12G of the twelfth transistor T12, the gate T2G of the second transistor T2, the gate T3G of the third transistor T3, the gate T18G of the eighteenth transistor T18, the gate T22G of the twenty-second transistor T22, the gate T6G of the sixth transistor T6, the gate T7G of the seventh transistor T7, the gate T9G of the ninth transistor T9, the gate T8G of the output control transistor T8, the gate T5G of the fifth transistor T5, the gate T16G of the sixteenth transistor T16, the gate T11G of the eleventh transistor T11, the gate T20G of the twentieth transistor T20, the gate T19G of the nineteenth transistor T19, the gate T15G of the fifteenth transistor, the first plate C1a of the first capacitor C1, the first plate C2a of the second capacitor C2 and the first plate C3a of the third capacitor C3.

[0122] Referring to FIG. 7 to FIG. 9The first plate C1a of the first capacitor C1 is connected with the gate T6G of the sixth transistor T6, the first plate C3a of the third capacitor C3 is connected with the gate T19G of the nineteenth transistor T19, and the first plate C2a of the second capacitor C2 is connected with the gate T11G of the eleventh transistor T11.

[0123] Referring to FIG. 7 to FIG. 9 The gate T18G of the eighteenth transistor T18, the gate T5G of the fifth transistor T5, and the gate T22G of the twenty-second transistor T22 are arranged along the second direction Y and are connected.

[0124] Referring to FIG. 7 to FIG. 9 The first gate layer 125 further includes a first transfer segment ET1, a second transfer segment ET2, a third transfer segment ET3, a fourth transfer segment ET4, and a fifth transfer segment ET5. The first transfer segment ET1, the second transfer segment ET2, and the third transfer segment ET3 extend along the second direction Y, and the fourth transfer segment ET4 and the fifth transfer segment ET5 extend along the first direction X.

[0125] One end of the first transfer segment ET1 is connected with the gate T22G of the twenty-second transistor T22, the other end of the first transfer segment ET1 is connected with the gate T7G of the seventh transistor T7, and the gate T20G of the twentieth transistor T20 is connected with a middle segment of the first transfer segment ET1. The second transfer segment ET2 is used to connect the twenty-first transistor T21 and the output control transistor T8 to transmit the signal of the node M. The third transfer segment ET3 and the fourth transfer segment ET4 are connected and used to transmit the signal of the node K. One end of the fifth transfer segment ET5 is connected with the gate T8G of the output control transistor T8, and the other end of the fifth transfer segment ET5 is connected with the signal of the node P(n-1) of the upper two stages.

[0126] In the embodiment, the output control transistor T8 is arranged between the second frequency division unit 316b and the second type clock line NCK, and the output control transistor T8 is a double-gate structure.

[0127] Referring to FIG. 7 to FIG. 9 The gate T8G of the output control transistor T8 includes two branch electrodes arranged at intervals, and the two branch electrodes are connected, that is, the gate T8G of the output control transistor T8 can be in a U shape. In the embodiment, since the output control transistor T8 is used to control the potential of the gate T6G of the sixth transistor T6, in order to ensure the accuracy of the potential of the gate T6G of the sixth transistor T6, the gate T8G of the output control transistor T8 of the present application adopts a double-gate structure, which reduces the leakage current of the output control transistor T8.

[0128] Referring to FIG. 7 to FIG. 9Since the ninth transistor T9 is used for outputting the NscanA or NscanB signal, and the gate T6G of the sixth transistor T6 is used for outputting the PscanA signal, the area of the gate T9G of the ninth transistor T9 and the area of the gate T6G of the sixth transistor T6 are both larger than the area of the gate of other transistors that are not used for outputting a load, for example, the area of the sixth transistor T6 is larger than the area of the seventh transistor T7.

[0129] In this embodiment, the area of the tenth transistor T10 is larger than the area of the ninth transistor T9, although the ninth transistor T9 is used for outputting a load to a sub-pixel, the tenth transistor T10 of the present application is an oxide transistor, that is, the mobility of the tenth transistor T10 is small, and in order to improve the mobility of the tenth transistor T10, the area of the tenth transistor T10 is increased to ensure the mobility of the tenth transistor T10.

[0130] Please refer to FIG. 10 to FIG. 12 The gate T9G of the ninth transistor T9, the gate T6G of the sixth transistor T6, and the gate T7G of the seventh transistor T7 all include branch gates extending along the second direction Y; for example, the gate T9G of the ninth transistor T9 and the gate T7G of the seventh transistor T7 both include one branch gate arranged along the first direction X and spaced apart, and the gate T6G of the sixth transistor T6 includes four branch gates arranged along the first direction X and spaced apart.

[0131] Please refer to FIG. 10 to FIG. 12 The spacing between the gate T7G of the seventh transistor T7 and the branch gate of the sixth transistor T6 can be equal to the spacing between two adjacent branch gates of the sixth transistor T6.

[0132] Please refer to FIG. 21 to FIG. 23 The first active layer 123 includes the active pattern T12A of the twelfth transistor T12, the active pattern T2A of the second transistor T2, the active pattern T3A of the third transistor T3, the active pattern T18A of the eighteenth transistor T18, the active pattern T22A of the twenty-second transistor T22, the active pattern T6A of the sixth transistor T6, the active pattern T7A of the seventh transistor T7, the active pattern T9A of the ninth transistor T9, the active pattern T8A of the output control transistor T8, the active pattern T5A of the fifth transistor T5, the active pattern T16A of the sixteenth transistor T16, the active pattern T11A of the eleventh transistor T11, the active pattern T20A of the twentieth transistor T20, the active pattern T19A of the nineteenth transistor T19, and the active pattern T15A of the fifteenth transistor.

[0133] Please refer to FIG. 21 to FIG. 23The active pattern T6A of the sixth transistor T6 and the active pattern T7A of the seventh transistor T7 are connected, the active pattern T6A of the sixth transistor T6, the active pattern T7A of the seventh transistor T7 and the active pattern T9A of the ninth transistor T9 each include at least two active sub-pattems arranged at intervals along the second direction Y, and the active sub-pattems of the sixth transistor T6 and the seventh transistor T7 are connected in the first direction X.

[0134] Please refer to FIG. 10 to FIG. 12 The active pattern T12A of the twelfth transistor T12 and the gate T12G of the twelfth transistor T12 have an overlapping portion, the active pattern T2A of the second transistor T2 and the gate T2G of the second transistor T2 have an overlapping portion, the active pattern T3A of the third transistor T3 and the gate T3G of the third transistor T3 have an overlapping portion, the active pattern T18A of the eighteenth transistor T18 and the gate T18G of the eighteenth transistor T18 have an overlapping portion, the active pattern T22A of the twenty-second transistor T22 and the gate T22G of the twenty-second transistor T22 have an overlapping portion, the active pattern T6A of the sixth transistor T6 and the gate T6G of the sixth transistor T6 have an overlapping portion, the active pattern T7A of the seventh transistor T7 and the gate T7G of the seventh transistor T7 have an overlapping portion, the active pattern T9A of the ninth transistor T9 and the gate T9G of the ninth transistor T9 have an overlapping portion, the active pattern T8A of the output control transistor T8 and the gate T8G of the output control transistor T8 have an overlapping portion, the active pattern T5A of the fifth transistor T5 and the gate T5G of the fifth transistor T5 have an overlapping portion, the active pattern T16A of the sixteenth transistor T16 and the gate T16G of the sixteenth transistor T16 have an overlapping portion, the active pattern T11A of the eleventh transistor T11 and the gate T11G of the eleventh transistor T11 have an overlapping portion, the active pattern T20A of the twentieth transistor T20 and the gate T20G of the twentieth transistor T20 have an overlapping portion, the active pattern T19A of the nineteenth transistor T19 and the gate T19G of the nineteenth transistor T19 have an overlapping portion, the active pattern T15A of the fifteenth transistor T15 and the gate T15G of the fifteenth transistor T15 have an overlapping portion, and the above-mentioned overlapping portions correspond to the channels of the transistors.

[0135] Please refer to FIG. 10 to FIG. 12Since the length of the gate T9G of the ninth transistor T9, the gate T6G of the sixth transistor T6, and the gate T7G of the seventh transistor T7 along the second direction Y is relatively long, that is, the channel width of the transistors is increased, in order to further increase the channel width of the transistors, the size of the active pattern T25A of the active pattern T6A of the sixth transistor T6, the active pattern T7A of the seventh transistor T7, and the active pattern T9A of the ninth transistor T9 along the second direction Y can be increased as much as possible; however, since the size of the low-temperature polysilicon semiconductor along the second direction Y is too large, the active part will have a problem of static electricity concentration, which will cause the active part to be damaged by static electricity, and therefore the structure of the active pattern T6A of the sixth transistor T6, the active pattern T7A of the seventh transistor T7, and the active pattern T9A of the ninth transistor T9 can be arranged as a plurality of sub-active parts arranged at intervals.

[0136] Referring to FIG. 13 to FIG. 15 , the width of the sub-active part in the active pattern T6A of the sixth transistor T6 and the active pattern T7A of the seventh transistor T7 can be the same.

[0137] Referring to FIG. 13 to FIG. 15 , the width of the active pattern T12A of the twelfth transistor T12 along the second direction Y is greater than that of the transistors other than the sixth transistor T6, the seventh transistor T7, the tenth transistor T10, and the ninth transistor T9. Since the twelfth transistor T12 is used to regulate the potential of the node O, the fluctuation of the potential of the node O is positively correlated with the potential of the node K, and therefore in order to ensure the accuracy of the potential of the node K, the width of the active pattern T12A of the twelfth transistor T12 is increased to improve the mobility of the twelfth transistor T12.

[0138] Referring to FIG. 21 to FIG. 23 , the second gate layer 127 includes the first gate T13Ga of the thirteenth transistor T13, the first gate T1Ga of the first transistor T1, the first gate T17Ga of the seventeenth transistor T17, the first gate T21Ga of the twenty-first transistor T21, the first gate T4Ga of the fourth transistor T4, the first gate T14Ga of the fourteenth transistor T14, the first gate T10Ga of the tenth transistor T10, the second plate C1b of the first capacitor C1, the second plate C2b of the second capacitor C2, and the second plate C3b of the third capacitor C3.

[0139] Referring to FIG. 21 to FIG. 23 , the first gate T17Ga of the seventeenth transistor T17, the first gate T4Ga of the fourth transistor T4, and the first gate T21Ga of the twenty-first transistor T21 are arranged along the second direction Y and connected to each other.

[0140] Referring to FIG. 13 to FIG. 15The second plate C1b of the first capacitor C1 is arranged corresponding to the first plate C1a of the first capacitor C1, the second plate C2b of the second capacitor C2 is arranged corresponding to the second plate C2a of the second capacitor C2, and the second plate C3b of the third capacitor C3 is arranged corresponding to the first plate C3a of the third capacitor C3.

[0141] In this embodiment, the area of the second plate C1b of the first capacitor C1 is greater than the area of the first plate C1a of the first capacitor C1, the area of the second plate C2b of the second capacitor C2 is greater than the area of the second plate C2a of the second capacitor C2, and the area of the second plate C3b of the third capacitor C3 is greater than the area of the first plate C3a of the third capacitor C3.

[0142] Please refer to FIG. 21 to FIG. 23 The first gate T10Ga of the tenth transistor T10 includes a plurality of branch gates arranged at intervals, and the interval of adjacent two branch gates is the same.

[0143] In this embodiment, in the second direction Y, the total length of the first gate T10Ga of the tenth transistor T10 is greater than the total length of the gate T9G of the ninth transistor T9, that is, the sum of the total lengths of the branch gates in the tenth transistor T10 is greater than the sum of the total lengths of the branch gates in the ninth transistor T9.

[0144] Since the tenth transistor T10 is a metal oxide semiconductor transistor with low mobility, in order to improve the driving capability of the tenth transistor T10, the total length of the branch gates in the tenth transistor T10 is increased, that is, the channel width of the tenth transistor T10 is increased, the electron mobility in the tenth transistor T10 is improved, and the driving capability of the tenth transistor T10 is ensured.

[0145] Please refer to FIG. 13 to FIG. 15 , FIG. 21 to FIG. 23 The second gate layer 127 further includes a sixth transmission segment ET6, one end of the sixth transmission segment ET6 is connected with the second plate C2b of the second capacitor C2, and the other end of the sixth transmission segment ET6 is connected with the seventeenth transistor T17, that is, the sixth transmission segment ET6 is used for transmitting the signal of the node M.

[0146] Please refer to FIG. 16 to FIG. 17 , FIG. 21 to FIG. 23 The second gate layer 127 further includes a seventh transmission segment ET7, the seventh transmission segment ET7 is connected with the output end of the third gate circuit 230 or the fourth gate circuit 240, so as to transmit the control signal to the display area AA.

[0147] Please refer to FIG. 18 to FIG. 20The second active layer 129 includes an active pattern T13A of the thirteenth transistor T13, an active pattern T1A of the first transistor T1, an active pattern T17A of the seventeenth transistor T17, an active pattern T21A of the twenty-first transistor T21, an active pattern T4A of the fourth transistor T4, an active pattern T14A of the fourteenth transistor T14, and an active pattern T10A of the tenth transistor T10.

[0148] Referring to FIG. 21 to FIG. 23 The active pattern T13A of the thirteenth transistor T13 has an overlapping portion with the first gate T13Ga of the thirteenth transistor T13, the active pattern T1A of the first transistor T1 has an overlapping portion with the first gate T1Ga of the first transistor T1, the active pattern T17A of the seventeenth transistor T17 has an overlapping portion with the first gate T17Ga of the seventeenth transistor T17, the active pattern T21A of the twenty-first transistor T21 has an overlapping portion with the first gate T21Ga of the twenty-first transistor T21, the active pattern T4A of the fourth transistor T4 has an overlapping portion with the first gate T4Ga of the fourth transistor T4, the active pattern T14A of the fourteenth transistor T14 has an overlapping portion with the first gate T14Ga of the fourteenth transistor T14, and the active pattern T10A of the tenth transistor T10 has an overlapping portion with the first gate T10Ga of the tenth transistor T10.

[0149] In this embodiment, since the tenth transistor T10 is a metal oxide semiconductor transistor, this type of transistor has the advantage of low leakage current, but has a small mobility, so in order to improve the mobility of the tenth transistor T10, the width of the channel portion in the first active portion T10A needs to be increased, that is, the width of the active pattern T10A of the tenth transistor T10 is increased; at the same time, in order to avoid the technical problem of static electricity concentration of the active pattern T10A of the tenth transistor T10, the active pattern T10A of the tenth transistor T10 is provided as two sub-active portions arranged at intervals.

[0150] At the same time, in order to ensure the output capability of the tenth transistor T10, the area of the tenth transistor T10 can be greater than the area of the ninth transistor T9.

[0151] In this embodiment, since the tenth transistor T10 and the ninth transistor T9 output the NscanA or NscanB signal to the sub-pixel PL, the output load of the tenth transistor T10 and the ninth transistor T9 is greater than the output load of the seventh transistor T7 and the sixth transistor T6, so the area of the tenth transistor T10 of the present application is greater than the area of the seventh transistor T7, and the area of the tenth transistor T10 is greater than the area of the sixth transistor T6.

[0152] Referring to FIG. 21 to FIG. 23The third gate layer 131 includes the second gate T13Gb of the thirteenth transistor T13, the second gate T1Gb of the first transistor T1, the second gate T17Gb of the seventeenth transistor T17, the second gate T21Gb of the twenty-first transistor T21, the second gate T4Gb of the fourth transistor T4, the second gate T14Gb of the fourteenth transistor T14, and the second gate T10Gb of the tenth transistor T10.

[0153] In this embodiment, since the thirteenth transistor T13, the first transistor T1, the seventeenth transistor T17, the twenty-first transistor T21, the fourth transistor T4, the fourteenth transistor T14, and the tenth transistor T10 are all metal-oxide-semiconductor transistors, which have the advantage of low leakage current but the disadvantage of low mobility, this application uses a dual-gate design to improve the mobility of the above transistors.

[0154] Please see FIG. 18 to FIG. 23 The second gate T13Gb of the thirteenth transistor T13 overlaps with the active pattern T13A of the thirteenth transistor T13; the second gate T1Gb of the first transistor T1 overlaps with the active pattern T1A of the first transistor T1; the second gate T17Gb of the seventeenth transistor T17 overlaps with the active pattern T17A of the seventeenth transistor T17; the second gate T21Gb of the twenty-first transistor T21 overlaps with the active pattern T21A of the twenty-first transistor T21; the second gate T4Gb of the fourth transistor T4 overlaps with the active pattern T4A of the fourth transistor T4; the second gate T14Gb of the fourteenth transistor T14 overlaps with the active pattern T14A of the fourteenth transistor T14; and the second gate T10Gb of the tenth transistor T10 overlaps with the active pattern T10A of the tenth transistor T10, and the aforementioned overlapping portions are the channels of the corresponding transistors.

[0155] Please see FIG. 18 to FIG. 23 Since the first gate and the second gate of the thirteenth transistor T13, the first transistor T1, the seventeenth transistor T17, the twenty-first transistor T21, the fourth transistor T4, the fourteenth transistor T14, and the tenth transistor T10 are all located on the upper and lower sides of the corresponding active patterns, and the second gate is used as a mask in the ion doping process of the active patterns of the above transistors.

[0156] Meanwhile, in order to improve the mobility of the thirteenth transistor T13, the first transistor T1, the seventeenth transistor T17, the twenty-first transistor T21, the fourth transistor T4, the fourteenth transistor T14, and the tenth transistor T10, this application can reduce the width of the second gate in the above transistors to reduce the channel length, that is, the width of the second gate of the above transistors is smaller than the width of the first gate.

[0157] Referring to FIG. 18 to FIG. 23 , the third gate layer 131 further comprises an eighth transfer segment ET8, the eighth transfer segment ET8 is in L shape, one end of the eighth transfer segment ET8 is connected to the second gate T10Gb of the tenth transistor T10, the other end of the eighth transfer segment ET8 is connected to the eleventh transistor T11, to transfer the signal of the node K.

[0158] Referring to FIG. 18 to FIG. 23 , the third gate layer 131 further comprises a ninth transfer segment ET9, one end of the ninth transfer segment ET9 is connected to the middle segment of the eighth transfer segment ET8, the other end of the ninth transfer segment ET9 is connected to the second gate T1Gb of the first transistor T1, to transfer the signal of the node K.

[0159] Referring to FIG. 24 to FIG. 29 , the third gate layer 131 further comprises a tenth transfer segment ET10, one end of the tenth transfer segment ET10 is connected to the output end of the ninth transistor T9, to transfer the control signal to the display area AA.

[0160] Referring to FIG. 24 to FIG. 29 , the third gate layer 131 further comprises an eleventh transfer segment ET11, a twelfth transfer segment ET12, a thirteenth transfer segment ET13, a fourteenth transfer segment ET14, a fifteenth transfer segment ET15, a sixteenth transfer segment ET16, which are all used to transfer the control signal of the node P of the gate circuit to the next stage, the next two stages, and the control signals of the node P of the gate circuit transferred by different transfer segments are different.

[0161] Referring to FIG. 24 to FIG. 29 , the first source-drain layer 133 comprises the source T6S of the sixth transistor T6, the drain T6D of the sixth transistor T6, the source T7S of the seventh transistor T7, the drain T7D of the seventh transistor T7, the source T10S of the tenth transistor T10, the drain T10D of the tenth transistor T10, the source T9S of the ninth transistor T9, and the drain T9D of the ninth transistor T9.

[0162] Referring to FIG. 24 to FIG. 29 , the source T6S of the sixth transistor T6, the drain T6D of the sixth transistor T6, the source T7S of the seventh transistor T7, the drain T7D of the seventh transistor T7, the source T10S of the tenth transistor T10, the drain T10D of the tenth transistor T10, and the source T9S of the ninth transistor T9 all comprise branch electrodes extending along the second direction Y and arranged at intervals along the first direction X.

[0163] Referring to FIG. 24 to FIG. 29 , the branch electrodes of the source T6S of the sixth transistor T6 close to the drain T7D of the seventh transistor T7 are shared by the source T6S of the sixth transistor T6 and the source T7S of the seventh transistor T7.

[0164] Referring to FIG. 24 to FIG. 29 , the branch electrode of the gate T9G of the ninth transistor T9 is disposed between the branch electrodes of the source T9S and the drain T9D of the ninth transistor T9 which are arranged at intervals, the branch electrodes of the first and second gates T10Ga and T10Gb of the tenth transistor T10 are disposed between the branch electrodes of the source T10S and the drain T10D of the tenth transistor T10 which are arranged at intervals, the branch electrode of the gate T6G of the sixth transistor T6 is disposed between the branch electrodes of the source T6S and the drain T6D of the sixth transistor T6 which are arranged at intervals, and the branch electrode of the gate T7G of the seventh transistor T7 is disposed between the branch electrodes of the source T7S and the drain T7D of the seventh transistor T7 which are arranged at intervals.

[0165] Referring to FIG. 24 to FIG. 29 , the first source-drain layer 133 includes a first connection segment CT1, one end of the first connection segment CT1 is connected to the fifteenth transfer segment ET15, and the other end of the first connection segment CT1 is connected to the gate T12G of the twelfth transistor T12.

[0166] Referring to FIG. 24 to FIG. 29 , the first source-drain layer 133 includes a second connection segment CT2, one end of the second connection segment CT2 is connected to one end of the active pattern T19A of the nineteenth transistor T19, and the other end of the second connection segment CT2 is connected to one end of the active pattern T15A of the fifteenth transistor T15.

[0167] Referring to FIG. 24 to FIG. 29 , the first source-drain layer 133 includes a third connection segment CT3, one end of the third connection segment CT3 is connected to the other end of the active pattern T15A of the fifteenth transistor T15, and the other end of the third connection segment CT3 is connected to the first first high potential line Pvgh1.

[0168] Referring to FIG. 24 to FIG. 29 , the first source-drain layer 133 includes a fourth connection segment CT4, one end of the fourth connection segment CT4 is connected to one end of the active pattern T2A of the second transistor T2, and the other end of the fourth connection segment CT4 is connected to the first control clock line NCK1.

[0169] Referring to FIG. 24 to FIG. 29 , the first source-drain layer 133 includes a fifth connection segment CT5, one end of the fifth connection segment CT5 is connected to the gate T15G of the fifteenth transistor T15, and the other end of the fifth connection segment CT5 is connected to the control signal line CTL.

[0170] Referring to FIG. 24 to FIG. 29The first source-drain layer 133 includes a sixth connection segment CT6 connecting one end of the first second-low-potential line Nvgl1 and the active pattern T13A of the thirteenth transistor T13.

[0171] Referring to FIG. 24 to FIG. 29 The first source-drain layer 133 includes a seventh connection segment CT7 connecting the gate T12G of the twelfth transistor T12 and the gate T13G of the thirteenth transistor T13.

[0172] Referring to FIG. 24 to FIG. 29 The first source-drain layer 133 includes an eighth connection segment CT8 connecting the other end of the active pattern T2A of the second transistor T2, one end of the active pattern T12A of the twelfth transistor T12, and the other end of the active pattern T13A of the thirteenth transistor T13.

[0173] Referring to FIG. 24 to FIG. 29 The first source-drain layer 133 includes a ninth connection segment CT9 connecting the first first-high-potential line Pvgh1 and the other end of the active pattern T12A of the twelfth transistor T12.

[0174] Referring to FIG. 24 to FIG. 29 The first source-drain layer 133 includes a tenth connection segment CT10 connecting one end of the active pattern T16A of the sixteenth transistor T16 and the first frequency-divided signal line NLF.

[0175] Referring to FIG. 24 to FIG. 29 The first source-drain layer 133 includes an eleventh connection segment CT11 connecting one end of the active pattern T3A of the third transistor T3 and the first first-high-potential line Pvgh1.

[0176] Referring to FIG. 24 to FIG. 29 The first source-drain layer 133 includes a twelfth connection segment CT12 connecting the other end of the active pattern T16A of the sixteenth transistor T16 and the first plate C2a of the second capacitor C2.

[0177] Referring to FIG. 24 to FIG. 29 The first source-drain layer 133 includes a thirteenth connection segment CT13 connecting the second plate C2b of the second capacitor C2, one end of the active pattern T11A of the eleventh transistor T11, and the gate T9G of the ninth transistor T9.

[0178] Referring to FIG. 24 to FIG. 29 The first source-drain layer 133 includes a fourteenth connection segment CT14 connecting the other end of the active pattern T11A of the eleventh transistor T11 and the eighth transfer segment ET8.

[0179] Referring to FIG. 24 to FIG. 29 , the first source-drain layer 133 includes a fifteenth connection segment CT15 connecting a gate T16G of the sixteenth transistor T16, the other end of the active pattern T3A of the third transistor T3, the one end of the active pattern T1A of the first transistor T1, a gate T14G of the fourteenth transistor T14, and a gate T18G of the eighteenth transistor T18.

[0180] Referring to FIG. 24 to FIG. 29 , the first source-drain layer 133 includes a sixteenth connection segment CT16 connecting the other end of the active pattern T1A of the first transistor T1 and the first first low potential line Pvgl1.

[0181] Referring to FIG. 24 to FIG. 29 , the first source-drain layer 133 includes a seventeenth connection segment CT17 connecting a gate T3G of the third transistor T3, a gate T1G of the first transistor T1, the one end of the active pattern T14A of the fourteenth transistor T14, the other end of the active pattern T2A of the second transistor T2, and the third transfer segment ET3.

[0182] Referring to FIG. 24 to FIG. 29 , the first source-drain layer 133 includes an eighteenth connection segment CT18 connecting the other end of the active pattern T14A of the fourteenth transistor T14 and the first second low potential line Nvgl1.

[0183] Referring to FIG. 24 to FIG. 29 , the first source-drain layer 133 includes a nineteenth connection segment CT19 connecting the one end of the active pattern T18A of the eighteenth transistor T18 and the one end of the active pattern T17A of the seventeenth transistor T17.

[0184] Referring to FIG. 24 to FIG. 29 , the first source-drain layer 133 includes a twentieth connection segment CT20 connecting the one end of the active pattern T5A of the fifth transistor T5 and the one end of the active pattern T4A of the fourth transistor T4.

[0185] Referring to FIG. 24 to FIG. 29 , the first source-drain layer 133 includes a twenty-first connection segment CT21 connecting the one end of the active pattern T22A of the twenty-second transistor T22 and the one end of the active pattern T21A of the twenty-first transistor T21.

[0186] Referring to FIG. 24 to FIG. 29The first source-drain layer 133 includes a twenty-second connection segment CT22, and the twenty-second connection segment CT22 connects the other end of the active pattern T8A of the output control transistor T8, the active pattern T5A of the fifth transistor T5, and the active pattern T22A of the twenty-second transistor T22.

[0187] Referring to FIG. 30 to FIG. 35 The first source-drain layer 133 includes a twenty-third connection segment CT23, and the twenty-third connection segment CT23 connects the other end of the active pattern T17A of the seventeenth transistor T17 and the sixth transfer segment ET6.

[0188] Referring to FIG. 30 to FIG. 35 The first source-drain layer 133 includes a twenty-fourth connection segment CT24, and the twenty-fourth connection segment CT24 connects the other end of the active pattern T4A of the fourth transistor T4 and the intersection of the third transfer segment ET3 and the fourth transfer segment ET4.

[0189] Referring to FIG. 30 to FIG. 35 The first source-drain layer 133 includes a twenty-fifth connection segment CT25, and the twenty-fifth connection segment CT25 connects the other end of the active pattern T21A of the twenty-first transistor T21 and the second transfer segment ET2.

[0190] Referring to ​ The first source-drain layer 133 includes a twenty-sixth connection segment CT26, and the twenty-sixth connection segment CT26 connects the gate T21G of the twenty-first transistor T21 and the first control clock line NCK1.

[0191] Referring to ​ The first source-drain layer 133 includes a twenty-seventh connection segment CT27, and the twenty-seventh connection segment CT27 connects one end of the active pattern T20A of the twentieth transistor T20 and the first plate C3a of the third capacitor C3.

[0192] Referring to ​ The first source-drain layer 133 includes a twenty-eighth connection segment CT28, and the twenty-eighth connection segment CT28 connects the eleventh transfer segment ET11 and the sixteenth transfer segment ET16.

[0193] Referring to ​ The first source-drain layer 133 includes a twenty-ninth connection segment CT29, and the twenty-ninth connection segment CT29 connects the other end of the active pattern T20A of the twentieth transistor T20 and the second frequency division signal line PLF.

[0194] Referring to ​ The first source-drain layer 133 includes a thirtieth connection segment CT30, and the thirtieth connection segment CT30 connects the thirteenth transfer segment ET13 and the gate T20G of the twentieth transistor T20.

[0195] Referring to ​ The first source-drain layer 133 includes a thirty-first connection segment CT31 connecting the tenth transfer segment ET10 and the seventeenth transfer segment ET17.

[0196] Referring to ​ The first source-drain layer 133 includes a thirty-second connection segment CT32 connecting the other end of the active pattern T19A of the nineteenth transistor T19, the second plate C3b of the third capacitor C3, the second transfer segment ET2 and one end of the active pattern T8A of the output control transistor T8.

[0197] Referring to ​ The first source-drain layer 133 includes a thirty-third connection segment CT33 connecting the twelfth transfer segment ET12 and the fifth transfer segment ET5.

[0198] Referring to ​ The first source-drain layer 133 includes a thirty-fourth connection segment CT34 connecting the other end of the active pattern T8A of the output control transistor T8 and the gate T6G of the sixth transistor T6.

[0199] Referring to ​ The first source-drain layer 133 includes a thirty-fifth connection segment CT35 connecting the drain T6D of the sixth transistor T6 and the first output clock line PCK1.

[0200] Referring to ​ The first source-drain layer 133 includes a thirty-sixth connection segment CT36 connecting the first gate T10Ga and the second gate T10Gb of the tenth transistor T10.

[0201] It should be noted that the sixth transistor T6 of the current stage is connected with the first output clock line PCK1, the fourth transistor T4, the seventeenth transistor T17 and the twenty-first transistor T21 of the current stage are connected with the first control clock line NCK1; the sixth transistor T6 of the next stage is connected with the second output clock line PCK2, the fourth transistor T4, the seventeenth transistor T17 and the twenty-first transistor T21 of the current stage are connected with the second control clock line NCK2.

[0202] Referring to ​, the second source-drain layer 135 includes two second high potential signal lines Nvgh, three second low potential signal lines, a first frequency division signal line NLF, a control signal line CTL, three first high potential signal lines, a second frequency division signal line PLF, two first low potential signal lines, a first control clock line NCK1, a second control clock line NCK2, a third control clock line NCK3, a fourth control clock line NCK4, a first output clock line PCK1, a second output clock line PCK2, a third output clock line PCK3, a fourth output clock line PCK4, and a start signal line STV.

[0203] Referring to ​ , the second low potential signal line Nvgl2, the third low potential signal line Nvgl2, and the two second high potential signal lines Nvgh are arranged in the second direction Y in sequence and at intervals, and all overlap the second output module 320.

[0204] Referring to ​ , the first frequency division signal line NLF, the start signal line STV, the control signal line CTL, the first control clock line NCK1, the second control clock line NCK2, the third control clock line NCK3, the fourth control clock line NCK4, the second frequency division signal line PLF, the fourth output clock line PCK4, the third output clock line PCK3, the second output clock line PCK2, and the first output clock line PCK1 are arranged in the second direction Y in sequence and at intervals.

[0205] The first high potential line Pvgh1, the first low potential line Pvgl1, and the first low potential line Nvgl1 are arranged in the second direction Y in sequence and at intervals, and are arranged between the start signal line STV and the control signal line CTL, and the second high potential line Pvgh2 is arranged between the control signal line CTL and the first control clock line NCK1.

[0206] In this embodiment, since the third first high potential signal line Pvgh3 overlaps and is connected with the first output module 330, and the first first high potential signal line Pvgh1, the second first high potential signal line Pvgh2, and the transistor in the signal generation module 310 are connected, the output load of the third first high potential signal line Pvgh3 is greater than the output load of the first first high potential signal line Pvgh1 and the second first high potential signal line Pvgh2, that is, the width of the third first high potential signal line Pvgh3 of the present application is greater than the width of the first first high potential signal line Pvgh1 and the second first high potential signal line Pvgh2.

[0207] In the embodiments of the present application, in order to ensure that the output signals of different output clock lines are the same, the present application can make the line widths of the four output clock lines equal.

[0208] Meanwhile, since the signal output by the first type clock line NCK is mainly used for turning on and turning off the transistor, the load of the first type clock line NCK is smaller than the load of the second type clock line PCK, that is, the present application can make the widths of the clock lines in the first type clock line NCK all smaller than the widths of the clock lines in the second type clock line PCK, that is, the width of the control clock line of the present application is smaller than the width of the output clock line.

[0209] For example, the widths of the first control clock line NCK1, the second control clock line NCK2, the third control clock line NCK3 and the fourth control clock line NCK4 are all the same and are all smaller than the widths of the first output clock line PCK1, the second output clock line PCK2, the third output clock line PCK3 and the fourth output clock line PCK4.

[0210] It should be noted that the present application also proposes a display device, which comprises the display panel described above, and the display device of the present application can be any product or component with display function, such as mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator, etc.

[0211] In the description of the present application, the terms "first", "second" are only used for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0212] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0213] In the above embodiments, the structure shown in the drawings is only a schematic diagram, and the specific structure of the display panel of the present application is mainly described in the description.

[0214] The embodiments, implementation manners and related technical features of the present application can be combined or replaced with each other without conflict.

[0215] The above is only the preferred embodiments of the present application, and does not limit the present application in any form, but any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, without departing from the technical solution of the present application, still belongs to the scope of the technical solution of the present application.

Claims

1. A display panel, characterized in that, Includes a display area and a non-display area; wherein, the display panel includes: A gate driving circuit is disposed in the non-display area, and the gate driving circuit includes a plurality of cascaded gate driving units arranged along a first direction. A pixel driving circuit is disposed in the display area, and the pixel driving circuit includes a compensation transistor and a first reset transistor connected to each other. The gate driving unit includes a first gate circuit and a second gate circuit arranged along the first direction. The output terminal of the first gate circuit is connected to the compensation transistor, and the output terminal of the second gate circuit is connected to the first reset transistor.

2. The display panel as described in claim 1, characterized in that, Both the first gate circuit and the second gate circuit include a signal generation module, a first output module, and a second output module connected to each other; The first output module and the second output module are located on both sides of the signal generation module along the second direction, and the second output module is located close to the display area. The first direction and the second direction are opposite.

3. The display panel as described in claim 2, characterized in that, The signal generation module includes a signal level transmission module, a first frequency division unit, and a second frequency division unit connected to each other. The first frequency division unit and the second frequency division unit are located on both sides of the signal level transmission module along the second direction. The first frequency divider unit is located close to the first output module, and the second frequency divider unit is located close to the second output module. The first frequency divider unit is connected to an internal node of the first output module, and the second frequency divider unit is connected to an internal node of the second output module.

4. The display panel as described in claim 3, characterized in that, The signal generation module is connected to the first type of clock line, the first output module is connected to the signal generation module, and the second output module is connected to the second type of clock line and the signal generation module. The first output module is configured to output a first gate control signal based on the signal output by the signal generation module, wherein the effective level of the first gate control signal is high; the second output module is configured to output a second gate control signal based on the second type of clock line and the signal output by the signal generation module, wherein the effective level of the second gate control signal is low.

5. The display panel as described in claim 4, characterized in that, The first type of clock line includes multiple control clock lines arranged along the second direction, and the second type of clock line includes multiple output clock lines arranged along the second direction; Among them, multiple clock control lines are located between the signal level transmission module and the second frequency division unit, and multiple output control lines are located between the second frequency division unit and the first output module.

6. The display panel as described in claim 5, characterized in that, The width of the control clock line is smaller than the width of the output clock line.

7. The display panel as described in claim 4, characterized in that, The signal transmission module includes a first control unit, a second control unit, an output control unit, a third control unit, a fourth control unit, and a reset unit connected to each other; The first control unit and the second control unit are arranged along the first direction and are both adjacent to the first frequency division unit. The third control unit, the output control unit, and the fourth control unit are arranged along the second direction. The third control unit is adjacent to the second control unit, and the fourth control unit is adjacent to the first type of clock line. The reset unit is located between the first type of clock line and the first control unit.

8. The display panel as described in claim 2, characterized in that, The pixel driving circuit also includes a switching transistor electrically connected to the compensation transistor; In this configuration, the first output module of the first gate circuit is connected to the compensation transistor, the first output module of the second gate circuit is connected to the first reset transistor, and the second output modules of the first gate circuit and the second gate circuit are connected to different switching transistors.

9. The display panel as described in any one of claims 1 to 8, characterized in that, The gate driving unit further includes a third gate circuit and a fourth gate circuit, the third gate circuit and the fourth gate circuit are arranged along the first direction, the fourth gate circuit is disposed on the side of the first gate circuit away from the display area, and the third gate circuit is disposed on the side of the second gate circuit away from the display area; The pixel driving circuit further includes a first light-emitting transistor and a second reset transistor connected to each other, a fourth gate circuit connected to one of the first light-emitting transistor and the second reset transistor, and a third gate circuit connected to the other of the first light-emitting transistor and the second reset transistor.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 9.

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