Markov chain device and control method of markov chain device

Abstract

Embodiments of the present application provide a Markov chain device and a control method of the Markov chain device. The Markov chain device comprises a control unit and a storage unit electrically connected, the storage unit comprises a magnetic storage device, the magnetic storage device comprises a spin-orbit torque layer and a magnetic tunnel junction arranged adjacently; the control unit is configured to output a periodic pulse signal, each cycle of the pulse signal comprises a unidirectional write pulse and a read pulse, and the write pulse is applied to the spin-orbit torque layer; in each cycle of the pulse signal, the magnetic storage device generates a bidirectional flip between a high resistance state and a low resistance state in response to the write pulse to realize a write of state transition of the Markov chain, and the control unit reads the resistance state of the magnetic storage device through the read pulse to realize a read of the state transition of the Markov chain. The Markov chain device uses the spin-orbit torque magnetic random access memory as the storage unit and adopts a unidirectional write pulse, thereby reducing the delay and power consumption and improving the durability and reliability.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor, and in particular to a Markov chain device and a control method of the Markov chain device. BACKGROUND

[0002] Magnetic Random Access Memory (MRAM) is a non-volatile magnetic random memory, which uses magnetic resistance effect to store data. The core structure of MRAM includes a magnetic tunnel junction (MTJ), and the magnetization direction of one ferromagnetic layer in the MTJ is difficult to change, which is called a fixed layer or a reference layer; the magnetization direction of the other ferromagnetic layer can be changed by a magnetic field or a current, which is called a free layer. When the magnetization direction of the free layer is parallel to the magnetization direction of the fixed layer (P state), the MTJ is in a low resistance state, which can represent data '0'; when the magnetization direction of the free layer is anti-parallel to the magnetization direction of the fixed layer (AP state), the MTJ is in a high resistance state, which can represent data '1'. The conversion of the magnetization direction of the free layer, that is, the conversion of the two resistance states, can be controlled by the direction and size of the current. As the current increases, the resistance state conversion probability gradually increases, showing a probability flipping characteristic.

[0003] A Markov chain is a random process that represents the transition of a state in a state space to another state, and is a random process with no memory. The core feature is that the probability distribution of the next state is determined only by the current state, and is independent of the historical state. Markov chains are commonly used in machine learning and artificial intelligence algorithms, and the matrix operation of a large number of parameters requires a large amount of time and energy consumption. A new type of memory naturally has state probability transfer, which can be used to implement a Markov chain device in a hardware architecture to greatly reduce latency and energy consumption.

[0004] At present, the Markov chain technology based on spin transfer torque magnetic random access memory (STT-MRAM) uses two writing pulses with opposite polarities to realize the state transition writing of the Markov chain, and then uses a reading pulse to realize the state transition reading of the Markov chain. There is still room for optimization in terms of latency and power consumption. SUMMARY

[0005] Embodiments of the present application provide a Markov chain device and a control method of the Markov chain device to reduce latency and power consumption.

[0006] In a first aspect, embodiments of the present application provide a Markov chain device, comprising:

[0007] a control unit and a storage unit connected electrically, the storage unit comprising a magnetic storage device, the magnetic storage device comprising a spin orbit torque layer and a magnetic tunnel junction arranged adjacently.

[0008] The control unit is configured to output a periodic pulse signal, each cycle of the pulse signal comprising a unidirectional write pulse and a read pulse, the write pulse being applied to the spin-orbit torque layer;

[0009] In each cycle of the pulse signal, the magnetic memory device is configured to generate a bidirectional flip between a high resistance state and a low resistance state in response to the write pulse to implement a write of a state transition of a Markov chain, and the control unit is configured to read a resistance state of the magnetic memory device by the read pulse to implement a read of the state transition of the Markov chain.

[0010] In some embodiments, in each cycle of the pulse signal, the write pulse is always a positive pulse, or the write pulse is always a negative pulse.

[0011] In some embodiments, the write pulse has a magnitude in a first voltage interval, the first voltage interval being greater than a second voltage interval;

[0012] wherein, when a write pulse applied to the storage unit has a magnitude in the first voltage interval, the resistance state of the magnetic memory device is bidirectionally flipped between the high resistance state and the low resistance state; and when a write pulse applied to the storage unit has a magnitude in the second voltage interval, the resistance state of the magnetic memory device is unidirectionally flipped between the high resistance state and the low resistance state.

[0013] In some embodiments, the magnitude of the first voltage interval is negatively correlated with the size of a leakage magnetic field of a synthetic antiferromagnetic layer in the magnetic tunnel junction.

[0014] In some embodiments, the synthetic antiferromagnetic layer comprises a first ferromagnetic layer and a second ferromagnetic layer, and the two layers form an antiferromagnetic coupling therebetween;

[0015] wherein, the magnetic field direction of the first ferromagnetic layer is consistent with the direction of an Oersted field generated by a write current flowing in the spin-orbit torque layer, and the thickness of the first ferromagnetic layer is negatively correlated with the magnitude of the first voltage interval;

[0016] the magnetic field direction of the second ferromagnetic layer is opposite to the direction of the Oersted field generated by the write current flowing in the spin-orbit torque layer, and the thickness of the second ferromagnetic layer is positively correlated with the magnitude of the first voltage interval.

[0017] In some embodiments, the control unit controls the probability of the state transition of the Markov chain by adjusting the magnitude of the write pulse to control the flipping probability between the high resistance state and the low resistance state of the magnetic memory device.

[0018] In some embodiments, a first end of the spin-orbit torque layer is electrically connected to a bit line through a first switch tube, and a second end of the spin-orbit torque layer is electrically connected to a source line.

[0019] The first end of the magnetic tunnel junction is electrically connected with the bit line through a second switch tube, and the second end of the magnetic tunnel junction is adjacent to the spin-orbit torque layer;

[0020] The write pulse is applied to the bit line and the source line;

[0021] The read pulse is applied to the bit line and the source line.

[0022] In some embodiments, the number of the storage units is a plurality, and the plurality of storage units constitute a storage array;

[0023] The plurality of target storage units in the storage array are connected with the same bit line and the same source line, and the plurality of target storage units are the same column of storage units, or the plurality of target storage units are the same row of storage units;

[0024] The control unit outputs corresponding pulse signals to the bit line and the source line of the plurality of target storage units.

[0025] In some embodiments, further comprising: an analog-to-digital converter electrically connected with the control unit, and a transimpedance amplifier electrically connected with the analog-to-digital converter and the storage unit respectively;

[0026] The transimpedance amplifier is configured to convert the sum of the read currents of the plurality of target storage units into a first voltage, and the analog-to-digital converter is configured to convert the first voltage into a corresponding digital signal and input the control unit;

[0027] The control unit is configured to determine the state transition probability of the plurality of target storage units according to the digital signal in a preset number of pulse periods.

[0028] The Markov chain device provided by the embodiments of the present application uses the spin-orbit torque magnetic random access memory (SOT-MRAM) as the storage unit, and only one unidirectional write pulse and one read pulse are needed to complete the write and read process of the state transition of the Markov chain, which can shorten the pulse period, improve the speed, and further reduce the delay and energy consumption compared with the existing Markov chain scheme based on the spin transfer torque magnetic random access memory (STT-MRAM). Compared with the existing scheme based on the spin transfer torque magnetic random access memory, which uses two bidirectional write pulses to realize the state transition of the Markov chain, the present application can further reduce the film layer loss caused by repeated write operations and improve the durability. Since the present application uses the spin-orbit torque magnetic random access memory as the storage unit, the read and write channels are separated, which can significantly improve the durability and reliability.

[0029] In a second aspect, the embodiments of the present application provide a control method of a Markov chain device, applied to the Markov chain device of the first aspect, and the control method comprises:

[0030] In each pulse signal cycle, the control unit outputs a unidirectional write pulse to the storage unit to control the magnetic storage device to generate a bidirectional flip between the high resistance state and the low resistance state to realize the state transition of the Markov chain, and the control unit outputs a read pulse to the storage unit to realize the reading of the state transition of the Markov chain by reading the resistance state of the magnetic storage device.

[0031] The control method of the Markov chain device provided by the embodiments of the present application can complete the writing and reading process of the state transition of the Markov chain by applying a unidirectional write pulse and a read pulse to the spin-orbit torque magnetic random access memory as the storage unit. Compared with the existing Markov chain scheme based on the spin transfer torque magnetic random access memory (STT-MRAM), the pulse cycle can be shortened, the speed can be improved, the delay and the energy consumption can be further reduced. Moreover, compared with the existing scheme of the Markov chain based on the spin transfer torque magnetic random access memory, which realizes the state transition of the Markov chain by using two bidirectional write pulses, the spin-orbit torque magnetic random access memory provided by the present application can further reduce the film layer loss caused by repeated write operations and improve the durability. Since the spin-orbit torque magnetic random access memory is used as the storage unit in the present application, the read-write channel is separated, and the durability and the reliability can be significantly improved. BRIEF DESCRIPTION OF DRAWINGS

[0032] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate embodiments consistent with the present application and, together with the description, further serve to explain the principles of the application.

[0033] Figure 1 A schematic diagram of the resistance state transition of a magnetic tunnel junction;

[0034] Figure 2 A schematic diagram of the resistance state transition probability of a magnetic tunnel junction;

[0035] Figure 3 A schematic diagram of the resistance state steady-state distribution of a magnetic tunnel junction;

[0036] Figure 4 A schematic diagram of the resistance state transition probability of a magnetic tunnel junction of a spin transfer torque magnetic random access memory;

[0037] Figure 5 A schematic diagram of a pulse signal of a Markov chain scheme based on a spin transfer torque magnetic random access memory;

[0038] Figure 6 A schematic diagram of the structure of a spin-orbit torque magnetic random access memory provided by the present application;

[0039] Figure 7 A schematic diagram of a magnetic resistance state transition phase of a magnetic tunnel junction of a spin orbit torque magnetic random access memory provided in the present application;

[0040] Figure 8 A schematic diagram of a spin current spin polarization direction of a write current of a spin orbit torque layer and an Oersted field direction provided in the present application;

[0041] Figure 9 A structure schematic of a Markov chain apparatus provided in the present application Figure 1 ;

[0042] Figure 10 A pulse signal schematic of a Markov chain apparatus provided in the present application

[0043] Figure 11 A structure schematic of a storage unit provided in the present application

[0044] Figure 12 A schematic diagram of a control unit controlling multiple storage units in parallel provided in the present application

[0045] Figure 13 A structure schematic of a Markov chain apparatus provided in the present application Figure 2 ;

[0046] Figure 14 A flowchart of a control method of a Markov chain apparatus provided in the present application

[0047] Figure 15 A structure schematic of a control unit provided in the present application.

[0048] The above-described drawings have shown specific embodiments of the present application, and more detailed descriptions will be given hereinafter. These drawings and written descriptions are not intended to limit the scope of the present application concept in any way, but to illustrate the present application concept to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0049] Exemplary embodiments will be described in detail herein below with reference to the drawings. In the following description, the same drawings reference numbers are used to denote like or similar elements unless otherwise denoted in the drawings. The embodiments described in the following exemplary embodiments are not representative of all embodiments consistent with the present application. Rather, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0050] The mathematical definition of a Markov chain is as follows:

[0051] Let a stochastic process have a time set state space ,Right now It is a time-discrete and state-discrete stochastic process. If for any integer... ,satisfy = Then it is called For a Markov chain, the above equation is called the Markov property or the property of no aftereffects. Markov chains have the memoryless property, meaning the probability distribution of the next state is determined only by the current state and is independent of historical states. Markov chains have wide applications in various fields, such as financial forecasting, weather forecasting, Monte Carlo sampling algorithms, natural language processing, cache system management, and bioinformatics research.

[0052] Markov chains are commonly used in machine learning and artificial intelligence algorithms, where matrix operations involving a large number of parameters require significant time and energy. Compared to software-implemented Markov chains, hardware-implemented Markov chains offer superior performance, with their parallel computing capabilities and low-latency response greatly reducing latency and energy consumption.

[0053] In schemes using magnetic random access memory to implement Markov chains, by applying write pulses that probabilistically flip the magnetic tunnel junction, the magnetoresistive state of the magnetic tunnel junction will probabilistically switch. The magnetoresistive state of the magnetic tunnel junction switches between low-resistance and high-resistance states, that is, between the P state and the AP state, as shown below. Figure 1 As shown, the probability of transitioning from state P to state P is The probability of transitioning from the P state to the AP state is The probability of transitioning from the AP state to the P state is The probability of transitioning from AP state to AP state is The magnetoresistive state transition matrix is .

[0054] As the number of write pulses increases, the magnetoresistive state transition probability statistics of the magnetic tunnel junction tend to stabilize, such as... Figure 2 As shown, the probability of the magnetic tunnel junction eventually being in state P or state AP, that is, the probability of being in state "0" or state "1", also tends to stabilize, as... Figure 3 As shown in the diagram. Therefore, the state transition process in a Markov chain can be represented by the probability of the magnetic tunnel junction being in one of two states after multiple pulse cycles. In steady state, the distributions of state "0" and state "1" are denoted as... And satisfy the following relationship: = .

[0055] Currently, in Markov chain schemes based on spin-transfer torque magnetic random access memory (STT-MRAM), the magnetoresistive state transition probability of the magnetic tunnel junction under write pulse is as follows: Figure 4As shown, under the application of a write pulse in one direction, the magnetic tunnel junction can be probabilistically converted from the P state to the AP state, but the probability of conversion from the AP state to the P state is 0. Under the application of a write pulse in the other direction, the magnetic tunnel junction can be probabilistically converted from the AP state to the P state, but the probability of conversion from the P state to the AP state is 0. That is, the magnetic tunnel junction can only be probabilistically unidirectionally flipped between the two resistance states under the action of a unipolar write pulse. Therefore, as shown in the pulse signal, two write pulses of opposite polarity (i.e., bidirectional write pulses) and one read pulse are used as a group to achieve the writing and reading of the state transition of the Markov chain once. Figure 5 As shown, under the application of a write pulse in one direction, the magnetic tunnel junction can be probabilistically converted from the P state to the AP state, but the probability of conversion from the AP state to the P state is 0. Under the application of a write pulse in the other direction, the magnetic tunnel junction can be probabilistically converted from the AP state to the P state, but the probability of conversion from the P state to the AP state is 0. That is, the magnetic tunnel junction can only be probabilistically unidirectionally flipped between the two resistance states under the action of a unipolar write pulse. Therefore, as shown in the pulse signal, two write pulses of opposite polarity (i.e., bidirectional write pulses) and one read pulse are used as a group to achieve the writing and reading of the state transition of the Markov chain once.

[0056] The Markov chain scheme based on the spin transfer torque magnetic random access memory must use two write pulses of opposite polarity and one read pulse to achieve the writing and reading of the state transition of the Markov chain once. The single pulse period is long, and the time consumed for completing the writing and reading of the state transition is long. At the same time, because the number of write / read pulses applied in the same pulse period is large, it also means that the power consumption required is also high. Therefore, the existing Markov chain scheme based on the spin transfer torque magnetic random access memory still has further optimization space in terms of delay and power consumption. In order to further reduce the delay and power consumption, a Markov chain scheme based on the spin orbit torque magnetic random access memory (SOT-MRAM) is proposed in the embodiments of the present application, which only needs to use a unidirectional write pulse to achieve the probabilistic bidirectional flipping between the two resistance states of the magnetic tunnel junction.

[0057] Regarding the structure of the spin orbit torque magnetic random access memory (SOT-MRAM), as shown in the figure, it includes a spin orbit torque layer, a magnetic tunnel junction (MTJ) disposed above the spin orbit torque layer (SOT layer), and a top electrode layer disposed above the magnetic tunnel junction. Figure 6

[0058] The magnetic tunnel junction is the core structure of the magnetic memory device, and the shape of the magnetic tunnel junction can be a cylinder, an elliptical cylinder, a rectangular body, a ring body, etc. The magnetic tunnel junction includes a free layer, a barrier layer, and a fixed layer stacked in order from bottom to top. When the magnetization directions of the free layer and the fixed layer are the same (i.e., parallel, P state), the magnetic tunnel junction is in a low resistance state, corresponding to storing data "0"; when the magnetization directions of the free layer and the reference layer are opposite (i.e., anti-parallel, AP state), the magnetic tunnel junction is in a high resistance state, corresponding to storing data "1".

[0059] ​Further, the magnetization direction of the free layer can be changed, and the magnetization direction of the fixed layer is fixed. The material of the free layer and the fixed layer both includes ferromagnetic material, for example, including at least one of Co, Fe, B, Ni, Ru, Ir, Pt. The material of the free layer and the fixed layer can be the same or different, and the embodiments of the present application are not limited to this. The barrier layer is used to isolate the free layer and the fixed layer, and the material of the barrier layer includes insulating material, for example, including at least one of MgO, Al2O3, SiO2.

[0060] The material of the synthetic anti-ferromagnetic (SAF) layer includes collinear anti-ferromagnetic material and non-collinear anti-ferromagnetic material, for example, at least one of IrMn, PtMn, FeMn, NiMn, MnSn.

[0061] The spin-orbit torque layer is used to generate corresponding spin-polarized current with different directions of write current, thereby generating different directions of spin torque. The spin-orbit torque layer is a single layer or a stack, and the material of the spin-orbit torque layer includes conductive material with strong spin-orbit coupling effect. For example, the material of the spin-orbit torque layer includes one or more of Pt, Pd, Hf, Au, AuPt, PtHf, PtCr, PtMn, FeMn, NiMn, Ta, W, Ir, IrMn, WOx, WN, WON, TaN, TaB, and topological insulator. The topological insulator includes Bi x Se 1-x , Bi x Sb 1-x , (Bi, Sb)2Te3, wherein x independently satisfies the value of 0.1-0.9.

[0062] The top electrode layer is also a conductive material, which is used to connect an external power supply.

[0063] For spin-orbit torque magnetic random access memory, as the amplitude of the unidirectional write pulse gradually increases, the magnetic resistance state transition of the magnetic tunnel junction will appear 5 different stages as shown in Figure 7 .

[0064] Stage 1: no flip stage;

[0065] Stage 2: probabilistic flip of the spin-polarized direction of the spin current;

[0066] Stage 3: deterministic flip of the spin-polarized direction of the spin current;

[0067] Stage 4: probabilistic flip of the spin-polarized direction and the opposite direction of the spin current;

[0068] Stage 5: deterministic flip of the opposite direction of the spin-polarized direction of the spin current.

[0069] In stage 4, a unidirectional write pulse can cause the magnetic tunnel junction to bidirectional probabilistic flip between two resistance states, because, as shown in Figure 8 the spin current spin polarization direction generated at the interface between the spin-orbit torque layer and the free layer is opposite to the oersted field direction generated by the write current flowing through the spin-orbit torque layer, when a larger write current is applied, the thermal stability of the magnetic storage device at a higher local temperature decreases, the effect of spin current spin polarization competes with the effect of oersted field, the magnetization direction of the free layer probabilistically flips to the spin current spin polarization direction or the opposite direction of the spin current spin polarization direction, thereby realizing unipolar writing to achieve bidirectional flip. Based on the above, when a Markov chain is implemented using a spin-orbit torque magnetic random memory, only one unidirectional write pulse and one read pulse are required in each pulse period to achieve writing and reading of state transition of a Markov chain once, and the pulse period is repeated to a certain number. The frequency of the appearance of data "0" and "1" states is counted as the probability of the steady-state distribution, and the random process prediction is completed.

[0070] It should be noted that the P state, low resistance state, and state "0" described in the embodiments of the present application represent the same state, and the AP state, high resistance state, and state "1" represent the same state.

[0071] The technical solutions of the present application and how the technical solutions of the present application solve the above technical problems will be described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes can not be described in detail in some embodiments. The embodiments of the present application will be described below with reference to the accompanying drawings.

[0072] Figure 9 The structure of the Markov chain device provided by the present application is shown in Figure 1 . As shown in Figure 9 , the Markov chain device includes a control unit 91 and a storage unit 92 connected electrically, the storage unit 92 includes a magnetic storage device 921, and the magnetic storage device 921 includes a spin-orbit torque layer 9211 and a magnetic tunnel junction 9212 arranged adjacent to each other.

[0073] The control unit 91 is configured to output a periodic pulse signal, each cycle of the pulse signal includes a unidirectional write pulse and a read pulse, and the write pulse is applied to the spin-orbit torque layer 9211.

[0074] In each pulse signal cycle, the magnetic storage device 921 generates bidirectional flip between high resistance state and low resistance state in response to the write pulse to achieve writing of state transition of the Markov chain, and the control unit 91 reads the resistance state of the magnetic storage device 921 through the read pulse to achieve reading of state transition of the Markov chain.

[0075] Referring to the foregoing description, for the magnetic storage device 921 composed of a spin-orbit matrix 9211 and a magnetic tunnel junction 9212, the control unit 91 outputs periodic pulse signals to the magnetic storage device 921, such as... Figure 10 As shown. When a unidirectional write pulse is applied to the spin orbital moment layer 9211, a write current is generated in the spin orbital moment layer 9211. The spin polarization effect of the spin current generated by the write current competes with the effect of the Oersted field. The magnetization direction of the free layer probabilistically flips in the direction of spin polarization of the spin current or in the opposite direction of spin polarization of the spin current. That is, the magnetic storage device 921 produces bidirectional flips between high-resistance and low-resistance states. In other words, the magnetic storage device 921 can flip from a high-resistance state to a low-resistance state or vice versa. Therefore, a state transition of the Markov chain can be written. Afterwards, when a read pulse is applied to the magnetic storage device 921, the control unit 91 reads the resistance state of the magnetic storage device 921, thus realizing the reading of the state transition of the Markov chain. By periodically outputting this pulse signal to a certain number of times, the control unit 91 counts the frequency of the occurrence of the high-resistance and low-resistance states as the probability of the steady-state distribution, thereby completing the prediction of the stochastic process of the Markov chain.

[0076] It is understood that, in the embodiments of this application, a unidirectional write pulse means that, within each pulse signal cycle, the write pulse is always a positive pulse, or the write pulse is always a negative pulse.

[0077] The Markov chain device in this application uses a spin-orbit-moment magnetic random access memory (SOT-MRAM) as its storage unit. It only requires one unidirectional write pulse and one read pulse to complete the writing and reading of a Markov chain state transition. Compared to existing Markov chain schemes based on spin-torque-moment magnetic random access memory (STT-MRAM), this shortens the pulse period, increases speed, and further reduces latency and power consumption. Furthermore, compared to existing schemes using two bidirectional write pulses to achieve Markov chain state transitions based on spin-torque-moment magnetic random access memory, this application uses only one unidirectional write pulse, which further reduces film loss caused by repeated write operations and improves durability. Since this application uses spin-orbit-moment magnetic random access memory as its storage unit, its read and write channels are separated, which also significantly improves durability and reliability.

[0078] In this embodiment, the amplitude of the unidirectional write pulse is within a first voltage range, which is greater than a second voltage range. When the amplitude of a write pulse applied to the memory cell is within the first voltage range, the resistive state of the magnetic storage device bidirectionally flips between a high-resistance state and a low-resistance state. When the amplitude of a write pulse applied to the memory cell is within the second voltage range, the resistive state of the magnetic storage device unidirectionally flips between a high-resistance state and a low-resistance state.

[0079] Continuing to refer to Figure 7 For example, the first voltage interval can be a bidirectional flipping voltage interval as shown in stage 4 in FIG. 2, in which case the resistance state of the magnetic tunnel junction can be flipped from the high resistance state to the low resistance state with a probability, or flipped from the low resistance state to the high resistance state with a probability, if the amplitude of the write pulse is within the interval. Figure 7 The second voltage interval can be a unidirectional flipping voltage interval as shown in stage 2 in FIG. 2, in which case the resistance state of the magnetic tunnel junction can only be flipped from the high resistance state to the low resistance state with a probability, or only be flipped from the low resistance state to the high resistance state with a probability, if the amplitude of the write pulse is within the interval. Figure 7 For example, the resistance state of the magnetic tunnel junction can only be flipped from the high resistance state to the low resistance state with a probability, as shown in stage 2 in FIG. 2. Figure 7 For example, the resistance state of the magnetic tunnel junction can only be flipped from the high resistance state to the low resistance state with a probability, as shown in stage 2 in FIG. 2.

[0080] The amplitude of the first voltage interval is negatively correlated with the leakage magnetic field of a synthetic anti-ferromagnetic (SAF) layer in the magnetic tunnel junction. That is, the greater the leakage magnetic field of the SAF layer, the lower the amplitude of the first voltage interval. Therefore, when preparing the magnetic storage device, the leakage magnetic field of the SAF layer can be controlled to be greater, so that the amplitude of the first voltage interval is lower, thereby reducing the power consumption.

[0081] In some embodiments, the SAF layer includes a first ferromagnetic layer and a second ferromagnetic layer, and the two layers form an anti-ferromagnetic coupling therebetween.

[0082] The magnetic field direction of the first ferromagnetic layer is consistent with the direction of the Oersted field generated by the write current flowing through the spin-orbit torque layer, and the thickness of the first ferromagnetic layer is negatively correlated with the amplitude of the first voltage interval.

[0083] The magnetic field direction of the second ferromagnetic layer is opposite to the direction of the Oersted field generated by the write current flowing through the spin-orbit torque layer, and the thickness of the second ferromagnetic layer is positively correlated with the amplitude of the first voltage interval.

[0084] Therefore, when preparing the magnetic storage device, the thickness of the first ferromagnetic layer can be appropriately increased, and the thickness of the second ferromagnetic layer can be appropriately reduced, so as to control the leakage magnetic field of the SAF layer to be greater, so that the amplitude of the first voltage interval is lower, thereby reducing the power consumption.

[0085] Optionally, when preparing the magnetic storage device, a medium with low heat dissipation effect can also be selected to increase the local temperature of the device, so as to reduce the amplitude of the first voltage interval, thereby reducing the power consumption.

[0086] When the amplitude of the write pulse is in the first voltage interval, bidirectional flipping between the high resistance state and the low resistance state of the magnetic storage device can be realized, but the flipping probability will be different when the amplitude of the write pulse is different, and the control unit can control the flipping probability of the magnetic storage device between the high resistance state and the low resistance state to control the state transition probability of the Markov chain by adjusting the amplitude of the write pulse.

[0087] Reference Figure 11 Further description is made to the storage unit. As shown in Figure 11 A structural schematic diagram of a storage unit is shown in the figure. As shown in the figure, the storage unit comprises a magnetic storage device composed of a spin-orbit torque layer 9211 and a magnetic tunnel junction 9212, and a first switch tube Q1 and a second switch tube Q2. Figure 11 The first end of the spin-orbit torque layer 9211 is electrically connected to the bit line BL through the first switch tube Q1, and the second end of the spin-orbit torque layer 9211 is electrically connected to the source line SL; the first end of the magnetic tunnel junction 9212 is electrically connected to the bit line BL through the second switch tube Q2, and the second end of the magnetic tunnel junction 9212 is arranged adjacent to the spin-orbit torque layer 9211.

[0088] The control end of the first switch tube Q1 is connected to the write word line WWL, and the control end of the second switch tube Q2 is connected to the read word line RWL.

[0089] The write pulse is applied to the bit line BL and the source line SL, and the read pulse is applied to the bit line BL and the source line SL.

[0090] During writing, the write word line WWL signal is effective, and the first switch tube Q1 is turned on. In the case that the write pulse is a positive pulse, the write current flowing through the magnetic storage device flows from the bit line BL to the source line SL through the first switch tube Q1 and the spin-orbit torque layer 9211; during reading, the read word line RWL signal is effective, and the second switch tube Q2 is turned on. The read current flowing through the magnetic storage device flows from the bit line to the source line SL through the second switch tube Q2 and the magnetic tunnel junction 9212.

[0091] Alternatively, during writing, the write word line WWL signal is effective, and the first switch tube Q1 is turned on. In the case that the write pulse is a negative pulse, the write current flowing through the magnetic storage device flows from the source line SL to the bit line BL through the spin-orbit torque layer 9211 and the first switch tube Q1; during reading, the read word line RWL signal is effective, and the second switch tube Q2 is turned on. The read current flowing through the magnetic storage device flows from the source line SL to the bit line BL through the magnetic tunnel junction 9212 and the second switch tube Q2.

[0092]

[0093] ​It can be seen that, in the Markov chain device of the embodiment of the application, the read and write channels of the storage units are separated, compared with the common read and write channel in the Markov chain scheme based on the spin transfer torque magnetic random access memory (STT-MRAM), the separation of the read and write channels of the storage units in the embodiment of the application can significantly improve the durability and reliability.

[0094] In Figure 11 Based on the storage unit shown in the figure, the number of storage units is multiple, such as Figure 12 As shown in the figure, the multiple storage units constitute a storage array; the multiple target storage units in the storage array are connected to the same bit line BL and the same source line SL, and the multiple target storage units are the same column of storage units, or the multiple target storage units are the same row of storage units.

[0095] The control unit outputs corresponding pulse signals to the bit lines BL and the source lines SL of the multiple target storage units.

[0096] The same column or the same row of storage units in the storage array are connected to the same bit line BL and the same source line SL, and taking the same column as an example, when the control unit outputs pulse signals to the corresponding bit line BL and the source line SL of the column of storage units, the pulse signals are output to each storage unit in the column, so as to realize the parallel writing and reading of the state transition of the Markov chain for each storage unit in the column, thereby further reducing the delay.

[0097] For example, M target storage units are arranged in a column, and Y pulse periods are written and read in parallel, that is, M times Y times of state transition of the Markov chain can be completed. Correspondingly, in actual application, the values of M and Y can be adjusted to balance the delay and the array area.

[0098] In addition to parallel processing of the same row or the same column of storage units, the control unit can also output corresponding pulse signals to each bit line and source line in parallel, that is, the control unit outputs pulse signals to all storage units in parallel, so that each row and each column of storage units perform the parallel writing and reading of the state transition of the Markov chain, thereby further reducing the delay.

[0099] The following describes how to read the resistance state of the storage unit. In some embodiments, referring to Figure 13 As shown in the figure, in addition to the control unit 91 and the storage unit 92, the Markov chain device also includes an analog-to-digital converter 94 electrically connected to the control unit 91, and a transimpedance amplifier 93 electrically connected to the analog-to-digital converter 94 and the storage unit 92 respectively.

[0100] The trans-impedance amplifier 93 is configured to convert the sum of the read currents of the plurality of target memory cells into a first voltage, and the analog-to-digital converter 94 is configured to convert the first voltage into a corresponding digital signal and input the digital signal into the control unit 91.

[0101] The control unit 91 is configured to determine the state transition probability of the plurality of target memory cells according to the digital signals in a preset number of pulse periods.

[0102] The plurality of target memory cells are memory cells in the same column or the same row. Taking the memory cells in the same column as an example, the trans-impedance amplifier 93 converts the sum of the read currents of the memory cells in the same column in a pulse period from a current signal into a voltage signal, i.e., into the first voltage, and the analog-to-digital converter 94 converts the analog signal of the first voltage into a corresponding digital signal through analog-to-digital conversion. It can be understood that the memory cells 92 in the high resistance state or the low resistance state correspond to different read currents, and the size of the digital signal corresponding to the sum of the read currents of the memory cells in the same column indicates the state transition probability of the memory cells in the same column in a pulse period. The more the number of pulse periods, the more stable the state distribution, and the control unit outputs a preset number of pulse periods to the memory cells in the same column. The size of the preset number can be set according to actual needs, and the state transition probability of the memory cells in the same column can be determined based on the preset number of digital signals in the preset number of pulse periods.

[0103] In addition to determining the state transition probability of the plurality of target memory cells based on the sum of the read currents of the plurality of target memory cells as described above, in some embodiments, the state transition probability of the plurality of target memory cells can also be determined based on the read voltage of each memory cell in the plurality of target memory cells. In this case, the Markov chain device includes a control unit and a memory unit, and an amplifier electrically connected to the control unit and the memory unit.

[0104] The amplifier is configured to convert the read voltage of each memory cell into the resistance state of each memory cell and input the resistance state of each memory cell into the control unit, and the control unit is configured to determine the state transition probability of the plurality of target memory cells according to the resistance state of each target memory cell in the plurality of target memory cells in a preset number of pulse periods.

[0105] The plurality of target storage units still represent the same column or the same row of storage units, and still taking the same column of storage units as an example, in this scheme, the control unit reads the resistance state of each storage unit in the same column of storage units respectively, and determines the state transition probability of the same column of storage units in a pulse period based on the resistance state of each storage unit in the pulse period. The more the number of pulse periods is, the more stable the state distribution is. The control unit outputs a preset number of pulse periods to the same column of storage units, and the size of the preset number can be set according to actual needs. Based on the resistance state of each storage unit in the preset number of pulse periods, the state transition probability of the same column of storage units can be determined.

[0106] Figure 14 A flowchart of a control method of a Markov chain device provided in the present application is provided. As shown in the figure, Figure 14 the method comprises the following steps of:

[0107] S1401. In each pulse signal period, the control unit outputs a unidirectional write pulse to the storage unit to control the magnetic storage device to generate a bidirectional flip between the high resistance state and the low resistance state to realize the state transition of the Markov chain, and the control unit outputs a read pulse to the storage unit to realize the reading of the state transition of the Markov chain by reading the resistance state of the magnetic storage device.

[0108] The implementation principle and technical effects of the control method can refer to the description in the foregoing embodiments, which will not be repeated here.

[0109] Figure 15 A structural diagram of a control unit provided in the present application is provided. As shown in the figure, Figure 15 the control unit 91 provided in the present embodiment comprises at least one processor 1501 and a memory 1502. Optionally, the control unit 91 further comprises a communication component 1503. The processor 1501, the memory 1502 and the communication component 1503 are connected through a bus.

[0110] In the specific implementation process, the at least one processor 1501 executes the computer execution instructions stored in the memory 1502, so that the at least one processor 1501 executes the method described above.

[0111] The specific implementation process of the processor 1501 can refer to the method embodiments described above, which has similar implementation principles and technical effects, and will not be repeated here.

[0112] In the above embodiments, it should be understood that the processor can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), etc. The general-purpose processor can be a microcontroller (MCU), or the processor can also be any conventional processor, etc. The steps of the method disclosed in combination with the application can be directly embodied as hardware processor execution, or executed by a combination of hardware and software modules in the processor.

[0113] The memory can include a random access memory (RAM), and can also include a non-volatile memory (NVM), such as at least one disk memory.

[0114] The bus can be an industry standard architecture (ISA) bus, a peripheral component (PCI) bus, or an extended industry standard architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, the bus in the drawings of the present application does not limit to only one bus or one type of bus.

[0115] The present application also provides a computer program product, comprising a computer program, which, when executed by a processor, implements the above method.

[0116] The present application also provides a computer readable storage medium, which stores computer execution instructions, and when a processor executes the computer execution instructions, the above method is implemented.

[0117] The above readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. The readable storage medium can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0118] An example readable storage medium is coupled to the processor such that the processor can read information from the readable storage medium and can write information to the readable storage medium. Of course, the readable storage medium can also be a part of the processor. The processor and the readable storage medium can be located in an application specific integrated circuit (ASIC). Of course, the processor and the readable storage medium can also exist as discrete components in the device.

[0119] The division of units is only a logical functional division, and in actual implementation, there can be another division manner, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interfaces, devices or units, and can be electrical, mechanical or other forms.

[0120] The units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, that is, can be located in one place, or can be distributed on multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment scheme.

[0121] In addition, the functional units in each embodiment of the present application can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit.

[0122] If the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application or the part of the present application that essentially contributes to the prior art or the part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method of each embodiment of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various program code storage media.

[0123] Those skilled in the art can understand that all or part of the steps of the above-mentioned method embodiments can be completed by program instruction related hardware. The foregoing program can be stored in a computer readable storage medium. The program executes to perform the steps of the above-mentioned method embodiments; and the foregoing storage medium includes various media capable of storing program codes, such as ROM, RAM, magnetic disk, or optical disk.

[0124] Finally, it should be noted that other embodiments of the present application will readily occur to those skilled in the art upon consideration of the specification and practice of the present application disclosed herein. The present application is intended to include all such variations as fall within the general scope of the application, and includes the generic principles disclosed and the best mode known to the inventors to be currently practiced as well as variations thereof, without departing from the scope of the present application as defined by the claims. The specification and examples give the best application of the present application as currently known, and together with the description of the application serve to best illustrate the principles of the application. The scope of the application is expressly set forth in the claims.

Claims

1. A Markov chain apparatus, characterized by, The device comprises: a control unit and a storage unit electrically connected, the storage unit comprising a magnetic storage device, the magnetic storage device comprising a spin-orbit torque layer and a magnetic tunnel junction arranged adjacently; the control unit is configured to output a periodic pulse signal, each cycle of the pulse signal comprising a unidirectional write pulse and a read pulse, the write pulse being applied to the spin-orbit torque layer, the write pulse having a magnitude within a first voltage range, when a write pulse applied to the storage unit has a magnitude within the first voltage range, the resistance state of the magnetic storage device is bidirectional probabilistically flipped between a high resistance state and a low resistance state, and the write pulse has different magnitudes and different flip probabilities; in each cycle of the pulse signal, the magnetic storage device generates bidirectional flip between the high resistance state and the low resistance state in response to the write pulse to achieve state transition of Markov chain, and the control unit reads the resistance state of the magnetic storage device through the read pulse to achieve state transition of Markov chain.

2. The Markov chain apparatus of claim 1, wherein, In each cycle of the pulse signal, the write pulse is always a positive pulse, or the write pulse is always a negative pulse.

3. The Markov chain apparatus of claim 1, wherein, The first voltage range is greater than the second voltage range; wherein, when a write pulse applied to the storage unit has a magnitude within the second voltage range, the resistance state of the magnetic storage device is unidirectional flipped between a high resistance state and a low resistance state.

4. The Markov chain apparatus of claim 3, wherein, The magnitude of the first voltage range is negatively correlated with the size of the leakage magnetic field of the synthetic antiferromagnetic layer in the magnetic tunnel junction.

5. The Markov chain apparatus of claim 4, wherein, The synthetic antiferromagnetic layer comprises a first ferromagnetic layer and a second ferromagnetic layer, and an antiferromagnetic coupling is formed between the two layers; wherein, the magnetic field direction of the first ferromagnetic layer is consistent with the direction of the Oersted field generated by the write current flowing through the spin-orbit torque layer, and the thickness of the first ferromagnetic layer is negatively correlated with the magnitude of the first voltage range; the magnetic field direction of the second ferromagnetic layer is opposite to the direction of the Oersted field generated by the write current flowing through the spin-orbit torque layer, and the thickness of the second ferromagnetic layer is positively correlated with the magnitude of the first voltage range.

6. The Markov chain apparatus of any one of claims 1 to 5, wherein, The control unit controls the flip probability between the high resistance state and the low resistance state of the magnetic storage device by adjusting the magnitude of the write pulse to control the state transition probability of the Markov chain.

7. The Markov chain device according to any one of claims 1 to 5, wherein: a first end of the spin-orbit torque layer is electrically connected to a bit line through a first switch tube, and a second end of the spin-orbit torque layer is electrically connected to a source line; a first end of the magnetic tunnel junction is electrically connected to the bit line through a second switch tube, and a second end of the magnetic tunnel junction is arranged adjacently to the spin-orbit torque layer; the write pulse is applied to the bit line and the source line; the read pulse is applied to the bit line and the source line.

8. The Markov chain apparatus of claim 7, wherein, The number of the storage units is multiple, and the multiple storage units constitute a storage array; a plurality of target storage units in the storage array are connected to the same bit line and the same source line, and the plurality of target storage units are the same column of storage units, or the plurality of target storage units are the same row of storage units; the control unit outputs corresponding pulse signals to the bit line and the source line of the plurality of target storage units.

9. The Markov chain apparatus of claim 8, wherein, Further comprising: An analog-to-digital converter electrically connected to the control unit, and a trans-impedance amplifier electrically connected to the analog-to-digital converter and the storage unit, respectively; The trans-impedance amplifier is configured to convert the sum of the read currents of the plurality of target storage units into a first voltage, and the analog-to-digital converter is configured to convert the first voltage into a corresponding digital signal and input the control unit; The control unit is configured to determine the state transition probability of the plurality of target storage units according to the digital signal in a preset number of pulse cycles.

10. A control method of a Markov chain apparatus, characterized by, The control method is applied to the Markov chain device of any one of claims 1 to 9, and the control method comprises: In each pulse signal cycle, the control unit outputs a unidirectional write pulse to the storage unit to control the magnetic storage device to generate a bidirectional flip between a high resistance state and a low resistance state to realize the state transition of the Markov chain, and the control unit outputs a read pulse to the storage unit to realize the read of the state transition of the Markov chain by reading the resistance state of the magnetic storage device.

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