Wafer-level system packaging structure and electronic device

Abstract

The invention provides a wafer-level system packaging structure and an electronic device, and relates to the technical field of semiconductors, the wafer-level system packaging structure comprises a substrate, first chips arranged in an array and bridging chips are formed on the substrate, the bridging chips are located on the sides, away from the substrate, of the first chips, and the bridging chips are arranged in the direction perpendicular to the plane where the substrate is located; the projection of the bridging chip on the substrate is at least partially overlapped with the first chips, and the bridging chip is used for connecting at least two adjacent first chips. According to the wafer-level packaging structure, the bridging chips are arranged in the wafer-level packaging structure, electric connection between the adjacent first chips can be achieved in the direction perpendicular to the plane where the substrate is located without a strict alignment process, the process difficulty and cost can be reduced, the bridging chips can be manufactured in batches, and the production period is shortened.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a wafer-level system packaging structure and electronic device. Background Technology

[0002] With the gradual development of high-end applications, integrating more integrated circuit chips in a smaller space and achieving interconnection between them with shorter distances is desirable. Therefore, 2.5D / 3D advanced packaging technologies, which enable higher integration and higher density chip interconnection, have received widespread attention. Among these advanced packaging technologies, TSMC's Chip-on-Wafer-on-Substrate (CoWoS) packaging and Intel's Embedded Multi-Die Interconnect Bridge (EMIB) packaging achieve fine, high-density electrical paths between chips. SoW (System-on-Wafer) or InFO_SoW (Integrated Fan-Out Reconfigurable System-on-Wafer) is another advanced semiconductor packaging technology developed by TSMC. It utilizes a single 300mm silicon wafer or fan-out reconfigurable wafer to form a powerful system, integrating multiple dedicated logic, memory (HBM), and photonic "chips" heterogeneously, providing extremely high computing density for artificial intelligence and high-performance computing (HPC) applications. It enables wafer-level integration of chips and other components without the need for traditional substrates and printed circuit boards (PCBs). This allows for the construction of high-density, high-bandwidth systems on a single wafer, thereby improving performance, reducing latency, and increasing energy efficiency, making it ideal for demanding applications such as high-performance computing (HPC) and artificial intelligence.

[0003] However, in current semiconductor integrated circuit manufacturing processes, achieving high-density electrical interconnection between chips is a complex and costly solution. Therefore, simplifying the high-density electrical interconnection process between chips and reducing costs has become a pressing technical problem for those skilled in the art. Summary of the Invention

[0004] To address the aforementioned technical issues, this disclosure provides a wafer-level system-in-package structure and electronic device that simplifies the high-density electrical interconnection process between chips and reduces costs.

[0005] In a first aspect, this disclosure provides a wafer-level system-on-a-chip (SoC) structure, comprising: a substrate on which a first array of chips is formed.

[0006] A bridging chip is located on the side of the first chip facing away from the substrate, along a direction perpendicular to the plane of the substrate. The projection of the bridging chip on the substrate at least partially overlaps with the first chip. The bridging chip is used to connect at least two adjacent first chips.

[0007] Optionally, the first chip includes a first sub-chip and a second sub-chip, and the first sub-chip and the second sub-chip are adjacent to each other along a direction parallel to the plane of the substrate.

[0008] The projection of the bridging chip onto the substrate at least partially overlaps with the first sub-chip and at least partially overlaps with the second sub-chip.

[0009] Optionally, the first chip includes an active surface, and the bridging chip is electrically connected to the active surface of the first sub-chip and to the active surface of the second sub-chip.

[0010] Optionally, the bridging chip is directly bonded to the first chip or electrically connected via conductive bumps.

[0011] Optionally, the size of the first chip is the same as the size of the photomask used in the lithography machine to etch the first chip.

[0012] Optionally, the bridging chip includes one or more active or passive devices.

[0013] Optionally, the first chip includes a third sub-chip and at least one fourth sub-chip, wherein the third sub-chip is different from the fourth sub-chip;

[0014] Along a direction perpendicular to the plane of the substrate, the projection of the fourth sub-chip onto the substrate is within the projection range of the third sub-chip onto the substrate.

[0015] Optionally, the fourth sub-chip is electrically connected to the third sub-chip, and the fourth sub-chips on at least two adjacent third sub-chips are electrically connected through the bridging chip.

[0016] Optionally, the packaging structure further includes a redistribution layer located on the side of the first chip facing the bridging chip.

[0017] Secondly, based on the same inventive concept, this disclosure provides an electronic device, including: a wafer-level system packaging structure as described in the first aspect.

[0018] Compared with the prior art, the technical solution provided in this disclosure has the following advantages: The wafer-level system packaging structure and electronic device provided in this disclosure, by setting a bridging chip at the position across the photomask splicing, can achieve electrical connection between adjacent first chips in a direction perpendicular to the plane of the substrate. Compared with related technologies that achieve electrical paths between adjacent chips in the parallel direction through photomask splicing, the electrical connection between adjacent first chips in the vertical direction does not require stringent alignment processes, reducing complex process steps, which helps to reduce process difficulty and costs. During the manufacturing process, the bridging chip can be independently batch-produced and then uniformly transferred to the position across adjacent photomasks, which helps to improve production stability and shorten the production cycle, facilitating rapid response to market demands.

[0019] Correspondingly, the electronic device provided in this disclosure also has the above-mentioned technical effects. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0021] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without creative effort.

[0022] Figure 1 The figure shown is a planar schematic diagram of a wafer-level packaging structure provided in an embodiment of this disclosure;

[0023] Figure 2 As shown Figure 1 A schematic diagram of the cross-section along section A-A'.

[0024] Figure 3 The figure shown is a planar schematic diagram of a wafer-level system packaging structure provided in an embodiment of this disclosure;

[0025] Figure 4 As shown Figure 3 A schematic diagram of the cross-section along section B-B'.

[0026] Figure 5 As shown Figure 3 Another schematic diagram of the cross section along section B-B'. Detailed Implementation

[0027] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0028] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0029] In current semiconductor integrated circuit manufacturing processes, photomasks are typically used for step-by-step scanning lithography on wafers or fan-out reconfigured wafers to route and fabricate chips. A photomask is typically 26x33mm in size. Chip lithography is completed within one photomask, and then the process moves to the next photomask area for chip lithography within that photomask. This repeated process partitions the pattern, exposes the chips sequentially, and ultimately assembles them into a large-size chip, thus completing chip fabrication on the wafer. Photomasks usually do not overlap, and chips in adjacent photomasks are independent of each other. However, InFO_SoW or SoW is wafer-level integration, requiring interconnections between chips in adjacent photomasks. The common solution is to stitch masks together. However, in actual photolithography, the size of the mask window exposed by the lithography machine is limited, so a single mask cannot completely cover the entire chip pattern. This necessitates stitching multiple masks together. This method is more expensive than the chip size itself. Precise alignment of the masks is crucial during stitching; even the slightest deviation can lead to discontinuities in the circuitry or performance degradation, thus affecting yield. Mask stitching typically requires multiple exposures and precise alignment, increasing mask changeover time and alignment complexity, thereby raising production costs.

[0030] To address the aforementioned issues, this disclosure provides a wafer-level system-in-package (WIP) structure and electronic device, which simplifies the interconnection paths between adjacent chips in the wafer-level package structure and reduces costs.

[0031] Figure 1 The figure shown is a planar schematic diagram of a wafer-level packaging structure provided in an embodiment of this disclosure. Figure 2 As shown Figure 1 Please refer to the cross-sectional diagram along section A-A'. Figure 1 and Figure 2 This disclosure provides a wafer-level system packaging structure 100, including a substrate 20. The embodiments of this disclosure do not limit the type of substrate 20, and all types of substrates known to those skilled in the art can be used. For example, the substrate 20 includes at least one of glass substrate, ceramic substrate, metal substrate, organic polymer material substrate and silicon wafer.

[0032] The first chip 10 is formed on the substrate 20 in an array. Understandably, the first chip 10 is grown on the substrate 20 by semiconductor process. The first chip 10 grown directly on the substrate 20 has higher reliability and can save more process steps compared to chips formed by other processes such as bonding.

[0033] The first chip 10 includes, but is not limited to, dies, chips, HBM (High Bandwidth Memory) stacks, such as HBM1, HBM2, HBM2E, HBM3, HBM3E, HBM4; ASIC (Application Specific Integrated Circuit), PLD (Programmable Logic Device), SOC (System-on-a-Chip), etc.

[0034] For simplicity of illustration, Figure 1 and Figure 2 The first chip 10 is shown only in the form of a box. It is conceivable that the structure of the first chip 10 may include multiple constituent elements and a redistribution structure (i.e., a metal interconnect structure) leading out the first chip 10. The metal interconnect structure may include multiple metal layers and contact holes that electrically connect adjacent metal layers. Of course, the structure of the first chip 10 may also not include the redistribution structure, etc. This disclosure does not limit it in this way.

[0035] Multiple first chips 10 may have the same or different functions, and correspondingly, multiple first chips 10 may have the same or different sizes, which is not limited in this disclosure. Figure 1 and Figure 2 The number and arrangement of the first chip 10 are for illustrative purposes only. This disclosure does not limit the actual number, function, or size of the first chip 10. The specific settings can be made according to actual needs.

[0036] Please refer to Figure 1 and Figure 2 The wafer-level system package structure 100 also includes a bridging chip 30, which is located on the side of the first chip 10 away from the substrate 20. Along the direction perpendicular to the plane of the substrate 20, the projection of the bridging chip 30 on the substrate 20 at least partially overlaps with the first chip 10. The bridging chip 30 is used to connect at least two adjacent first chips 10.

[0037] The wafer-level system-on-a-chip (SoC) structure 100 provided in this disclosure completes the packaging integration process on the substrate 20. By implementing interface interconnections within the wafer system, high-density, high-speed inter-chip communication can be achieved, thereby meeting the demands of modern electronic devices for high performance, high reliability, and low power consumption. This disclosure embodiment, by placing a bridging chip 30 across the photomask splicing position, enables electrical connections between adjacent first chips 10 in a direction perpendicular to the plane of the substrate 20. Compared to related technologies that use photomask splicing to establish electrical paths between adjacent chips in the parallel direction, the vertical electrical connection between adjacent first chips 10 does not require stringent alignment processes, reducing complex process steps and lowering process difficulty and cost. During the manufacturing process, the bridging chip 30 can be independently mass-produced and then uniformly transferred to the position across adjacent photomasks, improving production stability and shortening the production cycle, thus facilitating rapid response to market demands. In complex systems requiring the integration of multiple functional chips, photomask splicing may be insufficient to meet design requirements. The independent bridging chip 30 allows for the mixing and matching of various chiplet technologies, supporting heterogeneous integration and providing greater flexibility for chip design. Thus, by setting a bridging chip 30 inside the wafer-level system package structure 100, this disclosure can achieve electrical connection between adjacent first chips 10 in a direction perpendicular to the plane of the substrate 20 without the need for a strict alignment process. This helps to reduce process difficulty and cost, and the bridging chip 30 can be mass-produced, shortening the production cycle.

[0038] Please refer to Figure 2 In one optional embodiment provided in this disclosure, the first chip 10 includes a first sub-chip 11 and a second sub-chip 12. The first sub-chip 11 and the second sub-chip 12 are adjacent to each other along a direction parallel to the plane of the substrate 20. The projection of the bridging chip 30 on the substrate 20 at least partially overlaps with the first sub-chip 11 and at least partially overlaps with the second sub-chip 12.

[0039] The projection of the bridging chip 30 onto the substrate 20 partially overlaps with both the first sub-chip 11 and the second sub-chip 12, indicating that the bridging chip 30 is located above the boundary region between the two sub-chips. In other words, by providing a vertical interconnect structure along the longitudinal direction of adjacent first sub-chips 11 and second sub-chips 12, this embodiment of the present disclosure eliminates the need for high-precision alignment processes in the plane direction parallel to the first sub-chips 11 and second sub-chips 12, while still achieving electrical connection between adjacent first chips 10, thus reducing process complexity. Furthermore, this layout compresses the planar spacing between chips, making the overall structure more compact, which is particularly suitable for applications sensitive to package size.

[0040] The bridging chip 30 utilizes vertical space through vertical stacking, reducing the need for additional area on the substrate 20 plane for interconnects between sub-chips. This allows for the integration of more chips or functional modules within the same substrate 20 size, improving the area utilization of the package. In traditional planar layouts, the interconnect areas between sub-chips may generate localized hotspots due to concentrated signal transmission. The vertical interconnect structure of the bridging chip 30 disperses the signal transmission path across three-dimensional space, helping to balance heat distribution and avoid performance degradation or shortened lifespan caused by localized overheating.

[0041] As an independent functional module, the bridge chip 30 can be flexibly combined with sub-chips of different processes and functions (such as CPUs, GPUs, and AI accelerators), improving the flexibility of chip interconnection. When system performance needs to be upgraded, only some sub-chips or the bridge chip 30 need to be replaced, without redesigning the entire package. This flexibility facilitates product iteration, especially suitable for rapidly changing market demands.

[0042] Understandably, the first sub-chip 11 and the second sub-chip 12 may be manufactured using the same materials or processes, or using different materials or processes, and this disclosure does not limit them in this regard.

[0043] Please refer to Figure 2 The first chip 10 includes an active surface, which may or may not include a redistribution layer; this disclosure does not limit this.

[0044] The bridging chip 30 is electrically connected to the active surface of the first sub-chip 11 and to the active surface of the second sub-chip 12. The side of the bridging chip 30 facing the first sub-chip 11 and the second sub-chip 12 may or may not include a redistribution layer; this disclosure does not limit this.

[0045] In one optional embodiment provided in this disclosure, the side of the bridging chip 30 facing the first sub-chip 11 and the second sub-chip 12 does not include a redistribution layer, and the active surfaces of the first sub-chip 11 and the second sub-chip 12 do not include a redistribution layer. In the same bridging chip 30, at least a portion of the bridging chip 30 is electrically connected to the active surface of the first sub-chip 11, and at least a portion of the bridging chip 30 is electrically connected to the active surface of the second sub-chip 12.

[0046] In another optional embodiment provided in this disclosure, the side of the bridging chip 30 facing the first sub-chip 11 and the second sub-chip 12 includes a redistribution layer, the active surfaces of the first sub-chip 11 and the second sub-chip 12 do not include the redistribution layer, and in the same bridging chip 30, at least a portion of the redistribution layer of the bridging chip 30 is electrically connected to the active surface of the first sub-chip 11, and at least a portion of the redistribution layer of the bridging chip 30 is electrically connected to the active surface of the second sub-chip 12.

[0047] In another optional embodiment provided in this disclosure, the side of the bridging chip 30 facing the first sub-chip 11 and the second sub-chip 12 includes a redistribution layer. The active surface of the first sub-chip 11 facing the bridging chip 30 includes a redistribution layer, and the active surface of the second sub-chip 12 facing the bridging chip 30 includes a redistribution layer. In the same bridging chip 30, at least a portion of the redistribution layer of the bridging chip 30 is electrically connected to the redistribution layer of the active surface of the first sub-chip 11, and at least a portion of the redistribution layer of the bridging chip 30 is electrically connected to the redistribution layer of the active surface of the second sub-chip 12.

[0048] In actual fabrication, the bridging chip 30 can be directly connected to the active surfaces (i.e., the surfaces containing active elements such as transistors) of the first sub-chip 11 and the second sub-chip 12 using advanced interconnect technologies such as microbumps, through-silicon vias (TSVs), or hybrid bonding. Electrical connection between the first sub-chip 11 and the second sub-chip 12 can be achieved without the need for photomask splicing in the parallel direction. Instead of routing to the chip edge or through the substrate, the signal is transmitted along the shortest path, significantly reducing the signal transmission distance. The direct electrical connection between the bridging chip 30 and the active surfaces of the first sub-chip 11 and the second sub-chip 12 shortens the lead length, effectively reduces parasitic parameters, shortens signal rise time, reduces jitter, and improves signal transmission integrity.

[0049] Furthermore, the bridging chip 30 may include multiple parallel interconnect channels, each transmitting data independently, which helps to significantly increase the total bandwidth. When the bridging chip 30 and the first sub-chip 11 and the second sub-chip 12 use different process nodes, the bridging chip 30 can provide standardized high-speed interfaces (such as PCIe, HBM) to ensure high-bandwidth data exchange between heterogeneous chips.

[0050] Please continue to refer to this. Figure 2 In one optional embodiment provided in this disclosure, the bridging chip 30 is directly bonded to the first chip 10 or electrically connected through conductive bumps.

[0051] For example, direct bonding, including SiO2 fusion bonding and metal hot-press bonding, achieves atomic-level bonding through intermolecular forces or chemical bonds, eliminating the need for an intermediate layer and resulting in extremely low interface resistance. SiO2 fusion bonding can lock alignment precision through intermolecular forces during the room-temperature pre-bonding stage, meeting the high-density interconnect requirements of wafer-level packaging. The parasitic parameters of direct bonding, such as capacitance and inductance, are significantly lower than those of traditional wire bonding, supporting higher-frequency signal transmission and meeting the needs of high-speed data interfaces.

[0052] Conductive bumps can be metallic bumps, such as copper pillar bumps, or they can be solder balls, gold bumps, alloy bumps, or other suitable conductive bump structures. Conductive bumps mainly include metallic materials, including but not limited to at least one of tin, copper, nickel, silver-tin-copper alloys, or tin-based alloys.

[0053] Conductive bumps provide electrical connectivity interfaces by creating tiny metal bumps on the chip surface. They offer excellent thermal conductivity and electrical connectivity, making them particularly suitable for high-density packaging designs, supporting interconnect densities of thousands of I / Os per square millimeter. Compared to wire bonding, the electrical path length of conductive bumps is reduced to a fraction of that of wire bonding, resulting in significantly lower signal latency. In wafer-level packaging, conductive bump technology can also form bumps on the entire opposite side of the array chip or the first chip 10, enabling more I / O interfaces and supporting massively parallel computing.

[0054] Please refer to Figure 1 and Figure 2 In one optional embodiment provided in this disclosure, the size of the first chip 10 is the same as the size of the photomask used to etch the first chip 10.

[0055] Since actual photomasks cannot exceed the window of a lithography machine, wafer-level system integration typically requires photomask stitching techniques to achieve patterning larger than the photomask window. This can be achieved through multiple exposures and stitching techniques, such as photoresist stitching or step-and-repeat exposures, to complete the etching of the entire chip. This process involves complex alignment and stitching error control, leading to extended production cycles. Furthermore, multiple exposure stitching requires high-precision alignment systems, such as dual-stage systems and laser interferometers, to ensure the overlap accuracy of each exposure area. Alignment errors must be controlled at the nanometer level, demanding high precision. This embodiment of the present disclosure, by designing the size of the first chip 10 to be the same as the size of the photomask of the lithography machine used to etch the first chip 10, allows for flexible adjustment of the size of the photomask or the first chip 10 according to actual production needs, providing flexible design space for future process expansion. On the other hand, it allows for photolithography of different first chips 10 separately using the photomask, or for uniform photolithography of all first chips 10 on the substrate 20, eliminating the need for splicing adjacent first chips 10 in a direction parallel to the plane of the substrate 20 under the obstruction of the lithography machine window. Instead, electrical connection between adjacent first chips 10 is achieved through the bridging chip 30 located on the first chip 10, eliminating complex alignment steps and reducing operational complexity and equipment precision requirements.

[0056] In mass production, when the first chip 10 and the photomask are the same size, the lithography machine does not need to frequently adjust parameters or replace photomasks to adapt to chips of different sizes, thus improving equipment utilization and further shortening the overall production cycle. This simplifies the process and reduces operational complexity.

[0057] In traditional chip assembly processes, a safety zone must be reserved at the assembly boundary to avoid defects caused by alignment errors, which limits the chip integration density. The wafer-level system-on-package (WAP) structure 100 provided in this embodiment of the present disclosure does not require setting an assembly boundary between adjacent first chips 10, which can improve chip area utilization and support higher density chip integration.

[0058] In traditional chip fabrication processes, chip design must adhere to strict fabrication rules, such as the position of fabrication boundaries and the design of alignment marks, which limits the freedom of chip design. The wafer-level system packaging structure 100 provided in this disclosure eliminates fabrication constraints, allowing users to freely arrange chip functional modules and optimize signal paths.

[0059] Please refer to Figure 1 and Figure 2 In one alternative embodiment provided in this disclosure, the bridging chip 30 includes one or more active or passive devices.

[0060] The bridging chip 30 mentioned in the embodiments of this disclosure can be any kind of semiconductor chip, which may include active devices such as memory, logic circuits, power devices, bipolar devices, individual MOS transistors, microelectromechanical systems (MEMS), or even optoelectronic devices such as light-emitting diodes. It can also be a passive device, such as a resistor or capacitor. This disclosure does not limit the type of bridging chip 30, as long as it can connect two adjacent first chips 10.

[0061] Figure 3 The figure shown is a planar schematic diagram of a wafer-level system packaging structure provided in an embodiment of this disclosure. Figure 4 As shown Figure 3 A schematic diagram of the cross-section along section B-B'. Figure 5 As shown Figure 3 Please refer to another cross-sectional diagram along section B-B'. Figures 3 to 5 In one optional embodiment provided in this disclosure, the first chip 10 includes a third sub-chip 13 and at least one fourth sub-chip 14, wherein the third sub-chip 13 and the fourth sub-chip 14 are different. In this embodiment, the first chip 10 can be an integrated chip or a system-on-a-chip. For example, the third sub-chip 13 can be a PIC (Photonic Integrated Circuit) unit, and the fourth sub-chip 14 can be an EIC (Electronic Integrated Circuit) unit. Each fourth sub-chip 14 is interconnected with each third sub-chip 13 through 3D packaging to form an independent integrated chip, which is the first chip 10 in this embodiment of the disclosure. Figure 3This illustration only shows the case where the substrate 20 includes 16 first chips 10. This disclosure does not limit the arrangement or number of the first chips 10.

[0062] Please refer to Figure 4 and Figure 5 Along the direction perpendicular to the plane of substrate 20, the projection of the fourth sub-chip 14 onto substrate 20 lies within the projection range of the third sub-chip 13 onto substrate 20. This overcomes the limitations of a two-dimensional plane, achieving increased density through in-plane nesting in three-dimensional stacking. For example, if the third sub-chip 13 is a memory array (such as DRAM) and the fourth sub-chip 14 is a computing core (such as a CPU), the nested design allows the computing unit to be directly embedded inside the memory unit, improving the performance per unit area of ​​the in-memory computing architecture by more than 2 times, while reducing data transfer power consumption.

[0063] Of course, the third sub-chip 13 and the fourth sub-chip 14 can also be other types of chips. Furthermore, more than one fourth sub-chip 14 can be stacked on top of the third sub-chip 13, and other types of chips can also be stacked. This disclosure does not specifically limit this.

[0064] Please refer to Figure 4 and Figure 5 In one optional embodiment provided in this disclosure, the fourth sub-chip 14 is electrically connected to the third sub-chip 13, and the fourth sub-chip 14 on at least two adjacent third sub-chips 13 is electrically connected through a bridging chip 30.

[0065] By using a bridging chip 30 to electrically connect adjacent fourth sub-chips 14 in a direction parallel to the plane of substrate 20, the electrical connection between adjacent fourth sub-chips 14 can be achieved without the need for photomask splicing technology in the photolithography process. Since the projection of the fourth sub-chip 14 onto substrate 20 falls within the projection range of the third sub-chip 13 onto substrate 20, the fourth sub-chip 14 is more recessed than the third sub-chip 13 in the direction parallel to the plane of substrate 20. If photomask splicing technology were used, the length of the metal lines between adjacent fourth sub-chips 14 would be longer, and correspondingly, the alignment of the metal lines formed by photolithography on adjacent sides would be more difficult in the photomask splicing process. This embodiment of the present disclosure, by using a bridging chip 30 to electrically connect adjacent fourth sub-chips 14 in a direction parallel to the plane of substrate 20, eliminates the need for high-precision alignment processes, reducing process difficulty and achieving electrical connection between adjacent fourth sub-chips 14. It also shortens the interconnection path length between adjacent fourth sub-chips 14, reduces signal transmission loss and power consumption, optimizes the interconnection layout, and improves signal transmission efficiency.

[0066] Understandably, adjacent fourth sub-chips 14 are electrically connected through bridging chip 30, while in the same first chip 10, the fourth sub-chip 14 is electrically connected to the third sub-chip 13, that is, adjacent third sub-chips 13 can also be electrically connected.

[0067] Please refer to Figure 4 In one optional embodiment provided in this disclosure, the wafer-level system package structure 100 further includes a redistribution layer 40, which is located on the side of the first chip 10 facing the bridging chip 30.

[0068] Please refer to Figure 4 The redistribution layer 40 includes at least one patterned metal layer. For example, the redistribution layer 40 may include three patterned metal layers, or four patterned metal layers, or five patterned metal layers, etc., and so on. For simplicity, the accompanying drawings in this disclosure only illustrate the redistribution layer 40 as a single film layer. Insulating layers may also be included between the multiple metal layers in the redistribution layer 40, which can be specifically configured according to the actual number of metal layers. The metal layers are selected from metal materials with good conductivity, including but not limited to copper, titanium, gold, silver, aluminum, and tin.

[0069] In one optional embodiment provided in this disclosure, the bridging chip 30 may or may not include the redistribution layer 40; this disclosure does not limit this aspect. Figure 4 The illustration only takes the bridging chip 30 excluding the redistribution layer 40 as an example. The bridging chip 30 can be an active or passive device, and this disclosure does not limit it to this. In this embodiment, the bridging chip 30 is located on the side of the fourth sub-chip 14 away from the substrate 20. Without the need for complex photomask splicing technology, the bridging chip 30 can be electrically connected to the redistribution layer 40 of the first chip 10 through direct bonding or conductive bumps, thereby realizing electrical connections between adjacent fourth sub-chips 14 and between adjacent third sub-chips 13, which can reduce process difficulty and production costs.

[0070] Please refer to Figure 5 In another optional embodiment provided in this disclosure, the bridging chip 30 is embedded inside the substrate 20. The bridging chip 30 may or may not include a first redistribution layer 31. This disclosure does not limit the scope of the embodiment. Figure 5The illustration only takes the bridging chip 30 including the first redistribution layer 31 as an example. In this embodiment, since the bridging chip 30 is embedded inside the substrate 20, the electrical connection between the first redistribution layer 31 in the bridging chip 30 and the redistribution layer 40 in the first chip 10 can also achieve the electrical connection between the adjacent fourth sub-chip 14 and the adjacent third sub-chip 13 without the need for complex photomask splicing technology. Similarly, it does not require a strict alignment process, which helps to reduce the difficulty of the process and reduce the production cost.

[0071] Because the relative distance between the first redistribution layer 31 in the bridging chip 30 and the redistribution layer 40 in the first chip 10 is shorter, the bonding structure or conductive bumps in the bridging chip 30 can be set to a relatively short length to achieve electrical connection with the adjacent first chip 10, which can further reduce signal attenuation and latency, and improve signal transmission quality. In addition, embedding the bridging chip 30 inside the substrate 20 can reduce the height of the wafer-level system package structure 100, which is beneficial to achieving a thinner package structure.

[0072] Optionally, an organic layer may also be provided on the side of the redistribution layer 40 facing the bridging chip 30. The material of the organic layer may be polyimide, etc., and this disclosure does not limit it. The organic layer covers the surface of the redistribution layer 40 to provide protection for the redistribution layer 40, isolate water, oxygen, etc. in the external environment from corroding the metal layer and the chip, and also to relieve and disperse stress.

[0073] This disclosure provides an electronic device including the wafer-level system-on-package (WAP) structure 100 as described above. The electronic device provided in this disclosure has the technical effects corresponding to the wafer-level system-on-package (WAP) structure 100 provided in this disclosure, which will not be elaborated further.

[0074] The above are merely specific embodiments of this disclosure, enabling those skilled in the art to understand or implement this disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to these embodiments, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A wafer-level system packaging structure, characterized in that, Includes: a substrate, on which a first array of chips is formed. A bridging chip is located on the side of the first chip facing away from the substrate, along a direction perpendicular to the plane of the substrate. The projection of the bridging chip on the substrate at least partially overlaps with the first chip. The bridging chip is used to connect at least two adjacent first chips.

2. The packaging structure as described in claim 1, characterized in that, include: The first chip includes a first sub-chip and a second sub-chip, and the first sub-chip and the second sub-chip are adjacent to each other along a direction parallel to the plane of the substrate. The projection of the bridging chip onto the substrate at least partially overlaps with the first sub-chip and at least partially overlaps with the second sub-chip.

3. The packaging structure as described in claim 2, characterized in that, include: The first chip includes an active surface, and the bridging chip is electrically connected to the active surface of the first sub-chip and to the active surface of the second sub-chip.

4. The packaging structure as described in claim 1, characterized in that, include: The bridging chip is directly bonded to the first chip or electrically connected via conductive bumps.

5. The packaging structure as described in claim 1, characterized in that, include: The size of the first chip is the same as the size of the photomask used in the lithography machine to etch the first chip.

6. The packaging structure as described in claim 1, characterized in that, include: The bridging chip includes one or more active or passive devices.

7. The packaging structure as described in claim 1, characterized in that, include: The first chip includes a third sub-chip and at least one fourth sub-chip, wherein the third sub-chip is different from the fourth sub-chip; Along a direction perpendicular to the plane of the substrate, the projection of the fourth sub-chip onto the substrate is within the projection range of the third sub-chip onto the substrate.

8. The packaging structure as described in claim 7, characterized in that, include: The fourth sub-chip is electrically connected to the third sub-chip, and the fourth sub-chips on at least two adjacent third sub-chips are electrically connected through the bridge chip.

9. The packaging structure as described in claim 7, characterized in that, include: The packaging structure also includes a redistribution layer located on the side of the first chip facing the bridging chip.

10. An electronic device, characterized in that, include: The wafer-level system packaging structure as described in any one of claims 1-9.

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