Harmonic current suppression method, system and product of three-phase three-level inversion twin trawling system

Abstract

The invention relates to the field of three-level inversion twin-trawling systems, and particularly discloses a harmonic current suppression method, system and product of a three-phase three-level inversion twin-trawling system, and the method specifically comprises the following steps: S1, a bus voltage balance control step; s101, acquiring a bus voltage error value; s102, acquiring a bus voltage error correction value; s2, a neutral current harmonic suppression step; s201, acquiring a common-mode current flowing through a node connected with the power side and the load side; s202, acquiring a higher harmonic component in the common-mode current; s203, obtaining a higher harmonic component suppression correction value; and S3, superposing the corrected value and a three-phase voltage output modulation wave to obtain a three-phase inverter circuit modulation signal of a power side in the three-phase three-level inverter twin trawling system. The harmonic suppression algorithm of the output current can be provided based on the single-power three-phase dragging system, the cost can be reduced, and the current distortion can be reduced, so that the real current output condition can be simulated.

Description

Technical Field

[0001] This application relates to the field of three-level inverter parallel drive system technology, specifically to a harmonic current suppression method, system and product for a three-phase three-level inverter parallel drive system. Background Technology

[0002] Three-phase three-level inverter parallel drive systems are mostly used for testing high-power equipment or modules. They consist of two inverter units with a three-level topology. One unit serves as the master drive or simulates the power device under test, while the other serves as the slave drive or simulates the load. The two units are connected by a drive shaft or electrical connection to form a system in which energy can circulate between them.

[0003] Because inverter-driven parallel-drive systems have large neutral currents and numerous capacitors, current distortion is easily caused during parallel-drive operations. To avoid this problem, inverter-driven parallel-drive systems often employ a dual-supply clamping capacitor voltage mode. While this circuit topology design can reduce current distortion by lowering bus voltage imbalance, it significantly increases equipment costs and cannot solve the problem of high-order harmonics appearing in the neutral current due to various other reasons. Summary of the Invention

[0004] The purpose of this application is to overcome the shortcomings of the prior art and provide a method, system and product for suppressing harmonic current in a three-phase three-level inverter-driven system. It can provide a harmonic suppression algorithm for the output current of a single-power-supply three-phase driven system, which can reduce costs and reduce current distortion, thereby simulating the real current output situation.

[0005] Firstly, this application provides a method for suppressing harmonic currents in a three-phase three-level inverter-driven system, the technical solution of which includes the following steps: S1, Bus voltage balancing control steps; specifically including: S101, obtain the bus voltage error value; S102, Based on the bus voltage error value, obtain the bus voltage error correction value; S2, Neutral line current harmonic suppression step; specifically includes: S201, obtain the common-mode current flowing through the node connecting the power side and the load side in the three-phase three-level inverter parallel system; S202 performs harmonic analysis on the common-mode current to obtain the higher-order harmonic components in the common-mode current. S203, based on higher harmonic components, obtain the correction value for suppressing higher harmonic components; S3, the obtained bus voltage error correction value and the high-order harmonic component suppression correction value are superimposed, and then superimposed with the three-phase voltage output modulation wave to obtain the three-phase inverter circuit modulation signal on the power side of the three-phase three-level inverter-pull system with the bus voltage error correction modulation signal and the harmonic component suppression correction modulation signal loaded.

[0006] Through the above technical solution, two new control processes are introduced on the basis of the traditional inverter output voltage control process. One control process adjusts the error value of the bus voltage to achieve balance, and the other control process suppresses the high-order harmonic components in the measured neutral line common-mode current. By superimposing the modulation signals output by the two control processes with the three-phase voltage output modulation wave, the three-phase inverter circuit modulation signal of the power side switching transistor of the parallel drive system is obtained, thus solving the current distortion problem caused by bus voltage imbalance and neutral line common-mode harmonic components in the three-phase three-level inverter parallel drive system.

[0007] Preferably, in S101, the specific method for obtaining the bus voltage error value is to obtain the positive half bus voltage and the negative half bus voltage, and calculate the difference between the positive half bus voltage and the negative half bus voltage to obtain the bus voltage error value.

[0008] Preferably, the sampled digital values ​​of the positive half bus voltage and the negative half bus voltage are obtained. The true values ​​of the positive half bus voltage and the negative half bus voltage are obtained through a mapping table of the sampled digital values ​​of the bus voltage with respect to the true values ​​of the bus voltage. The bus voltage error value is obtained through the difference between the true values ​​of the positive half bus voltage and the true values ​​of the negative half bus voltage.

[0009] The above technical solution enables the acquisition of the true value of the bus voltage based on the digital values ​​of the positive and negative bus voltages obtained through sampling, using a mapping table. This avoids the sampling chip obtaining the digital values ​​of the bus sampling points by scaling the bus voltage, which would cause the digital values ​​to deviate from the true values. Thus, the bus voltage error value can be calculated from the true value of the bus voltage, serving as the basis for obtaining the bus voltage error correction value.

[0010] Preferably, in S102, the bus voltage error value is input to the proportional-integral controller to obtain the bus voltage error correction value. The bus voltage error correction value aims to reduce the voltage difference between the positive half and the negative half of the bus voltage and adjusts the amplitude of the positive or negative half of the phase voltage.

[0011] By inputting the bus voltage error value into the proportional-integral controller through the above technical solution, the bus voltage error value can be quickly responded to changes in bus voltage, realize feedforward control, accelerate the response speed to sudden changes in bus voltage, suppress current distortion, and reduce the burden of feedback control.

[0012] Preferably, in S201, the specific method for obtaining the common-mode current is to obtain the three-phase currents output from the power side of the three-phase three-level inverter system and add them vector-wise to obtain the common-mode current.

[0013] The above technical solution can conveniently and efficiently obtain the common-mode current, and enable the common-mode current to reflect the higher harmonics of the common-mode voltage waveform, serving as the basis for implementing the modulation strategy.

[0014] Preferably, in S202, a power analyzer or a spectrum analyzer is used to obtain the higher harmonic components in the common-mode current.

[0015] Preferably, the higher harmonic components in the common-mode current include several types of higher harmonic components of different frequencies. For any type of higher harmonic component corresponding to a specific frequency, a quasi-proportional resonant controller is matched to output a compensation voltage signal for the corresponding higher harmonic component. Several quasi-proportional resonant controllers are connected in parallel to output a correction value for suppressing higher harmonic components.

[0016] The above technical solution uses a power analyzer or spectrum analyzer to obtain the main harmonic components in the common-mode current, identify harmonics such as the third and fifth harmonics, and determine the target harmonics to be suppressed. The frequency and amplitude of the target harmonics are recorded. Then, a quasi-proportional resonant controller is configured for each type of higher harmonic. The quasi-proportional resonant controller generates a compensation voltage signal that is equal in magnitude and opposite in phase to the higher harmonic component, thereby suppressing the harmonics.

[0017] Secondly, the harmonic current suppression system of a three-phase three-level inverter coupled system provided in this application adopts a technical solution including a three-phase three-level inverter coupled circuit, a harmonic suppression circuit and a line voltage control circuit. The three-phase three-level inverter circuit includes a power supply circuit, a power side circuit, and a load side circuit. The power circuit includes power supply V. dc and respectively connected to power supply V dc Positive half-DC bus C of positive and negative terminals PO and negative half DC bus C ON Positive half DC bus C PO and negative half DC bus C ON They are interconnected, with point O as the neutral point of the connection. Both the power-side circuit and the load-side circuit are three-phase three-level inverter circuits with ANPC topology, and are powered through the power supply circuit. The harmonic suppression circuit is connected to the power supply circuit and to the output terminals of each phase inverter circuit of the power side circuit to obtain the correction modulation signal; The line voltage control loop is connected to the input terminals of each phase inverter circuit of the load-side loop. The correction modulation signal is superimposed with the three-phase voltage output modulation wave, and a PWM drive signal is obtained through the pulse width modulation module. The PWM drive signal modulates the switching transistors of each phase inverter circuit of the power-side loop.

[0018] Preferably, the harmonic suppression circuit includes a bus voltage equalization control circuit and a neutral line current harmonic suppression circuit. The bus voltage equalization control circuit is connected to the positive half DC bus C respectively. PO and negative half DC bus C ON The positive half bus voltage and the negative half bus voltage are obtained, the bus voltage error value is calculated, and then the bus voltage error correction value is obtained through the proportional-integral controller. The neutral line current harmonic suppression circuit is connected to the output terminals of each phase inverter circuit of the power side circuit to obtain the output three-phase current, and then vector-sums them to obtain the common-mode current. Then, the higher harmonic components of the common-mode current are obtained, and the correction value for suppressing the higher harmonic components is obtained through the quasi-proportional resonant controller. The correction modulation signal is obtained by superimposing the bus voltage error correction value and the higher harmonic component correction value, and then output to the line voltage control loop.

[0019] Thirdly, the computer program product provided in this application employs a technical solution including a computer program or instructions, which enables the computer program or instructions to implement the steps in the above-mentioned harmonic current suppression method for a three-phase three-level inverter coupled system.

[0020] In summary, this application includes at least one of the following beneficial technical effects: 1. This application can control the bus voltage imbalance and high harmonic content of output current that are prone to occur in single-power supply three-phase three-level inverter parallel drive systems. It does not require the configuration of dual power supply clamping capacitor voltage, and the parallel drive system architecture is simple and low cost.

[0021] 2. This application can effectively suppress the harmonics of the output current of a three-phase three-level inverter-driven system, reduce current distortion, and achieve the purpose of reasonably simulating the working conditions.

[0022] 3. This application and patent can balance the bus voltage and avoid damage to the test module caused by the imbalance of the bus voltage while ensuring that the current harmonics meet the standards. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the architecture of a single-power-mode three-phase three-level inverter-pull system in an embodiment of this application. Figure 2This is a schematic diagram of the bus voltage equalization control loop in the embodiments of this application; Figure 3 This is a schematic diagram of the neutral line current harmonic suppression control loop in the embodiments of this application; Figure 4 This is a schematic flowchart illustrating a harmonic current suppression method for a three-phase three-level inverter-driven system according to an embodiment of this application. Figure 5 This is a schematic diagram of the harmonic current suppression system architecture of a three-phase three-level inverter-driven system according to an embodiment of this application; Figure 6 This is a schematic diagram illustrating the process of superimposing the modified modulation signal and the three-phase current output modulation wave to obtain the PWM drive signal in another embodiment of this application. Detailed Implementation

[0024] This specific embodiment is merely an explanation of this application and is not intended to limit it. After reading this specification, those skilled in the art can make modifications to this embodiment without contributing any inventive step, but such modifications are protected by patent law as long as they are within the scope of this application.

[0025] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. It should be noted that in the optional embodiments of this application, the object information and other related data involved require the permission or consent of the object when the embodiments of this application are applied to specific products or technologies, and the collection, use, and processing of related data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. That is to say, if the embodiments of this application involve data related to the object, it needs to be obtained with the authorization and consent of the object, the authorization and consent of the relevant departments, and in compliance with the relevant laws, regulations, and standards of the country and region. If personal information is involved in the embodiments, the acquisition of all personal information requires the consent of the individual. If sensitive information is involved, the separate consent of the information subject is required, and the embodiments also need to be implemented with the authorization and consent of the object.

[0026] The embodiments of this application will now be described in further detail with reference to the accompanying drawings.

[0027] Please see Figure 1This is a schematic diagram of the architecture of a single-power-supply mode three-phase three-level inverter-driven system according to an embodiment of this application, including a power supply loop 1, a power-side loop 2, and a load-side loop 3. The power-side loop 2 and the load-side loop 3 employ an ANPC topology three-phase three-level inverter circuit. In this embodiment, the power-side loop 2 is used to simulate the power output from the generator unit to the grid, and the load-side loop 3 is used to simulate the load on the grid, thereby enabling the simulation testing of high-power modules.

[0028] Among them, power supply circuit 1 includes DC power supply V DC and respectively connected to power supply V dc Positive half-DC bus C of positive and negative terminals PO and negative half DC bus C ON Positive half DC bus C PO and negative half DC bus C ON The connections are made interconnected, with point O as the neutral point. The DC power supply is V. DC The positive terminal is point P, and the negative terminal is point N. The positive half-DC bus C... PO and negative half DC bus C ON It can smooth DC voltage fluctuations and ripples caused by high-speed switching of power devices, maintain voltage stability, provide the instantaneous large current required for high-speed switching of the inverter bridge's switching transistors, improve response speed, and maintain the potential balance of the neutral point O.

[0029] Because the system has a large neutral current and a large number of capacitors, current distortion can easily occur during system dragging, resulting in harmonics and affecting the system's test performance. The embodiments of this application employ two control loops to suppress harmonics.

[0030] Please see Figure 2 The first control loop is for equalizing the bus voltage. During the reverse operation, the imbalance between the current flowing into and out of the neutral point O will cause the positive half DC bus voltage V to decrease. PO and negative half DC bus voltage V ON Uneven voltage distribution causes neutral point potential shift, leading to output waveform distortion, increased harmonics, and increased voltage stress on the switching transistors. By modulating the output waveform on the power side, the positive and negative bus voltages are balanced, thereby improving the symmetry of the inverter circuit's output waveform and suppressing harmonic generation at its source. This control loop uses amplitude modulation based on bus voltage deviation and is a type of feedforward compensation.

[0031] The first control loop in this embodiment is described in detail below. First, the sampled digital values ​​of the positive half bus voltage and the negative half positive half bus voltage are obtained. Then, the positive half bus voltage V is obtained through a mapping table of the sampled digital values ​​with respect to the actual bus voltage values. PO and negative half bus voltage VON The true value of the bus voltage. By subtracting the two, the error value V of the bus voltage can be obtained. err , there is: V err =V PO -V ON .

[0032] It should be noted that since the voltage sampling chip cannot directly receive the amplitude of the actual bus voltage, the bus voltage needs to be scaled down to a reasonable range to be accepted by the sampling chip and converted into a digital value. Therefore, the digital value cannot directly reflect the actual amplitude of the bus voltage, and a mapping table is needed to convert the digital value into the actual value. The method for obtaining the mapping table is to use a linear fitting method to obtain the mapping table by pre-given n actual bus voltage values ​​and n sampled digital values. The accuracy of obtaining the actual bus voltage value directly affects the accuracy of obtaining the bus voltage error value, thus affecting the effect of harmonic removal. Therefore, it is necessary to obtain the actual bus voltage value through the mapping table before calculating the bus voltage error value.

[0033] The error value V of the bus voltage err The proportional-integral (PI) controller is input to obtain the bus voltage error correction value. This correction value aims to reduce the voltage difference between the positive and negative half of the bus voltage, adjusting the amplitude of the positive or negative half of the output voltage waveform of each phase on the power side. This bus voltage error correction value is then superimposed on the modulated waveform of the three-phase voltage output on the power side and input to the pulse width modulation (PWM) module to obtain the PWM drive signal for the power-side switching transistors, which carries the bus voltage error correction signal.

[0034] Please see Figure 3 The second control loop suppresses neutral line current harmonics. In a three-phase three-level parallel-drive system, when the current flowing through the load is not linearly related to the applied voltage, a nonlinear current is formed, generating harmonics. Three-level inverters, due to their switching action, are typical nonlinear loads, causing current waveform distortion and generating numerous high-order harmonics, such as the 3rd and 5th harmonics. Especially for the 3rd, 9th, and 15th harmonics (the 3Nth order), they are in phase in the three phases and do not cancel each other out when flowing to the neutral point, but rather directly superimpose. In a parallel-drive system, both inverters on both sides can generate harmonics. When the load changes or the control strategies on both sides are mismatched, it may lead to an imbalance in the three-phase current, which will further exacerbate harmonics of specific frequencies, especially the 3Nth order harmonics flowing and superimposing on the neutral line. By modulating the output waveform on the power side, neutral line current harmonics can be suppressed. This control loop is a modulation strategy specifically designed to cancel specific high-order harmonics in the load current in real time, belonging to feedback compensation.

[0035] The second control loop in this embodiment is described in detail below. The three-phase output currents Ia, Ib, and Ic of the power-side loop 2 are obtained, and their vector summation yields the common-mode current I flowing through the node connecting the power side and the load side. comm , there is I comm =Ia+Ib+Ic.

[0036] The common-mode current I can be obtained conveniently and efficiently using a power analyzer or a spectrum analyzer. comm The system detects various high-order harmonic components at different frequencies. For any type of high-order harmonic component at a specific frequency, a quasi-proportional resonant controller (PR) is matched to output a compensation voltage signal for the corresponding high-order harmonic component. Several quasi-proportional resonant controllers are connected in parallel to output a high-order harmonic component suppression correction value. This high-order harmonic component suppression correction value is superimposed on the three-phase voltage output modulation wave on the power side and input to the pulse width modulation module to obtain the PWM drive signal for the power-side switching transistors loaded with the high-order harmonic component suppression correction signal.

[0037] The first control loop of feedforward compensation and the second control loop of feedback compensation form a feedforward-feedback composite control loop, which can simultaneously improve the steady-state and dynamic harmonic suppression performance of the output waveform of the drive system. Feedforward compensation can accelerate the response speed to sudden changes in bus voltage and reduce the burden of feedback control; while harmonic feedback compensation can specifically suppress harmonics of a certain order to a lower level, significantly reducing the total harmonic distortion rate of the output current.

[0038] It should also be noted that, in order to simplify the modulation strategy and reduce system complexity, in the actual application of this application embodiment, the modulation signal of the bus voltage error correction value and the modulation signal of the correction value of the harmonic component suppression value are first superimposed, and then superimposed with the three-phase voltage output modulation wave, and then output to the pulse width modulation module to generate the PWM drive signal of the power side switching transistor.

[0039] Therefore, please refer to Figure 4 The harmonic current suppression method for a three-phase three-level inverter-driven system according to an embodiment of this application specifically includes the following steps: S1, Bus Voltage Balancing Control Steps. Specifically, these include: S101, Obtain the positive half-bus voltage V PO and negative half bus voltage V ON The difference is used to obtain the bus voltage error value.

[0040] S102, input the bus voltage error value into the proportional-integral controller PI to obtain the bus voltage error correction value.

[0041] S2, Neutral line current harmonic suppression step; specifically includes: S201: Obtain the three-phase currents Ia, Ib, and Ic flowing through the nodes connecting the power side and the load side in the three-phase three-level inverter system, and add the phasors to obtain the common-mode current.

[0042] S202, use a power analyzer or spectrum analyzer to perform harmonic analysis on the common-mode current to obtain the high-order harmonic components of different frequencies in the common-mode current.

[0043] S203 is configured with a quasi-proportional resonant controller PR corresponding to the higher harmonic components of each frequency. The quasi-proportional resonant controllers PR are connected in parallel to each other and output correction values ​​to suppress higher harmonic components.

[0044] S3, the obtained bus voltage error correction value and the high-order harmonic component suppression correction value are superimposed, and then superimposed with the three-phase voltage output modulation wave to obtain the three-phase inverter circuit modulation signal on the power side of the three-phase three-level inverter-pull system with the bus voltage error correction modulation signal and the harmonic component suppression correction modulation signal loaded.

[0045] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0046] Please see Figure 5 Another embodiment of this application provides a harmonic current suppression system for a three-phase three-level inverter-driven system, used to suppress harmonic currents in a three-phase three-level inverter-driven system. Figure 1 The single-supply mode three-phase three-level inverter in the system performs harmonic suppression. Specifically, it includes harmonic suppression circuit 4 and line voltage control circuit 5.

[0047] Among them, line voltage control loop 5 is a commonly used implementation method for providing a three-phase voltage output modulation wave. Line voltage control loop 5 is connected to the load-side input terminal to obtain the three-phase input voltage U. ab U bc U ca Then, the Parker transformation (dq transformation) is performed to convert the AC quantities in the three-phase stationary coordinate system into DC quantities in the two-phase rotating coordinate system (dq), so that the voltage vector is decomposed into two DC components U that remain constant in the rotating coordinate system. d and U q Then input it into the comparator and compare it with the target reference value U. d_ref and U q_refThe comparison is performed, and the result is input to a proportional-integral (PI) controller, which outputs an adjustment value. This value is then converted into a three-phase voltage output modulation wave through an inverse Parker transformer. In conventional implementations, the three-phase voltage output modulation wave is input to a pulse-width modulation (PWM) module to generate a three-phase PWM drive signal that controls the power-side switching transistors according to modulation requirements. However, this PWM drive signal cannot effectively suppress the generated harmonics.

[0048] In the harmonic current suppression system of the three-phase three-level inverter coupled system in this application embodiment, the harmonic suppression circuit 4 includes a bus voltage equalization control circuit and a neutral line current harmonic suppression circuit.

[0049] The bus voltage equalization control circuit is connected to the positive half DC bus C respectively. PO and negative half DC bus C ON The positive and negative bus voltages are obtained, the bus voltage error value is calculated, and then the bus voltage error correction value is obtained through a proportional-integral controller (PI).

[0050] The neutral line current harmonic suppression circuit is connected to the output terminals of each phase inverter circuit of the power side circuit, obtains the output three-phase currents Ia, Ib, and Ic, and adds them vectorively to obtain the common-mode current. Then, the higher harmonic components of the common-mode current are obtained, and the correction value for suppressing the higher harmonic components is obtained through the quasi-proportional resonant controller PR.

[0051] The correction modulation signal is obtained by superimposing the bus voltage error correction value and the higher harmonic component correction value, and then output to the line voltage control loop.

[0052] Line voltage control loop 5 superimposes the correction modulation signal with the three-phase voltage output modulation wave, and then obtains a PWM drive signal through the pulse width modulation module. This PWM drive signal is the modulation signal of the power-side inverter circuit that loads the bus voltage error correction modulation signal and the harmonic component suppression correction modulation signal, modulating the switching transistors of each phase inverter circuit in the power-side loop. The output waveform of the power-side loop adjusted by this PWM drive signal can effectively suppress various harmonics, reduce current distortion, and better simulate real-world operating conditions.

[0053] In the above embodiment, a line voltage control loop 5 is connected to the load-side input terminal to sample the three-phase voltage, perform Parker conversion, and compare it with a reference value to obtain the three-phase voltage output modulation wave. A corrected modulation signal is then superimposed on the three-phase voltage output modulation wave to obtain the PWM drive signal. For another implementation, please refer to... Figure 6Similarly, the modulation direction can be reversed. A line voltage control loop 5 is connected to the power-side output terminal to sample the three-phase current, perform Parker conversion, and compare it with a quasi-value to obtain the three-phase current output modulation wave. Then, the corrected modulation signal is superimposed on the three-phase current output modulation wave. The resulting signal is then subjected to inverse Parker conversion and input to a pulse width modulation module to obtain a PWM drive signal. In this implementation, the corrected modulation signal is a modulation signal related to the current waveform. The specific implementation method is similar to the aforementioned embodiments and will not be elaborated here.

[0054] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working process of the harmonic current suppression system of the three-phase three-level inverter coupled system described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here. Those skilled in the art will also understand that, for the sake of convenience and brevity, the above division of functional units and modules is only used as an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0055] Another embodiment of this application provides a computer program product comprising a computer program or instructions that enables the computer program or instructions to implement the steps in the above-described method for suppressing harmonic current in a three-phase three-level inverter-driven system.

[0056] As used in the above embodiments, depending on the context, the term "when..." can be interpreted as meaning "if...", "after...", "in response to determining...", or "in response to detecting...". Similarly, depending on the context, the phrase "when determining..." or "if (the stated condition or event) is interpreted as meaning "if determining...", "in response to determining...", "when (the stated condition or event) is detected", or "in response to detecting (the stated condition or event)".

[0057] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," "third," and similar terms used in this application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. The terms "an" or "a" and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms "comprising" or "including" and similar terms mean that the elements or objects preceding "comprising" or "including" encompass the elements or objects listed following "comprising" or "including" and their equivalents, and do not exclude other elements or objects. "Above," "below," "left," "right," etc., are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0058] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A method for suppressing harmonic currents in a three-phase three-level inverter-driven system, characterized in that, Includes the following steps: S1, Bus voltage balancing control steps; specifically including: S101, obtain the bus voltage error value; S102, Based on the bus voltage error value, obtain the bus voltage error correction value; S2, Neutral line current harmonic suppression step; specifically includes: S201, obtain the common-mode current flowing through the node connecting the power side and the load side in the three-phase three-level inverter parallel system; S202 performs harmonic analysis on the common-mode current to obtain the higher-order harmonic components in the common-mode current. S203, based on higher harmonic components, obtain the correction value for suppressing higher harmonic components; S3, the obtained bus voltage error correction value and the high-order harmonic component suppression correction value are superimposed, and then superimposed with the three-phase voltage output modulation wave to obtain the three-phase inverter circuit modulation signal on the power side of the three-phase three-level inverter-pull system with the bus voltage error correction modulation signal and the harmonic component suppression correction modulation signal loaded.

2. The method for suppressing harmonic currents in a three-phase three-level inverter-driven system according to claim 1, characterized in that, In S101, the specific method for obtaining the bus voltage error value is to obtain the positive half bus voltage and the negative half bus voltage, and calculate the difference between the positive half bus voltage and the negative half bus voltage to obtain the bus voltage error value.

3. The method for suppressing harmonic currents in a three-phase three-level inverter-driven system according to claim 2, characterized in that, Obtain the sampled digital values ​​of the positive half bus voltage and the negative half bus voltage. Through the mapping table of the sampled digital values ​​of the bus voltage with respect to the true value of the bus voltage, obtain the true value of the positive half bus voltage and the true value of the negative half bus voltage. Obtain the bus voltage error value by the difference between the true value of the positive half bus voltage and the true value of the negative half bus voltage.

4. The method for suppressing harmonic currents in a three-phase three-level inverter-driven system according to claim 2, characterized in that, In S102, the bus voltage error value is input to the proportional-integral controller to obtain the bus voltage error correction value. The bus voltage error correction value aims to reduce the voltage difference between the positive half and the negative half of the bus voltage and adjusts the amplitude of the positive or negative half of the output voltage waveform of each phase on the power side.

5. A method for suppressing harmonic currents in a three-phase three-level inverter-driven system according to claim 1, characterized in that, In S201, the specific method for obtaining the common-mode current is to obtain the three-phase currents output from the power side of the three-phase three-level inverter system and add them vectorwise to obtain the common-mode current.

6. The method for suppressing harmonic currents in a three-phase three-level inverter-driven system according to claim 1, characterized in that, In S202, a power analyzer or a spectrum analyzer is used to obtain the higher harmonic components in the common-mode current.

7. A method for suppressing harmonic currents in a three-phase three-level inverter-driven system according to claim 6, characterized in that, The higher harmonic components in the common-mode current include several types of higher harmonic components of different frequencies. For any type of higher harmonic component corresponding to a specific frequency, a quasi-proportional resonant controller is matched to output the compensation voltage signal of the corresponding higher harmonic component. Several quasi-proportional resonant controllers are connected in parallel to output correction values ​​for suppressing higher harmonic components.

8. A harmonic current suppression system for a three-phase three-level inverter-driven system, characterized in that, This includes a three-phase three-level inverter circuit, a harmonic suppression circuit, and a line voltage control circuit; The three-phase three-level inverter circuit includes a power supply circuit, a power side circuit, and a load side circuit. The power circuit includes power supply V. dc and respectively connected to power supply V dc Positive half-DC bus C of positive and negative terminals PO and negative half DC bus C ON Positive half DC bus C PO and negative half DC bus C ON They are interconnected, with point O as the neutral point of the connection. Both the power-side circuit and the load-side circuit are three-phase three-level inverter circuits with ANPC topology, and are powered through the power supply circuit. The harmonic suppression circuit is connected to the power supply circuit and to the output terminals of each phase inverter circuit of the power side circuit to obtain the correction modulation signal; The line voltage control loop is connected to the input terminals of each phase inverter circuit of the load-side loop. The correction modulation signal is superimposed with the three-phase voltage output modulation wave, and a PWM drive signal is obtained through the pulse width modulation module. The PWM drive signal modulates the switching transistors of each phase inverter circuit of the power-side loop.

9. The harmonic current suppression system for a three-phase three-level inverter coupled system according to claim 8, characterized in that, The harmonic suppression circuit includes a bus voltage equalization control circuit and a neutral line current harmonic suppression circuit. The bus voltage equalization control circuit is connected to the positive half DC bus C respectively. PO and negative half DC bus C ON The positive half bus voltage and the negative half bus voltage are obtained, the bus voltage error value is calculated, and then the bus voltage error correction value is obtained through the proportional-integral controller. The neutral line current harmonic suppression circuit is connected to the output terminals of each phase inverter circuit of the power side circuit to obtain the output three-phase current, and then vector-sums them to obtain the common-mode current. Then, the higher harmonic components of the common-mode current are obtained, and the correction value for suppressing the higher harmonic components is obtained through the quasi-proportional resonant controller. The correction modulation signal is obtained by superimposing the bus voltage error correction value and the higher harmonic component correction value, and then output to the line voltage control loop.

10. A computer program product, characterized in that, The computer program product includes a computer program or instructions that enable the computer program or instructions to perform the steps in the harmonic current suppression method for a three-phase three-level inverter coupled system according to any one of claims 1 to 7.

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