FPGA-based automatic calibration method and system for double-channel synchronous output of DAC

Abstract

The application discloses a DAC double-channel synchronous output automatic calibration method and system based on FPGA, relates to the technical field of multi-channel data synchronization, and comprises the following steps: calculating a clock delay calibration value according to a link delay value read from the register of a DAC chip, and configuring the register of the DAC chip according to the clock delay calibration value; calculating a data dynamic delay compensation value according to the phase difference value between the SYSREF phase measurement values read from two DAC chips; calculating a fixed delay compensation value corresponding to the two DAC chips according to the waveform phase difference time of two-channel test data; calculating a data delay compensation value according to the data dynamic delay compensation value and the fixed delay compensation value; and performing delay processing on the data needed to be sent to the two DAC chips by using the data delay compensation value. The application can automatically complete the DAC synchronous output calibration of double channels, and does not need to compile FPGA programs when producing double-channel board cards, thereby improving the production efficiency.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of multi-channel data synchronization, in particular to a DAC double-channel synchronous output automatic calibration method and system based on FPGA. BACKGROUND

[0002] AD9164 is a high-performance 16-bit digital-to-analog converter (DAC), which supports a high update rate of up to 6Gsps. In the baseband mode, the data rate of AD9164 supports up to 5Gsps. Therefore, AD9164 is often used in combination with a field programmable gate array (FPGA) in a high conversion rate arbitrary wave generator board card.

[0003] The FPGA mainly completes the SPI register configuration of the AD9164 chip and the JESD204B interface data output. Since the AD9164 chip is a single-channel DAC chip, two AD9164 chips are needed for a double-channel high conversion rate arbitrary wave generator board card. In actual application, the channels of the arbitrary wave generator need to be synchronized.

[0004] However, due to the differences in hardware wiring and output circuit and the like in signal transmission rate, the output delays of channels of different batches of high conversion rate arbitrary wave generator board cards are inconsistent, so that the delays of AD9164 output data in the FPGA program are inconsistent. Since the internal clock of AD9164 is a sampling clock that is divided by 4, the phase of the internal clock of two independent AD9164s after the sampling clock is divided is uncertain, so that the output data delays of AD9164 are inconsistent.

[0005] At present, the method for synchronously calibrating the AD9164 double channels mainly uses the DDS data generated by the FPGA to directly output to two AD9164s, uses a high sampling rate oscilloscope to test the waveforms of the interfaces of the output circuits corresponding to the two AD9164s, manually judges the delay difference of the output waveforms of the two AD9164s, and reads the SYSREF_PHASE phase values of AD9164 registers 0x037 and 0x038 through the SPI configuration logic of the FPGA controlled by the Virtual Input / Output (VIO) of Vivado. The phase values read are captured through the Integrated Logic Analyzer (ILA) of Vivado, and the delay difference corresponding to all the phase values is tested through multiple power-on and power-off tests. Then, the delay difference is compensated into the FPGA output signal logic link (equivalent to changing the program, which must be recompiled). During the multiple power-on and power-off tests, the manual calibration process is tedious and difficult, which is not conducive to the operation of production personnel in batch production and affects the production efficiency. Therefore, how to realize the automatic calibration of the AD9164 double-channel synchronous output is a problem to be solved. SUMMARY

[0006] The present application aims to provide a FPGA-based DAC dual-channel synchronous output automatic calibration method and system, which can automatically complete the DAC dual-channel synchronous output calibration, and does not need to compile FPGA program when producing dual-channel board, thereby improving production efficiency and facilitating mass production and practical application promotion.

[0007] To achieve the above-mentioned purpose, the following scheme is adopted:

[0008] In one aspect, the present application provides a FPGA-based DAC dual-channel synchronous output automatic calibration method, which specifically comprises the following steps:

[0009] S1, output single pulse SYSREF clock to two DAC chips respectively, and read link delay value from the register of the DAC chip respectively, and calculate clock delay calibration value of the two DAC chips according to the link delay value;

[0010] S2, configure the register of the two DAC chips according to the clock delay calibration value, output single pulse SYSREF clock to the DAC chip respectively, and read SYSREF phase measurement value from the register of the DAC chip;

[0011] S3, calculate the phase difference value between the SYSREF phase measurement values of the two DAC chips, and calculate data dynamic delay compensation value of the two DAC chips according to the phase difference value;

[0012] S4, output the DDS waveform data after delay by the corresponding data dynamic delay compensation value to the two DAC chips respectively, and collect two-channel test data after processing the DDS waveform data by the two DAC chips;

[0013] S5, calculate the fixed delay compensation value corresponding to the two DAC chips according to the waveform phase difference time of the two-channel test data;

[0014] S6, calculate data delay compensation value according to the data dynamic delay compensation value and the fixed delay compensation value, and delay the data to be sent to the two DAC chips by using the data delay compensation value.

[0015] In some specific embodiments, the specific process of calculating the clock delay calibration value in step S1 is as follows:

[0016] S11, power off the two AD9164 chips, then power on and initialize the register configuration;

[0017] S12, output single pulse SYSREF clock to the two DAC chips, and read link delay value from the register of the DAC chip respectively;

[0018] S13, repeating steps S11-S12 several times to obtain several link delay values read from each DAC chip;

[0019] S14, correcting the several link delay values of each DAC chip, and calculating a clock delay calibration value of the DAC chip according to the corrected link delay values.

[0020] In some embodiments, the specific process of step S14 is as follows:

[0021] S141, arranging the received several link delay values in order of reception, and determining whether there is a link delay value crossing the multi-frame edge in the arranged several link delay values;

[0022] S142, if there is a link delay value crossing the multi-frame edge, correcting the link delay value crossing the multi-frame edge to obtain corrected several link delay values;

[0023] S143, finding the maximum link delay value and the minimum link delay value from the corrected several link delay values;

[0024] S144, calculating a clock delay calibration value according to the maximum link delay value and the minimum link delay value.

[0025] In some embodiments, the specific process of determining whether the link delay value crosses the multi-frame edge in step S141 is as follows:

[0026] sequentially comparing whether the several link delay values are arranged in ascending order, if a change from large to small occurs, the two link delay values changed from large to small are taken as the link delay values corresponding to the frame edge;

[0027] When the previous link delay value in the two link delay values of the frame edge is the number of multi-frame periods of the DAC chip currently calculated minus 1 and the next link delay value is 0, it is determined that the link delay value crosses the multi-frame edge.

[0028] In some embodiments, the process of obtaining the corrected several link delay values is as follows:

[0029] correcting the subsequent link delay values starting from the next link delay value;

[0030] correcting the next link delay value to the number of multi-frame periods, and sequentially adding 1 to the number of multi-frame periods for the correction of the subsequent link delay values.

[0031] In some embodiments, the clock delay calibration value includes an LMF CVar calibration value and an LMF CDel calibration value, wherein the calculation method of the LMF CVar calibration value is:

[0032] LMFCVar = (MaxDelay + 1) - (MinDelay - 1) ;

[0033] The calculation method of LMFCDel calibration value is:

[0034] LMFCDel = (MinDelay - 1) % 8;

[0035] Wherein, MaxDelay represents the maximum link delay value, and MinDelay represents the minimum link delay value.

[0036] In some embodiments, the specific process of calculating the data dynamic delay compensation value in step S3 is:

[0037] If the difference value is the SYSREF phase measurement value of the first DAC chip minus the SYSREF phase measurement value of the second DAC chip;

[0038] If the difference value is less than 0, the data dynamic delay compensation value of the first DAC chip is equal to the absolute value of the difference value, and the data dynamic delay compensation value of the second DAC chip is equal to 0;

[0039] If not, the data dynamic delay compensation value of the first DAC chip is equal to 0, and the data dynamic delay compensation value of the second DAC chip is equal to the difference value.

[0040] In some embodiments, the specific process of calculating the fixed delay compensation value in step S5 is:

[0041] If the waveform difference time is the channel test data waveform corresponding to the first DAC chip minus the channel test data waveform corresponding to the second DAC chip;

[0042] If the waveform difference time is less than 0, the data fixed delay compensation value of the first DAC chip is equal to the absolute value of the waveform difference time*5, and the data fixed delay compensation value of the second DAC chip is equal to 0;

[0043] If not, the data fixed delay compensation value of the first DAC chip is equal to 0, and the data fixed delay compensation value of the second DAC chip is equal to x*5.

[0044] In some embodiments, the specific process of step S11 is:

[0045] Power off the two DAC chips respectively, and enable reset of the interface data sending modules corresponding to the two DAC chips at the same time;

[0046] After waiting for a preset time, power on the two DAC chips respectively, initialize and set the values corresponding to the register addresses in the two DAC chips, and configure the two DAC chips in order according to the register sequence;

[0047] After the configuration is completed, the interface data sending modules corresponding to the two DAC chips are simultaneously released from the reset.

[0048] In a second aspect, the application provides a FPGA-based DAC dual-channel synchronous output automatic calibration system, comprising a FPGA, an upper computer, and two DAC chips, wherein the upper computer comprises an LMFC deterministic delay calibration module and an inter-channel fixed delay calibration module which are respectively communicatively connected with the FPGA through a PCIE bus, and the FPGA module comprises a calibration module and a data delay module;

[0049] The calibration module is configured to output a single-pulse SYSREF clock to the two DAC chips respectively, and read link delay values from the registers of the DAC chips and upload the link delay values to the LMFC deterministic delay calibration module of the upper computer;

[0050] The calibration module is also configured to configure the registers of the two DAC chips according to the clock delay calibration values, output a single-pulse SYSREF clock to the DAC chips respectively, read SYSREF phase measurement values from the registers of the DAC chips, calculate a phase difference value between the SYSREF phase measurement values of the two DAC chips, and calculate data dynamic delay compensation values of the two DAC chips according to the phase difference value;

[0051] The LMFC deterministic delay calibration module is configured to calculate clock delay calibration values of the two DAC chips according to the link delay values and send the clock delay calibration values to the calibration module of the FPGA;

[0052] The data delay module is configured to output DDS waveform data to the two DAC chips after the DDS waveform data is delayed by corresponding data dynamic delay compensation values;

[0053] The data delay module is also configured to calculate a data delay compensation value according to the data dynamic delay compensation value and the fixed delay compensation value, and perform delay processing on data to be sent to the two DAC chips by using the data delay compensation value;

[0054] The inter-channel fixed delay calibration module is configured to collect two-channel test data of the DDS waveform data processed by the two DAC chips from an oscilloscope according to an instruction for collecting oscilloscope data sent by the calibration module, and calculate fixed delay compensation values corresponding to the two DAC chips according to a waveform phase difference time of the two-channel test data and send the fixed delay compensation values to the calibration module of the FPGA.

[0055] The application has the following beneficial effects:

[0056] The automatic calibration method and system provided by the application, by the cooperation of the upper computer and the FPGA, the automatic calibration method is adopted, so that the calibration process is simpler, the FPGA program complexity is reduced, the synchronous calibration process can be automatically completed, and human intervention is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0057] Figure 1 A flow chart of the FPGA-based DAC double-channel synchronous output automatic calibration method is provided for the embodiments of the application.

[0058] Figure 2 A block diagram of the FPGA-based DAC double-channel synchronous output automatic calibration system is provided for the embodiments of the application. DETAILED DESCRIPTION

[0059] The technical solutions in the embodiments of the application will be described clearly and completely below with reference to the drawings in the embodiments of the application. Obviously, the described embodiments are only part of the embodiments of the application, rather than all the embodiments. The description of the at least one exemplary embodiment is actually only illustrative, but not as any limitation on the application of the application or use. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative work are within the protection scope of the application.

[0060] Unless otherwise specified, the relative arrangement, numerical expressions and values of the components and steps set forth in the embodiments do not limit the scope of the application.

[0061] At the same time, it should be understood that, for the convenience of description, the sizes of the parts shown in the drawings are not drawn in accordance with the actual proportional relationship.

[0062] In addition, for the sake of clarity and brevity, the description of well-known structures, functions and configurations can be omitted. Those skilled in the art will recognize that various changes and modifications of the examples described herein can be made without departing from the spirit and scope of the disclosure.

[0063] The technology, methods and devices known to those skilled in the relevant art can not be discussed in detail, but should be considered as part of the authorized specification under appropriate circumstances.

[0064] In all examples shown and discussed herein, any specific values should be interpreted as merely exemplary, and not as a limitation. Thus, other examples of the exemplary embodiments can have different values.

[0065] Embodiment 1

[0066] As Figure 1 shown, the embodiment provides a FPGA-based DAC dual-channel synchronous output automatic calibration method, and the DAC chip in the embodiment is an AD9164 chip, and the method specifically comprises the following steps:

[0067] S1, output a single pulse SYSREF clock to two DAC chips respectively, read link delay values from the registers of the DAC chips respectively, and calculate clock delay calibration values of the two DAC chips according to the link delay values;

[0068] The specific process of calculating the clock delay calibration values in step S1 is as follows:

[0069] S11, power off the two AD9164 chips, then power on and initialize the registers;

[0070] The specific process of step S11 is as follows:

[0071] Power off the two DAC chips respectively, and simultaneously reset the interface data sending modules corresponding to the two DAC chips;

[0072] After waiting for a preset time (500 ms), power on the two DAC chips, initialize the values corresponding to the register addresses in the two DAC chips, and configure the two DAC chips according to the register order;

[0073] After the configuration is completed, simultaneously release the reset of the interface data sending modules corresponding to the two DAC chips.

[0074] S12, output a single pulse SYSREF clock to the two DAC chips, and read link delay values from the registers of the DAC chips respectively;

[0075] S13, repeat steps S11-S12 for several times to obtain several link delay values read from each DAC chip;

[0076] S14, correct the several link delay values of each DAC chip, and calculate the clock delay calibration value of the DAC chip according to the corrected link delay value.

[0077] The specific process of step S14 is as follows:

[0078] S141, arrange the received several link delay values in the receiving order in sequence, and determine whether there is a link delay value crossing the edge of multiple frames in the arranged several link delay values;

[0079] The specific process of determining whether the link delay value crosses the edge of multiple frames in step S141 is as follows:

[0080] sequentially compare the several link delay values in ascending order, if a change from large to small occurs, the two link delay values changed from large to small are taken as the link delay values corresponding to the frame edge;

[0081] when the previous link delay value in the two link delay values of the frame edge is the current calculated multi-frame period number-1 of the DAC chip and the latter link delay value is 0, it is judged that the link delay value has crossed the multi-frame edge.

[0082] the process of obtaining the corrected several link delay values is as follows:

[0083] the subsequent link delay values starting from the latter link delay value are corrected;

[0084] the latter link delay value is corrected to the multi-frame period number, and the subsequent link delay values are corrected by sequentially adding 1 on the basis of the multi-frame period number.

[0085] For example, assuming that the link delay values of the first AD9164 are 5, 6, 7, 0, 1, and the link delay values of the second AD9164 are 4, 5, 6; since the multi-frame period number of AD9164 is 8, the link delay values of 0 and 1 have crossed the edge of the multi-frame, so the link delay values of the first AD9164 are 5, 6, 7, 8, 9; the link delay values of the second AD9164, 4, 5, 6, have not crossed the edge of the multi-frame, so the link delay values of the second AD9164 are 4, 5, 6.

[0086] S142, if there is a link delay value crossing the multi-frame edge, the link delay value crossing the multi-frame edge is corrected to obtain the corrected several link delay values;

[0087] S143, find the maximum link delay value and the minimum link delay value from the corrected several link delay values;

[0088] S144, calculate the clock delay calibration value according to the maximum link delay value and the minimum link delay value.

[0089] Specifically, the clock delay calibration value includes an LMFCVar calibration value and an LMFCDel calibration value, the LMFCVar (Leading Edge Margin for Clock Variation) representing a tolerance delay of a leading edge of a clock signal, used to compensate for the influence of clock jitter or frequency fluctuation on sampling timing; this parameter ensures that the DAC can maintain stable sampling synchronization when there is a slight change in the clock signal. The LMFCDel (Leading Edge Margin for Clock Delay) refers to a fixed delay of the leading edge of the clock signal, used to adjust the phase relationship between the sampling clock and the input signal, to avoid sampling deviation caused by clock transmission delay; such delay is usually implemented through hardware circuit or register configuration.

[0090] The calculation method of the LMFCVar calibration value is:

[0091] LMFCVar = (MaxDelay + 1) - (MinDelay - 1);

[0092] The calculation method of the LMFCDel calibration value is:

[0093] LMFCDel = (MinDelay - 1) % 8;

[0094] Wherein, MaxDelay represents the maximum link delay value, and MinDelay represents the minimum link delay value.

[0095] S2, configure the registers of the two DAC chips according to the clock delay calibration value, respectively output a single-pulse SYSREF clock to the DAC chips, and read the SYSREF phase measurement value from the registers of the DAC chips;

[0096] S3, calculate the phase difference value between the SYSREF phase measurement values of the two DAC chips, and calculate the data dynamic delay compensation value of the two DAC chips according to the phase difference value;

[0097] The specific process of calculating the data dynamic delay compensation value in step S3 is:

[0098] If the phase difference value is the SYSREF phase measurement value of the first DAC chip minus the SYSREF phase measurement value of the second DAC chip;

[0099] Determine whether the phase difference value is less than 0, if yes, the data dynamic delay compensation value of the first DAC chip is equal to the absolute value of the phase difference value, and the data dynamic delay compensation value of the second DAC chip is equal to 0;

[0100] If not, the dynamic delay compensation value of the first DAC chip is equal to 0, and the dynamic delay compensation value of the second DAC chip is equal to the difference value.

[0101] Since register address 0x037 of both AD9164 chips is used to store the measured value of the SYSREF phase, and register address 0x038 is always 0x0F, the value of register address 0x038 is not read. Therefore, when reading the phase measurement value, the difference between the measured values ​​at register address 0x037 of the two AD9164 chips is calculated. Generally, the measured value at register address 0x037 has four phase values: 0x00, 0x80, 0xC0, and 0xE0. Phase value 0x00 is defined as 0, phase value 0x80 as 1, phase value 0xC0 as 2, and phase value 0xE0 as 3.

[0102] If the phase value of the first AD9164 is defined as PHA1, then when the first AD9164 reads a value of 0x00, PHA1=0; when the read value is 0x80, PHA1=1; when the read value is 0xC0, PHA1=2; and when the read value is 0xE0, PHA1=3.

[0103] Define the phase value of the second AD9164 as PHA2. When the second AD9164 reads a value of 0x00, PHA2=0; when the read value is 0x80, PHA2=1; when the read value is 0xC0, PHA2=2; and when the read value is 0xE0, PHA2=3. Then the phase difference DIFF_PHA = PHA1 - PHA2.

[0104] S4. Output the DDS waveform data after being delayed by the corresponding data dynamic delay compensation value to the two DAC chips respectively, and collect the two-channel test data after the two DAC chips process the DDS waveform data.

[0105] S5. Calculate the fixed delay compensation value for the two DAC chips based on the phase difference time of the waveforms in the two channel test data.

[0106] The specific process for calculating the fixed delay compensation value in step S5 is as follows:

[0107] If the waveform phase difference time is calculated by subtracting the test data waveform of the channel corresponding to the second DAC chip from the test data waveform of the channel corresponding to the first DAC chip;

[0108] Determine if the waveform phase difference time is less than 0. If so, the data fixed delay compensation value of the first DAC chip is equal to the absolute value of the waveform phase difference time * 5, and the data fixed delay compensation value of the second DAC chip is equal to 0.

[0109] If not, the data fixed delay compensation value of the first DAC chip is equal to 0, and the data fixed delay compensation value of the second DAC chip is equal to x*5.

[0110] S6, calculating the data delay compensation value according to the data dynamic delay compensation value and the fixed delay compensation value, and performing delay processing on the data to be sent to the two DAC chips by using the data delay compensation value.

[0111] Embodiment 2

[0112] As shown in the figure, the embodiment provides a FPGA-based DAC dual-channel synchronous output automatic calibration system, which comprises a board card containing FPGA, two DAC chips, a host computer (PC), and a high sampling rate oscilloscope, the board card is inserted into the PCIE slot of the PC, the output interface of the board card is connected to the high sampling rate oscilloscope, and the LAN interface of the high sampling rate oscilloscope is connected to the LAN interface of the PC. Figure 2 The board card further comprises an AD9164 power supply chip for providing power supply for the AD9164 chip, a clock chip for providing a clock signal, and an EEPROM chip.

[0113] The host computer comprises an LMFC deterministic delay calibration module and an inter-channel fixed delay calibration module.

[0114] The FPGA comprises an XDMA module, an instruction analysis and data return module, a calibration parameter control module, a calibration module, an initialization configuration module, a data selection module, a data delay module, an AD9164 power supply control module for controlling the AD9164 power supply chip, an SPI module 1, an SPI module 2, a JESD204B sending module 1, and a JESD204B sending module 2.

[0115] The LMFC deterministic delay calibration module and the inter-channel fixed delay calibration module are in communication connection with the XDMA module through the PCIE bus, and the inter-channel fixed delay calibration module is in communication connection with the high sampling rate oscilloscope.

[0116] The XDMA module, the instruction analysis and data return module, the calibration module, and the calibration parameter control module are connected in series, and the calibration parameter control module is connected with the EEPROM chip and the initialization configuration module.

[0117] The XDMA module, the instruction analysis and data return module, the calibration module, and the calibration parameter control module are connected in series, and the calibration parameter control module is connected with the EEPROM chip and the initialization configuration module.

[0118] The calibration module is connected with the data selection module, the data delay module, the AD9164 power supply control module, the SPI module 1 and the SPI module 2 respectively; wherein the data selection module is controlled by the calibration module to select to output the DDS waveform data or the application data; the data selection module is connected with the data delay module, the data delay module is connected with the JESD204B sending module 1 and the JESD204B sending module 2 respectively,

[0119] The initialization configuration module is connected with the SPI module 1, the SPI module 2 and the clock chip, the SPI module 1 is connected with the first DAC chip AD9164-1, and the SPI module 2 is connected with the second DAC chip AD9164-2. The JESD204B sending module 1 is connected with the AD9164-1, and the JESD204B sending module 2 is connected with the AD9164-2.

[0120] Based on the system of Figure 2 , the FPGA-based AD9164 double-channel synchronous output automatic calibration process is as follows:

[0121] 1. Device power-on initialization:

[0122] S001, the device is powered on, the calibration parameter control module of the FPGA reads the calibration parameters in the EEPROM chip, and the initialization configuration module in the FPGA initializes the AD9164 by the SPI module 1 and the SPI module 2 according to the register order of Table 42 and Table 43 in the AD9164 data manual, and the LMFCVar and LMFCDel calibration values (initial value is 0);

[0123] S002, the FPGA internal initialization configuration module releases the reset of the JESD204B sending module 1 and the JESD204B sending module 2 at the same time;

[0124] S003, the FPGA internal initialization configuration module controls the clock chip to output a single pulse SYSREF clock to the AD9164 and the JESD204B module in the FPGA;

[0125] 2. FPGA and host computer cooperate to determine the delay calibration

[0126] S004, the host computer LMFC deterministic delay calibration module sends a calibration instruction to the FPGA through PCIe, and the XDMA module of the FPGA sends the received instruction to the instruction analysis and data return module;

[0127] S005, the instruction analysis and data return module of the FPGA analyzes the LMFC deterministic delay calibration instruction and sends it to the calibration module;

[0128] The calibration module performs the following operations:

[0129] S006, the calibration module of the FPGA controls the AD9164 power supply control module to power off the AD9164 chip;

[0130] S007, the calibration module of the FPGA enables the reset of the JESD204B sending module 1 and the JESD204B sending module 2 at the same time;

[0131] S008, after waiting for 500 ms, the calibration module of the FPGA controls the AD9164 power supply control module to power on the AD9164 chip;

[0132] S009, the register address 0x03A value of the two AD9164 chips is set to 0x02, the register address 0x304 (LMFC delay) value is set to 0x00, the register address (LMFC variable) 0x306 value is set to 0x00, and the AD9164 is configured according to the register sequence of Table 42 and Table 43 in the AD9164 data manual through the SPI module 1 and the SPI module 2;

[0133] S010, the calibration module of the FPGA releases the reset of the JESD204B sending module 1 and the JESD204B sending module 2 at the same time;

[0134] S011, the calibration module of the FPGA controls the clock chip to output a single pulse SYSREF clock to the AD9164 and the JESD204B module in the FPGA;

[0135] S012, the calibration module of the FPGA reads the register address 0x302 value of the two AD9164 chips, that is, the link delay value, through the SPI module 1 and the SPI module 2. The calibration module of the FPGA records the link delay values of the two AD9164 chips and uploads them to the LMFC deterministic delay calibration module of the host computer through the instruction analysis and data return module and the XDMA module;

[0136] S013. Repeat steps S006~S012 20 times. After the host computer's LMFC deterministic delay calibration module receives 20 link delay values, the host computer counts the link delay values ​​of the two AD9164 chips respectively. Assume the link delay values ​​of the first AD9164 chip are 5, 6, 7, 0, 1, and the link delay values ​​of the second AD9164 chip are 4, 5, 6. Analyzing the link delay values ​​of the first AD9164 chip, since the multi-frame period of the AD9164 is 8, the change in link delay values ​​from 7 to 0, 1 indicates that it has crossed the edge of the multi-frame period. Therefore, the link delay values ​​of the first AD9164 chip are 5, 6, 7, 8, 9. Analyzing the link delay values ​​of the second AD9164 chip, the link delay values ​​of the second AD9164 chip are 4, 5, 6, which have not crossed the edge of the multi-frame period. Therefore, the link delay values ​​of the second AD9164 chip are 4, 5, 6.

[0137] Calculate the maximum and minimum values ​​of all link delays for the two AD9164 chips. The maximum value is MaxDelay=9 and the minimum value is MinDelay=4.

[0138] The calibration values ​​of LMFCVar and LMFCDel are then calculated using the following formula:

[0139] LMFCVar=(MaxDelay+1)-(MinDelay-1), calculate LMFCVar=(9+1)-(4-1)=7;

[0140] LMFCDel=(MinDelay-1)%8 calculates LMFCDel=(4-1)%8=3%8=3;

[0141] The LMFC deterministic delay calibration module sends the calculated LMFCVar and LMFCDel calibration values ​​to the FPGA calibration module via PCIe, the FPGA's XDMA module, and the instruction parsing and data return module.

[0142] The FPGA calibration module stores the LMFCVar and LMFCDel calibration values ​​into the EEPROM chip through the calibration parameter control module;

[0143] S014, The FPGA calibration module stores the LMFCVar and LMFCDel calibration values ​​into the EEPROM chip through the calibration parameter control module;

[0144] 3. FPGA and host computer work together to perform fixed delay calibration between channels.

[0145] S015. The fixed delay calibration module between channels of the host computer sends calibration instructions to the FPGA via PCIe. The XDMA module of the FPGA sends the received instructions to the instruction parsing and data return module.

[0146] S016, the instruction analysis and data return module of the FPGA analyzes the inter-channel fixed delay block calibration instruction and sends it to the calibration module;

[0147] S017, the calibration module of the FPGA controls the AD9164 power control module to power down the AD9164 chip;

[0148] S018, the calibration module of the FPGA enables the reset of the JESD204B sending module 1 and the JESD204B sending module 2 at the same time;

[0149] S019, after waiting for 500 ms, the calibration module of the FPGA controls the AD9164 power control module to power up the AD9164 chip;

[0150] S020, the calibration module sets the register address 0x304 (LMFC delay) value of the two AD9164 chips to the LMFCDel calibration value, and the register address (LMFC variable) 0x306 value to the LMFCVar calibration value, and configures the AD9164 according to the register sequence in Table 42 and Table 43 in the AD9164 data manual through the SPI module 1 and the SPI module 2;

[0151] S021, the calibration module of the FPGA releases the reset of the JESD204B sending module 1 and the JESD204B sending module 2 at the same time;

[0152] Specific correction process:

[0153] S022, the calibration module of the FPGA controls the clock chip to output a single pulse SYSREF clock to the AD9164 and the internal JESD204B module of the FPGA;

[0154] S023, the calibration module sets the register address 0x034 value of the two AD9164 chips to 0x00 through the SPI module 1 and the SPI module 2 to configure the AD9164;

[0155] S024, the calibration module of the FPGA reads the value of the register address 0x037 of the two AD9164 chips through the SPI module 1 and the SPI module 2, which is the measured value of the SYSREF phase. Since the value of the register address 0x038 is always 0x0F, the value of the register address 0x038 is not read;

[0156] S025, the calibration module of the FPGA calculates the difference between the measured values of the register address 0x037 of the two AD9164s. The measured values of the register address 0x037 have four phase values, i.e. 0x00, 0x80, 0xC0 and 0xE0. The phase value 0x00 is defined as 0, the phase value 0x80 is defined as 1, the phase value 0xC0 is defined as 2, and the phase value 0xE0 is defined as 3.

[0157] The phase value of the first AD9164 is defined as PHA1, and when the reading value of the first AD9164 is 0x00, PHA1 = 0, when the reading value is 0x80, PHA1 = 1, when the reading value is 0xC0, PHA1 = 2, and when the reading value is 0xE0, PHA1 = 3. The phase value of the second AD9164 is defined as PHA2, and when the reading value of the second AD9164 is 0x00, PHA2 = 0, when the reading value is 0x80, PHA2 = 1, when the reading value is 0xC0, PHA2 = 2, and when the reading value is 0xE0, PHA2 = 3. The difference value DIFF_PHA = PHA1 - PHA2;

[0158] The data dynamic delay compensation value A1 of the first AD9164 and the data dynamic delay compensation value A2 of the second AD9164 are calculated. When DIFF_PHA is less than 0, A1 is equal to the absolute value of DIFF_PHA, and A2 is equal to 0, otherwise A1 is equal to 0, and A2 is equal to DIFF_PHA;

[0159] S026, the data delay compensation value D1 of the first AD9164 of the FPGA data delay module = data dynamic delay compensation value A1 + data fixed delay compensation value B1, and the data delay compensation value D2 of the second AD9164 = data dynamic delay compensation value A2 + data fixed delay compensation value B2. B1 and B2 mainly compensate for the delay caused by the difference between the hardware wiring and the output circuit. B1 and B2 are set to 0, and the data delay module sends the data of the two AD9164s to the JESD20B module after compensating for the delay according to D1 and D2 respectively;

[0160] S027, the calibration module controls the data selection module to output the DDS waveform data, and the calibration module sends a command to the upper computer through the channel fixed delay calibration module to request the upper computer to collect oscilloscope data;

[0161] S028、Host channel fixed delay calibration module receives 2-channel data collected by high sampling rate oscilloscope through LAN interface; taking AD9164 data rate 5Gbps as an example, the host channel fixed delay calibration module analyzes and calculates the waveform difference time of 2-channel data. Assuming that the waveform difference time of channel 1 and channel 2 is xns, when x is less than 0, the data fixed delay compensation value B1 is equal to the absolute value of x*5, the data fixed delay compensation value B2 is equal to 0, otherwise the data fixed delay compensation value B1 is equal to 0, and the data fixed delay compensation value B2 is equal to x*5; the calculated B1 and B2 calibration values are sent to the calibration module of the FPGA through the PCIe, the XDMA module of the FPGA, the instruction analysis and data return module, and the calibration parameter control module of the FPGA;

[0162] S029、The calibration module of the FPGA stores the B1 and B2 calibration values in the EEPROM chip through the calibration parameter control module;

[0163] 4、Synchronization calibration is completed, and data transmission is performed

[0164] S030、After the above synchronization calibration process is completed, when the board card is used formally after calibration, the device is powered on, the calibration parameter control module of the FPGA reads the LMFCVar, LMFCDel, B1 and B2 calibration values in the EEPROM chip, and the internal initialization configuration module of the FPGA initializes the AD9164 through the SPI module 1 and the SPI module 2 according to the register sequence of Table 42 and Table 43 in the AD9164 data manual;

[0165] S031、The internal initialization configuration module of the FPGA releases the reset of the JESD204B sending module 1 and the JESD204B sending module 2 at the same time;

[0166] S032、The internal initialization configuration module of the FPGA controls the clock chip to output a single pulse SYSREF clock to the AD9164 and the internal JESD204B module of the FPGA;

[0167] S033、Repeat S022~S025;

[0168] S034、The first AD9164 data delay compensation value D1 of the FPGA data delay module is A1+B1, and the second AD9164 data delay compensation value D2 is A2+B2. According to B1, B2, A1 and A2 in S030 and S033, D1 and D2 are calculated, and the data delay module sends the data delay of the two AD9164s to the JESD20B module respectively according to the delay compensation values D1 and D2.

[0169] It can be understood that the double-channel synchronous output automatic calibration system of the embodiment can automatically complete AD9164 double-channel synchronous output calibration, does not need to compile FPGA program when producing AD9164 board card, improves production efficiency, and is beneficial to mass production and practical application promotion.

[0170] The above is only a preferred embodiment of the present application, and does not limit the present application in any form. According to the technical essence of the present application, any simple modification, equivalent replacement and improvement of the above embodiment within the spirit and principles of the present application are still within the protection scope of the technical scheme of the present application.

Claims

1. A FPGA-based DAC dual-channel synchronous output automatic calibration method, characterized in that, Specifically comprising the following steps: S1, output single pulse SYSREF clock to two DAC chips respectively, and read link delay values from the registers of the DAC chips respectively, and calculate clock delay calibration values of the two DAC chips according to the link delay values; S2, configure the registers of the two DAC chips according to the clock delay calibration values, output single pulse SYSREF clock to the DAC chips respectively, and read SYSREF phase measurement values from the registers of the DAC chips; S3, calculate the phase difference value between the SYSREF phase measurement values of the two DAC chips, and calculate data dynamic delay compensation values of the two DAC chips according to the phase difference value; The specific process of calculating the data dynamic delay compensation value in step S3 is as follows: If the phase difference value is the SYSREF phase measurement value of the first DAC chip minus the SYSREF phase measurement value of the second DAC chip; If the phase difference value is less than 0, the data dynamic delay compensation value of the first DAC chip is equal to the absolute value of the phase difference value, and the data dynamic delay compensation value of the second DAC chip is equal to 0; If not, the data dynamic delay compensation value of the first DAC chip is equal to 0, and the data dynamic delay compensation value of the second DAC chip is equal to the phase difference value; S4, output the DDS waveform data delayed by the corresponding data dynamic delay compensation value to the two DAC chips respectively, and collect two-channel test data processed by the two DAC chips on the DDS waveform data; S5, calculate the fixed delay compensation values corresponding to the two DAC chips according to the waveform phase difference time of the two-channel test data; The specific process of calculating the fixed delay compensation value in step S5 is as follows: If the waveform phase difference time is the waveform of the channel test data corresponding to the first DAC chip minus the waveform of the channel test data corresponding to the second DAC chip; If the waveform phase difference time is less than 0, the data fixed delay compensation value of the first DAC chip is equal to the absolute value of the waveform phase difference time*5, and the data fixed delay compensation value of the second DAC chip is equal to 0; If not, the data fixed delay compensation value of the first DAC chip is equal to 0, and the data fixed delay compensation value of the second DAC chip is equal to x*5, x represents the waveform phase difference time; S6, calculate the data delay compensation value according to the data dynamic delay compensation value and the fixed delay compensation value, data delay compensation value = data dynamic delay compensation value + fixed delay compensation value, and perform delay processing on the data to be sent to the two DAC chips by using the data delay compensation value.

2. The FPGA-based DAC dual-channel synchronous output automatic calibration method according to claim 1, characterized in that, The specific process of calculating the clock delay calibration value in step S1 is as follows: S11, power off and then power on the two AD9164 chips and initialize the registers; S12, output single pulse SYSREF clock to two DAC chips, and read link delay values from the registers of the DAC chips respectively; S13, repeat steps S11-S12 several times to obtain several link delay values read from each DAC chip; S14, correct the link delay values of each DAC chip, and calculate the clock delay calibration value of the DAC chip according to the corrected link delay values.

3. The FPGA-based DAC dual-channel synchronous output automatic calibration method according to claim 2, characterized in that, The specific process of step S14 is: S141, arrange the received link delay values in order according to the receiving order, and judge whether there is a link delay value that crosses the multi-frame edge in the arranged link delay values; S142, if there is a link delay value that crosses the multi-frame edge, correct the link delay value that crosses the multi-frame edge to obtain the corrected link delay values; S143, find the maximum link delay value and the minimum link delay value in the corrected link delay values; S144, calculate the clock delay calibration value according to the maximum link delay value and the minimum link delay value.

4. The FPGA-based DAC dual-channel synchronous output automatic calibration method according to claim 3, characterized in that, The specific process of judging whether the link delay value crosses the multi-frame edge in step S141 is: Compare the link delay values in order to see if they are arranged from small to large, if there is a change from large to small, the two link delay values that change from large to small are taken as the link delay values corresponding to the frame edge; When the two link delay values of the frame edge are the multi-frame period number-1 of the DAC chip currently calculated and 0 respectively, it is judged that the link delay value crosses the multi-frame edge.

5. The FPGA-based DAC dual-channel synchronous output automatic calibration method according to claim 4, characterized in that, The process of obtaining the corrected link delay values is: Correct the subsequent link delay values starting from the latter link delay value; The latter link delay value is corrected to the multi-frame period number, and the subsequent link delay values are corrected by adding 1 in order on the basis of the multi-frame period number.

6. The FPGA-based DAC dual-channel synchronous output automatic calibration method according to claim 3, characterized in that, The clock delay calibration value includes LMFCVar calibration value and LMFCDel calibration value, wherein the calculation method of LMFCVar calibration value is: LMFCVar=(MaxDelay+1)-(MinDelay-1); The calculation method of LMFCDel calibration value is: LMFCDel=(MinDelay-1)%8; Wherein, MaxDelay represents the maximum link delay value, and MinDelay represents the minimum link delay value.

7. The FPGA-based DAC dual-channel synchronous output automatic calibration method according to claim 2, characterized in that, The specific process of step S11 is: Power off the two DAC chips respectively, and enable reset of the interface data sending modules corresponding to the two DAC chips at the same time; After waiting for a preset time, power on the two DAC chips respectively, initialize and set the values corresponding to the register addresses in the two DAC chips, and configure the two DAC chips in order according to the register order; After the configuration is completed, release the reset of the interface data sending modules corresponding to the two DAC chips at the same time.

8. A FPGA-based automatic calibration system for dual-channel synchronous output of DAC, applying the FPGA-based automatic calibration method for dual-channel synchronous output of DAC according to claim 1, characterized in that, It includes FPGA, host computer, two DAC chips, wherein the host computer includes LMFC deterministic delay calibration module and inter-channel fixed delay calibration module which are respectively connected with FPGA through PCIE bus, and FPGA module includes calibration module and data delay module; The calibration module is used to output single pulse SYSREF clock to the two DAC chips respectively, and read the link delay values from the registers of the DAC chips and upload them to the LMFC deterministic delay calibration module of the host computer. Also used to configure the registers of the two DAC chips respectively according to the clock delay calibration values, output single pulse SYSREF clock to the DAC chips respectively, read the SYSREF phase measurement values from the registers of the DAC chips, calculate the phase difference value between the SYSREF phase measurement values of the two DAC chips, and calculate the data dynamic delay compensation values of the two DAC chips respectively according to the phase difference value; The LMFC deterministic delay calibration module is used to calculate the clock delay calibration values of the two DAC chips respectively according to the link delay values and send them to the calibration module of the FPGA; The data delay module is used to output the DDS waveform data to the two DAC chips respectively after delaying by the corresponding data dynamic delay compensation values; Also used to calculate the data delay compensation value according to the data dynamic delay compensation value and the fixed delay compensation value, and to perform delay processing on the data to be sent to the two DAC chips by using the data delay compensation value; The inter-channel fixed delay calibration module is used to collect the two-channel test data of the DDS waveform data processed by the two DAC chips from the oscilloscope according to the instruction of the host computer collecting the oscilloscope data sent by the calibration module, and to calculate the fixed delay compensation values corresponding to the two DAC chips according to the waveform phase difference time of the two-channel test data and send them to the calibration module of the FPGA.

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