IP address lookup method and apparatus

Abstract

An IP address lookup method applied to IPv6, the method comprising: constructing a lookup data structure tree based on a multi-bit Trie tree, wherein each internal Trie node with a real node corresponds to one or more IP prefixes in an IP forwarding table; determining a mappable pipeline stage range of each node according to a reverse distance of each node in the lookup data structure tree, a pipeline stage where a child node is located, a path length from the node to a root node, and a position of a pipeline stage where a parent node is located; wherein the reverse distance is defined as a maximum distance between the node and all successor leaf nodes thereof; dynamically mapping each node to an independent storage resource of a corresponding pipeline stage according to the mappable pipeline stage range and a storage space condition of each pipeline stage; and performing IP address lookup in parallel in each pipeline stage according to the node mapping result to realize pipeline parallel lookup. The method can improve lookup efficiency.

Description

Technical Field

[0001] This invention relates to the field of routing lookup technology, and in particular to an IP address lookup method and apparatus. Background Technology

[0002] Route lookup is a core function of routing and forwarding network devices (routers, Layer 3 switches, etc.). Its main task is to look up the corresponding next-hop information in the Forwarding Information Base (FIB) based on the destination IP address of a data packet, and then forward the data packet according to this information. Route lookup is also one of the most resource-intensive functions in network devices, mainly due to the current reliance on the complex Longest Prefix Matching (LPM) principle. In network environments with extremely stringent requirements for forwarding performance and latency, such as carrier networks and financial service networks, hardware-based route lookup methods are typically used. However, with the accelerated deployment of IPv6, traditional algorithm-based hardware route lookup methods face severe challenges in terms of storage efficiency and storage resource utilization due to the longer address length and larger address space of IPv6 addresses. Therefore, how to efficiently perform IP address lookup under IPv6 has become an urgent technical problem to be solved. Summary of the Invention

[0003] To address the problems existing in the prior art, embodiments of this application provide a method, apparatus, computing device, computer storage medium, and product containing a computer program for IP address lookup, which can improve storage efficiency and resource utilization, thereby enhancing the efficiency of IP address lookup.

[0004] In a first aspect, embodiments of this application provide an IP address lookup method applied to IPv6. The method includes: constructing a lookup data structure tree based on a multi-bit Trie tree, wherein each Trie node with real nodes corresponds to one or more IP prefixes in the IP forwarding table; determining the range of mappable pipelines for each node based on the inverse distance of each node in the lookup data structure tree, the pipeline level where the child node is located, the path length from the node to the root node, and the position of the pipeline level where the parent node is located; wherein the inverse distance is defined as the maximum distance between the node and all its successor leaf nodes; dynamically mapping each node to the independent storage resources of the corresponding pipeline level based on the range of mappable pipelines and the storage space status of each pipeline level; and performing IP address lookups in parallel according to the node mapping results in each pipeline level to achieve pipelined parallel lookups.

[0005] In some possible implementations, the dynamic mapping includes: calculating the lower bound L and upper bound U of the mappable pipeline range for each node, where the lower bound L = max(h1, h2 + 1) and the upper bound U = min(P - h3 - 1, h4 - 1), where h1 is the inverse distance of the node, h2 is the maximum number of pipelines containing all child nodes of the node, h3 is the path length from the node to the root node, h4 is the number of pipelines containing the parent node, and P is the total number of pipelines; starting from the lower bound L and increasing to the upper bound U, checking in turn whether the storage resources of each pipeline are sufficient to accommodate the node; and mapping the node to the first pipeline that meets the storage space conditions.

[0006] In some possible implementations, the method further includes: automatically calculating the storage resource allocation ratio for each pipeline stage based on the dynamic mapping results of the nodes.

[0007] In some possible implementations, the automatic calculation of the storage resource allocation ratio for each pipeline stage includes: initializing the storage resource allocation ratio for each pipeline stage; iteratively executing the following steps until convergence: calculating the actual storage resource usage ratio for each pipeline stage based on the current allocation ratio; identifying pipeline stages with excess storage resources; reducing the allocation weight of pipeline stages with excess storage resources and updating the allocation ratio; stopping the iteration when no pipeline stage has excess storage resources and determining the final storage resource allocation ratio.

[0008] In some possible implementations, the automatic calculation of the storage resource allocation ratio for each pipeline stage specifically involves: assuming the total number of pipeline stages is P, the current iteration round is T, and the number of pipeline stages S... i The allocation weight is w T (i), the allocation ratio is f T (i), and set the initial weights w0(i) to be equal; for a given M IPv6 FIBs corresponding to Trie_j (1≤j≤M), at the current allocation ratio f T (i) Using the dynamic mapping method, calculate the minimum total resource C required for each Trie_j to successfully map all multi-bit Trie nodes. T (j); According to C T (j) and f T (i) Calculate S for each flow stage i Actual storage usage c under the j-th Trie T (i,j), for each Trie_j, obtain the pipeline level S. i usage ratio By setting the fitting parameters α∈(0,1), f′ will be satisfied. T (i,j)<αf T (i), Flowing S iThe excess resources are assigned to the resource surplus set D1, and the rest are assigned to the effective utilization set D2; if D1 is empty, the iteration terminates, and the current f... T (i) represents the final allocation ratio; if D1 is a non-empty set, a variable iteration parameter λ∈(0,1) is set, and the pipeline S i The new weights are And update the new allocation ratio according to the new weights. At the same time, the value of the iteration parameter λ is reduced, and the iteration continues until D1 is empty.

[0009] In some possible implementations, the method further includes: classifying nodes with similar subtree structures in the search data structure tree; compressing and storing the classified similar subtrees using a unified next-hop bitmap; wherein the node itself only stores a pointer to the unified next-hop bitmap, so as to achieve efficient compression of node storage space.

[0010] In some possible implementations, the next-hop bitmap uses a bitmap method to mark the existence of real nodes in each layer inside the node. The next-hop information corresponding to all real nodes inside the node is stored in a contiguous manner. The node only stores a pointer to the first next-hop information. The next-hop information is indexed by calculating the offset of the real node in the next-hop bitmap.

[0011] In some possible implementations, the method further includes: introducing a best matching prefix (BMP) for each node, wherein the BMP records the next-hop address of the nearest real node on the path back from the current node to the root node; when there is no matching prefix within the node, the BMP is returned as the search result.

[0012] In some possible implementations, each pipeline level receives the pipeline level to which the node to be searched belongs, the corresponding storage address, and the remaining IP addresses to be searched from the previous pipeline level. If the pipeline level to which the node to be accessed belongs is the same as the current pipeline level, the node is obtained from the corresponding address and a query is performed. If the pipeline level to which the node to be accessed belongs is different from the current pipeline level, the relevant information is passed to the next pipeline level. The current pipeline level continues to receive the next query information, thus outputting a routing lookup result every clock cycle.

[0013] Secondly, embodiments of this application provide an IP address lookup device deployed on a router, the router employing IPv6. The device includes: a construction module, configured to construct a lookup data structure tree based on a multi-bit Trie tree, wherein each Trie node containing real nodes corresponds to one or more IP prefixes in an IP forwarding table; a processing module, configured to determine the range of mappable pipelines for each node based on the inverse distance of each node in the lookup data structure tree, the pipeline level where the child node is located, the path length from the node to the root node, and the position of the pipeline level where the parent node is located; wherein the inverse distance is defined as the maximum distance between the node and all its successor leaf nodes; the processing module is further configured to dynamically map each node to the independent storage resources of the corresponding pipeline level based on the range of mappable pipelines and the storage space status of each pipeline level; the processing module is further configured to perform IP address lookups in parallel in each pipeline level according to the node mapping results, thereby achieving pipelined parallel lookups.

[0014] Thirdly, embodiments of this application provide a computer-readable storage medium including computer-readable instructions that, when read and executed by a computer, cause the computer to perform the method as described in any of the first aspects.

[0015] Fourthly, embodiments of this application provide a computing device, including a processor and a memory, wherein the memory stores computer program instructions, which, when executed by the processor, perform the method as described in any of the first aspects.

[0016] Fifthly, embodiments of this application provide a product comprising a computer program that, when the computer program product is run on a processor, causes the processor to perform the method as described in any of the first aspects. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of a 3-bit address space FIB example provided in an embodiment of this application;

[0019] Figure 2 This is a schematic diagram of a multi-bit Trie tree provided in an embodiment of this application;

[0020] Figure 3 This is a schematic diagram of a multi-bit Trie and a lookup pipeline provided in an embodiment of this application;

[0021] Figure 4 This is a schematic diagram of a 10-bit address space FIB example provided in an embodiment of this application;

[0022] Figure 5 This is a schematic diagram of a pipelined storage resource allocation and node mapping technology based on tree features provided in an embodiment of this application;

[0023] Figure 6 This is a schematic diagram illustrating an example of a pipeline storage space allocation scheme provided in an embodiment of this application;

[0024] Figure 7 This is a schematic diagram of a data structure tree search provided in an embodiment of this application;

[0025] Figure 8 This is a schematic diagram of the distribution and encoding of real nodes within each node, provided in an embodiment of this application;

[0026] Figure 9 This is a complete data search structure tree provided in the embodiments of this application;

[0027] Figure 10 This is a schematic diagram of the structure of an IP address lookup device provided in an embodiment of this application. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] In this article, the term "and / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. The symbol " / " in this article indicates that the related objects are in an "or" relationship; for example, A / B means A or B.

[0030] The terms "first" and "second," etc., used in the specification and claims herein are used to distinguish different objects, not to describe a specific order of objects. For example, "first response message" and "second response message," etc., are used to distinguish different response messages, not to describe a specific order of response messages.

[0031] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0032] In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more, for example, multiple processing units means two or more processing units, multiple elements means two or more elements, etc.

[0033] To facilitate understanding of the embodiments of this application, the following will provide further explanation and description with reference to the accompanying drawings and specific embodiments. These embodiments do not constitute a limitation on the embodiments of the present invention.

[0034] For example, Figure 1 This is a schematic diagram of a 3-bit address space FIB example provided in an embodiment of this application. For example... Figure 1 As shown, in routing lookups, IP prefixes in the FIB are typically represented by strings of 0s and 1s ending with an asterisk (*) (the number of 0s and 1s indicates the length of the IP prefix), such as 101*, 1010*, etc. Given a destination IP address, the IP lookup engine of the routing forwarding device needs to find the longest IP prefix in the FIB that matches that address. For example, if an FIB contains three IP prefixes: P1 = 101*, P2 = 1010*, and P3 = 10101*, and the destination IP address to be searched is 10100000, this IP address matches both P1 and P2 in the FIB, but since P2 is longer, the longest prefix match is P2.

[0035] Currently, algorithm-based hardware routing lookup methods mainly employ pipelined parallel lookup techniques based on Trie. A Trie (also known as a Trie tree) is an efficient tree data structure suitable for storing and looking up key-value pairs (such as strings or IP prefixes). Its key-value pair is not directly stored in the node, but is determined by the node's position in the tree. Specifically, a key-value pair is represented by the path from the root node to a specific node. Therefore, all descendants of a node share the same prefix. In IP lookup, each IP prefix in the FIB corresponds to a real node in a single-bit Trie tree, defined by the path from the root node to that real node. Trie trees include single-bit Trie trees and multi-bit Trie trees. In a single-bit Trie tree, each level branches based on one bit of the IP prefix (0 for left child, 1 for right child) to form a binary tree. Each IP prefix in the FIB corresponds to a real node in a single-bit Trie tree, defined by the path from the root node to that real node. Each level of a multi-bit Trie tree branches based on K consecutive bits of the IP prefix. Therefore, a multi-bit Trie node corresponds to a subtree of height K in a single-bit Trie tree. Please refer to [reference needed]. Figure 2 and Figure 3 , Figure 2 The non-dashed part in the middle corresponds to the Figure 1 The example shown is a single-bit Trie tree constructed from the FIB sample. For example, the IP prefix C(11*) in the FIB corresponds to the single-bit Trie node N5. Figure 2 The diagram shows a K=2 multi-bit Trie tree, with the root node M0 of the multi-bit Trie corresponding to a subtree of height 2.

[0036] The storage efficiency of Trie-based routing lookup methods primarily depends on the encoding and compression efficiency of the Trie structure. The core principle of pipelined parallel lookup is to map Trie nodes to independent storage in different pipeline stages (such as SRAM, DRAM, and HBM-based RAM storage media). In this architecture, all pipeline stages can be processed in parallel each clock cycle, thus achieving a single-cycle output of a routing lookup result. Since the storage resources of each pipeline stage are independent, the storage resource utilization of Trie-based pipelined parallel lookup methods mainly depends on the allocation scheme of storage resources in each pipeline stage and the mapping strategy of Trie nodes in each pipeline stage. Please refer to [reference needed]. Figure 3 , Figure 3This diagram illustrates how Trie nodes are mapped to the storage spaces of different pipeline stages. The left side of the diagram shows an example of node mapping and pipelined lookup based on a single-bit Trie tree, while the right side shows an example of node mapping and pipelined lookup based on a K=2 multi-bit Trie tree. In a pipelined architecture, all pipeline stages process in parallel within each clock cycle; therefore, the storage resources of each pipeline stage are independent and need to be pre-allocated.

[0037] The overall storage efficiency of a pipelined lookup architecture primarily depends on the storage resource allocation scheme for each pipeline stage and the mapping strategy of Trie nodes within each pipeline stage. For example... Figure 3 As shown on the right, the multi-bit Trie is mapped to two pipeline stages. Multi-bit Trie node M0 is mapped to the first pipeline stage, while M1 and M2 are mapped to the second. Therefore, RAM1 requires at least one node's storage space, and RAM2 requires two nodes' storage space. During pipelined lookup, the first IP address query L1 (111) sequentially accesses nodes M0 and M2 in RAM1 and RAM2 over two clock cycles. When L1's query accesses node M2 ​​in RAM2 during the second clock cycle, the second IP address query L2 (001) simultaneously accesses node M0 in RAM1. Therefore, pipelined parallel lookup can output one routing lookup result per clock cycle.

[0038] However, current Trie-based pipelined IPv6 routing lookup methods face two key challenges. First, because the IPv6 prefix in the IPv6 FIB is typically longer than the IPv4 prefix, the storage overhead of the IPv6 prefix is ​​significantly increased, thus placing higher demands on the storage efficiency of IPv6 routing lookup methods. Second, because IPv6 has a larger address space, the distribution of IPv6 prefixes in the FIB varies significantly across different network scenarios. Existing methods based on uniform RAM resource allocation and fixed mapping, as well as uniform allocation and dynamic mapping, are difficult to adapt to diverse IPv6 prefix distributions, resulting in low storage resource utilization. In other words, improving the storage efficiency and storage resource utilization of Trie-based pipelined IP routing lookup methods has become a real problem.

[0039] In view of this, embodiments of this application provide an IP address lookup method based on a multi-bit Trie pipelined lookup architecture, achieving high storage resource utilization and high storage efficiency for IP route lookup. In a multi-bit Trie structure built from IPv6 FIB, leaf nodes typically constitute the majority, and the greater the distance relative to a leaf node, the fewer the number of nodes. Therefore, the mapping pipeline stage can be determined based on the inverse distance of a node; simultaneously, the storage resource allocation scheme of the pipeline stage is matched with the node mapping strategy. A detailed description follows.

[0040] Multi-bit Trie nodes need to encode two types of information: the index information of child nodes and the next-hop information corresponding to the IP prefix within the node (i.e., within the subtree). For the next-hop information corresponding to the IP prefix within the node, this invention employs a compression encoding method based on a next-hop bitmap (hereinafter referred to as "Next Hop Bitmap") and a pointer to the first next-hop information (hereinafter referred to as "Next Hop Pointer," NP). In the embodiments of this application, a bitmap of size 2 is used. K+1 A bitmap of -1 is used to mark the 2 bits in the subtree of height K. K+1 -1. The existence of next-hop information for internal nodes. Specifically, each layer within a multi-bit Trie node is marked using a bitmap: if a node is a real node, its corresponding bit is set to "1", otherwise it is set to "0". Please refer to [link / reference]. Figure 3 , Figure 3 In the subtree M0, the nodes at level 0 are real nodes (corresponding to IP prefix A), so the bitmap at level 0 is "1". At level 1, the first node is empty, and the second node is a real node (corresponding to IP prefix B), so the bitmap at level 1 is "01". Therefore, the next-hop bitmap of node M0 is formed by concatenating the bitmaps from level 0 and level 1, resulting in "101". When performing the longest prefix matching search in node M of height K, the bitmap is obtained from the next-hop bitmap of node M, decreasing from i = K - 1 to i = 0. Then, the first i bits of the IP segment to be queried (of length K) are truncated to obtain the index value Index. i And determine the index in the bit map. i Is the bit "1"? If the bit is "1", it indicates the existence of a corresponding real node, which is the matching node, and its corresponding prefix is ​​the matching prefix. During the search process, the first matching prefix found is the longest prefix match result within that node. Furthermore, the next-hop information corresponding to all real nodes within a node is stored contiguously. Therefore, only a pointer to the first next-hop information needs to be stored. During indexing, the next-hop information of all real nodes can be indexed simply by adding the offset of each real node relative to the first real node in the next-hop bitmap to this next-hop pointer. The offset of each real node can be obtained by calculating the number of "1"s between its current bit and the start bit in the next-hop bitmap. Let's continue with... Figure 3Taking a multi-bit Trie as an example, if the queried IP address is "100", when searching for node M0 using the first IP address segment ("10"), it is determined that there is no corresponding child node, so the matching prefix can only appear in node M0. Therefore, firstly, the first bit of the IP address segment "10" (i.e., "1", corresponding to the value 1) is used to check if the first bit of the corresponding internal first-level bitmap ("01") in the next-hop bitmap of node M0 is "1". In this example, the corresponding bit is "1", indicating that there is next-hop information (the next-hop information of the corresponding node N3). Then, the number of "1"s before this position in the next-hop bitmap is calculated, which is 1 in this example. If the next-hop pointer is NP1, then the address of the next-hop information of the corresponding node N3 is NP1+1, and the next-hop information is retrieved from memory through this address.

[0041] Based on this, this application defines the maximum distance between a node and all its successor leaf nodes as the "inverse distance" of that node. The inverse distance of a leaf node is always 0. For example, Figure 4 This illustration shows a schematic diagram of a 10-bit address space FIB example provided in an embodiment of this application. Figure 5 A schematic diagram of pipelined storage resource allocation and node mapping technology based on tree features is shown. Figure 5 The corresponding nodes in Figure 4 The FIB example in the following scheme description, unless otherwise specified, will be used as the reference. Figure 4 as well as Figure 5 Let's take a node as an example to illustrate. Please refer to... Figure 4 and Figure 5 ,exist Figure 5 There are four nodes with an inverse distance of 0: M1, M4, M7, and M6; two nodes with an inverse distance of 1: M2 and M5; one node with an inverse distance of 2: M3; and only one node with an inverse distance of 3: M0. After determining the inverse distance of a node, the node's pipeline level can be determined based on this distance. Specifically, nodes with an inverse distance of 0 are mapped to the last pipeline level, nodes with an inverse distance of 1 are mapped to the second-to-last pipeline level, and so on. For ease of description, let the total number of pipeline levels be P, and the numbering from the first pipeline level to the last pipeline level is as follows: S P-1 ,S P-2 ,...,S1,S0. For example, in Figure 5 In the process, nodes M1, M4, M7, and M6 are mapped to the memory RAM corresponding to pipeline stage S0; nodes M2 and M5 are mapped to the memory RAM corresponding to pipeline stage S1; node M3 is mapped to the memory RAM corresponding to pipeline stage S2; and node...

[0042] M0 is then mapped to the memory RAM corresponding to pipeline stage S3.

[0043] Furthermore, the actual mapping of nodes to pipeline stages has a certain degree of freedom. For example, in Figure 5 In this context, node M1 can be mapped to pipeline level S0, and also to higher pipeline levels S1 or S2; similarly, node M2 ​​can also be mapped to pipeline level S2. Therefore, in this embodiment, a dynamic mapping method based on a tree structure is adopted. Specifically, if the total number of pipeline levels is P, the range of pipeline levels that each node can be mapped to needs to comprehensively consider four key attribute values: 1) the inverse distance, denoted as h1; 2) the maximum number of pipeline levels of all child nodes, denoted as h2 (if the node has no child nodes, h2 defaults to -1); 3) the path length from the node to the root node, denoted as h3; and 4) the number of pipeline levels of the parent node, denoted as h4 (the root node's h4 defaults to P). Based on these four attribute values, the range of pipeline levels that each node can be mapped to can be expressed as [S max(h1,h2+1) ,S min(P-h3-1,h4-1) The lowest mappable pipeline level is determined by its own inverse distance and the confirmed mapping positions of its child nodes, while the highest mappable pipeline level is limited by the node's depth within the Trie structure and the confirmed mapping position of its parent node. The dynamic mapping mechanism provides greater mapping flexibility; when the storage space of a pipeline level is insufficient to accommodate a node, its mapping position can be adjusted, thereby improving the mapping success rate and enabling more efficient utilization of pipeline-level resources.

[0044] Therefore, when determining the actual mapping pipeline level for a node, in this embodiment, the corresponding pipeline level can be checked sequentially from the lowest to the highest according to the range of mappable pipeline levels for the node to determine whether it has sufficient storage space to accommodate the node, and it can be preferentially mapped to the first pipeline level that meets the condition. Specifically, for a node M, the specific process of dynamic mapping is as follows:

[0045] S11: Based on the inverse distance h1 of node M and the maximum value h2 of the pipeline levels of all child nodes, calculate the lower bound L = max(h1, h2 + 1) of the mappable pipeline level range; based on the path length h3 from node M to the root node and the pipeline level h4 of the parent node, calculate the upper bound U = min(P - h3 - 1, h4 - 1); combine these to obtain the mappable pipeline level range [S L ,S U ].

[0046] S12: From S L Start, increment to S U Check the storage capacity of each pipeline stage in turn. If the current pipeline stage S has sufficient storage... i If the storage space is sufficient to accommodate node M, then node M will be mapped to pipeline stage S. iAnd end the mapping process.

[0047] S13: If there is no space available in all pipeline stages, return a mapping failure indication.

[0048] Please continue to refer to this. Figure 5 In the diagram, the number of pipeline stages P is 4. For node M2, the inverse distance h1 of M2 is 1. Since M2 has only one child node M4, and the determined mapping position of M4 is S0, the h2 of M2 is 0. The path length h3 from M2 to the root node M0 is 1. The determined mapping position of the parent node of M2 is S3, so the h4 of M2 is 3. Therefore, the mapping range of M2 is [S1, S2]. The storage resources of S1 and S2 are checked in turn, and it is prioritized to map to the first pipeline stage that meets the conditions. If there are no free storage resources in S1 and S2, the mapping fails.

[0049] Based on this dynamic mapping scheme, this application adopts a pipelined storage resource allocation scheme that matches the dynamic mapping method. This allocation scheme matches the mapping strategy, allocating more resources to lower pipelines and relatively less to higher pipelines. Based on this idea, this application provides an automatic calculation method for pipelined storage resource allocation schemes. This method supports calculating the optimal overall allocation ratio of storage resources for each pipeline using at least one FIB. Assume there are M known FIBs, where the multi-bit Trie corresponding to the j-th FIB is a Trie. j (1≤j≤M). Assume the total number of flow stages is P, and the number of flow stages is S. i The allocation weight is denoted as w(i), the allocation ratio as f(i), and the minimum total resource C(j) required to successfully map all multi-bit Trie nodes using the dynamic mapping method described in this invention under this allocation ratio (0≤i<P,1≤j≤M). Further, it is assumed that the initial allocation ratio of storage resources for each pipeline stage is equal, that is, it is assumed that each pipeline stage S... i They have the same allocation weight w0(i). Therefore, initially, each flow stage S... i The initial allocation ratio is Subsequent iterations were conducted based on this allocation ratio. The specific process of the T-th round of allocation scheme iteration is as follows:

[0050] S21: Calculate the minimum total resources required for each FIB table under this allocation ratio. At the current pipeline allocation ratio f T (i) Under this condition, for each FIB corresponding to the Trie j Calculate the minimum total resource C required for all nodes to be successfully mapped using the dynamic mapping method described in this invention. T (j).

[0051] S22: Calculate the actual utilization rate of each flow stage under the current allocation ratio. Based on the Trie obtained in step one... j Minimum total resource C T (j) and the current allocation ratio f T (i) After using the dynamic mapping method described in this invention, if the actual storage overhead used by each pipeline stage is c T (i,j), calculate S for each flow stage i The actual proportion of total storage resources used is

[0052] S23: Based on the current resource usage, the pipeline stages are divided into two categories: pipeline stages with excess storage resources and pipeline stages with efficient storage resource utilization. This embodiment sets a fitting parameter α (α∈(0,1)). For all Trie corresponding to FIBs... j Both satisfy f′ T (i,j)<αf T (i) Flow level S i The set of pipeline stages with excess resources is denoted as D1; ​​the remaining pipeline stages are considered to have resources that have been effectively utilized, and their set is denoted as D2. If all pipeline stages are currently effectively utilized, i.e., D1 is an empty set, the iteration can terminate, and the allocation ratio at this point is the final ratio.

[0053] S24: If D1 is a non-empty set, iterate through the allocation ratio scheme. This embodiment sets a variable iteration parameter λ (which initially satisfies λ∈(0,1)). For pipeline stages S with excess resources... i For ∈D1, its assigned weight will be reduced, and the new weight will be... And update the new allocation ratio according to the new weights. At the same time, the value of the iteration parameter λ is reduced, and the process returns to step S21 to enter the next iteration.

[0054] For example, Figure 6 A schematic diagram illustrating an example of storage space allocation schemes for each pipeline stage is shown. Please refer to... Figure 6 This embodiment presents three pipelined storage resource allocation schemes (the total number of pipelines is 11). Except for pipeline S0 in scheme 3, which allocates less resources to S0 due to boundary conditions than S1, all other pipelines satisfy the requirement that subsequent pipelines allocate no less resources than preceding pipelines. It is worth noting that the allocation schemes described in this application include, but are not limited to, the specific allocation examples given. As long as the allocation primarily conforms to the principle that the storage resources of lower pipelines are no less than those of higher pipelines, and matches the mapping strategy, it falls within the scope of protection of this application.

[0055] To support dynamic mapping methods, for any given node, obtaining its child nodes requires encoding the following three types of information (collectively referred to as "child node information"): first, child node matching information (i.e., matching IP ranges); second, the pipeline level to which the child node belongs; and third, the specific storage address corresponding to the child node within that pipeline level. Figure 5 Taking node M0 as an example, the encoding information of its child node M2 ​​is as follows: (1) Matching information: 100 (indicating that the internal path of M2 through M0 is "100"); (2) Pipeline level: S1 (indicating that M2 is mapped to pipeline level S1); (3) Storage address: Addr2. In addition, the next-hop information corresponding to the IP prefix within the node is encoded using the next-hop bitmap as described above. Figure 5 The search data structure tree corresponding to the multi-bit Trie tree in the example is as follows: Figure 7 As shown.

[0056] For child nodes, the lookup process for each child node involves each pipeline level receiving the pipeline level S to which the node to be looked up belongs, the corresponding storage address Addr, and the remaining IP address to be looked up from the previous pipeline level. The specific lookup process for child nodes at each pipeline level may include the following steps:

[0057] S31: Receive the pipeline level S to which the node to be searched belongs, the corresponding storage address Addr, and the remaining IP address to be searched from the previous pipeline level; if the received information is valid, the current pipeline level proceeds to step S32; otherwise, the current pipeline level continues to repeat step S31.

[0058] S32: If the pipeline level S to which the node to be accessed belongs is the same as the current pipeline level, then obtain the node M from the address Addr and jump to step S33 to query node M; if the pipeline level S to which the node to be accessed belongs is different from the current pipeline level, then pass the passed pipeline level S, the storage address Addr and the remaining IP address to be searched to the next pipeline level, and the current pipeline level continues to repeat step S31.

[0059] S33: Extract the header K (search step size) bits from the remaining IP address to be searched, and perform parallel matching on the IP segments corresponding to all child nodes stored in the node. If a matching child node exists, it becomes the next node to be searched. Its pipeline level S, storage address Addr, and the remaining IP address to be searched are passed to the next pipeline level, and the current pipeline level continues to repeat step S31. If all matches fail, the child node search process for the current IP address ends, and the current pipeline level continues to repeat step S31.

[0060] Please refer to Figure 6 as well as Figure 7Assume the IP address to be queried is “0001011001”. In pipeline S3, the first clock cycle input includes the following: (1) pipeline S3 to which node M0 belongs; (2) the memory address Addr0 corresponding to node M0 in pipeline S3; (3) the remaining IP address to be queried, “0001011001”. Since the node to be queried, M0, is mapped to pipeline S3 and is the same as the current pipeline, node M0 is obtained from the address Addr0 in S3. Then, the first three digits of the remaining IP address to be queried (search step size is 3), i.e., “000”, are extracted and compared in parallel with the matching IP segments “000”, “100”, and “111” of child nodes M1, M2, and M3. Since child node M1 is successfully matched, its pipeline S0, the corresponding memory address Addr1, and the remaining IP address to be queried, “1011001”, are passed to the next pipeline S2.

[0061] In pipeline stage S2, the second clock cycle input includes the following: (1) the pipeline stage S0 to which node M1 belongs; (2) the memory address Addr0 corresponding to node M1 in pipeline stage S0; and (3) the remaining IP address to be queried, "1011001". Since the node to be queried, M2, is mapped to pipeline stage S0, which is different from the current pipeline stage, pipeline stage S2 passes the relevant information to the next pipeline stage S1.

[0062] In pipeline stage S1, the third clock cycle input includes the following: (1) the pipeline stage S0 to which node M1 belongs; (2) the memory address Addr0 corresponding to node M1 in pipeline stage S0; and (3) the remaining IP address to be queried, "1011001". Since the node to be queried, M2, is mapped to pipeline stage S0, which is different from the current pipeline stage, pipeline stage S1 passes the relevant information to the next pipeline stage S0.

[0063] In pipeline level S0, the input for the fourth clock cycle includes the following: (1) the pipeline level S0 to which node M1 belongs; (2) the memory address Addr0 corresponding to node M1 in pipeline level S0; and (3) the remaining IP address to be queried, "1011001". Since the node to be queried, M2, is mapped to pipeline level S0 and is the same as the current pipeline level, node M1 is obtained from the address Addr1 in S0. Subsequently, the first three digits "101" of the remaining IP address to be queried are extracted. Since node M1 has no child nodes, the matching fails, and the child node search process ends.

[0064] The above is an introduction to the tree-based pipelined storage resource allocation and mapping technique. Utilizing the general characteristics of tree structures—that leaf nodes typically constitute the largest number of nodes, and the number of nodes further from the leaf nodes decreases—a hierarchical mapping is applied to multi-bit Trie nodes: leaf nodes are mapped to the last pipeline stage, nodes with an inverse distance of 1 are mapped to the second-to-last pipeline stage, and so on. Simultaneously, the storage resource allocation scheme for each pipeline stage is matched to the mapping strategy, meaning the last pipeline stage receives relatively more storage resources, followed by the second-to-last, and so on, thus achieving high storage resource utilization. This technique can effectively address the problem of efficient allocation and mapping of storage resources.

[0065] Furthermore, to improve the storage efficiency of multi-bit Trie structures, embodiments of this application also provide a method for compressing search data structures based on subtree similarity. This method achieves efficient compression of next-hop information in the search structure by reusing the next-hop bitmap of the same subtree, thereby achieving high storage efficiency.

[0066] Specifically, multi-bit Trie nodes need to encode the index information of their child nodes and the next-hop information corresponding to the IP prefix within the node. The main encoding method for the child node index information has been described above; the next-hop information corresponding to the IP prefix is ​​encoded using the next-hop bitmap as previously described. To reduce the storage overhead required to store a single multi-bit Trie node, this embodiment classifies multiple subtrees with similar distribution patterns based on the structural similarity within the subtree and stores them using a unified encoding method, thereby reducing redundant information and improving storage efficiency.

[0067] In a multi-bit Trie structure, the real nodes (i.e., nodes containing IP prefixes) within multiple multi-bit Trie nodes (i.e., subtrees) often exhibit highly similar distribution patterns. Figure 8 This diagram illustrates the distribution and encoding of the real nodes within each node. Please refer to it. Figure 5 and Figure 8 In Figure 5, the distribution of real nodes within each node of a multi-bit Trie is only three types: M0, M2, and M... 5，Their actual nodes are all located at the first node position of the second level and the third node position of the third level within the subtree; similarly, nodes M1, M3, and M6 also exhibit similar distribution characteristics, while nodes M4 and M7 also show similarity. Therefore, a two-step strategy can be adopted for encoding the next-hop information: First, the encoding method for the next-hop information of all nodes is consistent with the aforementioned multi-bit Trie method, that is, using a bitmap to mark the position of the next-hop information within the node. Second, an indirect storage method is used to manage the next-hop bitmap of the node, that is, the next-hop bitmap of all nodes is stored independently in dedicated storage resources, while the node itself only records the address of the next-hop bitmap in storage (hereinafter referred to as "next-hop bitmap pointer"). Therefore, all nodes with the same next-hop bitmap share the same next-hop bitmap pointer, thus pointing to the same storage location in storage. After combining the subtree similarity-based search structure compression method, the complete search data structure tree is as follows: Figure 9 As shown, the size of the next-hop bitmap is typically much larger than the next-hop bitmap pointer. Therefore, the compression method based on subtree similarity effectively reduces the overhead required for nodes to store the next-hop bitmap.

[0068] Furthermore, to avoid backtracking, this application embodiment introduces a Best Matching Prefix (BMP) for each node. The BMP records the next-hop address of the nearest real node on the path backtracking from the current node to the root node in the original single-bit Trie. For example, in... Figure 5 In the diagram, the nearest real node to node M2 ​​is the node corresponding to IP prefix B. Therefore, the BMP of node M2 ​​is the next-hop address corresponding to IP prefix B.

[0069] After the child node lookup process is complete, the pipeline stage for calculating the next-hop address will begin, where the next-hop information for the last matching node M will be searched. The specific steps are as follows:

[0070] S41: Based on the next-hop bitmap pointer stored in the matching node M, retrieve the corresponding next-hop bitmap from the storage.

[0071] S42: Perform a longest prefix match search in node M at height K, i.e., decrease from i = K-1 to i = 0, and obtain the bit map of the i-th level in the next hop bit map of node M. Then, truncate the first i bits of the IP segment to be queried (length K) to obtain the index value Index. i And check the index in the bit map. i Is the bit "1"?

[0072] S43: During the search process, if a matching prefix exists, the first matching prefix found is the longest prefix matching result within that node. Obtain the next-hop address NP stored in node M and calculate the number of "1"s C between the position of the longest matching prefix and the start position in the next-hop bitmap. The next-hop information address corresponding to the longest matching prefix is ​​then returned as NP+C. If no matching prefix exists, the BMP stored within the node is returned.

[0073] Continuing with the example of the child node lookup process (i.e., IP address "0001011001"). Since the pipeline level where node M1 is located is S0, the child node lookup is first performed in S0. However, no matching child node is found at this level, so it is necessary to find the next-hop information of node M1. First, the next-hop bitmap pointer MAP1 and the next-hop pointer NP1 are obtained from node M1. Then, the next-hop bitmap "1000100" is obtained at the storage address MAP1 corresponding to the pipeline level for next-hop address calculation. Next, the longest prefix match search is performed in node M1 (node ​​height K=3). First, the first 3 bits ("101") are extracted from the remaining IP address "1011001" as the lookup IP segment. Then, the first 2 bits of the IP segment (i.e., "10", corresponding to the value 2) are extracted, and the second bit of the corresponding internal second-level bitmap ("0100") in the next-hop bitmap is checked to see if it is "1". In this example, the bit is "0". Therefore, we continue by extracting the first bit of the IP segment (i.e., "1", corresponding to the numerical value 1) and checking if the first bit of the corresponding internal layer 1 bitmap ("00") in the next-hop bitmap is "1". In this example, this bit is "0". Therefore, we continue by extracting the first 0 bits of the IP segment (i.e., corresponding to the numerical value 0) and checking if the 0th bit of the corresponding internal layer 0 bitmap ("1") in the next-hop bitmap is "1". In this example, this bit is "1", indicating a successful prefix match. We count the number of "1"s between the matching bit and the start bit of the next-hop bitmap, which is 0. Therefore, the next-hop address is NP1+0.

[0074] The above describes the IP address lookup method provided in this application. By utilizing the general characteristics of tree structures—namely, the largest number of leaf nodes and a relatively smaller number of nodes farther from the leaf nodes—a hierarchical mapping is performed on multi-bit Trie nodes: leaf nodes are mapped to the last pipeline stage, nodes with an inverse distance of 1 are mapped to the second-to-last pipeline stage, and so on. Simultaneously, the storage resource allocation scheme for each pipeline stage is matched with the mapping strategy, meaning the last pipeline stage receives relatively more storage resources, followed by the second-to-last, and so on, thereby achieving high storage resource utilization. Furthermore, the next-hop bitmap of the same subtree is reused to achieve efficient compression of the next-hop information in the lookup structure, thus achieving high storage efficiency. Through high storage resource utilization and high storage efficiency, the efficiency of IP address lookup is improved.

[0075] It is understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. Furthermore, in some possible implementations, each step in the above embodiments may be selectively executed according to actual circumstances; it may be partially or fully executed, without limitation here. All or part of any feature of any embodiment of this application can be freely and arbitrarily combined without contradiction. The combined technical solutions are also within the scope of this application.

[0076] Based on the methods in the above embodiments, this application also provides an IP address lookup device. For example, Figure 10 A schematic diagram of the IP lookup device provided in an embodiment of this application is shown. Figure 10 As shown, the IP lookup device 1000 includes a construction module 1001 and a processing module 1002.

[0077] Among them, the construction module 1001 is used to construct a lookup data structure tree based on a multi-bit Trie tree, wherein each Trie node corresponds to one or more IP prefixes in the IP forwarding table;

[0078] The processing module 1002 is used to determine the range of mappable pipeline stages for each node based on the inverse distance of each node in the search data structure tree, the pipeline stage where the child node is located, the path length from the node to the root node, and the position of the pipeline stage where the parent node is located; wherein, the inverse distance is defined as the maximum distance between the node and all its successor leaf nodes.

[0079] The processing module 1002 is also used to dynamically map each node to the independent storage resources of the corresponding pipeline level according to the range of mappable pipeline levels and the storage space status of each pipeline level.

[0080] The processing module 1002 is also used to perform IP address lookup in parallel in each pipeline stage based on the node mapping result, so as to realize pipeline parallel lookup.

[0081] It should be understood that the above-described device is used to execute the methods in the above embodiments. The implementation principle and technical effect of the corresponding program modules in the device are similar to those described in the above methods. The working process of the device can be referred to the corresponding process in the above methods, and will not be repeated here.

[0082] Based on the methods in the above embodiments, this application provides a computer-readable storage medium storing a computer program that, when run on a processor, causes the processor to execute the methods in the above embodiments.

[0083] Based on the methods in the above embodiments, this application provides a computer program product that, when run on a processor, causes the processor to execute the methods in the above embodiments.

[0084] It is understood that the processor in the embodiments of this application may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor may be a microprocessor or any conventional processor.

[0085] The method steps in the embodiments of this application can be implemented in hardware or by a processor executing software instructions. The software instructions can consist of corresponding software modules, which can be stored in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, portable hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can reside in an ASIC.

[0086] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted through the computer-readable storage medium. The computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state disk (SSD)).

[0087] It is understood that the various numerical designations used in the embodiments of this application are merely for descriptive convenience and are not intended to limit the scope of the embodiments of this application.

Claims

1. A method for looking up an IP address, characterized in that, Applied to IPv6, the method includes: A lookup data structure tree is constructed based on a multi-bit Trie tree, where each Trie node with a real node inside corresponds to one or more IP prefixes in the IP forwarding table; Based on the inverse distance of each node in the search data structure tree, the pipeline level of its child nodes, the path length from the node to the root node, and the position of the parent node in the pipeline level, the range of mappable pipeline levels for each node is determined; wherein, the inverse distance is defined as the maximum distance between a node and all its successor leaf nodes. Based on the mappable pipeline range and the storage space status of each pipeline, each node is dynamically mapped to the independent storage resources of the corresponding pipeline. This dynamic mapping includes: calculating the lower limit L and upper limit U of the mappable pipeline range for each node, where the lower limit L = max(h1, h2 + 1) and the upper limit U = min(P - h3 - 1, h4 - 1), where h1 is the inverse distance of the node, h2 is the maximum number of pipelines containing all child nodes of the node, h3 is the path length from the node to the root node, h4 is the number of pipelines containing the parent node, and P is the total number of pipelines; starting from the lower limit L and increasing to the upper limit U, the storage resources of each pipeline are checked sequentially to ensure sufficient storage space for the node; the node is then mapped to the first pipeline that meets the storage space requirements. In each pipeline stage, IP address lookup is performed in parallel based on the node mapping results to achieve pipelined parallel lookup.

2. The method according to claim 1, characterized in that, The method further includes: automatically calculating the storage resource allocation ratio of each pipeline stage based on the dynamic mapping results of the nodes.

3. The method according to claim 2, characterized in that, The automatic calculation of the storage resource allocation ratio for each pipeline stage includes: Initialize the storage resource allocation ratio for each pipeline stage; Iteratively execute the following steps until convergence: Calculate the actual storage resource usage ratio for each pipeline level based on the current allocation ratio; Identify pipelines with excess storage resources; Reduce the allocation weight of pipelines with excess storage resources and update the allocation ratio; When there is an excess of non-pipeline storage resources, stop the iteration and determine the final storage resource allocation ratio.

4. The method according to claim 3, characterized in that, The automatic calculation of the storage resource allocation ratio for each pipeline stage is specifically as follows: Let the total number of pipeline stages be P, the current iteration number be T, and the number of pipeline stages be S. i The allocation weight is w T (i), the allocation ratio is f T (i), and make the initial weights w0(i) equal; For a given M IPv6 FIBs corresponding to Trie_j (1≤j≤M), at the current allocation ratio f T (i) Using the dynamic mapping method, calculate the minimum total resource C required for each Trie_j to successfully map all multi-bit Trie nodes. T (j); According to C T (j) and f T (i) Calculate S for each flow stage i Actual storage usage c under the j-th Trie T (i,j), the flow level S is calculated for each Trie_j. i usage ratio ; Setting the fitting parameters α∈(0,1) will satisfy Flowing S i The excess resources are assigned to the resource surplus set D1, and the rest are assigned to the effective utilization set D2; if D1 is empty, the iteration terminates, and the current f... T (i) is the final allocation ratio; If D1 is a non-empty set, set a variable iteration parameter λ∈(0,1), and the pipeline S i The new weights are And update the new allocation ratio according to the new weights. Meanwhile, the value of the iteration parameter λ is reduced, and the iteration continues until D1 is empty.

5. The method according to claim 1, characterized in that, The method further includes: The nodes with similar subtree structures in the search data structure tree are categorized. Similar subtrees in the same category are compressed and stored using a unified next-hop bitmap; The node itself only stores a pointer to the unified next-hop bitmap to achieve efficient compression of node storage space.

6. The method according to claim 5, characterized in that, The next-hop bitmap uses a bitmap method to mark the existence of real nodes in each layer inside the node. The next-hop information corresponding to all real nodes inside the node is stored in a continuous manner. The node only stores a pointer to the first next-hop information. The next-hop information is indexed by calculating the offset of the real node in the next-hop bitmap.

7. The method according to claim 1, characterized in that, The method further includes: For each node, a Best Matching Prefix (BMP) is introduced, which records the next-hop address of the nearest real node on the path from the current node back to the root node. If no matching prefix exists within a node, the BMP is returned as the search result.

8. The method according to claim 1, characterized in that, Each pipeline level receives from the previous pipeline level the pipeline level to which the node to be searched belongs, the corresponding storage address, and the remaining IP addresses to be searched. If the pipeline level of the node to be accessed is the same as the current pipeline level, then retrieve the node from the corresponding address and perform the query. If the pipeline level to which the node to be accessed belongs is different from the current pipeline level, then the relevant information will be passed to the next pipeline level. The current pipeline stage continues to receive the next query information, and outputs a routing lookup result every clock cycle.

9. An IP address lookup device, characterized in that, Deployed on a router that uses IPv6, the device includes: The building module is used to construct a lookup data structure tree based on a multi-bit Trie tree, where each Trie node with a real node inside corresponds to one or more IP prefixes in the IP forwarding table; The processing module is used to determine the range of mappable pipeline stages for each node based on the inverse distance of each node in the search data structure tree, the pipeline stage where the child node is located, the path length from the node to the root node, and the position of the pipeline stage where the parent node is located; wherein, the inverse distance is defined as the maximum distance between the node and all its successor leaf nodes. The processing module is further configured to dynamically map each node to the independent storage resources of the corresponding pipeline level based on the mappable pipeline level range and the storage space status of each pipeline level; wherein, the dynamic mapping includes: calculating the lower limit L and upper limit U of the mappable pipeline level range for each node, where the lower limit L = max(h1, h2 + 1), and the upper limit U = min(P - h3 - 1, h4 - 1), where h1 is the inverse distance of the node, h2 is the maximum number of pipeline levels in which all child nodes of the node are located, h3 is the path length from the node to the root node, h4 is the number of pipeline levels in which the parent node is located, and P is the total number of pipeline levels; starting from the lower limit L and increasing to the upper limit U, checking in turn whether the storage resources of each pipeline level are sufficient to accommodate the node; and mapping the node to the first pipeline level that meets the storage space conditions; The processing module is also used to perform IP address lookup in parallel in each pipeline stage based on the node mapping result, so as to realize pipeline parallel lookup.

Images