Memory preparation method, memory and electronic equipment
By using a self-aligned multilayer vertical stacking structure and etching technology, a double-channel gate-surrounded field-effect transistor was fabricated, solving the problem of excessive DRAM cell area and realizing the fabrication of high-density and high-integration memory.
Patent Information
- Application Number
- CN202511119507.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-11
- Publication Date
- 2025-12-12
AI Technical Summary
Traditional DRAM cell area is difficult to shrink further. Existing 2T0C DRAM has a large cell area, and the self-alignment process leads to increased interlayer alignment deviation, affecting integration density and reliability.
By employing a self-aligned multilayer vertical stacked structure, grooves are formed through etching, and field-effect transistors with double-channel surround gates are fabricated within them, enabling self-aligned stacking of read and write transistors to form a capacitor-free memory cell.
The DRAM cell area has been effectively reduced to 4F2, and further compressed to 2F2, which has improved storage density and integration, simplified the process flow, and improved reliability.
Smart Images
Figure CN121126776A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated semiconductors, and more particularly to a method for fabricating a memory, a memory, and an electronic device. Background Technology
[0002] Dynamic random access memory (DRAM) typically uses a transistor and a capacitor (1T1C) structure as the memory cell of a chip. However, with the continuation of Moore's Law, the area reduction of traditional DRAM has encountered a bottleneck, so there is an urgent need for a method that can reduce the area of DRAM memory cells and increase storage density. Summary of the Invention
[0003] This application provides a method for fabricating a memory, a memory, and an electronic device, which can reduce the area of the memory cell and improve the storage density and integration.
[0004] In a first aspect, embodiments of this application provide a method for fabricating a memory, the method comprising: forming a stacked structure on a semiconductor substrate, wherein the stacked structure includes a first stacked structure, a first isolation structure, and a second stacked structure stacked sequentially from bottom to top; etching the second stacked structure, the first isolation structure, and the first stacked structure sequentially from top to bottom to form a first groove; forming a first channel structure and a first gate structure sequentially within the first groove, wherein the first channel structure is located between the first gate structure and a third stacked structure, and the third stacked structure is the etched first stacked structure; the height of the first channel structure is less than the height of the first gate structure, and the height of the first gate structure is less than the height of the second isolation structure; the second isolation structure is the etched first isolation structure; the first channel structure, the first gate structure, and the third stacked structure constitute a read transistor; forming a second channel structure and a second gate structure sequentially above the first gate structure within the first groove, wherein the second channel is located between the second gate structure and a fourth stacked structure, and the fourth stacked structure is the etched second stacked structure; and forming a write transistor comprising the second channel structure, the second gate structure, and the fourth stacked structure.
[0005] In some embodiments, the first stacked structure includes a first metal layer, a first isolation layer, and a second metal layer stacked sequentially from bottom to top; the second stacked structure includes a third metal layer and a second isolation layer stacked sequentially from bottom to top; wherein etching the second stacked structure, the first isolation structure, and the first stacked structure sequentially from top to bottom to form a first groove includes: etching at least a portion of the second isolation layer, the third metal layer, the first isolation structure, the second metal layer, the first isolation layer, and the first metal layer sequentially from top to bottom to form a first groove; wherein the etched first metal layer forms the first bit line BL metal in the read transistor, the etched second metal layer forms the first word line WL metal in the read transistor, and the etched third metal layer forms the second BL metal in the write transistor.
[0006] In some embodiments, the second gate structure includes a second WL metal written into the transistor.
[0007] In some embodiments, a first channel structure and a first gate structure are sequentially formed in a first groove, including: depositing an oxide material in the first groove to form an initial first channel structure, wherein the initial first channel structure covers the bottom and the wall of the first groove; etching the initial first channel structure to a preset height to form the first channel structure; wherein the first channel structure covers a first portion of the groove wall, and the first portion is opposite to a first metal layer, a first isolation layer, and a second metal layer; and sequentially depositing a gate dielectric material and a gate metal material in the first groove where the first channel structure is formed to form a first gate dielectric layer and a first gate electrode layer, respectively; wherein the first gate dielectric layer and the first gate electrode layer constitute a first gate structure, and the height of the first gate structure is less than the height of the second isolation structure and greater than the height of the first channel structure.
[0008] In some embodiments, a first channel structure and a first gate structure are sequentially formed in a first groove, comprising: depositing an oxide material in the first groove to form an initial first channel structure, wherein the initial first channel structure covers the bottom and walls of the first groove; depositing a dielectric material on the initial first channel structure to form a first sacrificial structure; etching the portion of the initial first channel structure not covered by the first sacrificial structure to form the first channel structure; wherein the first channel structure covers a first portion of the groove walls and the bottom of the groove, the first portion being opposite to a first metal layer, a first isolation layer, and a second metal layer; removing the first sacrificial structure; and sequentially depositing a gate dielectric material and a gate metal material in the first groove where the first channel structure is formed to form a first gate dielectric layer and a first gate electrode layer, respectively; wherein the first gate dielectric layer and the first gate electrode layer constitute a first gate structure, the height of the first gate structure being less than the height of the second isolation structure and greater than the height of the first channel structure.
[0009] In some embodiments, after forming a first channel structure and a first gate structure sequentially in a first groove, the method further includes: depositing a gate metal material on the first gate structure to form a first metal structure, wherein the height of the first metal structure is less than the height of the second isolation structure.
[0010] In some embodiments, a second channel structure and a second gate structure are sequentially formed on the first gate structure within the first groove, including: depositing an oxide material on the first gate structure within the first groove to form a second channel structure; and sequentially depositing a gate dielectric material and a gate metal material on the second channel structure to form a second gate dielectric layer and a second gate electrode layer, respectively; wherein the second gate dielectric layer and the second gate electrode layer constitute a second gate structure, and the height of the second gate structure is greater than the height of the fourth stacked structure.
[0011] Secondly, embodiments of this application provide a memory, which is fabricated using the fabrication method described in any of the embodiments of the first aspect. The memory includes a read transistor and a write transistor; the read transistor and the write transistor are self-aligned and stacked; wherein the read transistor includes a first channel structure, a first gate structure, and a bottom stack structure; the write transistor includes a second channel structure, a second gate structure, and a top stack structure; the first channel structure is located between the first gate structure and the bottom stack structure; the second channel structure is located between the second gate structure and the top stack structure; the height of the first channel structure is less than the height of the first gate structure;
[0012] The memory also includes: a transistor isolation structure located between the bottom stacked structure and the top stacked structure; the height of the first gate structure is less than the height of the transistor isolation structure.
[0013] In some embodiments, the bottom stack structure includes a first bit line (BL) metal in a read transistor, a first word line (WL) metal in a read transistor, and a first isolation layer structure; wherein the first isolation layer structure is located between the first BL metal and the first WL metal; the second gate structure includes a second WL metal in a write transistor, and the top stack structure includes a second BL metal in a write transistor and a second isolation layer structure; wherein the second isolation layer structure is located between the second BL metal and the second WL metal.
[0014] Thirdly, embodiments of this application provide an electronic device, which includes: a circuit board and a memory as described in the third aspect above, the memory being disposed on the circuit board.
[0015] In this application, a first groove can be formed by creating a stacked structure and etching the stacked structure. Then, the channel and gate structures of the read transistor and the channel and gate structures of the write transistor can be sequentially formed within the first groove. Thus, a double-layer channel-all-around (CAA) field-effect transistor is fabricated self-aligned using the first groove. Furthermore, the source and drain structures in the upper-layer field-effect transistor are in direct contact with the gate structure in the lower-layer field-effect transistor, forming a dual-transistor-capacitor-free (2T0C) DRAM. This process further reduces the cell area of the DRAM and improves integration performance.
[0016] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description
[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.
[0018] Figure 1 This is a first schematic diagram of the memory in an embodiment of this application.
[0019] Figure 2 This is a second schematic diagram of the memory in an embodiment of this application.
[0020] Figure 3 This is a third schematic diagram of the memory in the embodiments of this application.
[0021] Figure 4 This is a schematic diagram illustrating one implementation process of the memory fabrication method in this application.
[0022] Figure 5 This is a schematic diagram of the structure of a memory in an embodiment of this application.
[0023] Figures 6 to 15 This is a schematic diagram of the memory structure in the first fabrication process according to an embodiment of this application.
[0024] Figures 16 to 20 This is a schematic diagram of the memory structure in the second fabrication process according to an embodiment of this application.
[0025] Figure 21 This is a schematic diagram of the structure of the first type of memory array in the embodiments of this application.
[0026] Figure 22 for Figure 21 A schematic diagram of a cross-section of the memory array shown.
[0027] Figure 23This is a schematic diagram of the structure of the second type of memory array in the embodiments of this application.
[0028] Figure 24 This is a schematic diagram of the structure of the third type of memory array in the embodiments of this application.
[0029] The above images:
[0030] 10. Memory; 101. Read transistor; 102. Write transistor; 12. First channel structure; 13. First gate dielectric layer; 14. First gate electrode layer; 15. First BL metal; 16. First WL metal; 17. Second BL metal; 18. Second WL metal; 19. Second channel structure; 110. Second gate dielectric layer; 111. Second gate electrode layer;
[0031] 20. Substrate; 21. First metal layer; 22. First isolation layer; 23. Second metal layer; 24. First isolation structure; 25. Third metal layer; 26. Second isolation layer; 27. Hard mask structure; 28. First trench; 29. Third isolation layer; 30. Second isolation structure; 31. Fourth isolation layer; 32. Initial first channel structure; 33. Initial first gate dielectric; 34. Initial first gate electrode layer; 35. First metal structure; 36. First sacrificial structure. Detailed Implementation
[0032] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application.
[0033] In DRAM, ferroelectric random access memory (FeRAM), or other memories, a memory cell may include a transistor and a capacitor structure. The transistor is disposed on a substrate, and the capacitor structure is located at the end of the transistor furthest from the substrate; the transistor and the capacitor structure are electrically connected.
[0034] Taking DRAM as an example, the basic composition of DRAM is 1T1C. Currently, there are three main types of DRAM. The first type of DRAM has an area of 8F. 2 (F is the feature size of the DRAM cell), implemented by horizontally placing transistors and capacitors; the area of the second type of DRAM is 6F. 2 By tilting the transistor and capacitor structures, the density can be increased, thus achieving a smaller integration area; the third type of DRAM has an area of 4F. 2By vertically placing transistors and capacitors, the volume in the vertical direction is fully utilized, enabling the scaling of DRAM to a smaller area.
[0035] For example, Figure 1 This is a first schematic diagram of the memory in an embodiment of this application. Figure 1 Figure (a) shows the circuit structure of DRAM. DRAM includes a transistor Tp and a capacitor cap. The gate of transistor Tp is connected to the word line WL, one source / drain of transistor Tp is connected to the bit line BL, and the other source / drain is connected to the capacitor cap. Figure 1 (b) shows the physical structure of the DRAM. The capacitor cap is located above the transistor Tp. Figure 1 (c) shows the layout of the DRAM. When DRAM cells are integrated, the feature size of a single DRAM cell is not less than 2F × 3F.
[0036] However, the contradiction between reducing storage capacitors and increasing transistor leakage current limits the further miniaturization of DRAM. In recent years, 2TOC DRAM has become a research hotspot due to its elimination of storage capacitors and ultra-low leakage current. However, the cell area of existing planar 2TOC DRAM remains relatively large (approximately 20F). 2 Even with multiple stacking layers, its area is still difficult to exceed 4F. 2 .
[0037] For example, Figure 2 This is a second schematic diagram of the memory in an embodiment of this application. Figure 2 Figure (a) shows the circuit structure of a DRAM. The DRAM includes a write transistor Tw and a read transistor Tr, forming a node SN between them. The gate of the write transistor Tw is connected to the write word line WWL, one source / drain of the write transistor Tw is connected to the write bit line WBL, and the other source / drain is connected to the gate of the transistor Tr. One source / drain of the read transistor Tr is connected to the read bit line RBL, and the other source / drain is connected to the read word line RWL. Figure 2 (b) shows the physical structure of the DRAM. The write transistor Tw and the read transistor Tr are arranged in a planar configuration. Figure 2 (c) in the diagram shows the layout of the DRAM. The feature size of a single DRAM cell is not less than 4F × 5F.
[0038] Understandably, the storage principle of 2T0C DRAM includes: the gate of the write transistor Tw is connected to the write word line WWL. When the write word line WWL is open, information is transmitted from the write bit line WBL to the node SN. The node SN is made of a conductive material. The gate of the read transistor Tr is in contact with the node SN. When reading information, a fixed small voltage is applied across the two source / drain terminals of the read transistor Tr (connected to the read word line RWL and the read bit line RBL, respectively). The information is determined to be 0 or 1 by the read current.
[0039] Furthermore, in related technologies, a CAA structure DRAM is proposed. The fabrication process of this CAA structure DRAM may include: First, sputtering metal source / drain electrodes at the bottom as read bit lines (RBL). Second, sequentially depositing a dielectric layer and top metal source / drain electrodes via sputtering, with the dielectric layer serving as isolation between the read bit line (RBL) and the read word line (RWL), and the top metal source / drain electrodes serving as the read word line (RWL). Third, continuously etching to obtain etched holes using a dry etching process. Fourth, sequentially depositing channel material, gate dielectric layer, and gate electrode to complete the fabrication of the lower-layer transistor. Fifth, depositing metal as a storage node (SN) layer (the SN layer is the physical structure of the node SN, used to store charge information), the SN layer being electrically connected to the gate of the lower-layer transistor, and then depositing conductive material as the source / drain electrodes of the upper-layer transistor. Sixth, sequentially depositing a dielectric layer and metal source / drain electrodes, with the dielectric layer serving as isolation between the two source / drain electrodes of the upper-layer transistor, and the top metal source / drain electrodes serving as the write bit line (WBL). Step 7: Sequentially deposit the channel material, gate insulator, and gate electrode. The gate electrode is the write word line (WWL), completing the fabrication of the upper-layer transistor.
[0040] For example, Figure 3 This is a third schematic diagram of the memory in an embodiment of this application. For example... Figure 3 As shown, the DRAM is fabricated using steps one through seven described above. The write transistor Tw and the read transistor Tr are not self-aligned; their electrical connection relies on photolithographic alignment and the intermediate SN layer metal. Interlayer alignment deviations increase the cell area, hindering DRAM cell miniaturization. Therefore, a self-aligned vertical stacking structure is urgently needed to simplify the process and improve integration density and reliability.
[0041] Firstly, embodiments of this application provide a method for fabricating a memory, which can reduce the area of the memory cell and improve storage density and integration. Furthermore, it fully utilizes a self-aligned via design and a multi-layer vertical stacking architecture, achieving the fabrication of a self-aligned double-layer CAA field-effect transistor through deposition and selective etching, with the upper source / drain directly contacting the lower gate to form a capacitor-free memory cell. Its equivalent area is reduced to 4F. 2If the double-layer stack is further compressed to 2F 2 .
[0042] Figure 4 This is a schematic diagram illustrating one implementation process of the memory fabrication method in this application. Figure 4 As shown, the method for fabricating the memory in the embodiments of this application may include:
[0043] Step S101: Form a stacked structure on a semiconductor substrate.
[0044] Understandably, a stacked structure can be formed on a semiconductor substrate through deposition processes. The stacked structure can include a first stacked structure, a first isolation structure, and a second stacked structure stacked sequentially from bottom to top. Here, the first isolation structure is used to electrically isolate the first and second stacked structures. The first stacked structure is used to fabricate the structure in the read transistor, and the second stacked structure is used to fabricate the structure in the write transistor.
[0045] In some embodiments, the first stacked structure is closer to the semiconductor substrate than the second stacked structure.
[0046] In some embodiments, the first stacked structure may include a first metal layer, a first insulating layer, and a second metal layer stacked sequentially from bottom to top. The second stacked structure includes a third metal layer and a second insulating layer stacked sequentially from bottom to top. The first insulating structure is used to electrically isolate the second and third metal layers.
[0047] In some embodiments, step S101 may include: sequentially depositing and forming a first metal layer, a first isolation layer, a second metal layer, a first isolation structure, a third metal layer, and a second isolation layer on a semiconductor substrate.
[0048] Understandably, the first, second, and third metal layers can be formed by deposition of metallic materials. The first isolation layer, the first isolation structure, and the second isolation layer can be formed by deposition of insulating materials.
[0049] In some embodiments, the metallic material may be materials such as tungsten, aluminum, copper, molybdenum, titanium, ruthenium, or rhodium, etc., and this application does not limit this. The insulating material may be an oxide material, a nitride material, etc.
[0050] Step S102: Etch the second stacked structure, the first isolation structure, and the first stacked structure sequentially from top to bottom to form the first groove.
[0051] Understandably, after forming the stacked structure, a fin-like structure can be formed by etching the second stacked structure, the first isolation structure, and the first stacked structure sequentially from top to bottom in a single etching process. A self-aligned first groove can be formed between adjacent fin-like structures. After forming the first groove, the sidewalls of the second stacked structure, the first isolation structure, and the first stacked structure are exposed, and these sidewalls constitute the groove walls of the first groove.
[0052] In some embodiments, the first groove has a preset groove depth. In some embodiments, the preset groove depth is equal to or less than the height of the stacked structure. In embodiments of this application, the height may refer to the distance from the upper surface of the structure to the semiconductor substrate.
[0053] In some embodiments, where the first stacked structure may include a first metal layer, a first isolation layer, and a second metal layer stacked sequentially from bottom to top, and the second stacked structure includes a third metal layer and a second isolation layer stacked sequentially from bottom to top, step S102 may include: etching at least a portion of the second isolation layer, the third metal layer, the first isolation structure, the second metal layer, the first isolation layer, and the first metal layer sequentially from top to bottom to form a first groove.
[0054] Understandably, an initial first groove can be formed by self-aligning etching of the second isolation layer, the third metal layer, the first isolation structure, the second metal layer, and the first isolation layer from top to bottom. After forming the initial first groove, self-aligning etching of part or all of the first metal layer can make the initial first groove connected with the space released by etching the first metal layer, thus obtaining the first groove. Here, if it is a portion of the first metal layer that is self-aligned, then that portion is the part of the first metal layer that is away from the semiconductor substrate.
[0055] In some embodiments, the etched first metal layer forms the first BL metal in the read transistor, the etched second metal layer forms the first WL metal in the read transistor, and the etched third metal layer forms the second BL metal in the write transistor.
[0056] Understandably, the etched first and second metal layers are used to form the structure in the read transistor. Typically, the etched first metal layer can be the first source-drain metal connecting the first source-drain structure in the read transistor, and this first source-drain metal can also serve as the first bottom-line (BL) metal. The etched second metal layer can be the second source-drain metal connecting the second source-drain structure in the read transistor, and this second source-drain metal can also serve as the first bottom-line (WL) metal. The etched third metal layer is used to form the structure in the write transistor. Typically, the etched third metal layer can be the third source-drain metal of the third source-drain structure in the write transistor, and this third source-drain metal can also serve as the second bottom-line (BL) metal.
[0057] For ease of explanation, the source / drain structures mentioned in the embodiments of this application are abbreviations, specifically referring to the source structure and / or drain structure. That is, the transistor includes a first source / drain structure and a second source / drain structure. When the first source / drain structure is the drain, the second source / drain structure is the source; when the first source / drain structure is the source, the second source / drain structure is the drain. Furthermore, the same applies to source / drain metals, source / drain electrodes, etc.
[0058] In some embodiments, before step S102, the following may be included: depositing a hard mask structure on the stacked structure, using the hard mask structure as a mask, etching the stacked structure until a first groove is formed.
[0059] Understandably, a hard mask structure is formed on the stacked structure. The hard mask structure is used to locate the positions of the channel structure and the gate structure. By etching the stacked structure based on the hard mask structure, a first groove can be obtained. The channel structure and the gate structure are formed in the first groove.
[0060] In some embodiments, the hard mask structure can be formed from a dielectric material. In one embodiment, the dielectric material can be silicon dioxide, silicon nitride, etc.
[0061] It should be noted that the etching process in the embodiments of this application can be at least one of dry etching, reactive ion etching, etc.
[0062] Step S103: In the first groove, a first channel structure and a first gate structure are formed sequentially.
[0063] Understandably, to obtain a CAA field-effect transistor, after obtaining the first groove, a first channel structure can be formed on the groove wall of the first groove. Here, the first channel structure can be a hollow structure. The outer surface of the first channel structure is in contact with the groove wall of the first groove, and the inner surface of the first channel structure is in contact with the first gate structure subsequently formed.
[0064] In some embodiments, a first channel structure is located between a first gate structure and a third stacked structure, wherein the third stacked structure is the etched first stacked structure. The height of the first channel structure is less than the height of the first gate structure, and the height of the first gate structure is less than the height of the second isolation structure. The second isolation structure is the etched first isolation structure. The first channel structure, the first gate structure, and the third stacked structure constitute a readout transistor.
[0065] In some embodiments, both the first channel structure and the first gate structure can be formed by a deposition process. In the embodiments of this application, the deposition process may include: atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), etc.
[0066] In some embodiments, step S103 may include: depositing an oxide material in a first groove to form an initial first channel structure; etching the initial first channel structure to a predetermined height to form the first channel structure; and then sequentially depositing a gate dielectric material and a gate metal material in the first groove where the first channel structure is formed to form a first gate dielectric layer and a first gate electrode layer, respectively.
[0067] Understandably, the channel structure of a CAA field-effect transistor can be made of oxide material. An initial first channel structure can be formed by depositing oxide material in a first trench. Here, the initial first channel structure covers the bottom and walls of the first trench. The initial first channel structure can also cover the upper surface of the stacked structure. After forming the initial first channel structure, an etching process is used to etch the initial first channel structure to form the first channel structure. Here, the first channel structure covers a first portion of the trench wall of the first trench. The first channel structure does not cover the upper surface of the stacked structure. The first portion of the trench wall of the first trench is the lower half of the trench wall. The first portion of the trench wall of the first trench is at least opposite to the third stacked structure. That is, the first portion of the trench wall of the first trench is at least opposite to the first metal layer, the first isolation layer, and the second metal layer. After forming the first channel structure, a gate dielectric material can be deposited to form a first gate dielectric layer, and then a gate metal material can be deposited to form a first gate electrode layer. Here, the first gate dielectric layer and the first gate electrode layer can form a first gate structure. The first gate dielectric layer has a U-shaped structure, covering the bottom of the first groove and the inner surface of the first channel structure, and the first gate electrode layer is located in the middle of the first gate dielectric layer.
[0068] In some embodiments, the height of the first gate structure is less than the height of the second isolation structure, but greater than the height of the first channel structure.
[0069] Understandably, the height of the first gate structure is greater than the height of the first channel structure, allowing the first gate structure to be formed on top of the first channel structure. Thus, the conductivity of the first gate structure formed on top of the first channel structure can be utilized to form the node SN in a 2TOC DRAM.
[0070] In some embodiments, the first channel structure can be formed by fabricating a channel material. The channel material can be indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), indium zinc oxide (IZO), etc. In some embodiments, the first gate dielectric layer can be composed of a silicon oxide layer and a hafnium oxide layer with a high k-value, and the thicknesses of the silicon oxide layer and the hafnium oxide layer can be determined according to the polarity and performance of the transistor. In some embodiments, the first gate electrode layer can be composed of multiple layers of electrode materials, each layer of which includes, but is not limited to, hafnium, zirconium, titanium, tantalum, aluminum, and alloys of these metals.
[0071] In some embodiments, step S103 may include: depositing an oxide material in a first trench to form an initial first channel structure; depositing a dielectric material on the initial first channel structure to form a first sacrificial structure; etching the initial first channel structure not covered by the first sacrificial structure to form the first channel structure; removing the first sacrificial structure; and sequentially depositing a gate dielectric material and a gate metal material in the first trench where the first channel structure is formed to form a first gate dielectric layer and a first gate electrode layer, respectively.
[0072] Understandably, the channel structure of a CAA field-effect transistor can be made of oxide material. An initial first channel structure can be formed by depositing oxide material within a first trench. Here, the initial first channel structure covers the bottom and walls of the first trench. The initial first channel structure can also cover the upper surface of the stacked structure. After forming the initial first channel structure, a dielectric material can be deposited on top of the initial first channel structure to form a first sacrificial structure. Here, the height of the first sacrificial structure is greater than the height of the third stacked structure but less than the height of the second isolation structure. An etching process can then be used to etch away the portion of the initial first channel structure not covered by the first sacrificial structure to form the first channel structure. After forming the first channel structure, the first sacrificial structure can be removed, exposing the first channel structure not covered by the first sacrificial structure.
[0073] Here, the first channel structure covers a first portion of the trench wall and the bottom of the first trench. The first portion of the trench wall is the lower half of the trench wall. The first portion of the trench wall is at least opposite to the third stacked structure. That is, the first portion of the trench wall is at least opposite to the first metal layer, the first isolation layer, and the second metal layer. After forming the first channel structure, a gate dielectric material can be deposited to form a first gate dielectric layer, and then a gate metal material can be deposited to form a first gate electrode layer. Here, the first gate dielectric layer and the first gate electrode layer can form a first gate structure. The first gate dielectric layer has a U-shaped structure, covering the bottom of the first trench and the inner surface of the first channel structure, and the first gate electrode layer is located in the middle of the first gate dielectric layer.
[0074] In some embodiments, in order to increase the capacitance of node SN, step S103 may include: depositing gate metal material on the first gate structure to form a first metal structure.
[0075] Understandably, the first metal structure can be connected to the first gate structure. Simultaneously, the height of the first metal structure can be less than the height of the second isolation structure to prevent the first metal structure from affecting the fabrication of the write transistor.
[0076] Step S104: On top of the first gate structure within the first groove, a second channel structure and a second gate structure are sequentially formed.
[0077] Understandably, after forming the first gate structure, an oxide material, a gate dielectric material, and a gate metal material can be sequentially deposited on top of the first gate structure within the first groove to form a second channel structure, a second gate dielectric layer, and a second gate electrode layer, respectively. Here, the second gate dielectric layer and the second gate electrode layer constitute the second gate structure.
[0078] Understandably, to obtain a CAA field-effect transistor, after obtaining the first gate structure, a second channel structure can be formed on the trench wall of the first groove and the first gate structure. Here, the second channel structure can be a U-shaped structure. The outer surface of the second channel structure is in contact with the trench wall of the first groove and the first gate structure, and the inner surface of the first channel structure is in contact with the subsequently fabricated second gate structure.
[0079] In some embodiments, the second channel is located between the second gate structure and the fourth stacked structure, and the fourth stacked structure is the etched second stacked structure. The second channel structure, the second gate structure, and the fourth stacked structure constitute a write transistor.
[0080] In some embodiments, both the second channel structure and the second gate structure can be formed by a deposition process.
[0081] In some embodiments, the second channel structure further covers the upper surface of the fourth stacked structure. Thus, the second communication structure can be a T-shaped structure. In some embodiments, the second gate structure covers the second channel structure. The second gate structure can be a T-shaped structure.
[0082] In some embodiments, step S104 may include: depositing an oxide material on the first gate structure within the first trench to form a second channel structure; and sequentially depositing a gate dielectric material and a gate metal material on the second channel structure to form a second gate dielectric layer and a second gate electrode layer, respectively.
[0083] Understandably, the channel structure of a CAA field-effect transistor can be made of oxide material. A second channel structure can be formed by depositing oxide material on top of the first gate structure within the first trench. Here, the second channel structure can cover the upper surface of the first gate structure and the trench walls of the first trench. In some embodiments, the second channel structure can also cover the upper surface of the fourth stacked structure. After forming the second channel structure, a gate dielectric material can be deposited to form a second gate dielectric layer, followed by a gate metal material to form a second gate electrode layer. Here, the second gate dielectric layer and the second gate electrode layer can constitute a second gate structure. The height of the second gate structure can be greater than the height of the fourth stacked structure.
[0084] In some embodiments, the second gate dielectric layer has a T-shaped structure and can cover the inner surface of the second channel structure and the upper surface of the fourth stacked structure. The second gate electrode layer is located above the second gate dielectric layer and has a T-shaped structure, thus the second gate structure can have a T-shaped structure.
[0085] Understandably, when the second gate structure is a T-shaped structure, the conductivity of the second gate structure can be utilized to include a second WL metal written into the transistor.
[0086] In this application, a first groove can be formed by creating a stacked structure and etching the stacked structure. Then, the channel and gate structures of the read transistor and the channel and gate structures of the write transistor can be sequentially formed within the first groove. Thus, using the first groove, a double-channel gate-surrounding field-effect transistor is self-aligned and fabricated. Furthermore, the source / drain structures in the upper field-effect transistor are in direct contact with the gate structure in the lower field-effect transistor, forming a dual-transistor-capacitor-free (2T0C) DRAM. This process further reduces the cell area of the DRAM and improves integration performance.
[0087] The following describes the fabrication method of the memory provided in this application embodiment, taking an IGZO channel CAA field-effect transistor as an example. First, the first fabrication process is introduced, namely, the IGZO channel in the read transistor exhibits the first structure. Figure 5 This is a schematic diagram of the structure of a memory according to an embodiment of this application. Figure 5 As shown in (a), the memory 10 may include a read transistor 101 and a write transistor 102. The read transistor 101 includes a first BL metal 15 and a first WL metal 16. The write transistor 102 includes a second BL metal 17 and a second WL metal 18. The AA' section is a cross-section of the memory 10 along the transistor stacking direction; the BB' section is a cross-section of the memory 10 perpendicular to the transistor stacking direction. Figure 5As shown in (b), on the AA' section, the first WL metal 16 surrounds the first channel structure 12, the first channel structure 12 surrounds the first gate dielectric layer 13, and the first gate dielectric layer 13 surrounds the first gate electrode layer 14, thereby forming a CAA field-effect transistor.
[0088] Figures 6 to 15 This is a schematic diagram of the memory structure in the first fabrication process according to an embodiment of this application. Figures 6 to 15 This is a cross-sectional view of the memory along the AA' plane.
[0089] In one example, the fabrication process of memory 10 may include the following steps:
[0090] Step 1: Sequentially deposit a first metal layer 21, a first isolation layer 22, a second metal layer 23, a first isolation structure 24, a third metal layer 25, and a second isolation layer 26 on the substrate 20 to obtain the following: Figure 6 The structure shown.
[0091] Understandably, a metal layer is deposited on the substrate 20 as the first BL metal 15 of the read transistor 101 in the memory 10, which can also be called RBL. A first isolation layer 22 is then deposited between the first BL metal and the first WL metal. Another metal layer is deposited as the first WL metal 16 of the read transistor 101 in the memory 10, which can also be called RWL. Then, a first isolation structure 24 is deposited. The first isolation structure 24 serves as the isolation layer between the first WL metal 16 and the second BL metal 17, and the thickness of the first isolation structure 24 can be greater than the thickness of the first isolation layer 22. Then, another metal layer is deposited as the second BL metal 17 of the write transistor 102 in the memory 10, which can also be called WBL. Finally, a second isolation layer 26 is deposited between the second BL metal 17 and the second WL metal 18.
[0092] The second step involves forming a hard mask structure 27 on top of the second isolation layer 26. The hard mask structure 27 is used to position the channel structure and the gate structure. Then, deep holes are photolithographically etched and etched to form the first groove 28, resulting in... Figure 7 The structure shown.
[0093] Understandably, by forming the first groove 28 through photolithography and etching, and then fabricating the channel structure of the read transistor 101 and the write transistor 102 within the first groove 28, the self-aligned stacking of the read transistor 101 and the write transistor 102 can be achieved.
[0094] Understandably, the etched first metal layer 21 forms the first BL metal 15; the etched first isolation layer 22 forms the third isolation layer 29; the etched second metal layer 23 forms the first WL metal 16; the etched first isolation structure 24 forms the second isolation structure 30; the etched third metal layer 25 forms the second BL metal 17; and the etched second isolation layer 26 forms the fourth isolation layer 31. Understandably, the first BL metal 15 includes the first source-drain structure and the first source-drain metal in the read transistor 101. The first WL metal 16 includes the second source-drain structure and the second source-drain metal in the read transistor 101. The first source-drain structure, the second source-drain structure, and the first gate structure constitute the read transistor 101. The second BL metal 17 includes the third source-drain structure and the third source-drain metal in the write transistor 102.
[0095] It should be noted that the bottom of the first groove 28 only needs to be lower than the first BL metal 15, that is, it can be etched down to the substrate 20 to obtain the desired result. Figure 8 The structure shown.
[0096] Step 3: Deposit IGZO material using the ALD process to form the initial first channel structure 32 in the readout transistor 101, resulting in... Figure 9 The structure shown.
[0097] Step 4: The initial first channel structure 32 is dry-etched to a predetermined height to form the first channel structure 12, resulting in the desired structure. Figure 10 The structure shown.
[0098] Understandably, the height of the first channel structure 12 is less than the height of the second BL metal 17 (or the second isolation structure 30) but greater than the height of the first WL metal 16.
[0099] Step 5: Deposit gate dielectric material (such as Al2O3) and gate metal material (such as IZO) using the ALD process to form the initial first gate dielectric 33 and the initial first gate electrode layer 34, resulting in... Figure 11 The structure shown.
[0100] Understandably, the initial first gate dielectric 33 and the initial first gate electrode layer 34 have a T-shaped structure.
[0101] Step 6: Using a dry etching process, etch the initial first gate dielectric 33 and the initial first gate electrode layer 34 to a predetermined height to form the first gate dielectric layer 13 and the first gate electrode layer 14, respectively. The first gate dielectric layer 13 and the first gate electrode layer 14 form the first gate structure, resulting in the following... Figure 12 The structure shown.
[0102] Understandably, the height of the first gate structure is greater than the height of the first channel structure 12. The end of the first gate structure near the write transistor includes the fourth source-drain structure and the fourth source-drain metal in the write transistor 102. The third source-drain structure, the fourth source-drain structure, and the second gate structure constitute the write transistor 102.
[0103] As can be seen, the source-drain structure in the write transistor 102 is directly connected to the first gate structure in the read transistor 101.
[0104] In some embodiments, metal can be deposited on the first gate structure and etched back to form a first metal structure 35, resulting in... Figure 13 The structure is shown. Here, the height of the first metal structure 35 is less than the height of the second BL metal 17 (or the second isolation structure 30). The thickness of the first metal structure 35 affects the capacitance at node SN.
[0105] In some embodiments, the metal material forming the first metal structure 35 may be a gate metal material.
[0106] Step 7: Remove the hard mask structure 27, deposit IGZO material using an ALD process to form the second channel structure 19 written into the transistor 102, and deposit a gate dielectric material (such as Al2O3) to form the second gate dielectric layer 110, resulting in... Figure 14 The structure shown.
[0107] Step 8: Deposit a gate metal material (such as IZO) using an ALD process to form the second gate electrode layer 111, resulting in... Figure 15 The structure shown.
[0108] Understandably, the second gate dielectric layer 110 and the second gate electrode layer 111 constitute the second gate structure.
[0109] The second fabrication process is described below, which involves reading the IGZO channel in the transistor to reveal a second structure. Figures 16 to 20 This is a schematic diagram of the memory structure in the second fabrication process according to an embodiment of this application, wherein, Figures 16 to 20 This is a cross-sectional view of the memory along the AA' plane.
[0110] In one example, the fabrication process of memory 10 may include the following steps:
[0111] Step 1: Similar to steps 1 through 3 of the first preparation process, the result is as follows. Figure 16 The structure shown.
[0112] Step 2: Deposit the dielectric material using the ALD process and etch it back to the preset height to form the first sacrificial structure 36, resulting in... Figure 17 The structure shown.
[0113] Step 3: The initial first channel structure 32 is dry-etched to a predetermined height to form the first channel structure 12, resulting in the following: Figure 18 The structure shown.
[0114] Step 4: Remove the first sacrificial structure 36 to obtain the following... Figure 19 The structure shown.
[0115] Step 5: Same as steps 5 through 8 in the first preparation process, to obtain the following... Figure 20 The structure shown.
[0116] Understandably, the embodiments of this application utilize deposition and selective etching processes to achieve self-alignment of upper and lower transistor layers. At the same time, the upper source and drain electrodes are in direct contact with the lower gate structure, eliminating the traditional photolithography alignment and SN metal layer deposition steps, thus eliminating the problems of increased area and reduced integration density caused by interlayer deviation.
[0117] Understandably, the above two preparation processes can yield the following results: Figure 5 The memory 10 shown is illustrated. In some embodiments, multiple memories 10 may form a memory array. In some embodiments, the memories 10 may be stacked in two or more layers. In some embodiments, the memory array may be stacked in two or more layers.
[0118] For example, Figure 21 This is a schematic diagram of the structure of the first type of memory array in the embodiments of this application. Figure 21 As shown, memory 10 can form a 4×4 memory array. Figure 22 for Figure 21 A schematic diagram of a cross-section of the memory array is shown. Figure 22 As shown, the feature size of the memory 10 in the memory array can be 2F×2F. In some embodiments, the memory 10 can be stacked in two or more layers, thus further reducing the feature size of the memory 10 in the memory array to 2F. 2 . Figure 23 This is a schematic diagram of the structure of the second type of memory array in an embodiment of this application. For example... Figure 23 As shown, the memory 10 can form a two-layer stacked structure. Here, the two-layer stacked structures are isolated from each other by a dielectric layer. Figure 24 This is a schematic diagram of the structure of the third type of memory array in this application embodiment. For example... Figure 24 As shown, memory 10 can form a 4×4×2 memory array.
[0119] Furthermore, the memory provided in this application embodiment can be inspected using detection and analysis instruments, such as scanning electron microscope (SEM), transmission electron microscope (TEM), and scanning transmission electron microscopy (STEM). Taking TEM as an example, this application embodiment can use TEM slicing to inspect the 2TOC DRAM, which can reveal the presence of double-layer transistors, and that the upper source / drain layer is in direct contact with the lower gate layer structure.
[0120] Secondly, embodiments of this application provide a memory fabricated using any of the fabrication methods described in the first aspect. See also Figure 15 and Figure 20 As shown, the memory 10 may include: a read transistor and a write transistor; a self-aligned stack of the read transistor and the write transistor; wherein, the read transistor includes a first channel structure 12, a first gate structure and a bottom stack structure; the write transistor includes a second channel structure 19, a second gate structure and a top stack structure; the first channel structure 12 is located between the first gate structure and the bottom stack structure; the second channel structure 19 is located between the second gate structure and the top stack structure; the height of the first channel structure 12 is less than the height of the first gate structure.
[0121] The memory also includes: a transistor isolation structure located between the bottom stacked structure and the top stacked structure; the height of the first gate structure is less than the height of the transistor isolation structure.
[0122] Understandably, the transistor isolation structure is the same as the second isolation structure in the first aspect of the fabrication method, which is formed by etching the first isolation structure 24. The bottom layer stacked structure is the same as the third stacked structure in the first aspect of the fabrication method, which is formed by etching the first stacked structure. The top layer stacked structure is the same as the fourth stacked structure in the first aspect of the fabrication method, which is formed by etching the second stacked structure.
[0123] It is understood that the specific structure of the memory can be found in the description of any embodiment of the first aspect, and will not be repeated here for the sake of brevity.
[0124] In some embodiments, the underlying stacked structure may include a first bit line BL metal in the read transistor, a first word line WL metal in the read transistor, and a first isolation layer 22 structure; wherein the first isolation layer 22 structure is located between the first BL metal and the first WL metal.
[0125] The second gate structure may include a second WL metal in the write transistor, and the top layer stack structure includes a second BL metal in the write transistor and a second isolation layer 26 structure; wherein the second isolation layer 26 structure is located between the second BL metal and the second WL metal.
[0126] Understandably, this solution achieves self-aligned vertically stacked 2T0C DRAM with a cell area as low as 4F. 2 Double-layer stacking can reach 2F 2 Breaking through traditional miniaturization limits, self-aligned via technology reduces photolithography steps, lowering manufacturing costs. It is also fully compatible with back-end assembly (BEOL) processes, supporting 3D stacking with logic circuits on a single chip, providing a technological foundation for high-bandwidth memory (HBM) and in-memory computing. IGZO low-temperature deposition (250°C) avoids thermal damage, making it suitable for flexible electronics and advanced packaging.
[0127] Thirdly, embodiments of this application provide an electronic device, including: a circuit board and a semiconductor device as described in the above embodiments, the semiconductor device being disposed on the circuit board. The semiconductor device includes the aforementioned memory.
[0128] In the description of the embodiments in this application, the terms "an embodiment," "an example," "a specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the embodiments of this application. In this application, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine different embodiments or examples described in this application, as well as features of different embodiments or examples.
[0129] The above are merely preferred embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.
Claims
1. A method for producing a memory, characterized by, The method comprises: forming a stack structure on a semiconductor substrate, wherein the stack structure comprises a first stack structure, a first isolation structure and a second stack structure stacked in sequence from bottom to top; sequentially etching the second stack structure, the first isolation structure and the first stack structure from top to bottom to form a first recess; in the first recess, sequentially forming a first channel structure and a first gate structure, wherein the first channel structure is located between the first gate structure and a third stack structure, the third stack structure being the first stack structure after etching; the height of the first channel structure is less than the height of the first gate structure, and the height of the first gate structure is less than the second isolation structure; the second isolation structure is the first isolation structure after etching; the first channel structure, the first gate structure and the third stack structure constitute a read transistor; on the first gate structure in the first recess, sequentially forming a second channel structure and a second gate structure, wherein the second channel is located between the second gate structure and a fourth stack structure, the fourth stack structure being the second stack structure after etching; the second channel structure, the second gate structure and the fourth stack structure constitute a write transistor.
2. The method of claim 1, wherein The first stack structure comprises a first metal layer, a first isolation layer and a second metal layer stacked in sequence from bottom to top; the second stack structure comprises a third metal layer and a second isolation layer stacked in sequence from bottom to top; wherein sequentially etching the second stack structure, the first isolation structure and the first stack structure from top to bottom to form the first recess comprises: sequentially etching at least part of the second isolation layer, the third metal layer, the first isolation structure, the second metal layer, the first isolation layer and the first metal layer from top to bottom to form the first recess; wherein the first metal layer after etching forms a first bit line BL metal in the read transistor, the second metal layer after etching forms a first word line WL metal in the read transistor, and the third metal layer after etching forms a second BL metal in the write transistor.
3. The method of claim 2, wherein The second gate structure comprises a second WL metal in the write transistor.
4. The method of claim 2 wherein, sequentially forming the first channel structure and the first gate structure in the first recess comprises: depositing an oxide material in the first recess to form an initial first channel structure, wherein the initial first channel structure covers the bottom of the first recess and the wall of the first recess; etching the initial first channel structure to a preset height to form the first channel structure; wherein the first channel structure covers a first part of the wall, and the first part is opposite to the first metal layer, the first isolation layer and the second metal layer; in the first recess with the first channel structure, sequentially depositing a gate dielectric material and a gate metal material to form a first gate dielectric layer and a first gate electrode layer respectively; wherein the first gate dielectric layer and the first gate electrode layer constitute the first gate structure, the height of the first gate structure is less than the height of the second isolation structure and greater than the height of the first channel structure.
5. The method of claim 2 wherein, sequentially forming the first channel structure and the first gate structure in the first recess comprises: depositing an oxide material in the first recess to form an initial first channel structure, wherein the initial first channel structure covers the bottom of the first recess and the wall of the first recess; depositing a dielectric material on the initial first channel structure to form a first sacrifice structure; etching the initial first channel structure not covered by the first sacrificial structure to form a first channel structure; wherein the first channel structure covers a first portion of the slot wall and the slot bottom, the first portion being opposite to the first metal layer, the first isolation layer and the second metal layer; removing the first sacrificial structure; depositing, in the first recess formed with the first channel structure, a gate dielectric material and a gate metal material in sequence to form a first gate dielectric layer and a first gate electrode layer, respectively; wherein the first gate dielectric layer and the first gate electrode layer form a first gate structure, the height of the first gate structure being less than the height of the second isolation structure and greater than the height of the first channel structure.
6. The method of claim 1 wherein, After the first channel structure and the first gate structure are formed in the first recess in sequence, the method further comprises: depositing a gate metal material on the first gate structure to form a first metal structure, wherein the height of the first metal structure is less than the height of the second isolation structure.
7. The method of claim 1 wherein, forming, on the first gate structure in the first recess, a second channel structure and a second gate structure in sequence, comprising: depositing an oxide material on the first gate structure in the first recess to form the second channel structure; depositing, on the second channel structure, a gate dielectric material and a gate metal material in sequence to form a second gate dielectric layer and a second gate electrode layer, respectively; wherein the second gate dielectric layer and the second gate electrode layer form a second gate structure, the height of the second gate structure being greater than the height of the fourth layer structure.
8. A memory prepared by the method according to any one of claims 1 to 7, characterized by comprising: a read transistor and a write transistor; the read transistor and the write transistor are self-aligned and stacked; wherein the read transistor comprises the first channel structure, the first gate structure and the bottom layer structure; the write transistor comprises the second channel structure, the second gate structure and the top layer structure; the first channel structure is between the first gate structure and the bottom layer structure; the second channel structure is between the second gate structure and the top layer structure; the height of the first channel structure is less than the height of the first gate structure; the memory further comprises a transistor isolation structure between the bottom layer structure and the top layer structure; the height of the first gate structure is less than the height of the transistor isolation structure.
9. The memory according to claim 8, wherein the bottom layer structure comprises a first bit line BL metal in the read transistor, a first word line WL metal in the read transistor and a first isolation layer structure; wherein the first isolation layer structure is between the first BL metal and the first WL metal; the second gate structure comprises a second WL metal in the write transistor, and the top layer structure comprises a second BL metal in the write transistor and a second isolation layer structure; wherein the second isolation layer structure is between the second BL metal and the second WL metal.
10. An electronic device, comprising: comprising: a circuit board and the memory according to claim 8 or 9, the memory being arranged on the circuit board.