C-type contact structure of two-dimensional device and preparation method and application of C-type contact structure

Abstract

The invention relates to a C-type contact structure of a two-dimensional device and a preparation method and application of the C-type contact structure. The C-type contact structure comprises a substrate (1), a gate electrode (2), a gate dielectric layer (3), a first-layer source-drain electrode (4), a two-dimensional semiconductor channel (5) and a second-layer source-drain electrode (6) which are sequentially arranged from bottom to top. And the second layer of source and drain electrode (6) and the first layer of source and drain electrode (4) are contacted and connected at the two sides of the two-dimensional semiconductor channel (5) to form C-type contact, and the two sides of the two-dimensional semiconductor channel (5) are wrapped between the second layer of source and drain electrode (6) and the first layer of source and drain electrode (4). Compared with the prior art, an upper layer of contact metal and a lower layer of contact metal (the first layer of source-drain electrode and the second layer of source-drain electrode) are designed on the contact between a channel (a two-dimensional semiconductor channel) and the source and the drain to form a C-type metal-semiconductor contact structure, so that the contact area of the two is effectively increased, and the contact resistance is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of transistor technology, in particular to a C-type contact structure of a two-dimensional device and a preparation method and application thereof. BACKGROUND

[0002] A two-dimensional transistor is a transistor device manufactured by using a two-dimensional semiconductor material with an atomic thickness.

[0003] In the development process of integrated circuits, the performance, integration density and parallel computing capability of silicon complementary metal-oxide-semiconductor transistors are usually improved by reducing the size of the transistors, and the power consumption and cost are reduced. However, as the silicon transistors approach the limit in terms of power consumption, cost and basic physics, other methods need to be considered to reduce the energy consumption of the transistors and improve the computing speed.

[0004] CN117438376A discloses a preparation method of a complementary field effect transistor based on a two-dimensional semiconductor material: cleaning a substrate; preparing a mark layer on the substrate; preparing a first channel material; preparing a first source-drain electrode on the surface of the first channel material; oxygen-doping the first channel material; depositing a first gate medium on the surface of the first source-drain electrode and the first channel material, and preparing a gate electrode on the first gate medium, thereby preparing a bottom field effect transistor; preparing a back gate, depositing a second gate medium on the bottom field effect transistor; forming a second channel material on the surface of the second gate medium; preparing a second source-drain electrode on the second channel material, thereby completing the preparation of the CFET. However, the complementary field effect transistor prepared by this method has a small working current, a large parasitic capacitance and a slow response speed. SUMMARY

[0005] The present application aims to overcome the defects of the prior art and provides a C-type contact structure of a two-dimensional device and a preparation method and application thereof. The C-type contact structure has low contact resistance and low parasitic capacitance. The upper and lower layers of contact metal (the first layer of source-drain electrode and the second layer of source-drain electrode) are designed on the contact between the channel (two-dimensional semiconductor channel) and the source and drain, forming a "C-type" metal-semiconductor contact structure, which effectively increases the contact area and reduces the contact resistance.

[0006] The object of the present application can be achieved by the following technical solutions:

[0007] The first object of the present application is to provide a C-shaped contact structure of a two-dimensional device, which comprises, from bottom to top, a substrate, a gate electrode, a gate dielectric layer, a first layer of source-drain electrodes, a two-dimensional semiconductor channel, and a second layer of source-drain electrodes; the second layer of source-drain electrodes is in contact with and connected to the first layer of source-drain electrodes on both sides of the two-dimensional semiconductor channel, forming a C-shaped contact and wrapping both sides of the two-dimensional semiconductor channel between the second layer of source-drain electrodes and the first layer of source-drain electrodes.

[0008] Further, the gate dielectric layer is connected to the substrate on both sides.

[0009] Further, the first layer of source-drain electrodes is connected to the gate dielectric layer on both sides.

[0010] Further, the two-dimensional semiconductor channel is connected to the middle of the gate dielectric layer.

[0011] Further, the on-off current ratio of the C-shaped contact structure is 1x10 4 ~ 1x10 8 .

[0012] Further, the on-state current of the C-shaped contact structure is 10~1000 muA / mu m.

[0013] The second object of the present application is to provide a preparation method of a C-shaped contact structure of a two-dimensional device, which comprises the following steps:

[0014] Step 1: Form a gate electrode region on the substrate by electron beam lithography, evaporate gate metal by using an ultrahigh vacuum electron beam evaporator, and form a gate electrode after removing the photoresist;

[0015] Step 2: Grow a gate dielectric layer on the gate electrode by using an atomic layer deposition method;

[0016] Step 3: Form a first layer of source-drain electrode region by precise overlay, evaporate first source-drain metal by using an ultrahigh vacuum electron beam evaporator, and form a first layer of source-drain electrode after removing the photoresist;

[0017] Step 4: Transfer a two-dimensional material film to the gate dielectric layer and the first layer of source-drain electrode by using a transfer method to form a two-dimensional semiconductor channel;

[0018] Step 5: Form a second layer of source-drain electrode region by precise overlay, evaporate second source-drain metal by using an ultrahigh vacuum electron beam evaporator, and form a second layer of source-drain electrode and form a C-shaped contact with the first layer of source-drain electrode after removing the photoresist.

[0019] Further, the substrate is made of one or more of silicon, silicon oxide, aluminum oxide, and other rigid substrates.

[0020] Further, the thickness of the substrate is 500-1000 microns.

[0021] Further, before step 1, the following steps are performed:

[0022] The silicon substrate is cleaned by ultrasonic cleaning in the order of acetone, isopropyl alcohol, deionized water, and then dried with a nitrogen gun for standby, to obtain the substrate.

[0023] Further, step 1 specifically includes the following process:

[0024] Spin the photoresist on the substrate, expose it by electron beam lithography, develop it by soaking in developer, and then form the gate electrode by evaporating the gate metal in vacuum using an electron beam evaporator, and then soak it to form the gate electrode.

[0025] Further, the thickness of the gate electrode is 20-100 nm.

[0026] Further, in step 1, the photoresist is PMMA photoresist.

[0027] Further, in step 1, the dose of electron beam lithography exposure is 850 mJ / cm 2 .

[0028] Further, in step 1, the developer is a mixture of methyl isobutyl ketone and isopropyl alcohol. The volume ratio of methyl isobutyl ketone to isopropyl alcohol is 3:1.

[0029] Further, in step 1, the vacuum is greater than 1x10 -8 torr.

[0030] Further, in step 1, acetone is used for soaking.

[0031] Further, in step 1, the gate metal is a high work function metal, such as gold, titanium, chromium, aluminum, platinum, etc., one or more of which.

[0032] Further, in step 2, the growth temperature of atomic layer deposition is 90-220 degrees Celsius.

[0033] Further, in step 2, the thickness of the gate dielectric layer is 5-40 nm.

[0034] Further, in step 2, the material of the gate dielectric layer is a high dielectric constant material, such as molybdenum oxide, aluminum oxide, hafnium oxide, etc., one or more of which.

[0035] Further, in step 2, the top layer of the gate dielectric layer is covered with silicon oxide to assist subsequent step 4.

[0036] Further, step 3 specifically includes the following process:

[0037] A photoresist is spin-coated on the gate dielectric layer, exposed by electron beam lithography, and developed by soaking in a developer to form a first source-drain electrode region, and a first source-drain electrode is formed by evaporation of a first source-drain metal using an electron beam evaporator under vacuum, and then soaked and peeled off.

[0038] Further, the thickness of the first source-drain electrode is 10-50 nm.

[0039] Further, in step 3, the photoresist is PMMA photoresist.

[0040] Further, in step 3, the dose of electron beam lithography exposure is 850 mJ / cm 2 .

[0041] Further, in step 3, the developer is a mixed solution of methyl isobutyl ketone and isopropyl alcohol, and the volume ratio of methyl isobutyl ketone to isopropyl alcohol is 3:1.

[0042] Further, in step 3, the vacuum is greater than 1x10 -8 .

[0043] Further, in step 3, N-methyl pyrrolidone is used for soaking.

[0044] Further, in step 3, the first source-drain metal is a metal that is in good contact with two-dimensional semiconductor materials, such as one or more of gold, bismuth, antimony, chromium, titanium, platinum, etc.

[0045] Further, in step 4, the transfer method uses PMMA stamping method, and the specific steps include: spin-coating a layer of PMMA on the surface of the two-dimensional material film, curing, then sticking a thermal release tape on the PMMA film, placing the above-mentioned material in water at room temperature until the two-dimensional material film is naturally separated from the original substrate, taking it out and sticking it on the gate dielectric layer mentioned in step 4, heating to the release temperature of the thermal release tape, then removing the thermal release tape and cleaning the PMMA with acetone.

[0046] Further, in step 4, the two-dimensional material film is a transition metal chalcogen (VIA) compound, such as one or more of monolayer molybdenum sulfide, sulfide, platinum selenide, tungsten selenide.

[0047] Further, step 5 specifically includes the following process:

[0048] A photoresist is spin-coated on the gate dielectric layer, exposed by electron beam lithography, and developed by soaking in a developer to form a first source-drain electrode region, and a first source-drain electrode is formed by evaporation of a first source-drain metal using an electron beam evaporator under vacuum, and then soaked and peeled off.

[0049] Further, the thickness of the second source-drain electrode is 10-50 nm.

[0050] Further, in step 5, the photoresist is PMMA photoresist.

[0051] Further, in step 5, the dose of the electron beam lithography exposure is 850 mJ / cm 2 .

[0052] Further, in step 5, the developer is a mixed solution of methyl isobutyl ketone and isopropyl alcohol. The volume ratio of the methyl isobutyl ketone and the isopropyl alcohol is 3:1.

[0053] Further, in step 5, the vacuum is a vacuum degree greater than 1x10 -8 .

[0054] Further, in step 5, N-methyl pyrrolidone is used for soaking.

[0055] Further, in step 5, the second source-drain metal is a metal that is in good contact with the two-dimensional semiconductor material, such as one or more of gold, bismuth, antimony, chromium, titanium, platinum, etc.

[0056] A third object of the present application is to provide an application of a C-type contact structure of a two-dimensional device, and the C-type contact structure is used for a two-dimensional transistor.

[0057] Compared with the prior art, the present application has the following beneficial effects:

[0058] 1) The C-type contact structure of a two-dimensional device, the preparation method and the application thereof provided by the technical solution effectively increase the contact area of the two-dimensional semiconductor channel and the source and the drain and reduce the contact resistance by designing upper and lower two layers of contact metals (a first layer of source-drain electrodes and a second layer of source-drain electrodes) on the contact between the channel (a two-dimensional semiconductor channel) and the source and the drain to form a “C-type” metal-semiconductor contact structure.

[0059] 2) The C-type contact structure of a two-dimensional device, the preparation method and the application thereof provided by the technical solution eliminate the Fermi level pinning effect in the metal-semiconductor contact by transferring a single layer of two-dimensional material, i.e., by forming a van der Waals contact between the two-dimensional material and the metal by a transfer method, and form an air separation between the source and the drain and the gate, which effectively reduces the parasitic capacitance between the source and the drain and the gate, effectively reduces the energy consumption of the transistor, and improves the operation speed.

[0060] 3) The C-type contact structure of a two-dimensional device, and the preparation method and application thereof, further use a single layer of a chalcogenide compound (a transition metal chalcogenide compound) as a channel material of a transistor, and the contact resistance is low, and the contact resistance is further reduced by adjusting the type of the source and drain metal in contact with the two-dimensional material. BRIEF DESCRIPTION OF DRAWINGS

[0061] Figure 1 A structural schematic diagram of a C-type contact structure of a two-dimensional device provided by an embodiment of the present application;

[0062] Figure 2 A schematic diagram of a structure prepared in step 1 in a preparation method of a C-type contact structure of a two-dimensional device provided by an embodiment of the present application;

[0063] Figure 3 A schematic diagram of a structure prepared in step 2 in a preparation method of a C-type contact structure of a two-dimensional device provided by an embodiment of the present application;

[0064] Figure 4 A schematic diagram of a structure prepared in step 3 in a preparation method of a C-type contact structure of a two-dimensional device provided by an embodiment of the present application;

[0065] Figure 5 A schematic diagram of a structure prepared in step 4 in a preparation method of a C-type contact structure of a two-dimensional device provided by an embodiment of the present application;

[0066] Figure 6 A schematic diagram of a structure prepared in step 5 in a preparation method of a C-type contact structure of a two-dimensional device provided by an embodiment of the present application;

[0067] Figure 7 A transfer curve diagram of a C-type contact structure of a two-dimensional device provided by an embodiment of the present application, wherein (a) is a transfer curve diagram of a two-dimensional semiconductor channel using a P-type two-dimensional material WSe2, and (b) is a transfer curve diagram of a two-dimensional semiconductor channel using an N-type two-dimensional material MoS2.

[0068] In the drawings:

[0069] 1 - substrate; 2 - gate electrode; 3 - gate dielectric layer; 4 - first layer of source and drain electrodes; 5 - two-dimensional semiconductor channel; 6 - second layer of source and drain electrodes. DETAILED DESCRIPTION

[0070] The present application will be described in detail below with reference to the drawings and specific embodiments. In the present technical solution, components, material names, connection structures, control methods, algorithms, and other features that are not explicitly described are considered to be common technical features disclosed in the prior art.

[0071] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0072] It should be noted that in this invention, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0073] The present invention will be further described in detail below with reference to specific embodiments.

[0074] Example 1

[0075] like Figure 1 As shown, this embodiment provides a C-type contact structure for a two-dimensional device. The C-type contact structure includes, from bottom to top, a substrate 1, a gate electrode 2, a gate dielectric layer 3, a first source / drain electrode 4, a two-dimensional semiconductor channel 5, and a second source / drain electrode 6. The second source / drain electrode 6 and the first source / drain electrode 4 are in contact and connected on both sides of the two-dimensional semiconductor channel 5 to form a C-type contact, with the two sides of the two-dimensional semiconductor channel 5 enclosing between the second source / drain electrode 6 and the first source / drain electrode 4. The two sides of the gate dielectric layer 3 are connected to the substrate 1; the first source / drain electrode 4 is connected to the two sides of the gate dielectric layer 3; and the two-dimensional semiconductor channel 5 is connected to the middle of the gate dielectric layer 3.

[0076] This embodiment also provides a method for fabricating a C-type contact structure for a two-dimensional device.

[0077] Before preparation, the raw material substrate is first cleaned and treated, including the following steps:

[0078] The silicon + silicon dioxide substrate was ultrasonically cleaned in the order of acetone, isopropanol and deionized water, and then dried with a nitrogen gun for later use, to obtain the substrate 1. The substrate thickness is 550 micrometers, and the thickness of the silicon surface oxide layer (silicon dioxide) is about 200-300 nm.

[0079] The preparation method includes the following steps:

[0080] Step 1: As Figure 2 As shown, the gate region is formed on the substrate 1 by electron beam lithography, the gate metal is deposited by ultra-high vacuum electron beam evaporation, and the gate electrode 2 is formed after resist removal. The thickness of the gate electrode 2 is 50 nm. Step 1 specifically includes the following processes:

[0081] PMMA photoresist was spin-coated onto substrate 1 and exposed by electron beam lithography (dose: 850 mJ / cm²). 2 The gate region is formed by immersion and development in a developing solution (a mixture of methyl isobutyl ketone and isopropanol, with a volume ratio of 3:1). The gate region is then subjected to vacuum (greater than 1 x 10⁻⁶). -8 The gate metal is deposited using an electron beam evaporator under the conditions of ( ) and is gold. After being soaked in acetone and stripped, the gate electrode 2 is formed.

[0082] Step 2: As Figure 3 As shown, an atomic layer deposition method is used to grow a gate dielectric layer 3 on the gate electrode 2. The growth temperature of the atomic layer deposition is 200 degrees Celsius. The material of the gate dielectric layer 3 is aluminum oxide, and the thickness of the gate dielectric layer 3 is 20 nm. The top layer of the gate dielectric layer 3 is covered with 10 nm of silicon oxide to assist in the subsequent step 4.

[0083] Step 3: As Figure 4 As shown, the first source / drain electrode region is formed by precise overlay etching. The first source / drain electrode region is located on both sides of the gate dielectric layer 3. The middle of the gate dielectric layer 3 is used to connect the two-dimensional semiconductor channel 5 in the subsequent step 4. The first source / drain electrode metal is deposited using an ultra-high vacuum electron beam evaporator. After removing the resist, the first source / drain electrode 4 is formed. Step 3 specifically includes the following processes:

[0084] PMMA photoresist was spin-coated onto the gate dielectric layer 3 and exposed by electron beam lithography (dose 850 mJ / cm²). 2 The first source / drain electrode region is formed after immersion in a developing solution (a mixed solution of methyl isobutyl ketone and isopropanol, with a volume ratio of 3:1). This is done under vacuum (greater than 1 x 10⁻⁶). -8 The first source / drain metal, palladium, is deposited using an electron beam evaporator. After being soaked and stripped with N-methylpyrrolidone, the first source / drain electrode 4 is formed with a thickness of 20 nm.

[0085] Step 4: As Figure 5 As shown, a two-dimensional material thin film (commercially available, from Shenzhen Six Carbon Technology) prepared by chemical vapor deposition is transferred from a sapphire substrate to the gate dielectric layer 3 and the first source / drain electrode 4 by a transfer method. The material of the two-dimensional material thin film is a single layer of tungsten selenide (P-type two-dimensional material WSe2), forming a two-dimensional semiconductor channel 5. The transfer method adopts the PMMA stamping method. The specific steps are as follows: spin-coating a layer of PMMA of about 200nm on the surface of the two-dimensional material thin film, curing it at 180 degrees for 2 minutes, attaching a heat-release adhesive tape (commercially available product) to the PMMA film, immersing the above material in water at room temperature until the two-dimensional material thin film naturally separates from the original substrate, removing it and attaching it to the gate dielectric layer 3 mentioned in step 4, heating it to the release temperature of the heat-release adhesive, removing the heat-release adhesive tape, and cleaning the PMMA with acetone.

[0086] Step 5: As Figure 6 As shown, the second source / drain electrode region is formed by precise overlay etching. The second source / drain electrode metal is deposited using an ultra-high vacuum electron beam evaporator. After removing the resist, the second source / drain electrode 6 is formed and forms a C-type contact with the first source / drain electrode 4. Step 5 specifically includes the following processes:

[0087] PMMA photoresist was spin-coated onto both sides of the first source / drain electrode 4 and both sides of the two-dimensional semiconductor channel 5, and then exposed by electron beam lithography (dose of 850 mJ / cm²). 2 The second source / drain electrode region is formed by immersion and development in a developing solution (a mixture of methyl isobutyl ketone and isopropanol, with a volume ratio of 3:1). This is then carried out under vacuum (greater than 1 x 10⁻⁶). -8 The second source / drain metal, palladium, is deposited using an electron beam evaporator. After being soaked and stripped with N-methylpyrrolidone, a second source / drain electrode 6 is formed, with a thickness of 30 nm.

[0088] like Figure 7 As shown, with the source and drain voltages fixed at 1V, a scan voltage of -6–+4V is applied to the gate. During this process, the device (C-type contact structure, C-type contact transistor) of this embodiment exhibits good gate control (switching current ratio 10). 6 With a higher on-state current (100μA / μm), it has an on-state current density that is 1000 times greater than that of ordinary transistor devices (two-dimensional transistors with bottom gate structure under the same process).

[0089] Example 2

[0090] like Figures 1 to 6As shown, this embodiment provides a C-type contact structure for a two-dimensional device and a method for preparing the C-type contact structure for a two-dimensional device, which is basically the same as the C-type contact structure for a two-dimensional device and the method for preparing the C-type contact structure for a two-dimensional device in Embodiment 1. The difference is that in this embodiment, the two-dimensional material film used in step 4 is a single layer of molybdenum sulfide (N-type two-dimensional material MoS2).

[0091] like Figure 7 As shown, with the source and drain voltages fixed at 1V, a scan voltage of -6–+4V is applied to the gate. During this process, the device (C-type contact structure, C-type contact transistor) of this embodiment exhibits good gate control (switching current ratio 10). 6 With a higher on-state current (100μA / μm), it has an on-state current density that is 1000 times greater than that of ordinary transistor devices (two-dimensional transistors with bottom gate structure under the same process).

[0092] Comparative Example 1

[0093] This comparative example provides a non-C-type contact transistor in a two-dimensional device. The difference between this comparative example and Example 1 is that there is no first-layer source / drain electrode 4. The fabrication method of the non-C-type contact transistor device in this comparative example is basically the same as that in Example 1. The operating current of the non-C-type contact transistor device fabricated in this comparative example is reduced by three orders of magnitude compared to the C-type contact transistor, and the switching current ratio is reduced by three orders of magnitude, which is much lower than that in Example 1.

[0094] Comparative Example 2

[0095] This comparative example provides a non-C-type contact transistor in a two-dimensional device. The difference between this comparative example and Example 2 is that there is no first-layer source / drain electrode 4. The fabrication method of the non-C-type contact transistor device in this comparative example is basically the same as that in Example 2. The operating current of the non-C-type contact transistor device fabricated in this comparative example is reduced by three orders of magnitude compared to the C-type contact transistor, and the switching current ratio is reduced by three orders of magnitude, which is much lower than that in Example 2.

[0096] The above description of the embodiments is provided to enable those skilled in the art to understand and use the invention. It will be apparent to those skilled in the art that various modifications can be made to these embodiments, and the general principles of the ammonia desulfurization tower system described herein can be applied to other embodiments without inventive effort. Therefore, the present invention is not limited to the above embodiments, and any improvements and modifications made by those skilled in the art based on the disclosure of the present invention without departing from the scope of the invention should be within the protection scope of the present invention.

Claims

1. A C-type contact structure for a two-dimensional device, characterized in that, The C-type contact structure includes, from bottom to top, a substrate (1), a gate electrode (2), a gate dielectric layer (3), a first source / drain electrode (4), a two-dimensional semiconductor channel (5), and a second source / drain electrode (6); The second layer source / drain electrode (6) and the first layer source / drain electrode (4) are in contact and connected on both sides of the two-dimensional semiconductor channel (5) to form a C-type contact, which wraps the two sides of the two-dimensional semiconductor channel (5) between the second layer source / drain electrode (6) and the first layer source / drain electrode (4).

2. The C-type contact structure of the two-dimensional device according to claim 1, characterized in that, The two sides of the gate dielectric layer (3) are connected to the substrate (1); The first source / drain electrode (4) is connected to both sides of the gate dielectric layer (3); The two-dimensional semiconductor channel (5) is connected to the gate dielectric layer (3) in the middle.

3. The C-type contact structure of the two-dimensional device according to claim 1, characterized in that, The switching current ratio of the C-type contact structure is 1×10. 4 ~1×10 8 ; The on-state current of the C-type contact structure is 10–1000 μA / μm.

4. A method for fabricating a C-type contact structure of a two-dimensional device as described in any one of claims 1-3, characterized in that, The preparation method includes the following steps: Step 1: The gate region is formed on the substrate (1) by electron beam lithography, the gate metal is deposited by ultra-high vacuum electron beam evaporation, and the gate electrode (2) is formed after the resist is removed; Step 2: A gate dielectric layer (3) is grown on the gate electrode (2) using atomic layer deposition. Step 3: The first source and drain electrode region is formed by precise overlay, and the first source and drain electrode metal is deposited by ultra-high vacuum electron beam evaporation. After removing the resist, the first source and drain electrode is formed (4). Step 4: Transfer the two-dimensional material thin film onto the gate dielectric layer (3) and the first source / drain electrode (4) by a transfer method to form a two-dimensional semiconductor channel (5); Step 5: The second source / drain electrode region is formed by precise overlay etching. The second source / drain electrode metal is deposited by ultra-high vacuum electron beam evaporation. After removing the resist, the second source / drain electrode (6) is formed and forms a C-type contact with the first source / drain electrode (4).

5. The method for fabricating the C-type contact structure of the two-dimensional device according to claim 4, characterized in that, The substrate (1) is made of one or more of silicon, silicon oxide, and aluminum oxide; Before step 1, perform the following steps: The raw material substrate was ultrasonically cleaned in the order of acetone, isopropanol and deionized water, and then dried with a nitrogen gun for later use, to obtain the substrate (1). Step 1 specifically includes the following process: Photoresist is spin-coated on substrate (1), exposed by electron beam lithography, and developed by soaking in developer to form gate region. Gate metal is deposited by electron beam evaporator under vacuum, and gate electrode (2) is formed after soaking and peeling. In step 1, the photoresist is PMMA photoresist; In step 1, the electron beam lithography exposure dose is 850 mJ / cm. 2 ; In step 1, the developing solution is a mixed solution of methyl isobutyl ketone and isopropanol; the volume ratio of methyl isobutyl ketone to isopropanol is 3:

1. In step 1, the vacuum is defined as a vacuum degree greater than 1 x 10⁻⁶. -8 Entrust; In step 1, acetone is used for soaking; In step 1, the gate metal is a high work function metal, such as one or more of gold, titanium, chromium, aluminum, and platinum.

6. The method for fabricating the C-type contact structure of the two-dimensional device according to claim 4, characterized in that, In step 2, the growth temperature for atomic layer deposition is 90–220 degrees Celsius; In step 2, the thickness of the gate dielectric layer (3) is 5-40 nm; In step 2, the material of the gate dielectric layer (3) is a high dielectric constant material, such as one or more of molybdenum oxide, aluminum oxide, and hafnium oxide; In step 2, the top layer of the gate dielectric layer (3) is covered with silicon oxide to assist in the subsequent step 4.

7. The method for fabricating the C-type contact structure of the two-dimensional device according to claim 4, characterized in that, Step 3 specifically includes the following process: Photoresist is spin-coated on the gate dielectric layer (3), exposed by electron beam lithography, and developed by soaking in developer to form the first source and drain electrode region. The first source and drain metal is deposited by electron beam evaporator under vacuum, and the first source and drain electrode (4) is formed after soaking and peeling. In step 3, the photoresist is PMMA photoresist; In step 3, the electron beam lithography exposure dose is 850 mJ / cm. 2 ; In step 3, the developing solution is a mixed solution of methyl isobutyl ketone and isopropanol; the volume ratio of methyl isobutyl ketone to isopropanol is 3:

1. In step 3, the vacuum is defined as a vacuum degree greater than 1 x 10⁻⁶. -8 Entrust; In step 3, N-methylpyrrolidone is used for soaking; In step 3, the first source / drain metal is a metal that has good contact with the two-dimensional semiconductor material, such as one or more of gold, bismuth, antimony, chromium, titanium, and platinum.

8. The method for fabricating the C-type contact structure of the two-dimensional device according to claim 4, characterized in that, In step 4, the material of the two-dimensional material film is a transition metal chalcogenide.

9. The method for fabricating the C-type contact structure of the two-dimensional device according to claim 4, characterized in that, Step 5 specifically includes the following process: Photoresist is spin-coated on both sides of the first source / drain electrode (4) and both sides of the two-dimensional semiconductor channel (5), exposed by electron beam lithography, and developed by soaking in developer to form the second source / drain electrode region. The second source / drain electrode metal is deposited by electron beam evaporation under vacuum, and the second source / drain electrode (6) is formed after soaking and peeling. In step 5, the photoresist is PMMA photoresist; In step 5, the dose of electron beam lithography exposure is 850 mJ / cm. 2 ; In step 5, the developing solution is a mixed solution of methyl isobutyl ketone and isopropanol; the volume ratio of methyl isobutyl ketone to isopropanol is 3:

1. In step 5, the vacuum is defined as a vacuum degree greater than 1 x 10⁻⁶. -8 Entrust; In step 5, N-methylpyrrolidone is used for soaking; In step 5, the second source / drain metal is a metal that has good contact with the two-dimensional semiconductor material, such as one or more of gold, bismuth, antimony, chromium, titanium, and platinum.

10. An application of a C-type contact structure for a two-dimensional device as described in any one of claims 1-3, characterized in that, The C-type contact structure is used in two-dimensional transistors.

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