Power device with composite gate dielectric layer

Abstract

The disclosure relates to a power device (100), comprising: an n-type doped silicon carbide drift layer (103); a p-type doped well (104); an n-type doped source contact (106); an n-type doped substrate (101) acting as a drain contact; and a composite gate dielectric layer (111, 112) comprising a first dielectric layer (111) contributing to a first gate threshold voltage (V1) of the power device and a second dielectric layer (112) contributing to a second gate threshold voltage (V2) of the power device which is occasionally lower than the first gate threshold voltage (V1). The first dielectric layer (111) is overlapping the n-type doped source contact (106) and a first portion of the p-type doped well (104) to enable formation of a first part of a gate electrons channel (107). The second dielectric layer (112) is arranged above the remaining portion of the p-type doped well (104) to enable formation of the remaining part of the gate electrons channel (107) and thus current conduction through the gate electrons channel (107) in case that the second gate threshold voltage (V2) reaches the first gate threshold voltage (V1).

Description

[0001] POWER DEVICE WITH COMPOSITE GATE DIELECTRIC LAYER

[0002] TECHNICAL FIELD

[0003] The disclosure relates to the field of power devices, in particular Silicon Carbide (SiC) and 4H-SiC power devices and gate dielectric layer design for such power devices. The disclosure further relates to methods for manufacturing such power devices. In particular, the disclosure relates to dual gate oxide layer 4H-SiC MOSFETs.

[0004] BACKGROUND

[0005] Silicon Carbide devices have emerged as the most viable candidate for next-generation, low-loss semiconductors due to their low ON resistance and superior high-temperature, high-frequency, and high-voltage performance, when compared to silicon. In particular, the optimization of the gate process module plays a crucial role in SiC MOSFETs to enable high performance and reliability. Gate oxide interface and bulk characteristics are determined by the oxide / dielectric deposition and post deposition annealing processes affecting interface trapped density and bulk oxide trapped charge. The detectivity correlated to the gate oxide process module has a significant impact on both electrical characteristics (channel mobility, switching, gate threshold voltage and leakage) and reliability (gate oxide breakdown, threshold voltage instabilities, hysteresis effects).

[0006] SUMMARY

[0007] This disclosure provides a solution for improving the robustness of SiC MOSFETs using deposited oxides (either silicon oxide or High K materials). In particular, a design is presented reducing the likelihood of early device turn on in case the gate threshold voltage of the deposited oxide becomes very low due to process drifts and / or use in application.

[0008] The foregoing and other objects are achieved by the features of the independent claims. Further implementation forms are apparent from the dependent claims, the description and the figures.

[0009] Embodiments of the disclosure present power devices, in particular SiC MOSFETs, with a dual gate oxide layer given by thermal silicon oxide (layer 1) and a deposited dielectric layer (either SiO2 or high K dielectric layer like HfO2, AIN, TiO2, Si3N4 etc.) (layer 2). The two layers partially overlap the P well. The layer 1 overlaps the N+ source contact and an adjacent portion of P well while the layer 2 overlaps the remaining part of the P well and the whole N doped epitaxial region between contiguous P wells. The current conduction in the MOSFET is determined by the stable gate threshold voltage of the thermal oxide layer. This avoids current conduction at low gate bias, when the deposited oxide gate threshold voltage lowers due to process drifts or in application. On the other hand, the use of the deposited oxide layer on a large fraction of the P well area can enable higher channel mobility in some embodiments with suitable process flow design not including P well thermal oxidation and higher electrons channel density and enhanced reliability in some other embodiments using high K dielectric layers, due to the lower electrical field into the same gate layers.

[0010] The solution presented in this disclosure can be applied to SiC planar MOSFETs, regardless of the voltage class and current rating. Design features and exemplar process flows will be provided with reference to planar MOSFETs. However, the concept can be extended to other MOSFET technologies, including trench MOSFETs and other semiconductor material MOSFET technologies, especially wide band gap materials, where the high semiconductor critical field strength induces very high electrical field in the dielectric gate layer, resulting critical for reliability or long-term stability. The technical solutions presented in this disclosure allow to improve the SiC MOSFET gate characteristics by enhancing ruggedness and lifetime. At the same time an improvement of the channel current density can be allowed by the use of high K dielectric layer as deposited gate layers. Furthermore, the idea presented herein can enable an improvement of the channel mobility, in particular, in embodiments where not all the channel surface is oxidized to form thermal oxide.

[0011] In order to describe the disclosure in detail, the following terms and notations will be used.

[0012] SiC Silicon Carbide

[0013] Dit Defect Interface Traps

[0014] RCH Channel Resistance

[0015] RON ON Resistance

[0016] MOSFET Metal Oxide Semiconductor Field Effect Transistor

[0017] In this disclosure, SiC devices and SiC power devices are described. Such devices have emerged as the most viable candidate for next-generation, low-loss semiconductors due to their low ON resistance and superior high-temperature, high-frequency, and high-voltage performance, when compared to silicon. SiC power devices are currently used in smart appliances in domestic and commercial buildings, servers, power supply systems, renewable energy such as electric vehicles (SiC core market), wind power and solar photovoltaic, railway transportation, power grid converters and inverters. SiC power devices electrical characteristics, quality and final costs are determined by a number of process, design and materials challenges. Addressing them is crucial to improve the performance / robustness / cost trade off in a number of use cases.

[0018] As alreadv pointed out, the optimization of the gate process module plays a crucial role in SiC MOSFETs to enable high performance and reliability. Gate oxide interface and bulk characteristics are determined by the oxide / dielectric deposition and post deposition annealing processes affecting interface trapped density and bulk oxide trapped charge. The detectivity correlated to the gate oxide process module has a significant impact on both electrical characteristics (channel mobility, switching, gate threshold voltage and leakage) and reliability (gate oxide breakdown, threshold voltage instabilities, hysteresis effects).

[0019] The channel resistance RCH accounts for about 15%-25% the overall MOSFET RON (depending on voltage class and design). Therefore, RCH reduction, heavily affected by interface trapped density, is crucial to improve the conduction current density, with obvious benefits in terms of cost reduction and miniaturization. On the other hand, due to the very high SiC electrical breakdown strength, the electrical field inside the gate oxide layer is much higher than for example in Si MOSFETs, leading, together with the higher gate oxide defect density, to higher failure risks and poor ruggedness.

[0020] The two options used for gate oxide formation in SiC MOSFETs include thermal oxides or deposited oxides, including high K materials like metallic oxides. Thermal oxides deliver high gate oxide breakdown voltage, stable and higher gate threshold voltage, low leakage and excellent electrical characteristics stability with the process. However, they show quite limited channel mobility, due to the high defect interface trapped density arising from the formation of carbon related defects at the SiC interface during the thermal oxidation process. On the other hand, deposited oxides (usually by CVD, LPCVD, PECVD, ALD) show higher channel mobility, due to the fact the SiC surface is not oxidized during the deposition process. However, the quality of the oxide material is lower leading to low gate oxide breakdown voltage, lower and unstable gate threshold voltage, high leakage, hysteresis effects and process variations impact (especially for the post deposition annealing) on gate oxide characteristics (threshold voltage and leakage). High K gate layers deposited by ALD show further advantages in terms of higher electron channel density and higher robustness owing to the lower electric field in the dielectric layer, due to the high dielectric constant. However, they show the same weaknesses of deposited oxide layers. These limitations currently limit the effective use of deposited oxides in industrial SiC MOSFETs technologies.

[0021] SiC planar MOSFET devices mostly use thermal or CVD SiO2 single layers connecting the N+ Source, P Well and N-doped JFET region (either N- drift layer or N doped current spread layer between P wells to reduce JFET resistance.

[0022] Single thermal gate oxide layers exhibit better oxide quality, compared to deposited oxides leading to enhanced ruggedness and more stable electrical characteristics showing almost negligible variation with process drifts (oxidation or POA processes) or during use in application. However, thermal oxide layers show quite high defect interface trapped density, due to the oxidation process, producing low channel mobility which has a quite consistent impact on conduction current capability, especially on low-mid voltage class devices (<1.2 kV). On the other hand, deposited oxides or high-K dielectric layers allow for higher channel mobility but show quite poor ruggedness and reliability and significant dependence of the electrical characteristics on process drifts or application environment. In particular the gate threshold voltage turns out to be quite unstable and can drift towards very low values by enabling current conduction at very low bias in single gate oxide layer MOSFET configurations. This could bring to dangerous current imbalance (early turn on) leading in turn to premature failures.

[0023] This disclosure presents a gate oxide layer configuration combining some of the best characteristics of thermal oxide layers and deposited oxide or high-K dielectric layers allowing to by-pass most of the above-mentioned limitations.

[0024] According to a first aspect, the disclosure relates to a power device, comprising: an n-type doped silicon carbide drift layer; a p-type doped well formed in the n-type doped silicon carbide drift layer; an n-type doped source contact implanted in part of the p-type doped well; an n-type doped substrate acting as a drain contact; and a composite gate dielectric layer comprising a first dielectric layer contributing to a first gate threshold voltage VI of the power device and a second dielectric layer contributing to a second gate threshold voltage V2 of the power device which is occasionally lower than the first gate threshold voltage VI; wherein the first dielectric layer is overlapping the n-type doped source contact and a first portion of the p-type doped well to enable formation of a first part of a gate electrons channel in the p-type doped well between the n-type doped source contact and the n-type doped substrate acting as the drain contact; wherein the second dielectric layer is arranged above the remaining portion of the p-type doped well to enable formation of the remaining part of the gate electrons channel and thus current conduction through the gate electrons channel in case that the second gate threshold voltage V2 reaches the first gate threshold voltage VI .

[0025] All the p-type doped well can be implanted with p type dopants. The electron channel can be formed in the p-type doped implanted layer when a positive bias is applied to the gate contact and the surface layer of the p-type doped well becomes rich of electrons (inverted region).

[0026] The current conduction in the power device is determined by the stable gate threshold voltage VI of the first dielectric layer. This avoids current conduction at low gate bias, when the second gate threshold voltage V2 lowers due to process drifts or in application. On the other hand, the use of the second dielectric layer on a large fraction of the p-type doped well area can enable higher channel mobility, higher electrons channel density and better reliability.

[0027] In an exemplary implementation of the power device, the first dielectric lay er ( 111 ) is configured to disable formation of the remaining part of the gate electrons channel (107) and thus to disable current conduction through the gate electrons channel (107) in case that the second gate threshold voltage V2 is lower than the first gate threshold voltage VI . This means, it is the first dielectric layer having higher gate threshold voltage VI which disable current conduction in case the second dielectric layer has lower threshold voltage V2. In this case only the portion of P well below the second layer would be inverted while the portion below the first layer would not be inverted, so the current cannot flow from source to drain through the channel.

[0028] In an exemplary implementation of the power device, the first dielectric layer comprises a thermal oxide dielectric layer; and the second dielectric layer comprises a deposited dielectric layer comprising of one or a combination of a deposited silicon oxide layer and a high K dielectric layer.

[0029] Thus, the composite dielectric layer can combine the benefits of both dielectric layers, i.e., stable gate threshold voltage of the first dielectric layer and high channel mobility and higher electrons channel density of the second dielectric layer.

[0030] In an exemplary implementation of the power device, the second dielectric layer is overlapping at least part of the first dielectric layer.

[0031] In this way, the first dielectric layer is connected to the second dielectric layer and both dielectric layers connect the N+ source contact and the p-type doped well.

[0032] In an exemplary implementation of the power device, the second dielectric layer is overlapping the remaining portion of the p- type doped well.

[0033] In this way, the first part of the gate electrons channel and the remaining part of the gate electrons channel can be formed and thus current can be conducted through the gate electrons channel in case that the second gate threshold voltage V2 reaches the first gate threshold voltage VI .

[0034] In an exemplary implementation of the power device, the second dielectric layer is overlapping the n-type doped silicon carbide drift layer and a part of the first dielectric layer.

[0035] In this way, the second dielectric layer connects the first dielectric layer and the n-type doped silicon carbide drift layer.

[0036] In an exemplary implementation of the power device, an overlap of the second dielectric layer over the part of the first dielectric layer is projecting to the n-type doped silicon carbide drift layer.

[0037] This configuration can reduce possible negative effects at the interface region due to the removal of the first dielectric layer by wet etch process.

[0038] In an exemplary implementation of the power device, an overlap of the first dielectric layer over the first portion of the p-type doped well is five percent or larger.

[0039] It has shown that such an overlap results in optimal results with respect to stable gate threshold voltage VI of the first dielectric layer, high channel mobility, high electrons channel density and reliability.

[0040] In an exemplary implementation of the power device, the first dielectric layer is overlapping the n-type doped silicon carbide drift layer; and the second dielectric layer is overlapping part of the first dielectric layer. This reduces possible negative impact at the interface region due to the removal of the thermal oxide by wet etching process.

[0041] In an exemplary implementation of the power device, the second dielectric layer overlaps a portion of the p-type doped well and the second dielectric layer is aligned to an inner edge of the same p-type doped well.

[0042] In this way, the second dielectric layer can be arranged adjacent to the JFET region.

[0043] In an exemplary implementation of the power device, an overlap of the second dielectric layer over the remaining portion of the p-type doped well is within the p-type doped well.

[0044] This results in less strict alignment requirements.

[0045] In an exemplary implementation of the power device, the second dielectric layer comprises an undercut at the remaining portion of the p-type doped well; and the first dielectric layer fills the undercut of the second dielectric layer.

[0046] This allows using a self-aligned process to form the thermal oxide layer, i.e., the first dielectric layer.

[0047] In an exemplary implementation of the power device, the first dielectric layer is overlapping the n-type doped source contact, the p-type doped well and the n-type doped silicon carbide drift layer; wherein the first dielectric layer transitions from a first thickness in the first portion of the p-type doped well to a second thickness in the remaining portion of the p-type doped well.

[0048] This configuration allows to reduce possible negative effects on the SiC interface produced by the total removal of the first dielectric layer in the channel region, minimizes the possible negative effects of the deposited oxide threshold voltage shift in the channel region (separation from the channel area provided by the thin thermal oxide layer) while still guarantees an improvement of the channel electron density.

[0049] In an exemplary implementation of the power device, the second dielectric layer is overlapping the first dielectric layer above the p-type doped well, above the n-type doped silicon carbide drift layer and above part of the n-type doped source contact.

[0050] In this configuration the channel region is protected by the first dielectric layer which overlaps the p-type doped well, the n- type doped silicon carbide drift layer and part of the n-type doped source contact. When producing the second dielectric layer, the first dielectric layer is not fully removed down to the channel region. Parts of the first dielectric layer remain which ensures protection of the channel region.

[0051] In an exemplary implementation of the power device, the first gate layer comprises a thicker part and a thinner part; wherein the thicker part of the first gate layer has a higher threshold voltage than a remaining part given by an overlap of the thinner part of the first gate layer and the second gate layer.

[0052] The threshold voltage of the respective layers may depend on a thickness of the layers. By designing the different thicknesses of the first gate layer the different threshold voltages can be designed in an optimal way.

[0053] According to a second aspect, the disclosure relates to a method for producing a power device, the method comprising: providing a p-type doped well formed in an n-type doped silicon carbide drift layer, an n-type doped source contact implanted in part of the p-type doped well and an n-type doped substrate acting as a drain contact; forming a first dielectric layer of a composite gate dielectric layer overlapping the n-type doped source contact and a first portion of the p-type doped well to enable formation of a first part of a gate electrons channel in the p-type doped well; forming a second dielectric layer of the composite gate dielectric layer above the remaining portion of the p-type doped well to enable formation of the remaining part of the gate electrons channel; wherein the first dielectric layer contributes to a first gate threshold voltage VI of the power device and the second dielectric layer contributes to a second gate threshold voltage V2 of the power device that is occasionally lower than the first gate threshold voltage VI such that in case that during operation of the power device the second gate threshold voltage V2 reaches the first gate threshold voltage VI, the gate electrons channel is formed and current is conducted through the gate electrons channel.

[0054] The current conduction in the power device is determined by the stable gate threshold voltage of the thermal oxide layer, i.e., the first dielectric layer. This avoids current conduction at low gate bias when the deposited oxide gate threshold voltage V2 lowers due to process drifts or in application. On the other hand, the use of the deposited oxide layer, i.e., the second dielectric layer, on a large fraction of the P well area can enable higher channel mobility in some embodiments with suitable flow design not including P well thermal oxidation and higher electrons channel density and better reliability, due to the lower electrical field into the gate layer in some other embodiments using high K dielectric layers.

[0055] In an exemplary implementation of the method, forming the first dielectric layer comprises thermal oxidation of a main surface of the power device formed by at least the p-type doped well, the n-type doped silicon carbide drift layer and the n-type doped source contact to grow the first dielectric layer; post deposition annealing the grown first dielectric layer; and patterning the grown first dielectric layer to remove the first dielectric layer from at least the remaining portion of the p-type doped well.

[0056] This allows formation of a first dielectric layer with a stable threshold voltage by thermal oxidation.

[0057] In an exemplary implementation of the method, forming the second dielectric layer comprises depositing the second dielectric layer on the patterned first dielectric layer; patterning the deposited second dielectric layer; and post deposition annealing the patterned second dielectric layer.

[0058] This allows formation of a second dielectric layer with a high channel mobility, high electrons channel density and high reliability.

[0059] BRIEF DESCRIPTION OF THE DRAWINGS

[0060] Further embodiments of the disclosure will be described with respect to the following figures, in which:

[0061] Figure 1 shows a cross section of a power device 100 according to a first embodiment;

[0062] Figure 2 shows a schematic process flow constituting a method 200 for producing a power device according to the disclosure;

[0063] Figure 3 shows a cross section of a first variant 100a and a second variant 100b of a power device according to a second embodiment;

[0064] Figure 4 shows a cross section of a power device 100c according to a third embodiment; and

[0065] Figure 5 shows a cross section of a power device lOOd according to a fourth embodiment. DETAILED DESCRIPTION OF EMBODIMENTS

[0066] In the following detailed description, reference is made to the accompanying drawings, which form a part thereof, and in which is shown by way of illustration specific aspects in which the disclosure may be practiced. It is understood that other aspects may be utilized and structural or logical changes may be made without departing from the scope of the disclosure. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the disclosure is defined by the appended claims.

[0067] It is understood that comments made in connection with a described method may also hold true for a corresponding device or system configured to perform the method and vice versa. For example, if a specific method step is described, a corresponding device may include a unit to perform the described method step, even if such unit is not explicitly described or illustrated in the figures. Further, it is understood that the features of the various exemplary aspects described herein may be combined with each other, unless specifically noted otherwise.

[0068] Figure 1 shows a cross section of a power device 100 according to a first embodiment.

[0069] The power device 100 comprises: an n-type doped silicon carbide drift layer 103; a p-type doped well 104 formed in the n-type doped silicon carbide drift layer 103; an n-type doped source contact 106 implanted in part of the p-type doped well 104; an n- type doped substrate 101 acting as a drain contact; and a composite gate dielectric layer 111, 112 comprising a first dielectric layer 111 contributing to a first gate threshold voltage VI of the power device and a second dielectric layer 112 contributing to a second gate threshold voltage V2 of the power device which is occasionally lower than the first gate threshold voltage VI .

[0070] The first dielectric layer 111 is overlapping the n-type doped source contact 106 and a first portion (denoted as x in Figure 1) of the p-type doped well 104 to enable formation of a first part (also denoted as x in Figure 1) of a gate electrons channel 107 in the p-type doped well 104 between the n-type doped source contact 106 and the n-type doped substrate 101 acting as the drain contact.

[0071] The second dielectric layer 112 is arranged above the remaining portion (marked as w-x in Figure 1) of the p-type doped well 104 to enable formation of the remaining part (also marked as w-x in Figure 1) of the gate electrons channel 107 and thus current conduction through the gate electrons channel 107 in case that the second gate threshold voltage V2 reaches the first gate threshold voltage VI .

[0072] All the p-type doped well 104 is implanted with p type dopants. The electrons channel 107 is formed in the p-type doped implanted layer when a positive bias is applied to the gate contact and the surface layer of the p-type doped well 104 becomes rich of electrons (inverted region).

[0073] Beside the layers mentioned above, the power device 100 shown in Figure 1 further comprises an SiC substrate 102 placed on top of the n-type doped substrate 101 acting as the drain contact (which metallization is not shown here). The n-type doped silicon carbide drift layer 103 is placed on top of the SiC substrate 102. A P+ contact 105 is implanted in another part of the p- type doped well 104 next to the n-type doped source contact 106. A polysilicon layer 108 is formed on top of the composite gate dielectric layer 111, 112. An intermetal dielectric 109 is covering the polysilicon layer 108 and part of the composite gate dielectric layer 111, 112. A source metal contact 110 is formed above the n-type doped source contact 106, the P+ contact 105 and the intermetal dielectric 109. The first dielectric layer 111 may be configured to disable formation of the remaining part of the gate electrons channel 107 and thus to disable current conduction through the gate electrons channel 107 in case that the second gate threshold voltage V2 is lower than the first gate threshold voltage VI .

[0074] This means, it is the first layer 111 having higher gate threshold voltage which disable current conduction in case the second layer 112 has lower threshold voltage. In this case only the portion of P well 104 below the second layer 112 would be inverted while the portion below the first layer 111 would not be inverted, so the current cannot flow from source to drain through the channel 107.

[0075] The first dielectric layer 111 may comprise a thermal oxide dielectric layer 111. The second dielectric layer 112 may comprise a deposited dielectric layer 112 comprising of one or a combination of a deposited silicon oxide layer and a high K dielectric layer.

[0076] The second dielectric layer 112 may overlap at least part of the first dielectric layer 111 as shown in Figure 1.

[0077] The second dielectric layer 112 may overlap the remaining portion of the p-type doped well 104 as shown in Figure 1.

[0078] The second dielectric layer 112 may overlap the n-type doped silicon carbide drift layer 103 and a part of the first dielectric layer 111 as shown in Figure 1.

[0079] An overlap of the second dielectric layer 112 over the part of the first dielectric layer 111 may be projecting to the n-type doped silicon carbide drift layer 103 as shown in Figure 1.

[0080] An overlap of the first dielectric layer 111 over the first portion of the p-type doped well 104 (denoted as x in Figure 1) can be 5 percent or larger, for example.

[0081] The power device 100 shown in Figure 1 can be a SiC MOSFET, for example. In this implementation, it has a dual gate oxide layer given by thermal silicon oxide (layer 1) 111 and a deposited dielectric layer (either SiO2 or high K dielectric layer like HfO2, AIN, TiO2, Si3N4 etc) (layer 2) 112. The two layers 111, 112 partially overlap the P well 104. The layer 1 overlaps the N+ source contact 106 and an adjacent portion of P well 104 while the layer 2 overlaps the remaining part of the P well 104 and the whole N doped epitaxial region 103 between contiguous P wells 104 as shown in Figure 1. With reference to Figure 1, the gate dielectric layer 1 overlap (x) with the P well 104 can be at >5% (preferably >20%) the inner portion of P well width (w) not implanted with N+ Source 106 and P+ contact 105. Moreover, the epitaxial region between contiguous P wells 104 can be implanted with an N doped current spread implant, not shown in the figure.

[0082] The P well region underneath the two different gate dielectric layers 111, 112 is inverted at different threshold voltages (VI, V2 in Figure 1). Electrons current conduction between the N+ source 106 to the N+ drain terminals 101 can occur only when both P well regions underneath the two different gate layers 111, 112 are inverted. In case the threshold voltage of the deposited gate layer, highly susceptible to variations due to process drift or application environment, shifts to a value below the stable threshold voltage of the thermal oxide layer 111, no current conduction can occur until when the gate voltage reaches the thermal oxide threshold voltage (VI), preventing in this way early turn on and current imbalance phenomena. This is due to the fact the gate layer connecting the N+ source contact 106 and P well 104 is a thermal oxide. In this embodiment a higher electrons channel density and better reliability due to the lower electrical field into the gate layer can be achieved when high K dielectric layers are used as gate dielectric layer 2. Figure 2 shows a schematic process flow constituting a method 200 for producing a power device according to the disclosure, e.g., a power device 100 as shown in Figure 1.

[0083] The method 200 comprises providing 201 a p-type doped well 104 formed in an n-type doped silicon carbide drift layer 103, an n-type doped source contact 106 implanted in part of the p-type doped well 104 and an n-type doped substrate 101 acting as a drain contact, e.g., as shown in Figure 1.

[0084] The method 200 comprises forming 201, 202 a first dielectric layer 111 of a composite gate dielectric layer 111, 112 overlapping the n-type doped source contact 106 and a first portion of the p-type doped well 104 to enable formation of a first part of a gate electrons channel 107 in the p-type doped well 104.

[0085] The method 200 comprises forming 203 a second dielectric layer 112 of the composite gate dielectric layer 111, 112 above the remaining portion of the p-type doped well 104 to enable formation of the remaining part of the gate electrons channel 107; wherein the first dielectric layer 111 contributes to a first gate threshold voltage VI of the power device and the second dielectric layer 112 contributes to a second gate threshold voltage V2 of the power device that is occasionally lower than the first gate threshold voltage VI such that in case that during operation of the power device the second gate threshold voltage V2 reaches the first gate threshold voltage VI , the gate electrons channel 107 is formed and current is conducted through the gate electrons channel 107, e.g., as described above with respect to Figure 1.

[0086] Forming 201, 202 the first dielectric layer 111 may comprise thermal oxidation of a main surface of the power device formed by at least the p-type doped well 104, the n-type doped silicon carbide drift layer 103 and the n-type doped source contact 106 to grow the first dielectric layer 111 ; post deposition annealing the grown first dielectric layer 111; and patterning the grown first dielectric layer 111 to remove the first dielectric layer 111 from at least the remaining portion of the p-type doped well 104.

[0087] Forming 203 the second dielectric layer 112 may comprise depositing the second dielectric layer 112 on the patterned first dielectric layer 111; patterning the deposited second dielectric layer 112; and post deposition annealing the patterned second dielectric layer 112.

[0088] The schematic process flow shown in Figure 2 can be applied for an integration of the dual gate oxide layer (i.e., composite gate dielectric layer 111, 112 as described above) configuration in a standard SiC planar MOSFET structure. Defining and activating all the implanted regions prior to the gate layers growth or deposition and to create contacts and metallization regions after the gate oxide process module can be performed by known methods. In this embodiment the thermal oxide 111 is grown first after an optional surface pre-conditioning treatment carried out at high temperature in H2 or Ar environment. A photomask and wet etching processes are used to remove the thermal oxide layer 111 from the central JFET region and adjacent portions of P well 104. The second gate oxide layer 112 is then deposited on the MOSFET surface and then patterned by using a photomask and a time pointed dry etching process. In this embodiment two different post deposition annealing processes are used to improve the interface characteristics by reducing the interface trapped density.

[0089] Figure 3 shows a cross section of a first variant 100a and a second variant 100b of a power device according to a second embodiment.

[0090] These two variants 100a, 100b shown in Figure 3 correspond to the power device 100 described above with respect to Figure 1 in which specific implementations of the two dielectric layers 111, 112 are applied. For both variants 100a, 100b, the first dielectric layer 111 is overlapping the n-type doped silicon carbide drift layer 103 and the second dielectric layer 112 is overlapping part of the first dielectric layer 111.

[0091] The second dielectric layer 112 is arranged on two levels, a first level that corresponds to the level of the first dielectric layer 111 and a second level above the first dielectric layer 111. In particular, the second dielectric layer 112 at the first level implements a through via or passage through the first dielectric layer 111 and the second dielectric layer 112 at the second level is embedded in the polysilicon layer 108.

[0092] For the first variant 100a, the second dielectric layer 112 overlaps a portion of the p-type doped well 104 and the second dielectric layer 112 is aligned to an inner edge of the same p-type doped well 104 as can be seen from the top picture of Figure 3.

[0093] For the second variant 100b, an overlap of the second dielectric layer 112 over the remaining portion of the p-type doped well 104 is within the p-type doped well 104.

[0094] As can be seen from Figure 3, in the second embodiment, the thermal oxide 111 (gate dielectric layer 1 ) is removed only in an inner portion of the P well 104 which can be adjacent to the JFET region (first variant 100a) or just within the P well 104 (second variant 100b) to reduce possible negative effects at the interface region due to the removal of the thermal oxide by wet etch process. As additional advantage, the second variant 100b has less stringent alignment requirements compared to the first variant 100a of the second embodiment.

[0095] Figure 4 shows a cross section of a power device 100c according to a third embodiment.

[0096] This power device according to the third embodiment 100c shown in Figure 4 corresponds to the power device 100 described above with respect to Figure 1 in which another specific implementation of the two dielectric layers 111, 112 is applied.

[0097] As can be seen from Figure 4, the second dielectric layer 112 comprises an undercut 401 at the remaining portion of the p-type doped well 104; and the first dielectric layer 111 fills the undercut 401 of the second dielectric layer 112.

[0098] As can be seen from Figure 4, in the third embodiment of the power device 100c, a self-aligned process can be used to form the thermal oxide layer (first dielectric layer 111) this time after the deposition of the SiO2 or high K dielectric layer (second dielectric layer 112). An exemplary process flow can be:

[0099] • H2 surface conditioning prior to oxide deposition;

[0100] • SiO2 / High K dielectric layer deposition (gate dielectric layer 112);

[0101] • Deposited SiO2 / High K dielectric layer patterning and dry / wet etching

[0102] • Thin Si3N4 layer deposition;

[0103] • Si3N4 spacer etch;

[0104] • Thermal oxidation to create the second dielectric layer in the SiC exposed regions

[0105] (gate dielectric layer 111);

[0106] • Si3N4 wet etch;

[0107] • Post oxidation and deposition annealing;

[0108] • Patterning and oxide layers dry / wet etching in the area outside the gate region. In this case a thin thermal oxide layer will grow on SiC surface at the intersection region below the deposited oxide layer, relieving the stress at the interface between the two oxide layers. Moreover, in this embodiment the full thermal oxidation of the whole device surface is avoided which generates defectivity due to carbon clusters formation. As a further advantage, just one post oxidation annealing treatment can be used instead of two, as reported instead for the first embodiment.

[0109] Figure 5 shows a cross section of a power device lOOd according to a fourth embodiment.

[0110] This power device according to the fourth embodiment lOOd shown in Figure 5 corresponds to the power device 100 described above with respect to Figure 1 in which another specific implementation of the two dielectric layers 111, 112 is applied.

[0111] As can be seen from Figure 5, the first dielectric layer 111 is overlapping the n-type doped source contact 106, the p-type doped well 104 and the n-type doped silicon carbide drift layer 103. The first dielectric layer 111 transitions from a first thickness in the first portion of the p-type doped well 104 to a second thickness in the remaining portion of the p-type doped well 104. The part of the first thickness can be referred to as the thicker part and the part of the second thickness can be referred to as the thinner part.

[0112] The second dielectric layer 112 is overlapping the first dielectric layer 111 above the p-type doped well 104, above the n-type doped silicon carbide drift layer 103 and above part of the n-type doped source contact 106.

[0113] As mentioned above, the first gate layer 111 may comprise a thicker part and a thinner part. The thicker part of the first gate layer 111 has a higher threshold voltage than a remaining part given by an overlap of the thinner part of the first gate layer 111 and the second gate layer 112.

[0114] As shown in Figure 5, in the fourth embodiment of the power device lOOd, the thermal oxide 111 (first gate dielectric layer) is partially removed in a central region including part of the P wells 104 and N-doped area 103 in between, while the second gate dielectric layer 112 is deposited on top of the first dielectric layer 111 and is separated from the P well 104 by a thinner and a thicker portion of the thermal oxide layer 111 in an the inner area of the P well 104 and in the P well area closer to the N+ source 106, respectively.

[0115] This configuration allows to reduce possible negative effects on the SiC interface produced by the total removal of the thermal oxide 111 in the channel region, minimizes the possible negative effects of the deposited oxide threshold voltage shift in the channel region (separation from the channel area provided by the thin thermal oxide layer) while still guarantees an improvement of the channel electron density.

[0116] In all the above-described embodiments, a double gate oxide layer (also referred herein as composite gate dielectric layer) is formed by a first thermal oxide layer connecting the N+ Source with part of the P well and a second deposited dielectric layer (either SiO2 or high K) is covering the remaining part of the P well and JFET region. The dual gate layer (or composite gate dielectric layer) configuration enables a double gate threshold voltage behavior in SiC MOSFETs. This prevents current flow at low gate bias voltage in the case the deposited layer threshold voltage shifts towards low values, due to process shifts or application environment.

[0117] While a particular feature or aspect of the disclosure may have been disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features or aspects of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms "include", "have", "with", or other variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term "comprise". Also, the terms "exemplary", "for example" and "e.g." are merely meant as an example, rather than the best or optimal. The terms “coupled” and “connected”, along with derivatives may have been used. It should be understood that these terms may have been used to indicate that two elements cooperate or interact with each other regardless whether they are in direct physical or electrical contact, or they are not in direct contact with each other.

[0118] Although specific aspects have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and / or equivalent implementations may be substituted for the specific aspects shown and described without departing from the scope of the disclosure. This application is intended to cover any adaptations or variations of the specific aspects discussed herein.

[0119] Although the elements in the following claims are recited in a particular sequence with corresponding labeling, unless the claim recitations otherwise imply a particular sequence for implementing some or all of those elements, those elements are not necessarily intended to be limited to being implemented in that particular sequence.

[0120] Many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the above teachings. Of course, those skilled in the art readily recognize that there are numerous applications of the disclosure beyond those described herein. While the disclosure has been described with reference to one or more particular embodiments, those skilled in the art recognize that many changes may be made thereto without departing from the scope of the disclosure. It is therefore to be understood that within the scope of the appended claims and their equivalents, the disclosure may be practiced otherwise than as specifically described herein.

Claims

CLAIMS1. A power device (100), comprising: an n-type doped silicon carbide drift layer (103); a p-type doped well (104) formed in the n-type doped silicon carbide drift layer (103); an n-type doped source contact (106) implanted in part of the p-type doped well (104); an n-type doped substrate (101) acting as a drain contact; and a composite gate dielectric layer (111, 112) comprising a first dielectric layer (111) contributing to a first gate threshold voltage (VI) of the power device and a second dielectric layer (112) contributing to a second gate threshold voltage (V2) of the power device which is occasionally lower than the first gate threshold voltage (VI); wherein the first dielectric layer (111) is overlapping the n-type doped source contact (106) and a first portion of the p-type doped well (104) to enable formation of a first part of a gate electrons channel (107) in the p-type doped well (104) between the n-type doped source contact (106) and the n-type doped substrate (101) acting as the drain contact; wherein the second dielectric layer (112) is arranged above the remaining portion of the p-type doped well (104) to enable formation of the remaining part of the gate electrons channel (107) and thus current conduction through the gate electrons channel (107) in case that the second gate threshold voltage (V2) reaches the first gate threshold voltage (VI).

2. The power device (100) of claim 1, wherein the first dielectric layer (111) is configured to disable formation of the remaining part of the gate electrons channel (107) and thus to disable current conduction through the gate electrons channel (107) in case that the second gate threshold voltage (V2) is lower than the first gate threshold voltage (VI).

3. The power device (100) of claim 1 or 2, wherein the first dielectric layer (111) comprises a thermal oxide dielectric layer (111); and wherein the second dielectric layer (112) comprises a deposited dielectric layer (112) comprising of one or a combination of a deposited silicon oxide layer and a high K dielectric layer.

4. The power device (100) of any of the preceding claims, wherein the second dielectric layer (112) is overlapping at least part of the first dielectric layer (111).

5. The power device (100) of any of the preceding claims, wherein the second dielectric layer (112) is overlapping the remaining portion of the p-type doped well (104).

6. The power device (100) of any of the preceding claims, wherein the second dielectric layer (112) is overlapping the n-type doped silicon carbide drift layer (103) and a part of the first dielectric layer (111).

7. The power device (100) of claim 6, wherein an overlap of the second dielectric layer (112) over the part of the first dielectric layer (111) is projecting to the n-type doped silicon carbide drift layer (103).

8. The power device (100) of any of the preceding claims, wherein an overlap of the first dielectric layer (111) over the first portion of the p-type doped well (104) is 5 percent or larger.

9. The power device (100) of any of the preceding claims, wherein the first dielectric layer (111) is overlapping the n-type doped silicon carbide drift layer (103); and wherein the second dielectric layer (112) is overlapping part of the first dielectric layer (111).

10. The power device (100) of claim 9, wherein the second dielectric layer (112) overlaps a portion of the p-type doped well (104) and the second dielectric layer (112) is aligned to an inner edge of the same p-type doped well (104).

11. The power device (100) of claim 9, wherein an overlap of the second dielectric layer (112) over the remaining portion of the p-type doped well (104) is within the p-type doped well (104).

12. The power device (100) of any of claims 1-8, wherein the second dielectric layer (112) comprises an undercut (401) at the remaining portion of the p-type doped well (104); and wherein the first dielectric layer (111) fills the undercut (401) of the second dielectric layer (112).

13. The power device (100) of any of claims 1-4, wherein the first dielectric layer (111) is overlapping the n-type doped source contact (106), the p-type doped well (104) and the n-type doped silicon carbide drift layer (103); wherein the first dielectric layer (111) transitions from a first thickness in the first portion of the p-type doped well (104) to a second thickness in the remaining portion of the p-type doped well (104).

14. The power device (100) of claim 13, wherein the second dielectric layer (112) is overlapping the first dielectric layer (111) above the p-type doped well (104), above the n-type doped silicon carbide drift layer (103) and above part of the n-type doped source contact (106).

15. The power device (100) of claim 13 or 14, wherein the first gate layer (111) comprises a thicker part and a thinner part;wherein the thicker part of the first gate lay er ( 111 ) has a higher threshold voltage than a remaining part given by an overlap of the thinner part of the first gate layer (111) and the second gate layer (112).

16. A method (200) for producing a power device (100), the method comprising: providing (201) a p-type doped well (104) formed in an n-type doped silicon carbide drift layer (103), an n-type doped source contact (106) implanted in part of the p-type doped well (104) and an n-type doped substrate (101) acting as a drain contact; forming (201, 202) a first dielectric layer (111) of a composite gate dielectric layer (111, 112) overlapping the n- type doped source contact (106) and a first portion of the p-type doped well (104) to enable formation of a first part of a gate electrons channel (107) in the p-type doped well (104); forming (203) a second dielectric layer (112) of the composite gate dielectric layer (111, 112) above the remaining portion of the p-type doped well (104) to enable formation of the remaining part of the gate electrons channel (107); wherein the first dielectric layer (111) contributes to a first gate threshold voltage (VI) of the power device and the second dielectric layer (112) contributes to a second gate threshold voltage (V2) of the power device that is occasionally lower than the first gate threshold voltage (VI ) such that in case that during operation of the power device the second gate threshold voltage (V2) reaches the first gate threshold voltage (VI), the gate electrons channel (107) is formed and current is conducted through the gate electrons channel (107).

17. The method (200) of claim 16, wherein forming (201, 202) the first dielectric layer (111) comprises thermal oxidation of a main surface of the power device formed by at least the p-type doped well (104), the n-type doped silicon carbide drift layer (103) and the n-type doped source contact (106) to grow the first dielectric layer (111); post deposition annealing the grown first dielectric layer (111); and patterning the grown first dielectric layer ( 111 ) to remove the first dielectric lay er ( 111 ) from at least the remaining portion of the p-type doped well (104).

18. The method (200) of claim 17, wherein forming (203) the second dielectric layer (112) comprises depositing the second dielectric layer (112) on the patterned first dielectric layer (111); patterning the deposited second dielectric layer (112); and post deposition annealing the patterned second dielectric layer (112).15

Images