Synchronous binoculus variable refresh rate update for VR displays

Abstract

This disclosure provides systems, devices, apparatuses, and methods, including computer programs encoded on a storage medium, for synchronous binocular variable refresh rate updates for VR displays. The display processor obtains an indication of a synchronous flush or an asynchronous flush with respect to the first DPU and / or the second DPU. The display processor determines whether a first flush operation and / or a second flush operation are available at the instance of time, wherein the first flush operation and the second flush operation are associated with the first DPU and / or the second DPU. The display processor performs the first flush operation and / or the second flush operation based on the VSync instance based on whether the first flush operation and / or the second flush operation is available at the time instance and based on an indication of a synchronous flush or an asynchronous flush.

Description

Cross-reference to related applications

[0001] This application claims the benefit of U.S. Non-Provisional Patent Application Serial No. 18 / 318,646, filed May 16, 2023, entitled “SYNCHRONIZED DUAL EYE VARIABLE REFRESH RATE UPDATEFOR VR DISPLAY”, the entire contents of which are expressly incorporated herein by reference. Technical Field

[0002] This disclosure relates generally to processing systems, and more specifically to one or more techniques for display processing. Background Technology

[0003] Computing devices typically perform graphics and / or display processing (e.g., utilizing a graphics processing unit (GPU), a central processing unit (CPU), a display processor, etc.) to render and display visual content. Such computing devices can include, for example, computer workstations, mobile phones (such as smartphones), embedded systems, personal computers, tablet computers, and video game consoles. A GPU is configured to execute a graphics processing pipeline comprising one or more processing stages that operate together to execute graphics processing commands and output frames. A CPU controls the operation of a GPU by issuing one or more graphics processing commands to it. Modern CPUs are typically capable of executing multiple applications concurrently, each of which may require the use of a GPU during execution. A display processor can be configured to convert digital information received from the CPU into analog values ​​and can issue commands to a display panel to display visual content. Devices that provide content for visual presentation on a display can utilize a CPU, GPU, and / or display processor.

[0004] Current techniques for variable refresh rate updates for virtual reality (VR) displays may not be able to resolve skew drift that can occur due to variable refresh rate updates. Improved techniques are needed to mitigate skew drift. Summary of the Invention

[0005] The following is a simplified summary of one or more aspects of the invention to provide a basic understanding of these aspects. This summary is not a broad overview of all anticipated aspects, nor is it intended to identify key or essential elements of all aspects, nor to depict the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed descriptions that follow.

[0006] In one aspect of this disclosure, a method, computer-readable medium, and apparatus for display processing are provided. The apparatus includes: a memory; and a processor coupled to the memory, and configured, based on information stored in the memory, to: obtain an indication for a synchronous flush or an indication for an asynchronous flush with respect to at least one of a first display processing unit (DPU) or a second DPU; determine whether at least one of a first flush operation or a second flush operation is available at a time instance, wherein the first flush operation and the second flush operation are associated with at least one of the first DPU or the second DPU, and wherein the first flush operation and the second flush operation are associated with an exchange of a double-buffered register configuration; and perform at least one of the first flush operation or the second flush operation based on a vertical synchronization (VSync) instance, based on whether at least one of the first flush operation or the second flush operation is available at that time instance and based on the indication for the synchronous flush or the indication for the asynchronous flush.

[0007] To achieve the foregoing and related objectives, one or more aspects include the features fully described below and specifically pointed out in the claims. The following description and drawings set forth some exemplary features of one or more aspects in detail. However, these features indicate only some of the various ways in which the principles of the various aspects may be employed, and this description is intended to include all such aspects and their equivalents. Attached Figure Description

[0008] Figure 1 This is a block diagram illustrating an example of a system for generating content based on one or more techniques of this disclosure.

[0009] Figure 2 Example GPUs based on one or more techniques according to this disclosure are illustrated.

[0010] Figure 3 An example display framework including a display processor and a display GPU is illustrated according to one or more technologies of this disclosure.

[0011] Figure 4 This is an illustration of an example configuration of a high-throughput display processing unit (DPU) according to one or more technologies of this disclosure.

[0012] Figure 5 This is a diagram illustrating an example of a low-throughput DPU configuration according to one or more techniques of this disclosure.

[0013] Figure 6 This is an illustration of an example aspect of variable refresh rate updates according to one or more technologies disclosed herein.

[0014] Figure 7This is a diagram illustrating an example of a main flush delay that results in a positive drift due to skew, according to one or more techniques of this disclosure.

[0015] Figure 8 This is a diagram illustrating an example of negative drift from scouring delay resulting in skew, according to one or more techniques of this disclosure.

[0016] Figure 9 This is an illustration of an example aspect of variable refresh rate updates with hardware synchronization according to one or more techniques of this disclosure.

[0017] Figure 10 This is an illustration of an example of a DPU according to one or more technologies of this disclosure.

[0018] Figure 11 This is a diagram illustrating an example of a main DPU according to one or more technologies of this disclosure.

[0019] Figure 12 This is a diagram illustrating an example of a DPU operating in synchronous mode according to one or more techniques of this disclosure.

[0020] Figure 13 This is a diagram illustrating an example of a main DPU operating in synchronous mode according to one or more techniques of this disclosure.

[0021] Figure 14 This is a diagram illustrating an example of a DPU operating in asynchronous mode according to one or more techniques of this disclosure.

[0022] Figure 15 This is a diagram illustrating an example of a main DPU operating in asynchronous mode according to one or more techniques of this disclosure.

[0023] Figure 16 This is a diagram illustrating an example of a DPU in a power failure state under synchronous mode according to one or more techniques of this disclosure.

[0024] Figure 17 This is a diagram illustrating an example of a master DPU in synchronous mode when the slave DPU is in a power failure state, according to one or more techniques of this disclosure.

[0025] Figure 18 This is a diagram illustrating an example of a power failure state of a DPU in asynchronous mode according to one or more techniques of this disclosure.

[0026] Figure 19 This is a diagram illustrating an example of a master DPU in asynchronous mode when the slave DPU is in a power failure state, according to one or more techniques of this disclosure.

[0027] Figure 20 This is a diagram illustrating an example of a behavioral flow associated with a flushing operation according to one or more techniques of this disclosure.

[0028] Figure 21 This is a diagram illustrating an example of flushing a synchronization timeline according to one or more techniques of this disclosure.

[0029] Figure 22 This is a diagram illustrating an example of a flush synchronization timeline where the main DPU flush is unavailable at a snapshot point, according to one or more techniques of this disclosure.

[0030] Figure 23 This is a diagram illustrating an example of a flush synchronization timeline that is unavailable at a snapshot point from a DPU flushing according to one or more techniques of this disclosure.

[0031] Figure 24 This is a diagram illustrating an example of flushing a synchronization timeline according to one or more techniques of this disclosure.

[0032] Figure 25 This is a diagram illustrating an example of flushing a synchronization timeline according to one or more techniques of this disclosure.

[0033] Figure 26 This is a diagram illustrating an example of dynamic switching between synchronous and asynchronous modes according to one or more techniques of this disclosure.

[0034] Figure 27 This is a call flowchart illustrating example communication between a DPU and a display component according to one or more technologies of this disclosure.

[0035] Figure 28 This is a flowchart illustrating an example method of processing according to one or more techniques disclosed herein.

[0036] Figure 29 This is a flowchart illustrating an example method of processing according to one or more techniques disclosed herein. Detailed Implementation

[0037] Various aspects of the systems, apparatuses, computer program products, and methods will be described more fully below with reference to the accompanying drawings. However, this disclosure may be embodied in many different forms and should not be construed as limited to any particular structure or function presented throughout this disclosure. Rather, these aspects are provided so that this disclosure will be comprehensive and complete, and will fully communicate the scope of this disclosure to those skilled in the art. Based on the teachings herein, those skilled in the art will understand that the scope of this disclosure is intended to cover any aspect of the systems, apparatuses, computer program products, and methods disclosed herein, whether implemented independently of or in combination with other aspects of this disclosure. For example, any number of aspects set forth herein may be used to implement an apparatus or practice. Furthermore, the scope of this disclosure is intended to cover such apparatuses or methods implemented using structures, functionalities, or structures and functionalities other than or different from the various aspects of the disclosure set forth herein. Any aspect disclosed herein may be embodied by one or more elements of the claims.

[0038] Although various aspects are described herein, many variations and substitutions of these aspects fall within the scope of this disclosure. While some potential benefits and advantages of the aspects of this disclosure are mentioned, the scope of this disclosure is not intended to be limited to particular benefits, uses, or objectives. Rather, the aspects of this disclosure are intended to be broadly applicable to different wireless technologies, system configurations, processing systems, networks, and transmission protocols, some of which are illustrated by way of example in the accompanying drawings and the description below. The detailed description and drawings are merely illustrative and not limiting of this disclosure, and the scope of this disclosure is defined by the appended claims and their equivalents.

[0039] Several aspects are presented with reference to various apparatuses and methods. These apparatuses and methods are described in detail below and illustrated in the accompanying drawings by various blocks, components, circuits, processes, algorithms, etc. (collectively referred to as "elements"). These elements can be implemented using electronic hardware, computer software, or any combination thereof. Whether these elements are implemented as hardware or software depends on the specific application and the design constraints imposed on the system as a whole.

[0040] By way of example, an element, any part of an element, or any combination of elements can be implemented as a “processing system” including one or more processors (which may also be referred to as processing units). Examples of processors include microprocessors, microcontrollers, graphics processing units (GPUs), general-purpose GPUs (GPGPUs), central processing units (CPUs), application processors, digital signal processors (DSPs), reduced instruction set computing (RISC) processors, system-on-a-chip (SoCs), baseband processors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic components, discrete hardware circuits, and other suitable hardware configured to perform the various functionalities described throughout this disclosure. One or more processors in the processing system can execute software. Whether referred to as software, firmware, middleware, microcode, hardware description language, or other names, software is broadly understood to mean instructions, instruction sets, code, code segments, program code, programs, subroutines, software components, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, procedures, functions, etc.

[0041] The term "application" can refer to software. As described herein, one or more technologies can refer to an application (e.g., software) configured to perform one or more functions. In such examples, the application may be stored in memory (e.g., on-chip memory of a processor, system memory, or any other memory). Hardware described herein, such as a processor, may be configured to execute the application. For example, an application may be described as including code that, when executed by the hardware, causes the hardware to perform one or more technologies described herein. As an example, the hardware may access and execute code accessed from memory to perform one or more technologies described herein. In some examples, components are identified in this disclosure. In such examples, a component may be hardware, software, or a combination thereof. Each component may be a separate component or a subcomponent of a single component.

[0042] In one or more examples described herein, the described functionality can be implemented in hardware, software, or any combination thereof. If implemented in software, the functionality can be stored or encoded as one or more instructions or code on a computer-readable medium. Computer-readable media includes computer storage media. Storage media can be any available medium accessible to a computer. By way of example, and not limitation, such computer-readable media may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable ROM (EEPROM), optical disc storage devices, magnetic disk storage devices, other magnetic storage devices, combinations of computer-readable media of the types described above, or any other medium that can be used to store computer-executable code in the form of instructions or data structures accessible to a computer.

[0043] As used herein, instances of the term "content" may refer to "graphic content," "image," etc., regardless of whether the term is used as an adjective, noun, or other part of speech. In some examples, as used herein, the term "graphic content" may refer to content produced by one or more processes in a graphics processing pipeline. In other examples, as used herein, the term "graphic content" may refer to content produced by a processing unit configured to perform graphics processing. In yet another example, as used herein, the term "graphic content" may refer to content produced by a graphics processing unit.

[0044] Display devices (e.g., virtual reality (VR) headsets) may include a first display panel and a second display panel, wherein the first display panel presents frames intended to be viewed by a user's first eye (e.g., left eye), and the second display panel presents frames intended to be viewed by a user's second eye (e.g., right eye). These frames allow the user to perceive an immersive experience when viewed through different eyes on the first and second display panels. An offset (e.g., 8.3 ms) may exist between the first and second display panels, meaning that the first frame may be displayed on the first display panel at a first time point, and the second frame may be displayed on the second display panel at a second time point. However, when perceived by the user, due to physiological reasons, the first and second frames may appear to be presented to the user concurrently, and thus, through the offset, the first and second frames may form a coherent image to the user. The display device may be configured with an offset between the display panels such that display-related activities between the display panels (e.g., panel calibration, backlight adjustment, etc.) can occur in a mutually exclusive manner. For example, such display-related activities may occur during idle periods of the display device. Without skew, two display panels can have identical instances of blank periods, and performing display-related activities can utilize up to twice the peak power of the display panels. Peak power consumption can be reduced by interleaving (i.e., skewing) the display-related activities between the two display panels. The first and / or second display panels may undergo variable refresh rate updates, where the refresh rate of the first and / or second display panels can change. Variable refresh rate updates can cause a drift (e.g., increase or decrease) in skew between the first and second display panels. For example, skew drift might be caused by latency in implementing variable refresh rate updates at one of the first or second displays. Skew drift can affect the user experience.

[0045] This document describes various techniques related to synchronized binocular variable refresh rate updates for VR displays (or another type of display, such as extended reality (XR) displays). In one example, a device (e.g., a DPU in a VR display) receives an instruction for synchronous flushing or an instruction for asynchronous flushing with respect to at least one of a first DPU or a second DPU. Synchronous flushing may refer to a flushing (i.e., a flushing operation) that occurs after (1) receiving an instruction for flushing from the software and (2) after the first DPU and the second DPU (or the first controller and the second controller of the first DPU) exchange confirmation that a flushing will be performed. Asynchronous flushing may refer to a flushing that is performed after the software receives an instruction for flushing. Asynchronous flushing may be performed independently at different DPUs (i.e., without receiving confirmation). The device determines whether at least one of the first flushing operation or the second flushing operation is available at a time instance, wherein the first flushing operation and the second flushing operation are associated with at least one of the first DPU or the second DPU, and wherein the first flushing operation and the second flushing operation are associated with an exchange of a double-buffered register configuration. The device performs at least one of the first or second flush operations based on a VSync instance, depending on whether at least one of the first or second flush operations is available at a time instance and based on an indication for synchronous flushing or an indication for asynchronous flushing. Performing at least one of the first or second flush operations may include: performing a handshake between the software associated with at least one of the first or second DPUs and the hardware associated with at least one of the first or second DPUs. Performing the handshake may cause the hardware associated with at least one of the first or second DPUs to exchange double-buffered register configurations and clear the flush flag associated with at least one of the first or second flush operations. Compared to the techniques described above, the device can eliminate or mitigate skew drift between the first and second display panels. Therefore, the techniques described above can help improve the user experience of VR displays (or other types of displays).

[0046] In VR use cases (which may involve skewing the right and left eye displays), variable refresh rate updates can cause skew drift due to asynchronous flushing. In one aspect, the master software (SW) and slave software can operate independently on their respective Vsyncs. Flushing can be independent for the SW, and internally, the hardware (HW) can synchronize flushing between DPU cores. This paper discusses the synchronous HW flushing logic. After a flush snapshot, if both DPUs have a flush available, the flush can be consumed for the upcoming Vsync. Otherwise, the flush can be omitted, and previous frames can be used. Dynamic switching between synchronous and asynchronous flushing is also discussed.

[0047] The examples described herein may relate to the use and functionality of a graphics processing unit (GPU). As used herein, a GPU can be any type of graphics processor, and a graphics processor can be any type of processor designed or configured to process graphical content. For example, a graphics processor or GPU can be a dedicated circuit designed to process graphical content. As an additional example, a graphics processor or GPU can be a general-purpose processor configured to process graphical content.

[0048] Figure 1 This is a block diagram illustrating an example content generation system 100 configured to implement one or more technologies of this disclosure. The content generation system 100 includes a device 104. Device 104 may include one or more components or circuitry for performing the various functions described herein. In some examples, one or more components of device 104 may be components of a System-on-a-Chip (SOC). Device 104 may include one or more components configured to perform one or more technologies of this disclosure. In the illustrated example, device 104 may include a processing unit 120, a content encoder / decoder 122, and a system memory 124. In some aspects, device 104 may include multiple components (e.g., a communication interface 126, a transceiver 132, a receiver 128, a transmitter 130, a display processor 127, and one or more displays 131). Display 131 may refer to one or more displays 131. For example, display 131 may include a single display or multiple displays, which may include a first display and a second display. The first display may be a left-eye display, and the second display may be a right-eye display. In some examples, the first and second displays may receive different frames for presentation on the first and second displays. In other examples, the first and second displays may receive the same frames used for rendering on both displays. In yet another example, the results of graphics processing may not be displayed on the device; for example, the first and second displays may not receive any frames used for rendering on either display. Instead, the frames or graphics processing results may be transferred to another device. In some respects, this is referred to as split rendering.

[0049] Processing unit 120 may include internal memory 121. Processing unit 120 may be configured to perform graphics processing using graphics processing pipeline 107. Content encoder / decoder 122 may include internal memory 123. In some examples, device 104 may include a processor configured to perform one or more display processing techniques on one or more frames generated by processing unit 120, and then display those frames through one or more displays 131. Although the processor in example content generation system 100 is configured as display processor 127, it should be understood that display processor 127 is one example of a processor and other types of processors, controllers, etc., may be used instead of display processor 127. Display processor 127 may be configured to perform display processing. For example, display processor 127 may be configured to perform one or more display processing techniques on one or more frames generated by processing unit 120. One or more displays 131 may be configured to display or otherwise present the frames processed by display processor 127. In some examples, one or more displays 131 may include one or more of the following: liquid crystal display (LCD), plasma display, organic light-emitting diode (OLED) display, projection display device, augmented reality display device, virtual reality display device, head-mounted display, or any other type of display device.

[0050] Memory (such as system memory 124) external to processing unit 120 and content encoder / decoder 122 may be accessible to processing unit 120 and content encoder / decoder 122. For example, processing unit 120 and content encoder / decoder 122 may be configured to read from and / or write to external memory (such as system memory 124). Processing unit 120 may be communicatively coupled to system memory 124 via a bus. In some examples, processing unit 120 and content encoder / decoder 122 may be communicatively coupled to internal memory 121 via the bus or via a different connection.

[0051] Content encoder / decoder 122 can be configured to receive graphic content from any source, such as system memory 124 and / or communication interface 126. System memory 124 can be configured to store received encoded or decoded graphic content. Content encoder / decoder 122 can be configured to receive encoded or decoded graphic content from system memory 124 and / or communication interface 126, for example, in the form of encoded pixel data. Content encoder / decoder 122 can be configured to encode or decode any graphic content.

[0052] Internal memory 121 or system memory 124 may include one or more volatile or non-volatile memories or storage devices. In some examples, internal memory 121 or system memory 124 may include RAM, static random access memory (SRAM), dynamic random access memory (DRAM), erasable programmable ROM (EPROM), EEPROM, flash memory, magnetic data media or optical storage media, or any other type of memory. According to some examples, internal memory 121 or system memory 124 may be a non-transitory storage medium. The term "non-transitory" may indicate that the storage medium is not embodied in a carrier wave or propagating signal. However, the term "non-transitory" should not be construed as meaning that internal memory 121 or system memory 124 is not removable or that its contents are static. For example, system memory 124 may be removed from device 104 and moved to another device. Alternatively, system memory 124 may not be removable from device 104.

[0053] Processing unit 120 may be a CPU, GPU, GPGPU, or any other processing unit configured to perform graphics processing. In some examples, processing unit 120 may be integrated into the motherboard of device 104. In other examples, processing unit 120 may reside on a graphics card mounted in a port on the motherboard of device 104, or may otherwise be incorporated into a peripheral device configured to interoperate with device 104. Processing unit 120 may include one or more processors, such as one or more microprocessors, GPUs, ASICs, FPGAs, arithmetic logic units (ALUs), DSPs, discrete logic components, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If the technology is partially implemented in software, processing unit 120 may store instructions for software in a suitable non-transitory computer-readable storage medium (e.g., internal memory 121) and may use one or more processors to execute instructions in hardware to perform the technology of this disclosure. Any of the foregoing (including hardware, software, combinations of hardware and software, etc.) may be considered as one or more processors.

[0054] The content encoder / decoder 122 can be any processing unit configured to perform content decoding. In some examples, the content encoder / decoder 122 may be integrated into the motherboard of device 104. The content encoder / decoder 122 may include one or more processors, such as one or more microprocessors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), video processors, discrete logic components, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If the technology is partially implemented in software, the content encoder / decoder 122 may store instructions for software in a suitable non-transitory computer-readable storage medium (e.g., internal memory 123) and may use one or more processors to execute instructions in hardware to perform the technology of this disclosure. Any of the foregoing (including hardware, software, combinations of hardware and software, etc.) can be considered as one or more processors.

[0055] In some aspects, the content generation system 100 may include a communication interface 126. The communication interface 126 may include a receiver 128 and a transmitter 130. The receiver 128 may be configured to perform any of the receiving functions described herein with respect to device 104. Additionally, the receiver 128 may be configured to receive information from another device, such as eye or head positioning information, rendering commands, and / or location information. The transmitter 130 may be configured to perform any of the transmitting functions described herein with respect to device 104. For example, the transmitter 130 may be configured to transmit information to another device, which may include a request for content. The receiver 128 and the transmitter 130 may be combined to form a transceiver 132. In such an example, the transceiver 132 may be configured to perform any of the receiving and / or transmitting functions described herein with respect to device 104.

[0056] Refer again Figure 1 In some aspects, the display processor 127 may include a refresh rate updater 198 configured to: obtain an indication for synchronous flushing or an indication for asynchronous flushing with respect to at least one of a first DPU or a second DPU; determine whether at least one of a first flushing operation or a second flushing operation is available at a time instance, wherein the first flushing operation and the second flushing operation are associated with at least one of the first DPU or the second DPU, and wherein the first flushing operation and the second flushing operation are associated with an exchange of a double-buffered register configuration; and perform at least one of the first flushing operation or the second flushing operation based on a VSync instance, based on whether at least one of the first flushing operation or the second flushing operation is available at a time instance and based on the indication for synchronous flushing or the indication for asynchronous flushing. Although the following description may focus on display processing, the concepts described herein are applicable to other similar processing techniques.

[0057] Devices such as device 104 can refer to any device, apparatus, or system configured to perform one or more of the technologies described herein. For example, a device can be a server, base station, user equipment, client device, station, access point, computer (such as a personal computer, desktop computer, laptop computer, tablet computer, computer workstation, or mainframe computer), end product, apparatus, telephone, smartphone, server, video game platform or console, handheld device (such as a portable video game device or personal digital assistant (PDA)), wearable computing device (such as a smartwatch, augmented reality device, or virtual reality device), non-wearable device, display or display device, television, set-top box, intermediate network device, digital media player, video streaming device, content streaming device, in-vehicle computer, any mobile device, any device configured to generate graphical content, or any device configured to perform one or more of the technologies described herein. The processes described herein may be described as being performed by a specific component (e.g., GPU), but in other embodiments, other components (e.g., CPU) consistent with the disclosed embodiments may be used to perform them.

[0058] A GPU can process various types of data or data packets within its pipeline. For example, in some aspects, a GPU can process two types of data or data packets, such as context register packets and draw call data. Context register packets can be a set of global state information, such as information about global registers, shaders, or constant data, which can adjust how the graphics context will be processed. For example, a context register packet may include information about the color format. In some aspects of a context register packet, there may be one or more bits indicating which workload belongs to the context register. Additionally, multiple functions or programs can run simultaneously and / or in parallel. For example, a function or program may describe an operation, such as a color mode or color format. Therefore, context registers can define various states of the GPU.

[0059] Context states can be used to determine how individual processing units (e.g., vertex extractors (VFDs), vertex shaders (VSs), shader processors, or geometry processors) operate and / or in which mode they operate. To do this, the GPU uses context registers and programming data. In some aspects, the GPU can generate workloads in the pipeline based on the context register definitions of modes or states, such as vertex or pixel workloads. Certain processing units (e.g., VFDs) can use these states to determine certain functions, such as how to aggregate vertices. Because these modes or states can change, the GPU may need to modify the corresponding context. Additionally, the workload corresponding to a mode or state may follow the changed mode or state.

[0060] Figure 2 Example GPU 200 is illustrated according to one or more technologies according to this disclosure. For example... Figure 2 As shown, GPU 200 includes a command processor (CP) 210, a draw call group 212, a VFD 220, a VS 222, a vertex cache (VPC) 224, a triangle setup engine (TSE) 226, a rasterizer (RAS) 228, a Z-process engine (ZPE) 230, a pixel interpolator (PI) 232, a fragment shader (FS) 234, a rendering backend (RB) 236, an L2 cache (UCHE) 238, and system memory 240. Although Figure 2 The GPU 200 includes processing units 220 to 238, but the GPU 200 may include multiple additional processing units. Additionally, processing units 220 to 238 are merely examples, and the GPU may use any combination or order of processing units in accordance with this disclosure. The GPU 200 also includes a command buffer 250, a context register group 260, and a context state 261.

[0061] like Figure 2 As shown, the GPU can use a CP (e.g., CP 210) or a hardware accelerator to resolve the command buffer into context register groups (e.g., context register group 260) and / or draw call data groups (e.g., draw call group 212). Subsequently, CP 210 can transfer the context register group 260 or the draw call group 212 to a processing unit or block in the GPU via a separate path. Furthermore, the command buffer 250 can alternate between different states of the context registers and draw calls. For example, the command buffer can simultaneously store the following information: the context register of context N, the draw call of context N, the context register of context N+1, and the draw call of context N+1.

[0062] GPUs can render images in a variety of different ways. In some cases, GPUs can render images using direct rendering and / or tiled rendering. In a tiled rendering GPU, an image can be divided or separated into different parts or tiles. After the image is divided, each part or tile can be rendered individually. A tiled rendering GPU can divide a computer graphics image into a grid format, so that each part of the grid (i.e., a tile) is rendered individually. In some aspects of tiled rendering, the image can be divided into different bins or tiles during binning passes. In some aspects, a visibility stream can be constructed during binning passes, where visible primitives or draw calls can be identified. A rendering pass can be performed after a binning pass. In contrast to tiled rendering, direct rendering does not divide a frame into smaller bins or tiles. Instead, in direct rendering, the entire frame is rendered at once (i.e., without binning passes). Additionally, some types of GPUs allow both tiled rendering and direct rendering (e.g., flex rendering).

[0063] In some respects, a GPU can apply the drawing or rendering process to different bins or tiles. For example, a GPU can render a bin and perform all drawing for the primitives or pixels within that bin. During the bin-based rendering process, the rendering target can be located in GPU Internal Memory (GMEM). In some instances, after rendering a bin, the contents of the rendering target can be moved to system memory, and GMEM can be freed to render the next bin. Additionally, a GPU can render another bin and perform drawing for the primitives or pixels within that bin. Thus, in some respects, there may be a small number of bins covering all the drawing on a surface, for example, four bins. Furthermore, a GPU can loop through all the drawing in a bin but perform drawing only for visible drawing calls, i.e., drawing calls that include visible geometry. In some respects, a visibility stream can be generated, for example, in binning passes, to determine the visibility information of each primitive in an image or scene. For example, such a visibility stream can identify whether a primitive is visible. In some respects, this information can be used to remove invisible primitives, such that, for example, invisible primitives are not rendered in a rendering pass. Additionally, at least some primitives that are marked as visible can be rendered in the rendering pass.

[0064] In some aspects of tile rendering, there can be multiple processing stages or passes. For example, rendering can be performed in two passes, such as a binning, visibility, or box visibility pass and a rendering or box rendering pass. During a visibility pass, the GPU can input a rendering workload, record the positions of primitives or triangles, and then determine which primitives or triangles fall into which bins or regions. In some aspects of a visibility pass, the GPU can also identify or mark the visibility of each primitive or triangle in the visibility stream. During a rendering pass, the GPU can input a visibility stream and process one bin or region at a time. In some aspects, the visibility stream can be analyzed to determine which primitives or primitive vertices are visible or invisible. Thus, visible primitives or primitive vertices can be processed. By doing so, the GPU can reduce the unnecessary workload of processing or rendering invisible primitives or triangles.

[0065] In some aspects, certain types of primitive geometry, such as localized geometry, can be processed during visibility passes. Additionally, primitives can be categorized into different bins or regions based on their localization or position. In some instances, categorizing primitives or triangles into different bins can be performed by determining visibility information for those primitives or triangles. For example, the GPU can determine the visibility information for each primitive in each bin or region or write it to, for example, system memory. This visibility information can be used to determine or generate a visibility stream. In a rendering pass, the primitives in each bin can be rendered individually. In these cases, the visibility stream can be retrieved from memory and used to remove primitives that are not visible to that bin.

[0066] Some aspects of the GPU or GPU architecture can provide multiple different options for rendering (e.g., software rendering and hardware rendering). In software rendering, the driver or CPU can process each view... Figure 1 The entire frame geometry is copied each time. Additionally, some different states can change depending on the viewpoint. Therefore, in software rendering, the software can copy the entire workload by changing some states that can be used for rendering for each viewpoint in the image. In some respects, this can lead to increased overhead because the GPU may submit the same workload multiple times for each viewpoint in the image. In hardware rendering, the hardware or GPU may be responsible for copying or processing the geometry for each viewpoint in the image. Therefore, the hardware can manage the copying or processing of primitives or triangles for each viewpoint in the image.

[0067] Figure 3 This is a block diagram 300 illustrating an example display frame including a processing unit 120, system memory 124, display processor 127, and display 131, as identified by incorporable device 104.

[0068] A GPU may be included in a device that provides content for visual presentation on a display. For example, processing unit 120 may include GPU 310 configured to render graphics data for display on a computing device (e.g., device 104), which may be a computer workstation, mobile phone, smartphone or other intelligent device, embedded system, personal computer, tablet computer, video game console, etc. The operation of GPU 310 may be controlled based on one or more graphics processing commands provided by CPU 315. CPU 315 may be configured to execute multiple applications concurrently. In some cases, each of the concurrently executing applications may utilize GPU 310 simultaneously. Processing techniques may be performed by outputting frames via processing unit 120 on a physical or wireless communication channel.

[0069] System memory 124, executable by processing unit 120, may include user space 320 and kernel space 325. User space 320 (sometimes referred to as "application space") may include software applications and / or application frameworks. For example, software applications may include operating systems, media applications, graphics applications, workspace applications, etc. Application frameworks may include frameworks used by one or more software applications, such as libraries, services (e.g., display services, input services, etc.), application programming interfaces (APIs), etc. Kernel space 325 may also include display driver 330. Display driver 330 may be configured to control display processor 127. For example, display driver 330 may cause display processor 127 to synthesize frames and send data of the frames to the display.

[0070] Display processor 127 includes display control block 335 and display interface 340. Display processor 127 can be configured to (e.g., based on input received from display driver 330) manipulate the functions of display 131. Display control block 335 can also be configured to output image frames to display 131 via display interface 340. In some examples, display control block 335 may additionally or alternatively perform post-processing of image data provided based on the processing unit 120's execution of system memory 124.

[0071] Display interface 340 can be configured to cause display 131 to display image frames. Display interface 340 can output image data to display 131 according to an interface protocol, such as, for example, MIPI DSI (Mobile Industry Processor Interface, Display Serial Interface) . That is, display 131 can be configured according to the MIPI DSI standard. The MIPI DSI standard supports video mode and command mode. In an example where display 131 operates in video mode, display processor 127 can continuously refresh the graphic content of display 131. For example, the entire graphic content can be refreshed in each refresh cycle (e.g., line by line). In an example where display 131 operates in command mode, display processor 127 can write the graphic content of a frame to buffer 350.

[0072] In some such examples, display processor 127 may not continuously refresh the graphics content of display 131. Instead, display processor 127 may use a vertical sync (Vsync) pulse to coordinate the rendering and consumption of graphics content at buffer 350. For example, when a Vsync pulse is generated, display processor 127 may output new graphics content to buffer 350. Thus, the generation of a Vsync pulse indicates that current graphics content has been rendered at buffer 350.

[0073] A frame is displayed on the monitor 131 based on the display controller 345, the display client 355, and the buffer 350. The display controller 345 can receive image data from the display interface 340 and store the received image data in the buffer 350. In some examples, the display controller 345 can output the image data stored in the buffer 350 to the display client 355. Therefore, the buffer 350 can represent local memory of the monitor 131. In some examples, the display controller 345 can directly output the image data received from the display interface 340 to the display client 355.

[0074] Display client 355 may be associated with a touch panel that senses interaction between the user and display 131. When the user interacts with display 131, one or more sensors in the touch panel may output signals to display controller 345 indicating which of the one or more sensors is active, the duration of the sensor activity, the pressure applied to the one or more sensors, etc. Display controller 345 may use the sensor outputs to determine how the user interacts with display 131. Display 131 may further be associated with / include other devices such as cameras, microphones, and / or speakers that operate in conjunction with display client 355.

[0075] Some processing techniques of device 104 may be performed through three levels (e.g., level 1: rendering level; level 2: compositing level; and level 3: display / delivery level). However, other processing techniques may combine the compositing and display / delivery levels into a single level, allowing the processing techniques to be performed based on a total of two levels (e.g., level 1: rendering level; and level 2: compositing / display / delivery level). During the rendering level, GPU 310 may process the content buffer based on the execution of the application that generates content on a pixel-by-pixel basis. During the compositing and display levels, pixel elements may be assembled to form a frame, which is then delivered to the physical display panel / subsystem (e.g., display 131) that displays the frame.

[0076] Instructions executed by the CPU (e.g., software instructions) or by the display processor can cause the CPU or display processor to search for and / or generate compositing strategies for compositing frames based on dynamic priorities and runtime statistics associated with one or more compositing strategy groups. A frame to be displayed by a physical display device (such as a display panel) may include multiple layers. Furthermore, frame compositing may be based on combining multiple layers into a frame (e.g., based on a frame buffer). After combining the multiple layers into a frame, the frame can be provided to the display panel for display on that display panel. The process of combining each of the multiple layers into a frame may be referred to as compositing, frame compositing, compositing process, compositing handling, etc.

[0077] A frame compositing process or strategy can correspond to a technique used to combine different layers from multiple layers into a single frame. Multiple layers can be stored in double data rate (DDR) memory. Each of the multiple layers can further correspond to a separate buffer. A compositor or hardware compositor (HWC) associated with a block or function determines the input to each layer / buffer and performs the frame compositing process to generate an output indicating the composite frame. That is, the input can be layers, and the output can be a frame compositing process used to synthesize the frame to be displayed on a display panel.

[0078] Some aspects of display processing can utilize different types of mask layers, such as shape masks. A mask layer is a layer that can represent a portion of a display or display panel. For example, an area of ​​the mask layer may correspond to an area of ​​the display, but the entire mask layer can depict a portion of the content actually displayed on the display or panel. For example, a mask layer may include a top and bottom portion of the display area, but the middle portion of the mask layer may be empty. In some examples, multiple mask layers may exist to represent different portions of the display area. Furthermore, for certain portions of the display area, the contents of different mask layers may overlap each other. Therefore, a mask layer can represent a portion of the display area that may or may not overlap with other mask layers.

[0079] Figure 4This is a diagram 400 illustrating an example of a high-throughput DPU configuration. GPU 402 may have a first frame 404A and a second frame 404B. The first frame 404A and the second frame 404B may be associated with user content (UC) to be displayed to a user (e.g., concurrently displayed to the user). In one example, the first frame 404A may be displayed on a first display 406A of a wearable headset 408, and the second frame 404B may be displayed on a second display 406B of the wearable headset 408. For example, the first frame 404A may be displayed to the user's left eye, and the second frame 404B may be displayed to the user's right eye. In one example, the first display 406A and the second display 406B may be embedded DisplayPort (eDP) displays. In another example, the first display 406A and the second display 406B may be part of a single display panel; that is, the first display 406A may be a first portion (e.g., the left portion) of a single display, and the second display 406B may be a second portion (e.g., the right portion) of a single display. The wearable headset 408 can be an augmented reality (AR) headset, a virtual reality (VR) headset, a mixed reality (MR) headset, and / or an extended reality (XR) headset. Therefore, the first frame 404A and the second frame 404B can be associated with augmented reality content, VR content, MR content, and / or XR content. In one example, the first frame 404A and the second frame 404B can have a resolution of 4300 × 4300 pixels.

[0080] GPU 402 can provide the first frame 404A to the first DPU 410A (in Figure 4 (marked as "DPU0"). The first DPU 410A may be included in the wearable headset 408. The first DPU 410A may divide the first frame 404A into a first slice 412A and a second slice 412A. N Slice 412B, in which N It is a positive integer greater than one. The first slice 412A and the second... N Slice 412B can be collectively referred to as "the first plurality of slices 412A-412B". In one example, each slice in the first plurality of slices 412A-412B can be a vertical slice. N In the example with 4 slices, each of the first plurality of slices 412A-412B can have a resolution of 1075×4300 pixels. N In the example with 2, each of the first plurality of slices 412A-412B can have a resolution of 2150×4300 pixels.

[0081] The first DPU 410A performs chromatic aberration correction (CAC) on each of the first plurality of slices 412A-412B. Chromatic aberration refers to the optical aberration caused by a lens's inability to focus all colors at the same point. Chromatic aberration can be observed as color fringes along the boundary separating the dark and bright parts of an image. CAC refers to the process of minimizing chromatic aberration.

[0082] The first DPU 410A can perform a scaling / DSC operation on each of the first plurality of slices 412A-412B. The scaling / DSC operation may refer to display stream compression. Display stream compression may be visual lossless compression that reduces bandwidth requirements on the DPU. The first DPU 410A can merge each of the first plurality of slices 412A-412B to generate a first processed frame 414A. The first processed frame 414A may have the same resolution as the first frame 404A (e.g., 4300×4300 pixels). The first embedded DisplayPort (eDP) controller 416 of the first DPU 410A can cause the first processed frame 414A (e.g., via an eDP interface) to be displayed on a first display 406A.

[0083] An eDP cross switch (e.g., "eDP XBAR 418") can be used with a first DPU 410A and a second DPU 410B (in... Figure 4 This is associated with a device labeled "DPU1". In one example, the eDP XBAR 418 may be part of a first DPU 410A and / or a second DPU 410B. The eDP XBAR 418 may receive instructions to display (e.g., render) the UC at a high resolution (e.g., 4300 × 4300 pixels on each of the first display 406A and the second display 406B). The eDP XBAR 418 may determine, based on these instructions, to utilize the second DPU 410B to drive the display of the second frame 404B. In one aspect, the eDP XBAR 418 may be an XBAR module that can be implemented as a multiplexer (MUX) of the eDP interface from the controller of the first DPU 410A and the eDP interface of the second DPU 410B. The eDP XBAR 418 may be software controllable. According to the example, the eDP XBAR 418 may be controlled by a display driver, display driver software, or a CPU. In one example, the first DPU 410A and the second DPU 410B can be part of a system-on-a-chip (SoC).

[0084] Based on the output of eDP XBAR 418, GPU 402 can provide the second frame 404B to the second DPU 410B. The second DPU 410B can be included in wearable headphones 408. The second DPU 410B can divide the second frame 404B into a first slice 420A and a second slice 420B.N Slice 420B, in which N It is a positive integer greater than one. The first slice 420A and the second... N Slice 420B can be collectively referred to as "the second plurality of slices 420A-420B". In one example, each slice in the second plurality of slices 420A-420B can be a vertical slice. N In the example with 4 slices, each of the second plurality of slices 420A-420B can have a resolution of 1075×4300 pixels. N In the example with 2, each of the second plurality of slices 420A-420B can have a resolution of 2150×4300 pixels.

[0085] The second DPU 410B can perform CAC on each of the second plurality of slices 420A-420B. The second DPU 410B can perform scaling / DSC operations on each of the second plurality of slices 420A-420B. The second DPU 410B can merge each of the second plurality of slices 420A-420B to generate a second processed frame 414B. The second processed frame 414B can have the same resolution as the second frame 404B (e.g., 4300×4300 pixels). The eDP controller 422 of the second DPU 410B can cause the second processed frame 414B to be displayed concurrently with the first processed frame 414A (e.g., via an eDP interface) on a second display 406B. The second eDP controller 424 of the first DPU 410A can remain inactive based on the eDP XBAR 418 to determine whether to render UC at high resolution.

[0086] Figure 5 Figure 500 illustrates an example of a low-throughput DPU configuration. In a low-throughput DPU configuration, the eDP XBAR 418 receives an instruction to display (e.g., render) the UC at a low resolution (e.g., 2048 × 2048 pixels on each of the first display 406A and the second display 406B). Based on this instruction, the eDP XBAR 418 can determine that the second eDP controller 424 of the first DPU 410A should be utilized to drive the display of the second frame 404B, while the second DPU 410B should be placed in a power-down state. The term power-down state can refer to a situation in which power is removed from the DPU (i.e., current and voltage are cut off). In one example, the power-down state could be a globally distributed switch (GDS) power-down state.

[0087] In a low-throughput DPU configuration, GPU 402 can obtain a first frame 404A and a second frame 404B. Based on the determination of eDP XBAR418, GPU 402 can provide the first frame 404A and the second frame 404B to a first DPU 410A. The first DPU 410A can divide the first frame 404A and the second frame 404B into a first plurality of slices 412A-412B and a second plurality of slices 420A-420B. In one example, each slice in the first plurality of slices 412A-412B and each slice in the second plurality of slices 420A-420B can have a resolution of 1024×2048 pixels. The first DPU 410A can perform CAC on each of the first plurality of slices 412A-412B and the second plurality of slices 420A-420B. The first DPU 410A can perform scaling / DSC operations on each of the first plurality of slices 412A-412B and each of the second plurality of slices 420A-420B. The first DPU 410A can merge each of the first plurality of slices 412A-412B to generate a first processed frame 414A. The first DPU 410A can merge each of the second plurality of slices 420A-420B to generate a second processed frame 414B.

[0088] The first eDP controller of the first DPU 410A enables the first processed frame 414A to be displayed on the first display 406A. Similarly, based on the determination of eDP XBAR 418, the second eDP controller 424 of the first DPU 410A enables the second processed frame 414B to be concurrently displayed on the second display 406B while the first processed frame 414A is displayed on the first display 406A.

[0089] Figure 6 Figure 600 illustrates an example aspect of variable refresh rate updates according to one or more technologies of this disclosure. An extended reality (XR) headset (e.g., a virtual reality (VR) headset, an augmented reality (AR) headset, or a mixed reality (MR) headset) may include a first display panel and a second display panel, wherein the first display panel may display frames intended to be viewed by a first eye (e.g., the left eye) of a user wearing the headset, and wherein the second display panel may display frames intended to be viewed by a second eye (e.g., the right eye) of a user wearing the headset. The first display panel (e.g., first display 406A) may be driven by a first DPU (e.g., first DPU 410A), and the second display panel (e.g., second display 406B) may be driven by a second DPU (e.g., second DPU 410B).

[0090] In one example, the first display panel (e.g., first display 406A) of the display device (e.g., wearable headphones 408, XR headphones, etc.) may be provided by a first DPU 602 (in Figure 6 The first DPU 602 may include a first hardware scheduler 604 (referred to as "DPU 0" in the original text). Figure 6 The first hardware scheduler 604, referred to as "HW scheduler 0", is responsible for performing actions related to the display of the schedule frame on the first display panel. The display device may include first DPU software 606 (in...). Figure 6 The first DPU software (referred to as "DPU0 SW") can communicate with the first hardware scheduler 604 to facilitate the display of frames on the first display panel. Similarly, the second display panel of the display device (e.g., the second display 406B) can be controlled by the second DPU 608 (in... Figure 6 The second DPU 608 may include a second hardware scheduler 610 (referred to as "DPU 1" in the original text). Figure 6 The second hardware scheduler 610, referred to as "HW scheduler 1", is responsible for performing actions related to the display of the schedule frame on the second display panel. The display device may include second DPU software 612 (in...). Figure 6 The second DPU software (referred to as "DPU1 SW") can communicate with the second hardware scheduler 610 to facilitate the display of frames on the second display panel. The first DPU software 606 and the second DPU software 612 can be synchronized with each other to facilitate the presentation of frames on the first and second display panels. For example, by synchronizing with each other, the first DPU software 606 and the second DPU software 612 can help ensure that the first frame is displayed on the first display panel and the second frame is displayed on the second display panel, so that the first and second frames form a coherent image to the user. In one example, the first frame may display the left half of an object at a point in time, and the second frame may display the right half of the object at that point in time. Through synchronization, the user can simultaneously perceive the left half (via the left eye) and the right half (via the right eye) of the object.

[0091] A display device can present frames with an offset between a first display panel and a second display panel. That is, a first frame can be displayed on the first display panel at a first time point, and a second frame can be displayed on the second display panel at a second time point. However, when perceived by a user, due to physiological reasons, the first and second frames may appear to be presented to the user concurrently, and therefore, through the offset, the first and second frames can form a coherent image to the user. The display device can be configured with an offset between the display panels such that display-related activities between the display panels (e.g., panel calibration, backlight adjustment, etc.) can occur in a mutually exclusive manner. For example, such display-related activities can occur during the blank periods of the display device. Without the offset, the two display panels may have the same instance of blank periods, and performing display-related activities can utilize up to twice the peak power of the display panels. By interleaving (i.e., offsetting) the display-related activities between the two display panels, peak power consumption can be reduced. In one example, if there is an 8.3 ms offset between the first and second display panels, the first display panel can display the first frame, and the second display panel can display the second frame corresponding to the first frame 8.3 ms after displaying the first frame.

[0092] The display device can present frames at different frame rates on a first display panel and a second display panel. For example, the display panels can present frames at 60 frames per second (FPS) on both the first and second display panels, or at 45 FPS on both the first and second display panels, and so on. The display device can synchronize the frame rate of the content with the refresh rate of the display panels (via a vertical synchronization process, which may be referred to as vsync, Vsync, VSync, or VSYNC). For example, the content may be available at 60 FPS, and the first and second display panels may have a refresh rate of 95 Hz. Through Vsync, the refresh rate of the first and second display panels can be set to 60 Hz to match the 60 FPS content.

[0093] Additionally, when skew is present and Vsync is enabled, the frame rate / refresh rate can (temporarily) vary between the first and second display panels. In one example, skew (e.g., 8.3ms) may exist between the first and second display panels. The first display panel may display content at 60 FPS (60Hz), and the second display panel may also display content at 60 FPS (60Hz). Variable refresh rate updates may occur, causing the frame rate / refresh rate to update from 60 FPS (60Hz) to 45 FPS (45Hz). Due to the skew, there may be a period of time (e.g., an 8.3ms skew) during which the first display panel displays content at 60 FPS (60Hz) and the second display panel displays content at 45 FPS (45Hz). After this period has elapsed, the first display panel may be updated to display content at 45 FPS (45Hz), resulting in both the first and second display panels displaying content at 45 FPS (45Hz).

[0094] Variable refresh rate updates can be performed via software synchronization (e.g., between the first DPU software 606 and the second DPU software 612). Variable refresh rate updates synchronized via software may not be deterministic and may therefore cause skew drift between the first and second display panels. For example, a delay in the refresh rate update of the DPU core of the first DPU 602 or the second DPU 608 can cause skew drift. If the skew drift exceeds (or falls below) the expected skew (e.g., 8.3ms), it may affect the user experience.

[0095] In one example, a first DPU 602 may display content at 60 FPS on a first display panel, and a second DPU 608 may display content at 60 FPS on a second display panel, wherein a first offset 614 (e.g., 8.3 ms) may exist between the first and second display panels. Variable refresh rate updates (when Vsync is enabled) may occur, changing the frame rate from 60 FPS to 45 FPS. However, the latency of the refresh rate update of the first DPU 602 may cause the first offset 614 to drift to a second offset 616 (e.g., greater than or less than 8.3 ms). The second offset 616 may affect the user experience.

[0096] Figure 7Figure 700 illustrates an example of a main flush delay causing positive drift according to one or more techniques of this disclosure. As discussed above, a display device (e.g., a VR headset) may skew the display of frames between the left and right display panels of the display device. In one example, the skew may be 8.3 ms. However, when a variable refresh rate update occurs, the skew may drift due to asynchronous flushing. In one example, flushing may be a handshake between software (e.g., first DPU software 606, second DPU software 612) and hardware (e.g., first DPU 602, second DPU 608) for exchanging double-buffered register configurations. Flushing may be associated with a programmable register that the software sets as a final flag to exchange register configurations. On the next Vsync, the hardware may exchange double-buffered register configurations and automatically clear the flush flag associated with the flush. Flushing may also be referred to as a flush operation. Double buffering may refer to using two buffers to hold data to increase processing speed. In the example of double buffering, a first frame configuration can be written to a first buffer, while the hardware processes a second frame configuration using a second buffer. When a swap occurs, the first frame configuration can be written to the second buffer, and a new frame configuration can be written to the first buffer. A flush can be available when the programmable registers associated with the flush are fully configured to enable the swapping of register configurations. Figure 700 illustrates a master flush (i.e., a flush performed by the master DPU) that results in a positive drift (i.e., an increase) causing skew. A flush operation can refer to performing a handshake between software (e.g., first DPU software 606, second DPU software 612) and hardware (e.g., first DPU 602, second DPU 608) to swap double-buffered register configurations. Performing a flush operation can refer to performing a handshake between software (e.g., first DPU software 606, second DPU software 612) and hardware (e.g., first DPU 602, second DPU 608) to swap double-buffered register configurations, and performing additional processing to facilitate the handshake. Performing a flushing operation may include consuming the flushing process.

[0097] In one example, at 702, the new frame could begin several lines before Vsync in the DPU0 panel reaches 704. More specifically, prefetching (in...) Figure 7 The process referred to as "DPU0 Programmable Extraction / Mobile Display Processor (MDP) VSYNC" can occur at 702. However, the flushing of frame N 706a may not be available at 702; that is, at 702, the software may still configure the registers for frame N 706a at 702, where frame N 706a will be displayed in conjunction with the first DPU (in... Figure 7The first display panel associated with the first DPU (referred to as "DPU0") is shown at 702. At 702, a fencing is available for frame N 706a. Fencing availability indicates that the CPU and / or GPU have completed processing operations on the frame for display. Since flushing is unavailable at 702 regarding frame N 706a, frame N-1 (i.e., the previously displayed frame) can be passed to the first display panel associated with the first DPU at Vsync occurrence 704 on the DPU0 panel. However, flushing regarding frame N 706b can be available at the pre-fetch location occurring at 710, where frame N 706b will be displayed on the first display panel associated with the second DPU (in...). Figure 7 This is done on the second display panel associated with the second DPU (referred to as "DPU1" in the original text). Therefore, frame 706b can be passed to the second display panel associated with the second DPU at point Vsync 712 on the DPU1 panel. Passing frame 708a to the first display panel and frame 706b to the second display panel can cause a positive skew drift, meaning the skew can increase from 8.3ms to a value greater than 8.3ms. As noted above, this skew drift can affect the user experience.

[0098] Figure 8 Figure 800 illustrates an example of a negative drift from a flush delay resulting in skew, according to one or more techniques of this disclosure. In one example, at 802, a new frame may begin several rows before the DPU1 panel Vsync occurs at 804. More specifically, pre-fetching (in...) Figure 7 The process, referred to as "DPU1 Programmable Extraction / MDP VSYNC", can occur at 802. However, the flushing of frame N 806b may not be available at 802; that is, at 802, the software may still be configuring registers for frame N 806b, where frame N 806b will be displayed in conjunction with the second DPU (in... Figure 8 The second display panel associated with the second DPU (referred to as "DPU1") is shown at 802. At 802, the fencing is available for frame N 806b. Since the flushing is unavailable at 802 regarding frame N 806b, frame N-1 (i.e., the previously displayed frame) can be passed to the second display panel associated with the second DPU at Vsync occurrence 804 on the DPU1 panel. However, the flushing regarding frame N 806a can be available at the pre-fetch location occurring at 810, where frame N 806a will be displayed on the second display panel associated with the first DPU (in...). Figure 8The first display panel associated with the first DPU (referred to as "DPU0") is used for this purpose. Therefore, frame 806a (Nth frame) can be transmitted to the first display panel associated with the first DPU at point Vsync 812 on the DPU0 panel. Transmitting frame 806a to the first display panel and transmitting frame 808b (N-1th frame) to the second display panel results in a negative drift due to skew; that is, the skew can be reduced from 8.3ms to a value less than 8.3ms. As noted above, this skew drift can affect the user experience.

[0099] Figure 9 Figure 900 illustrates an example aspect of variable refresh rate updates with hardware synchronization according to one or more technologies of this disclosure. An extended reality (XR) headset (e.g., a virtual reality (VR) headset, an augmented reality (AR) headset, or a mixed reality (MR) headset) may include a first display panel and a second display panel, wherein the first display panel may display frames intended to be viewed by a first eye (e.g., the left eye) of a user wearing the headset, and wherein the second display panel may display frames intended to be viewed by a second eye (e.g., the right eye) of a user wearing the headset. The first display panel (e.g., first display 406A) may be driven by a first DPU (e.g., first DPU 410A), and the second display panel (e.g., second display 406B) may be driven by a second DPU (e.g., second DPU 410B).

[0100] In one example, the first display panel (e.g., first display 406A) of the display device (e.g., wearable headphones 408, XR headphones, etc.) may be provided by a first DPU 902 (in Figure 9 The first DPU 902 may include a first hardware scheduler 904 (referred to as "DPU 0" in the original text). Figure 9 The first hardware scheduler 904, referred to as "HW scheduler 0", is responsible for performing actions related to the display of the schedule frame on the first display panel. The display device may include first DPU software 906 (in...). Figure 9 The first DPU software (referred to as "DPU0 SW") can communicate with the first hardware scheduler 904 to facilitate the display of frames on the first display panel. Similarly, the second display panel of the display device (e.g., the second display 406B) can be controlled by the second DPU 908 (in... Figure 9 The second DPU 908 may include a second hardware scheduler 910 (referred to as "DPU 1" in the original text). Figure 9 The second hardware scheduler 910, referred to as "HW scheduler 1", is responsible for performing actions related to the display of the schedule frame on the second display panel. The display device may include a second DPU software 912 (in...). Figure 9The second DPU software (referred to as "DPU1 SW") can communicate with the second hardware scheduler 910 to facilitate the display of frames on the second display panel. The first hardware scheduler 904 and the second hardware scheduler 910 can synchronize with each other to facilitate the presentation of frames on the first and second display panels. For example, by synchronizing with each other, the first hardware scheduler 904 and the second hardware scheduler 910 can help ensure that the first frame is displayed on the first display panel and the second frame is displayed on the second display panel, so that the first and second frames form a coherent image to the user. In one example, the first frame may display the left half of an object at a certain point in time, and the second frame may display the right half of the object at that point in time. Through synchronization, the user can simultaneously see the left half (via the left eye) and the right half (via the right eye) of the object. Unlike software synchronization, hardware synchronization allows both the first and second display panels to switch to a new refresh rate simultaneously. Hardware synchronization between the first hardware scheduler 904 and the second hardware scheduler 910 can prevent or mitigate the drift of skew 914, meaning that the value of skew 914 can remain constant when a variable refresh rate update occurs.

[0101] This document discloses various techniques related to synchronized dual-eye variable refresh rate updates for VR displays. In one aspect, the master software (SW) and slave SW can operate independently on their respective vertical synchronizations (VSync). Flushing can be independent for both the master and slave SWs, and internal hardware can synchronize flushing between the master and slave DPU cores, where flushing can be a handshake between the SW and the hardware (HW) for exchanging double-buffered register configurations. Flushing can be associated with a programmable register that the SW can set as a final flag to exchange register configurations, and on the next VSync, the HW can exchange the double-buffered register configurations and automatically clear the flush flag. In another aspect, synchronized flushing for variable refresh rate (VRR) updates with a tilted display can occur. Synchronization can be supported between two DPU cores or between two operations within the same DPU. As used herein, the term "operation" (which may be abbreviated as OP0, OP1, etc.) can refer to fetching data from the buffer, processing data, and providing data to the display panel. In other words, synchronization can be supported between OP0 (i.e., the controller of the DPU core) or between OP0 and OP1 (i.e., the controller) of the same DPU core. Synchronization can introduce a 1-frame delay based on the time instance of the flush occurrence. In one aspect, asynchronous flushing can be used for other latency-sensitive use cases. In another aspect, dynamic switching between asynchronous and synchronous flushing can occur.

[0102] Figure 10 Figure 1000 is an example of a DPU 1002 according to one or more technologies of this disclosure. Figure 11Figure 1100 illustrates an example of a master DPU 1102 according to one or more technologies of this disclosure. The slave DPU 1002 and the master DPU 1102 can communicate with each other to facilitate the display of frames on a first display panel and a second display panel. In one example, the slave DPU 1002 may be or include a second DPU 410B or a second DPU 908. In one example, the master DPU 1102 may be or include a first DPU 410A or a first DPU 902. In some configurations, the roles of the slave DPU 1002 and the master DPU 1102 may be reversed; that is, the slave DPU 1002 may become the master DPU, and the master DPU 1102 may become the slave DPU.

[0103] For reference Figure 10 The DPU 1002 may include an MDP scheduler 1004 and a timing engine generator 1006 (in Figure 10 This is referred to as DISP INTF (DSI0) in the code. The timing engine generator 1006 can be configured to generate timing (e.g., Vsync pulses). The timing engine generator 1006 can also be configured to generate flush snapshot pulses 1008 (in... Figure 10 This is referred to as "FLUSH_SNAPSHOT_PULSE" in the code. The flush snapshot pulse 1008 can be defined as a pulse with a software-configurable duration that occurs before the Vsync instance. The flush snapshot pulse 1008 can also occur before pre-fetching (i.e., before DPU1 programmable fetching / MDPVSync).

[0104] MDP scheduler 1004 may be or include a second hardware scheduler 910. MDP scheduler 1004 may include a first operation controller 1010 (in... Figure 10 The second operation controller 1012 (referred to as "OP0 CTL") is a second operation controller 1012. Figure 10 (Referring to as "OP1CTL" in the original text). The first operation controller 1010 can be configured to fetch data (e.g., frames) from a buffer, process the data, and provide the data to a first display panel for display on the first display panel. The second operation controller 1012 can be configured to fetch data from a buffer, process the data, and provide the data to a second display panel for display on the second display panel. Depending on the configuration from the DPU 1002, both the first operation controller 1010 and the second operation controller 1012 can be enabled, or either the first operation controller 1010 or the second operation controller 1012 can be disabled.

[0105] MDP scheduler 1004 may include flushing synchronization logic 1014 (in... Figure 10This is referred to as "flushing synchronization" in the code. Flushing synchronization logic 1014 can coordinate flushing operations within DPU 1002 and / or with the master DPU 1102. MDP scheduler 1004 may include synchronization mode register 1016 (in...). Figure 10 This is referred to as "asynchronous mode" in the DPU. The synchronous mode register 1016 may include a bit whose value indicates whether a synchronous flush or an asynchronous flush will be performed from the DPU 1002. The MDP scheduler 1004 may include a master selection register 1018 (in...). Figure 10 This is referred to as "OP1_EN_MASTER_SEL" in the DPU. The master select register 1018 may include a bit whose value indicates whether the synchronization will occur within the DPU (e.g., synchronization between the first operation controller 1010 and the second operation controller 1012) or between the DPUs (e.g., between the slave DPU 1002 and the master DPU 1102).

[0106] MDP scheduler 1004 may include control register 1020 (in... Figure 10 This is referred to as "CTL Reg" in the code. Control register 1020 may refer to the module where the configuration register of a specific display controller is located. The MDP scheduler 1004 may include a flush synchronization slave device selection register 1022 (in...). Figure 10 This is referred to as "FLUSH_SYNC_SLAVE_SEL". The flush synchronization select register 1022 can be configured to enable slave DPU functionality (and therefore disable master DPU functionality) or enable master DPU functionality (and therefore disable slave DPU functionality).

[0107] For reference Figure 11 The main DPU 1102 may include an MDP scheduler 1104 and a timing engine generator 1106 (in Figure 11 This is referred to as "DISP INTF (DSI0)" in the code. The timing engine generator 1106 can be configured to generate timing (e.g., Vsync pulses). The timing engine generator 1106 can also be configured to generate flush snapshot pulses 1108 (in... Figure 11 This is referred to as "FLUSH_SNAPSHOT_PULSE" in the code. The flush snapshot pulse 1108 can be defined as a pulse with a software-configurable duration that occurs before the Vsync instance. The flush snapshot pulse 1108 can also occur before pre-fetching (i.e., before DPU0 programmable fetching / MDPVSync).

[0108] MDP scheduler 1104 may be or include a second hardware scheduler 910. MDP scheduler 1104 may include a first operation controller 1110 (in... Figure 11The second operation controller 1112 (referred to as "OP0 CTL") is a second operation controller. Figure 11 (Referring to "OP1CTL" in the original text). The first operation controller 1110 can be configured to fetch data (e.g., frames) from a buffer, process the data, and provide the data to a first display panel for display on the first display panel. The second operation controller 1112 can be configured to fetch data from a buffer, process the data, and provide the data to a second display panel for display on the second display panel. Depending on the configuration from the DPU 1002, both the first operation controller 1110 and the second operation controller 1112 can be enabled, or either the first operation controller 1110 or the second operation controller 1112 can be enabled, or both the first operation controller 1110 and the second operation controller 1112 can be disabled.

[0109] MDP scheduler 1104 may include flushing synchronization logic 1114 (in... Figure 11 This is referred to as "flushing synchronization" in the code. Flushing synchronization logic 1114 can coordinate flushing operations from within DPU 1002 and / or with the master DPU 1102. The MDP scheduler 1104 may include a synchronization mode register 1116 (in...). Figure 11 This is referred to as "asynchronous mode" in the code. The synchronous mode register 1116 may include a bit whose value indicates whether the master DPU 1102 will perform a synchronous flush or an asynchronous flush. The MDP scheduler 1104 may include a master selection register 1118 (in...). Figure 11 (This is referred to as "OP1_EN_MASTER_SEL" in the original text). The master select register 1118 may include a bit, the value of which can indicate whether the synchronization will occur within the DPU (e.g., synchronization between the first operation controller 1110 and the second operation controller 1112) or between DPUs (e.g., between the slave DPU 1002 and the master DPU 1102).

[0110] MDP scheduler 1104 may include control register 1120 (in Figure 11 This is referred to as "CTL Reg" in the code. Control register 1120 may refer to the module where the configuration register of a specific display controller is located. The MDP scheduler 1104 may include a flush synchronization slave device selection register 1122 (in...). Figure 11 This is referred to as "FLUSH_SYNC_SLAVE_SEL" in the code. The flush synchronization select register 1122 can be configured to enable slave DPU functionality (and therefore disable master DPU functionality) or enable master DPU functionality (and therefore disable slave DPU functionality).

[0111] Joint Reference Figure 10 and Figure 11The flushing synchronization logic 1014 can be configured to receive flushing snapshots from the timing engine generator 1006. The flushing synchronization logic 1014 can also be configured to receive flushing requests from the first operation controller 1010 and / or the second operation controller 1012 (i.e., Figure 10 The flush synchronization logic 1014 can be configured to send flush confirmations to the first operation controller 1010 and / or the second operation controller 1012 (i.e., "flush_req" in the code). Figure 10 The flush synchronization logic 1014 can be configured to send a flush request to the first operation controller 1110 and / or the second operation controller 1112 of the main DPU 1102 (i.e., "flush_ack" in the code). Figure 10 The flush synchronization logic 1014 can be configured to send flush confirmations to the first operation controller 1110 and / or the second operation controller 1112 of the main DPU 1102 (i.e., Dpu1_to_dpu0_Flush_req). Figure 10 The flush synchronization logic 1014 can be configured to receive flush requests from the first operation controller 1110 and / or the second operation controller 1112 of the master DPU 1102 (i.e., Dpu1_to_dpu0_Flush_ack). Figure 10 The flush synchronization logic 1014 can be configured to receive flush confirmations from the first operation controller 1110 and / or the second operation controller 1112 of the master DPU 1102 (i.e., Dpu0_to_dpu1_Flush_req). Figure 10 (in "Dpu0_to_dpu1_Flush_ack").

[0112] The flush synchronization logic 1114 can be configured to receive flush snapshots from the timing engine generator 1106. The flush synchronization logic 1114 can also be configured to receive flush requests from the first operation controller 1110 and / or the second operation controller 1112 (i.e., Figure 11 The flush synchronization logic 1114 can be configured to send flush confirmations to the first operation controller 1110 and / or the second operation controller 1112 (i.e., "flush_req" in the code). Figure 11 The flush synchronization logic 1114 can be configured to send a flush request to the first operation controller 1010 and / or the second operation controller 1012 from the DPU 1002 (i.e., "flush_ack"). Figure 11 The flush synchronization logic 1114 can be configured to send flush confirmations (i.e., from the first operation controller 1010 and / or the second operation controller 1012 of the DPU 1002) to the first operation controller 1010 and / or the second operation controller 1012. Figure 11The flush synchronization logic 1114 can be configured to receive flush requests from the first operation controller 1010 and / or the second operation controller 1012 of the DPU 1002 (i.e., Dpu0_to_dpu1_Flush_ack). Figure 11 The flush synchronization logic 1114 can be configured to receive flush confirmations from the first operation controller 1010 and / or the second operation controller 1012 of the DPU 1002 (i.e., Dpu1_to_dpu0_Flush_req). Figure 11 (Dpu1_to_dpu0_Flush_ack in the file).

[0113] Figure 12 Figure 1200 illustrates an example of a DPU 1002 operating in synchronous mode according to one or more techniques of this disclosure. Figure 13 Figure 1300 illustrates an example of a main DPU operating in synchronous mode according to one or more techniques of this disclosure. Reference is now made in conjunction with... Figure 12 and Figure 13 In one aspect, the master DPU 1102 and slave DPU 1002 can operate in synchronous mode. When operating in synchronous mode, the master DPU 1102 can perform the first flush operation based on the Vsync instance, and the slave DPU 1002 can perform the second flush operation at the Vsync instance, when both the first flush operation and the second flush operation are available at a time instance that occurs before the Vsync instance. In one example, if the second flush operation is not available at that time instance, the master DPU 1102 can wait to perform the first flush operation until a subsequent time instance where both the first and second flush operations are available. The master DPU 1102 can repeat previous frames until a time when both the first and second flush operations are available.

[0114] In one example, flush synchronization logic 1114 may receive flush snapshots generated by timing engine generator 1106. The flush snapshot may be associated with flush snapshot pulse 1108. First operation controller 1110 may send a first flush request to flush synchronization logic 1114. First operation controller 1010 may send a second flush request to flush synchronization logic 1114. Flushing synchronization logic 1114 may send a first flush acknowledgment to first operation controller 1010 and a second flush acknowledgment to first operation controller 1110 based on receiving the first and second flush requests. First operation controllers 1010 and 1110 may each consume their respective flush at the next Vsync instance.

[0115] Figure 14Figure 1400 illustrates an example of a DPU operating in asynchronous mode according to one or more techniques of this disclosure. Figure 15 Figure 1500 is an example illustrating a main DPU operating in asynchronous mode according to one or more techniques of this disclosure. Reference is now made in conjunction with... Figure 14 and Figure 15 In one aspect, the master DPU 1102 and the slave DPU 1002 can operate in asynchronous mode. When operating in asynchronous mode, when the master DPU 1102's first operation controller 1110 receives a first instruction for software flushing from software associated with the master DPU 1102 (e.g., first DPU software 906), the master DPU 1102's first operation controller 1110 can consume the first flush at a first VSync instance, and when the slave DPU 1002's first operation controller 1010 receives a second instruction for software flushing from software associated with the slave DPU 1002 (e.g., second DPU software 912), the slave DPU 1002's first operation controller 1010 can consume the second flush at a second VSync instance. The first VSync instance and the second VSync instance can be the same or different. In other words, both the first and second VSync instances can be the next available VSync instances for the master DPU 1102 and slave DPU 1002, respectively, or the first VSync instance can be the next available VSync instance for the master DPU 1102, and the second VSync instance can be a VSync instance that occurs after the next available VSync instance for the slave DPU 1002. Therefore, when operating in asynchronous mode, the master DPU 1102 and slave DPU 1002 can consume flushes independently of each other. For example, even if the second flush is unavailable for the slave DPU 1002 at its next available VSync instance, the master DPU 1102 can still consume the first flush at its next available VSync instance.

[0116] Figure 16 Figure 1600 illustrates an example of a power failure state from a DPU in a synchronous mode according to one or more technologies of this disclosure. Figure 17 Figure 1700 illustrates an example of a master DPU in synchronous mode when the slave DPU is in a power failure state, according to one or more techniques of this disclosure. Reference is now made in conjunction with... Figure 16 and Figure 17The master DPU 1102 can operate in synchronous mode, and the slave DPU 1002 can be in a power failure state. When the master DPU 1102 is operating in synchronous mode and the slave DPU 1002 is in a power failure state, the first operation controller 1110 of the master DPU 1102 can perform master DPU functions, and the second operation controller 1112 of the master DPU 1102 can perform slave DPU functions.

[0117] In one example, flush synchronization logic 1114 may receive flush snapshots generated by timing engine generator 1106. The flush snapshot may be associated with flush snapshot pulse 1108. A first operation controller 1110 may send a first flush request to flush synchronization logic 1114. A second operation controller 1112 may send a second flush request to flush synchronization logic 1114. Flushing synchronization logic 1114 may send a first flush acknowledgment to the first operation controller 1110 and a second flush acknowledgment to the second operation controller 1112 based on receiving the first and second flush requests. The first and second operation controllers 1110 and 1112 may each consume the corresponding flush at their respective next available Vsync instance.

[0118] Figure 18 Figure 1800 illustrates an example of a power failure state from a DPU in asynchronous mode according to one or more techniques of this disclosure. Figure 19 Figure 1900 illustrates an example of a master DPU in asynchronous mode when the slave DPU is in a power failure state, according to one or more techniques of this disclosure. Reference is now made in conjunction with... Figure 18 and Figure 19 The master DPU 1102 can operate in asynchronous mode, and the slave DPU 1002 can be in a power failure state. When the master DPU 1102 operates in asynchronous mode and the slave DPU 1002 is in a power failure state, the first operation controller 1110 of the master DPU 1102 can perform the master DPU functionality, and the second operation controller 1112 of the master DPU 1102 can perform the slave DPU functionality. When operating in asynchronous mode, when the first operation controller 1110 of the primary DPU 1102 receives a first instruction for software flushing from the software associated with the primary DPU 1102 (e.g., the first DPU software 906), the first operation controller 1110 of the primary DPU 1102 may consume the first flush at the first VSync instance, and when the second operation controller 1112 of the primary DPU 1102 receives a second instruction for software flushing from the software associated with the primary DPU 1102 (e.g., the first DPU software 906), the second operation controller 1112 of the primary DPU 1102 may consume the second flush at the second VSync instance.

[0119] Table 1 details various aspects related to the Flush Synchronization Register (“FLUSH_SYNC”). Table 2 details various aspects related to the Flush Synchronization Mode Register (“FLUSH_SYNC_MODE”). Table 3 details various aspects related to the Flush Snapshot Register (“FLUSH_SNAPSHOT”). Table 4 details various aspects related to the Interface Configuration Register (“INTF CONFIG”). Tables 1 through 4 include details related to the Flush Synchronization Configuration Register and sequence.

[0120] Referring to Tables 1 through 4, the master DPU initialization process is described below. Flush synchronization can be enabled via the EN field of FLUSH_SYNC. The first DPU can be configured as the master DPU, and the second DPU as the slave DPU, via the MODE SEL field of FLUSH_SYNC. Additionally or alternatively, the PAIR SEL field of FLUSH_SYNC can be configured. Then, additional registers can be configured. The VALUE field of FLUSH_SNAPSHOT (i.e., the FLUSH_SNAPSHOT_EN / VALUE register) can be configured to indicate when the scheduler should take a snapshot of the flush. The VALUE field of FLUSH_SNAPSHOT can be the minimum half-line before the Mobile Display Processor (MDP) VSync. Flush can be asserted via asynchronous mode (e.g., when the SEL field of FLUSH_SYNC_MODE is 1). The (configured) master DPU can wait for the slave DPU to initialize. When the slave flush is complete, the timing engine can be enabled. During the initialization of the main DPU, the flushing of the main DPU can be the same as that of the main INTF.

[0121] Referring to Tables 1 through 4, the DPU initialization process is described below. The DPU initialization process can target either OP0 of the slave DPU or the slave OP (OP1) of DPU0. Flush synchronization can be enabled via the EN field of FLUSH_SYNC. The MODE SEL field of FLUSH_SYNC can be set to slave. PAIR SEL can also be configured. Additional registers can then be configured. Flush can be asserted via asynchronous mode (e.g., when the SEL field of FLUSH_SYNC_MODE is 1). During slave DPU initialization, the flushing master DPU can be the same as the INTF master.

[0122] Referring to Tables 1 through 4, the master and slave configurations for subsequent updates are described below. Configurable registers. These can be asserted and flushed via the SEL field of FLUSH_SYNC_MODE (e.g., synchronous / asynchronous mode). For the master DPU, the VALUE field of FLUSH_SNAPSHOT (i.e., FLUSH_SNAPSHOT_VALUE) can be updated according to a new timing (which can be the same as the programmable fetch start value). The master or slave DPU can wait for flushing by hardware in response to the corresponding Vsync interrupt request (irq).

[0123] Figure 20 Figure 2000 illustrates an example of a behavioral flow associated with a flushing operation according to one or more techniques of this disclosure. Figure 2000 illustrates a main operation flow 2002, a synchronization logic operation flow 2004, and a slave operation flow 2006. In one example, the main operation flow 2002 may be associated with a first operation controller of the main DPU, the synchronization logic operation flow 2004 may be associated with flushing synchronization logic, and the slave operation flow 2006 may be associated with a second operation controller of the main DPU or a first operation controller of the slave DPU.

[0124] At 2007, the flush synchronization logic can determine whether a flush snapshot has been received (e.g., from the timing engine generator). If a flush snapshot has not yet been received, the flush synchronization logic can wait to receive a flush snapshot.

[0125] At 2008, the first operation controller of the main DPU receives an indication to enable DPU synchronization features, which may indicate whether synchronous flushing or asynchronous flushing is enabled. At 2010, the first operation controller determines the flushing type (synchronous or asynchronous) based on this indication. At 2012, if the flushing type is synchronous, the first operation controller determines whether an indication for software flushing has been received; that is, the first operation controller determines whether an indication for flushing has been received from the software associated with the main DPU. If no indication for software flushing has been received, the first operation controller may wait to receive it. If an indication for software flushing has been received, at 2014, the first operation controller may send a flush request to the flush synchronization logic (i.e., "assert flush_req to the synchronization logic").

[0126] At 2016, the flush synchronization logic can determine whether a flush request has been received from the master DPU (i.e., from the first operation controller of the master DPU). If a flush request has not been received from the master DPU, the flush synchronization logic can return to 2007 and wait to receive a flush snapshot.

[0127] At 2018, if a flush snapshot has been received and a flush request has been received from the master DPU, the flush synchronization logic can determine whether a flush request has been received from the slave DPU. At 2020, if a flush request has been received from the slave DPU, the flush synchronization logic can send an acknowledgment of the flush to the first operation controller of the master DPU (i.e., "assert flush acknowledgment"). The flush synchronization logic can then revert to 2007.

[0128] At 2022, the first operation controller of the main DPU can determine whether an acknowledgment of the flush has been received (i.e., "assert flush acknowledgment"). If no acknowledgment of the flush has been received, the first operation controller can wait for acknowledgment. At 2024, if an acknowledgment of the flush has been received, the first operation controller can consume the flush at the next Vsync instance. Consuming the flush may include a handshake between the DPU hardware and DPU software to exchange double-buffered register configurations and automatically clear the flush flag.

[0129] At point 2026, the second operation controller of the primary DPU or the operation controller of the secondary DPU receives an indication to enable the DPU synchronization feature, wherein the indication may specify whether synchronous flushing or asynchronous flushing is enabled. At point 2028, the second operation controller of the primary DPU or the operation controller of the secondary DPU determines the flushing type (synchronous or asynchronous) based on this indication. At point 2030, if the flushing type is synchronous, the first operation controller determines whether an indication for software flushing has been received; that is, the second operation controller of the primary DPU or the operation controller of the secondary DPU determines whether an indication for flushing has been received from software (e.g., software associated with the primary DPU or software associated with the secondary DPU). If no indication for software flushing has been received, the second operation controller of the primary DPU or the operation controller of the secondary DPU may wait to receive the indication. If an indication for software flushing has been received, at point 2032, the second operation controller of the primary DPU or the operation controller of the secondary DPU may send a flush request to the flushing synchronization logic (i.e., "assert flush_req to the synchronization logic").

[0130] At 2018, the flush synchronization logic determines whether a flush request has been received. At 2020, if a flush request has been received, the flush synchronization logic sends an acknowledgment of the flush to the second operation controller of the master DPU or the operation controller of the slave DPU (i.e., "assert flush acknowledgment"). The flush synchronization logic can then return to 2007.

[0131] At point 2034, after sending a flush request to the synchronization logic, the second operation controller of the primary DPU or the operation controller of the secondary DPU can determine whether an acknowledgment for the flush has been received. If no acknowledgment has been received, the second operation controller of the primary DPU or the operation controller of the secondary DPU can wait to receive the flush acknowledgment. At point 2036, if the second operation controller of the primary DPU or the operation controller of the secondary DPU determines that a flush acknowledgment has been received, then the second operation controller of the primary DPU or the operation controller of the secondary DPU consumes the flush on the next vsync instance.

[0132] Returning to 2010, if the flush type is asynchronous, then at 2038, the first operation controller can determine whether an instruction for a software flush has been received; that is, the first operation controller can determine whether an instruction for a flush has been received from the software associated with the main DPU. If no instruction for a software flush has been received, the first operation controller can wait to receive it. If an instruction for a software flush has been received, then at 2024, the first operation controller can consume the flush at the next Vsync instance.

[0133] Returning to 2028, if the flush type is asynchronous, then at 2040, the second operation controller of the primary DPU or the operation controller of the secondary DPU can determine whether an instruction for flushing has been received from the software associated with the primary or secondary DPU. If no instruction for software flushing has been received, the second operation controller of the primary DPU or the operation controller of the secondary DPU can wait to receive the instruction. If an instruction for software flushing has been received, then at 2036, the first operation controller can consume the flush at the next Vsync instance.

[0134] Figure 21 Figure 2100 illustrates an example of a flush synchronization timeline according to one or more techniques of this disclosure. In one example, DPU0 and DPU1 can operate in synchronization mode as described above. A timing engine generator can generate a flush snapshot 2102, wherein the flush snapshot is an indication of a time instance. The flush snapshot 2102 can be displayed on the DPU1 panel Vsync instance 2104 (in... Figure 21 The pre-extraction of DPU1 panel (referred to as "DPU1 panel VSYNC") and DPU0 pre-extraction 2106 (in Figure 21This occurs at any time between what is referred to as “DPU 0 Programmable Extraction / MDP VSYNC”. In the example, at flush snapshot 2102, the first flush is available for DPU0 and the second flush is available for DPU1. Based on (1) DPU0 and DPU1 operating in synchronous mode and (2) the first flush being available and the second flush being available, at (next available) DPU0 panel VSync instance 2108, DPU0 may consume the first flush with respect to frame 2110a. Furthermore, at the next available DPU1 panel VSync instance 2112, DPU1 may consume the second flush with respect to frame 2110b.

[0135] Figure 22 Figure 2200 illustrates an example of a flush synchronization timeline where the primary DPU flush is unavailable at a snapshot point, according to one or more techniques of this disclosure. In one example, DPU0 and DPU1 can operate in synchronization mode as described above. A timing engine generator can generate flush snapshot 2202, where the flush snapshot is an indication of a time instance. Flushing snapshot 2202 can be displayed on the DPU1 panel Vsync instance 2204 (in... Figure 22 The pre-extraction of DPU1 panel (referred to as "DPU1 panel VSYNC") and DPU0 pre-extraction 2206 (in Figure 22 This occurs at any time between what is referred to as “DPU 0 Programmable Extraction / MDP VSYNC”. In the example, at flush snapshot 2202, the first flush may not be available for DPU0, and the second flush may be available for DPU1. Based on (1) DPU0 and DPU1 operating in sync mode and (2) the first flush being unavailable and the second flush being available, at the next available DPU0 panel VSync instance 2208, DPU0 may not consume the first flush with respect to frame N 2210a, and therefore, DPU0 may repeat frame N-1 2212a (i.e., the previous frame). Furthermore, at the next available DPU1 panel VSync instance 2214, even if the second flush is available, DPU1 may not consume the second flush with respect to frame N 2210b. Therefore, DPU1 may repeat frame N-1 2212b (i.e., the previous frame).

[0136] Figure 23 Figure 2300 illustrates an example of a flush synchronization timeline that is not available at a snapshot point from a DPU flush according to one or more techniques of this disclosure. In one example, DPU0 and DPU1 can operate in synchronization mode as described above. A timing engine generator can generate a flush snapshot 2302, wherein flush snapshot 2302 is an indication of a time instance. Flushing snapshot 2302 can be displayed on the DPU1 panel Vsync instance 2304 (in... Figure 23 The pre-extraction of DPU1 panel (referred to as "DPU1 panel VSYNC") and DPU0 pre-extraction 2306 (in Figure 23 This occurs at any time between what is referred to as “DPU 0 Programmable Extraction / MDP VSYNC”. In the example, at flush snapshot 2302, the first flush may be available for DPU0, and the second flush may not be available for DPU1. Based on (1) DPU0 and DPU1 operating in synchronous mode and (2) the first flush being available and the second flush being unavailable, at the next available DPU0 panel VSync instance 2308, DPU0 may not consume the first flush with respect to frame N 2310a, even if the first flush is available. Therefore, DPU0 may repeat frame N-1 2312a (i.e., the previous frame). Furthermore, at the next available DPU1 panel VSync instance 2314, DPU1 may not consume the second flush with respect to frame N 2310b, and therefore, DPU1 may repeat frame N-1 2312b (i.e., the previous frame).

[0137] Figure 24 Figure 2400 illustrates an example of a flushing synchronization timeline according to one or more techniques of this disclosure. Figure 25 Figure 2500 is an example illustrating a flushing synchronization timeline according to one or more techniques of this disclosure. Reference is now made in conjunction with... Figure 24 and Figure 25 DPU0 and DPU1 can operate in asynchronous mode, as described above. When operating in asynchronous mode, DPU0 and DPU1 can consume flushes independently of each other. For example, even if a second flush is not available for DPU1 at its corresponding VSync instance, DPU0 can still consume a first flush at its VSync instance.

[0138] Figure 26 Figure 2600 illustrates an example of dynamic switching between synchronous and asynchronous modes according to one or more technologies of this disclosure. In one aspect, DPU0 and DPU1 can dynamically switch between synchronous and asynchronous modes. For example, DPU0 and DPU1 can dynamically switch between synchronous and asynchronous modes based on instructions received from software (e.g., first DPU software 906, second DPU software 912, etc.).

[0139] In the example, DPU0 and DPU1 can operate in synchronous mode. DPU0 can consume the first flush with respect to frame N, 2602a, and DPU1 can consume the second flush with respect to frame N, 2602b. Subsequently, DPU0 and DPU1 can switch to asynchronous mode. DPU1's (asynchronous) flush can be delayed, and thus DPU1 can repeat frame N, 2602b, while DPU0 consumes the flush with respect to frame N+1, 2604a. Subsequently, DPU0 and DPU1 can switch to synchronous mode. DPU0 can receive synchronous flushes (i.e., flushes can be available for DPU0); however, DPU1's synchronous flushes can be delayed because the previous asynchronous flush is still in progress. Therefore, DPU0's synchronous flush may not be consumed, and DPU0 can repeat frame N+1, 2604a. Subsequently, when in synchronous mode and when flushing is available for both DPU0 and DPU1, DPU0 may consume flushing for frame N+1 2604a, and DPU1 may consume flushing for frame N+1 2604b.

[0140] Figure 27 This is a call flowchart 2700 illustrating example communication between a DPU 2702 and a display component 2704 according to one or more technologies of this disclosure. The DPU may include a master DPU (i.e., a first DPU). The DPU may also include a slave DPU (i.e., a second DPU). The display component 2704 may be a component of the DPU or a component of a display panel.

[0141] At 2706, DPU 2702 may obtain an indication of synchronous flushing or asynchronous flushing with respect to the first DPU and / or the second DPU. At 2708, DPU 2702 may determine whether the first flushing operation and / or the second flushing operation are available at the time instance. The first flushing operation and the second flushing operation may be associated with the first DPU and / or the second DPU. The first flushing operation and the second flushing operation may be associated with the exchange of a double-buffered register configuration. At 2710, DPU 2702 may perform the first flushing operation and / or the second flushing operation at the VSync instance based on whether the first flushing operation and / or the second flushing operation are available at the time instance and based on the indication of synchronous flushing or asynchronous flushing. At 2712, the DPU may store the indication of the first flushing operation and / or the second flushing operation in memory, cache, and / or buffer. At 2714, DPU 2702 can send instructions to display component 2704 for a first flushing operation and / or a second flushing operation.

[0142] Figure 28 This is a flowchart 2800 illustrating an example method of processing according to one or more techniques of this disclosure. The method can be performed by means such as combining... Figures 1 to 27This includes various aspects of the display processing devices, such as the DPU or other display processors, and wireless communication devices. In one example, this method can be executed by a refresh rate updater 198.

[0143] At 2802, the device (e.g., DPU) receives an instruction for synchronous flushing or an instruction for asynchronous flushing with respect to at least one of the first DPU or the second DPU. For example, Figure 27 At 2706, it is shown that DPU 2702 can obtain instructions for synchronous flushing or asynchronous flushing with respect to at least one of the first DPU or the second DPU. In the example, the first DPU may be or include first DPU 410A, first DPU 902, or master DPU 1102. In the example, the second DPU may be or include second DPU 410B, second DPU 908, or slave DPU 1002. In one example, the first DPU and the second DPU may be within a VR headset. In one example, the foregoing aspects may correspond to Figure 20 2008 and / or 2026 in the example. In one example, 2802 can be performed by refresh rate updater 198.

[0144] At 2804, the device (e.g., a DPU) determines whether at least one of a first flush operation or a second flush operation is available at the time instance, wherein the first flush operation and the second flush operation are associated with at least one of a first DPU or a second DPU, and wherein the first flush operation and the second flush operation are associated with an exchange of a double-buffered register configuration. For example, Figure 28 At 2708, it is shown that DPU 2702 can determine whether at least one of a first flush operation or a second flush operation is available at a time instance, wherein the first flush operation and the second flush operation are associated with at least one of a first DPU or a second DPU, and wherein the first flush operation and the second flush operation are associated with an exchange of a double-buffered register configuration. In one example, flushing can be available when the programmable registers associated with the flush have been fully configured to enable the performance of register configuration exchanges. In one example, the foregoing aspect may correspond to Figure 20 2038, 2022, 2040, and / or 2034 in the example. In one example, the time instance could be a flush snapshot (e.g., flush snapshot 2102, flush snapshot 2202, etc.). In one example, 2804 could be performed by the refresh rate updater 198.

[0145] At 2806, the device (e.g., DPU) performs at least one of the first flushing operation or the second flushing operation based on whether at least one of the first flushing operation or the second flushing operation is available at the time instance and based on an indication for synchronous flushing or an indication for asynchronous flushing, on the VSync instance. For example, Figure 27 At 2710, it is shown that DPU 2702 can perform at least one of the first flush operation or the second flush operation based on whether it is available at a time instance, and based on an indication of synchronous flushing or an indication of asynchronous flushing, based on a VSync instance (e.g., immediately before VSync instance, at VSync instance, immediately after VSync instance). In one example, the foregoing aspect may correspond to Figure 20 2024 and / or 2036 in the example. In one example, the VSync instance could be DPU1 panel VSync instance 2104, DPU0 panel VSync instance 2108, etc. In one example, 2806 could be executed by refresh rate updater 198.

[0146] Figure 29 This is a flowchart 2900 illustrating an example method of processing according to one or more techniques of this disclosure. The method can be performed by means such as combining... Figures 1 to 27 The various aspects used include display processing devices, DPUs or other display processors, wireless communication devices, etc. In one example, the method (including the various aspects detailed below) may be executed by a refresh rate updater 198.

[0147] At 2902, the device (e.g., DPU) receives an instruction for synchronous flushing or an instruction for asynchronous flushing with respect to at least one of the first DPU or the second DPU. For example, Figure 28 At 2706, it is shown that DPU 2702 can obtain instructions for synchronous flushing or asynchronous flushing with respect to at least one of the first DPU or the second DPU. In the example, the first DPU may be or include first DPU 410A, first DPU 902, or master DPU 1102. In the example, the second DPU may be or include second DPU 410B, second DPU 908, or slave DPU 1002. In one example, the first DPU and the second DPU may be within a VR headset. In one example, the foregoing aspects may correspond to Figure 20 2008 and / or 2026 in the example. In one example, 2902 can be performed by refresh rate updater 198.

[0148] At 2904, the device (e.g., a DPU) determines whether at least one of a first flush operation or a second flush operation is available at the time instance, wherein the first flush operation and the second flush operation are associated with at least one of a first DPU or a second DPU, and wherein the first flush operation and the second flush operation are associated with an exchange of a double-buffered register configuration. For example, Figure 28At 2708, it is shown that DPU 2702 can determine whether at least one of a first flush operation or a second flush operation is available at a time instance, wherein the first flush operation and the second flush operation are associated with at least one of a first DPU or a second DPU, and wherein the first flush operation and the second flush operation are associated with an exchange of double-buffered register configurations. In one example, flushing can be available when the programmable registers associated with flushing have been fully configured to enable the exchange of register configurations. In one example, the time instance can be a flush snapshot (e.g., flush snapshot 2102, flush snapshot 2202, etc.). In one example, the foregoing aspects may correspond to Figure 20 2038, 2022, 2040, and / or 2034. In one example, a VSync instance could be DPU1 panel VSync instance 2104, DPU0 panel VSync instance 2108, etc. In one example, 2904 could be executed by refresh rate updater 198.

[0149] At 2906, the device (e.g., DPU) performs at least one of the first flushing operation or the second flushing operation based on whether at least one of the first flushing operation or the second flushing operation is available at the time instance and based on an indication for synchronous flushing or an indication for asynchronous flushing, on the VSync instance. For example, Figure 27 At 2710, it is shown that DPU 2702 can perform at least one of the first flush operation or the second flush operation based on whether it is available at a time instance, and based on an indication of synchronous flushing or an indication of asynchronous flushing, based on a VSync instance (e.g., immediately before VSync instance, at VSync instance, immediately after VSync instance). In one example, the foregoing aspect may correspond to Figure 20 2024 and / or 2036 in the example. In one example, 2906 can be performed by refresh rate updater 198.

[0150] In one aspect, performing at least one of the first flushing operation or the second flushing operation may include: performing a handshake between software associated with at least one of the first DPU or the second DPU and hardware associated with at least one of the first DPU or the second DPU. In one example, the software associated with at least one of the first DPU or the second DPU may be or include first DPU software 906 and / or second DPU software 912. In one example, the hardware associated with at least one of the first DPU or the second DPU may be or include first DPU 902 (or first hardware scheduler 904) and / or second DPU 908 (or second hardware scheduler 910). In one example, performing at least one of the first flushing operation or the second flushing operation at 2710 may include: performing a handshake between software associated with at least one of the first DPU or the second DPU and hardware associated with at least one of the first DPU or the second DPU.

[0151] In one aspect, performing a handshake may configure a hardware double-buffered register associated with at least one of the first or second DPUs and clear a flush flag associated with at least one of the first or second flush operations. In one example, performing a handshake at 2710 between the software associated with at least one of the first or second DPUs and the hardware associated with at least one of the first or second DPUs may include configuring a hardware double-buffered register associated with at least one of the first or second DPUs and clearing a flush flag associated with at least one of the first or second flush operations.

[0152] In one aspect, an instruction for synchronization flushing can be obtained, wherein the VSync instance can be the next available VSync instance occurring after the time instance, and wherein performing at least one of a first flushing operation or a second flushing operation can include: performing the first flushing operation and the second flushing operation at the next available VSync instance based on the availability of the first flushing operation and the second flushing operation at the time instance. In one example, the foregoing aspect may correspond to Figure 20 2008, 2010, 2012, 2022, and 2024. In another example, the aforementioned aspects may correspond to... Figure 20 The dates 2026, 2028, 2030, and 2036. In other examples, the foregoing aspects may be combined with the above. Figure 21 The described aspects are related.

[0153] In one aspect, at 2908, the device (e.g., DPU) can obtain an indication of asynchronous flushing based on the execution of the first flushing operation and the second flushing operation. In one example, the foregoing aspect can be combined with the above. Figures 24 to 26The described aspects are related. In one example, 2908 can be performed by refresh rate updater 198.

[0154] In one aspect, at 2910, the device (e.g., a DPU) can determine whether at least one of a third flush operation or a fourth flush operation is available at a second time instance occurring after the time instance, wherein the third flush operation and the fourth flush operation can be associated with at least one of a first DPU or a second DPU, and wherein the third flush operation and the fourth flush operation can be associated with a second exchange configured with a second double-buffered register. In one example, the foregoing aspects can be combined with the above. Figures 24 to 26 The described aspects are related. In one example, 2910 can be performed by refresh rate updater 198.

[0155] In one aspect, at 2912, the device (e.g., DPU) may perform the third or fourth flush operation at a second next available VSync instance based on the fact that the third or fourth flush operation is available at a second time instance, wherein the second next available VSync instance may be after the next available VSync instance. In one example, the foregoing aspect may be combined with the above. Figures 24 to 26 The described aspects are related. In one example, 2912 can be performed by refresh rate updater 198.

[0156] In one aspect, instructions for a synchronization flush can be obtained, wherein the VSync instance can be the next available VSync instance where both the first and second flush operations are available, and performing at least one of the first or second flush operations can include: performing the first and second flush operations at the next available VSync instance where both the first and second flush operations are available, based on the fact that the first and second flush operations are available at the time instance. In one example, the foregoing aspects may be combined with the above. Figure 22 or Figure 23 The described aspects are related.

[0157] In one aspect, an instruction for asynchronous flushing can be obtained, wherein the VSync instance can be the next available VSync instance, and wherein performing at least one of the first flushing operation or the second flushing operation can include: performing the first flushing operation or the second flushing operation at the next available VSync instance based on the fact that one of the first flushing operation or the second flushing operation is available at the next available VSync instance. In one example, the foregoing aspect may be combined with the above. Figure 20 The aspects described in 2008, 2010, 2038, and 2024 are related. In one example, the aforementioned aspects may be combined with the above. Figure 20The aspects described in 2026, 2028, 2040, and 2036 are related. In one example, the aforementioned aspects may be combined with the above. Figures 24 to 26 The described aspects are related.

[0158] In one aspect, at 2914, the device (e.g., DPU) can obtain an indication of synchronous flushing based on the execution of a first flushing operation or a second flushing operation. In one example, the foregoing aspect can be combined with the above. Figure 26 The described aspects are related. In one example, 2914 can be performed by refresh rate updater 198.

[0159] In one aspect, at 2916, the device (e.g., a DPU) can determine whether at least one of a third flush operation or a fourth flush operation is available at a second time instance occurring after the time instance, wherein the third flush operation and the fourth flush operation can be associated with at least one of a first DPU or a second DPU, and wherein the third flush operation and the fourth flush operation can be associated with a second exchange configured with a second double-buffered register. In one example, the foregoing aspects can be combined with the above. Figures 21 to 23 The described aspects are related. In one example, 2916 can be performed by refresh rate updater 198.

[0160] In one aspect, at 2918, the device (e.g., DPU) may perform the third and fourth flush operations at a second next available VSync instance based on the availability of the third or fourth flush operation at the second time instance, wherein the second next available VSync instance may be after the next available VSync instance. In one example, the foregoing aspect may be combined with the above. Figures 21 to 23 The described aspects are related. In one example, 2918 can be performed by refresh rate updater 198.

[0161] In one aspect, the first flushing operation may be associated with a first controller of the first DPU, and the second flushing operation may be associated with a second controller of the second DPU. For example, the first controller of the first DPU may be a first operation controller 1110, and the second controller of the second DPU may be a first operation controller 1010.

[0162] In one aspect, the first flushing operation may be associated with a first controller of the first DPU, and the second flushing operation may be associated with a second controller of the first DPU. For example, the first controller of the first DPU may be a first operation controller 1110, and the second controller of the first DPU may be a second operation controller 1112.

[0163] In one aspect, performing at least one of the first flushing operation or the second flushing operation can maintain a skew between a first frame displayed on the first display panel and a second frame displayed on the second display panel, wherein at least one of the first DPU or the second DPU can be associated with the first display panel and the second display panel. For example, maintaining the skew can include the combination of the above. Figure 9 The aspects described. In one example, the first display panel may be a first display 406A, and the first frame may be included in frame 414A of the first processing. In one example, the second display panel may be a second display 406B, and the second frame may be included in frame 414B of the second processing.

[0164] In one aspect, at least one of the first flushing operation or the second flushing operation can be performed based on performing a VRR update with respect to at least one of the first display panel or the second display panel. For example, the foregoing aspect can be combined with the above. Figure 9 The described aspects are related.

[0165] In one aspect, at 2920, the device (e.g., DPU) may output an instruction to execute at least one of a first flushing operation or a second flushing operation. For example, Figure 27 At 2712 and / or 2714, an instruction is shown that the DPU can output instructions for the execution of at least one of a first flush operation or a second flush operation. In one example, 2920 may be executed by a refresh rate updater 198.

[0166] In one aspect, outputting an instruction to execute at least one of the first flushing operation or the second flushing operation may include storing the instruction to execute at least one of the first flushing operation or the second flushing operation in at least one of a memory, a cache, or a buffer. For example, Figure 27 At 2712, DPU 2702 is shown to store instructions for the execution of at least one of a first flush operation or a second flush operation in at least one of a memory, a cache, or a buffer.

[0167] In one aspect, outputting an instruction to execute at least one of the first flushing operation or the second flushing operation may include: sending an instruction to execute at least one of the first flushing operation or the second flushing operation. For example, Figure 27 At 2714, it is shown that the DPU 2702 can send instructions for the execution of at least one of a first flushing operation or a second flushing operation.

[0168] In one aspect, performing at least one of the first flush operation or the second flush operation may include consuming at least one of the first flush operation or the second flush operation at the VSync instance based on whether at least one of the first flush operation or the second flush operation is available at the time instance and based on an indication for synchronous flushing or an indication for asynchronous flushing. For example, performing at least one of the first flush operation or the second flush operation at 2712 may include consuming at least one of the first flush operation or the second flush operation at the VSync instance based on whether at least one of the first flush operation or the second flush operation is available at the time instance and based on an indication for synchronous flushing or an indication for asynchronous flushing.

[0169] In each configuration, a method or apparatus for display processing is provided. The apparatus may be a Display Processing Unit (DPU), a display processor, or some other processor capable of performing display processing. In various aspects, the apparatus may be a display processor 127 within device 104, or some other hardware within device 104 or another device. The apparatus may include components for obtaining an indication of synchronous flushing or an indication of asynchronous flushing with respect to at least one of a first display processing unit (DPU) or a second DPU. The apparatus may also include components for determining whether at least one of a first flushing operation or a second flushing operation is available at a time instance, wherein the first flushing operation and the second flushing operation are associated with at least one of the first DPU or the second DPU, and wherein the first flushing operation and the second flushing operation are associated with an exchange of a double-buffered register configuration. The apparatus may also include components for performing at least one of the first flushing operation or the second flushing operation based on a vertical synchronization (VSync) instance, based on whether at least one of the first flushing operation or the second flushing operation is available at a time instance and based on the indication of synchronous flushing or the indication of asynchronous flushing. The apparatus may further include components for obtaining an indication of an asynchronous flush based on the execution of a first flush operation and a second flush operation. The apparatus may further include components for determining whether at least one of a third or fourth flush operation is available at a second time instance occurring after the first time instance, wherein the third and fourth flush operations are associated with at least one of a first or second DPU, and wherein the third and fourth flush operations are associated with a second exchange configured with a second double-buffered register. The apparatus may further include components for executing the third or fourth flush operation at a second next available VSync instance based on the availability of the third or fourth flush operation at the second time instance, wherein the second next available VSync instance follows the next available VSync instance. The apparatus may further include components for obtaining an indication of a synchronous flush based on the execution of a first or second flush operation. The apparatus may further include components for determining whether at least one of a third flush operation or a fourth flush operation is available at a second time instance occurring after the previous time instance, wherein the third flush operation and the fourth flush operation are associated with at least one of a first DPU or a second DPU, and wherein the third flush operation and the fourth flush operation are associated with a second exchange configured with a second double-buffered register. The apparatus may further include components for performing the third flush operation and the fourth flush operation at a second next available VSync instance based on the availability of the third flush operation or the fourth flush operation at the second time instance, wherein the second next available VSync instance follows the next available VSync instance. The apparatus may further include components for outputting an indication of the execution of at least one of the first flush operation or the second flush operation.

[0170] It should be understood that the specific order or hierarchy of boxes / steps in the processes, flowcharts, and / or call flowcharts disclosed herein are merely illustrative of example methods. It should be understood that the specific order or hierarchy of boxes / steps in these processes, flowcharts, and / or call flowcharts may be rearranged based on design preferences. Furthermore, some boxes / steps may be combined or omitted. Other boxes / steps may also be added. The appended method claims provide the elements of various boxes / steps in an exemplary order, but are not intended to limit one to the given specific order or hierarchy.

[0171] The foregoing description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Therefore, the claims are not intended to be limited to the aspects shown herein, but should be given the full scope consistent with the language of the claims, wherein, unless specifically stated otherwise, references to elements in the singular are not intended to mean “one and only one,” but rather “one or more.” The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0172] Unless otherwise specified, the term "some" refers to one or more, and unless otherwise specified in the context, the term "or" may be interpreted as "and / or". Combinations such as "at least one of A, B, or C", "one or more of A, B, or C", "at least one of A, B, and C", "one or more of A, B, and C", and "A, B, C, or any combination thereof" include any combination of A, B, and / or C, which may include multiple A, multiple B, or multiple C. Specifically, combinations such as "at least one of A, B, or C", "one or more of A, B, or C", "at least one of A, B, and C", "one or more of A, B, and C", and "A, B, C, or any combination thereof" may be only A, only B, only C, A and B, A and C, B and C, or A and B and C, wherein any such combination may contain one or more members of A, B, or C. All structural and functional equivalents of the elements throughout the various aspects described herein that are known to or will later be known to a person skilled in the art are expressly incorporated herein by reference and are intended to be covered by the claims. Furthermore, nothing disclosed herein is intended to be offered to the public, whether or not such disclosure is expressly recited in the claims. The terms “module,” “mechanism,” “element,” “device,” etc., cannot replace the word “component.” Therefore, no claim element will be construed as a functional component unless the element is expressly recited using the phrase “component for…”.

[0173] In one or more examples, the functionality described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, although the term "processing unit" is used throughout this disclosure, such a processing unit may be implemented in hardware, software, firmware, or any combination thereof. If any functionality, processing unit, technique, or other module described herein is implemented in software, then such functionality, processing unit, technique, or other module may be stored on or transmitted on a computer-readable medium as one or more instructions or code.

[0174] Computer-readable media may include computer data storage media and communication media, including any media that facilitates the transfer of computer programs from one place to another. In this way, computer-readable media may generally correspond to: (1) a non-transitory tangible computer-readable storage medium; or (2) a communication medium, such as a signal or carrier wave. Data storage media may be any available medium that can be accessed by one or more computers or one or more processors to extract instructions, code, and / or data structures for implementing the techniques described in this disclosure. By way of example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, compressed optical disc read-only memory (CD-ROM) or other optical disc storage devices, magnetic disk storage devices, or other magnetic storage devices. As used herein, magnetic disks and optical discs include compressed optical discs (CD), laser optical discs, optical discs, digital versatile optical discs (DVD), floppy disks, and Blu-ray discs, wherein magnetic disks typically magnetically copy data, while optical discs optically copy data using lasers. Combinations of the above should also be included within the scope of computer-readable media. Computer program products may include computer-readable media.

[0175] The techniques disclosed herein can be implemented in a wide variety of devices or apparatuses, including wireless mobile phones, integrated circuits (ICs), or IC sets (e.g., chipsets). Various components, modules, or units are described in this disclosure to emphasize functional aspects of a device configured to perform the disclosed techniques, but they do not necessarily need to be implemented by different hardware units. Rather, as described above, various units can be combined in any hardware unit or provided by a collection of interoperable hardware units (including one or more processors as described above) combined with suitable software and / or firmware. Therefore, the term "processor" as used herein can refer to any of the above-described structures or any other structure suitable for implementing the techniques described herein. Furthermore, these techniques can be fully implemented in one or more circuit or logic elements.

[0176] The following aspects are merely illustrative and may be combined with other aspects or teachings described herein without limitation.

[0177] Aspect 1 is a display processing method, the method comprising: obtaining an indication for synchronous flushing or an indication for asynchronous flushing with respect to at least one of a first display processing unit (DPU) or a second DPU; determining whether at least one of a first flushing operation or a second flushing operation is available at a time instance, wherein the first flushing operation and the second flushing operation are associated with at least one of the first DPU or the second DPU, and wherein the first flushing operation and the second flushing operation are associated with an exchange of a double-buffered register configuration; and performing at least one of the first flushing operation or the second flushing operation based on a vertical synchronization (VSync) instance based on whether at least one of the first flushing operation or the second flushing operation is available at the time instance and based on the indication for synchronous flushing or the indication for asynchronous flushing.

[0178] Aspect 2 may be combined with aspect 1 and includes: performing at least one of the first flushing operation or the second flushing operation includes: performing a handshake between software associated with at least one of the first DPU or the second DPU and hardware associated with at least one of the first DPU or the second DPU.

[0179] Aspect 3 may be combined with aspect 2 and includes: performing the handshake to cause the hardware associated with at least one of the first DPU or the second DPU to exchange the double buffer register configuration, and clearing the flush flag associated with at least one of the first flush operation or the second flush operation.

[0180] Aspect 4 may be combined with any of aspects 1 to 3 and includes: obtaining the instruction for the synchronization flush, wherein the VSync instance is the next available VSync instance that occurs after the time instance, and wherein performing at least one of the first flush operation or the second flush operation includes: performing the first flush operation and the second flush operation at the next available VSync instance based on the fact that the first flush operation and the second flush operation are available at the time instance.

[0181] Aspect 5 may be combined with aspect 4 and further includes: obtaining the indication for the asynchronous flush based on the execution of the first flush operation and the second flush operation; determining whether at least one of the third flush operation or the fourth flush operation is available at a second time instance occurring after the time instance, wherein the third flush operation and the fourth flush operation are associated with at least one of the first DPU or the second DPU, and wherein the third flush operation and the fourth flush operation are associated with a second exchange of a second double-buffered register configuration; and performing the third flush operation or the fourth flush operation at a second next available VSync instance based on the availability of the third flush operation or the fourth flush operation at the second time instance, wherein the second next available VSync instance is after the next available VSync instance.

[0182] Aspect 6 may be combined with any one of aspects 1 to 3 and includes: obtaining the instruction for the synchronous flush, wherein the VSync instance is the next available VSync instance in which both the first flush operation and the second flush operation are available, and wherein performing at least one of the first flush operation or the second flush operation includes: performing the first flush operation and the second flush operation at the next available VSync instance based on the fact that the first flush operation and the second flush operation are available at the time instance.

[0183] Aspect 7 may be combined with any one of aspects 1 to 3 and includes: obtaining the instruction for the asynchronous flush, wherein the VSync instance is the next available VSync instance, and wherein performing at least one of the first flush operation or the second flush operation includes: performing the first flush operation or the second flush operation at the next available VSync instance based on the fact that one of the first flush operation or the second flush operation is available at the next available VSync instance.

[0184] Aspect 8 may be combined with aspect 7 and further includes: obtaining the indication of the synchronization flush based on the execution of the first flush operation or the second flush operation; determining whether at least one of the third flush operation or the fourth flush operation is available at a second time instance occurring after the time instance, wherein the third flush operation and the fourth flush operation are associated with at least one of the first DPU or the second DPU, and wherein the third flush operation and the fourth flush operation are associated with a second exchange of a second double-buffered register configuration; and performing the third flush operation and the fourth flush operation at a second next available VSync instance based on the availability of the third flush operation or the fourth flush operation at the second time instance, wherein the second next available VSync instance is after the next available VSync instance.

[0185] Aspect 9 may be combined with any one of aspects 1 to 8, and includes: the first flushing operation is associated with a first controller of the first DPU, and the second flushing operation is associated with a second controller of the second DPU.

[0186] Aspect 10 may be combined with any one of aspects 1 to 8, and includes: the first flushing operation is associated with a first controller of the first DPU, and the second flushing operation is associated with a second controller of the first DPU.

[0187] Aspect 11 may be combined with any one of aspects 1 to 10 and includes: performing at least one of the first flushing operation or the second flushing operation to maintain a skew between a first frame displayed on a first display panel and a second frame displayed on a second display panel, wherein at least one of the first DPU or the second DPU is associated with the first display panel and the second display panel.

[0188] Aspect 12 may be combined with aspect 11 and includes: at least one of the first flushing operation or the second flushing operation is performed based on performing a variable refresh rate (VRR) update with respect to at least one of the first display panel or the second display panel.

[0189] Aspect 13 may be combined with any one of aspects 1 to 12, and further includes: outputting an instruction on the execution of at least one of the first flushing operation or the second flushing operation.

[0190] Aspect 14 may be combined with aspect 13 and includes: outputting the instruction for the execution of at least one of the first flushing operation or the second flushing operation includes: storing the instruction for the execution of at least one of the first flushing operation or the second flushing operation in at least one of a memory, a cache, or a buffer.

[0191] Aspect 15 may be combined with any one of aspects 1 to 14 and includes: outputting the instruction for the execution of at least one of the first flushing operation or the second flushing operation includes: sending the instruction for the execution of at least one of the first flushing operation or the second flushing operation.

[0192] Aspect 16 may be combined with any one of aspects 1 to 15 and includes: performing at least one of the first flushing operation or the second flushing operation includes: consuming at least one of the first flushing operation or the second flushing operation at the VSync instance based on whether the first flushing operation or the second flushing operation is available at the time instance and based on the indication for the synchronous flushing or the indication for the asynchronous flushing.

[0193] Aspect 17 is an apparatus for display processing, the apparatus comprising: a processor coupled to a memory, and configured to implement the method according to any one of aspects 1 to 16 based on information stored in the memory.

[0194] Aspect 18 may be combined with aspect 17 and includes: the device is a wireless communication device, the wireless communication device including at least one of a transceiver or an antenna coupled to the processor.

[0195] Aspect 19 is an apparatus for display processing, the apparatus including components for implementing the method according to any one of aspects 1 to 16.

[0196] Aspect 20 is a computer-readable medium (e.g., a non-transitory computer-readable medium) storing computer-executable code that, when executed by a processor, causes the processor to implement the method according to any one of aspects 1 to 16.

[0197] Various aspects have been described herein. These and other aspects are within the scope of the following claims.

Claims

1. An apparatus for display processing, the apparatus comprising: Memory; and A processor, coupled to the memory, and configured based on information stored in the memory, to: The first display processing unit (DPU) or the second DPU receives an instruction for synchronous flushing or an instruction for asynchronous flushing. Determine whether at least one of a first flush operation or a second flush operation is available at a time instance, wherein the first flush operation and the second flush operation are associated with at least one of the first DPU or the second DPU, and wherein the first flush operation and the second flush operation are associated with an exchange of a double-buffered register configuration. as well as Based on whether at least one of the first flushing operation or the second flushing operation is available at the time instance, and based on the indication for the synchronous flushing or the indication for the asynchronous flushing, perform at least one of the first flushing operation or the second flushing operation based on the vertical synchronization (VSync) instance.

2. The apparatus of claim 1, wherein, in order to perform at least one of the first flushing operation or the second flushing operation, the processor is configured to perform a handshake between software associated with at least one of the first DPU or the second DPU and hardware associated with at least one of the first DPU or the second DPU.

3. The apparatus of claim 2, wherein, in order to perform at least one of the first flushing operation or the second flushing operation, the processor is configured to cause the hardware associated with at least one of the first DPU or the second DPU to swap the double-buffered register configuration and clear the flushing flag associated with at least one of the first flushing operation or the second flushing operation.

4. The apparatus of claim 1, wherein the processor is configured to receive the instruction for the synchronization flush, wherein the VSync instance is the next available VSync instance occurring after the time instance, and wherein, in order to perform at least one of the first flush operation or the second flush operation, the processor is configured to: The first flushing operation and the second flushing operation are performed at the next available VSync instance, based on the availability of the first flushing operation and the second flushing operation at the time instance.

5. The apparatus of claim 4, wherein the processor is configured to: The instruction for the asynchronous flushing is obtained based on the execution of the first flushing operation and the second flushing operation; Determine whether at least one of a third or fourth flush operation is available at a second time instance occurring after the stated time instance, wherein the third and fourth flush operations are associated with at least one of the first or second DPU, and wherein the third and fourth flush operations are associated with a second exchange configured with a second double-buffered register; and The third flushing operation or the fourth flushing operation is performed at a second next available VSync instance based on the availability of the third flushing operation or the fourth flushing operation at the second time instance, wherein the second next available VSync instance is after the next available VSync instance.

6. The apparatus of claim 1, wherein the processor is configured to receive the instruction for the synchronous flush, wherein the VSync instance is the next available VSync instance in which both the first flush operation and the second flush operation are available, and wherein, in order to perform at least one of the first flush operation or the second flush operation, the processor is configured to: Based on the availability of the first flushing operation and the second flushing operation at the time instance, the first flushing operation and the second flushing operation are performed at the next available VSync instance where both the first flushing operation and the second flushing operation are available.

7. The apparatus of claim 1, wherein the processor is configured to receive the instruction for the asynchronous flush, wherein the VSync instance is the next available VSync instance, and wherein, in order to perform at least one of the first flush operation or the second flush operation, the processor is configured to: The first flushing operation or the second flushing operation is performed at the next available VSync instance if either the first flushing operation or the second flushing operation is available at the next available VSync instance.

8. The apparatus of claim 7, wherein the processor is configured to: The instruction for the synchronous flushing is obtained based on the execution of the first flushing operation or the second flushing operation; Determine whether at least one of a third or fourth flush operation is available at a second time instance occurring after the stated time instance, wherein the third and fourth flush operations are associated with at least one of the first or second DPU, and wherein the third and fourth flush operations are associated with a second exchange configured with a second double-buffered register; and The third flushing operation or the fourth flushing operation is performed at the second next available VSync instance based on the availability of the third flushing operation or the fourth flushing operation at the second time instance, wherein the second next available VSync instance is after the next available VSync instance.

9. The apparatus of claim 1, wherein the first flushing operation is associated with a first controller of the first DPU, and the second flushing operation is associated with a second controller of the second DPU.

10. The apparatus of claim 1, wherein the first flushing operation is associated with a first controller of the first DPU, and the second flushing operation is associated with a second controller of the first DPU.

11. The apparatus of claim 1, wherein, in order to perform at least one of the first flushing operation or the second flushing operation, the processor is configured to maintain an skew between a first frame displayed on a first display panel and a second frame displayed on a second display panel, wherein at least one of the first DPU or the second DPU is associated with the first display panel and the second display panel.

12. The apparatus of claim 11, wherein, in order to perform at least one of the first flushing operation or the second flushing operation, the processor is configured to perform the first flushing operation or the second flushing operation based on performing a variable refresh rate (VRR) update with respect to at least one of the first display panel or the second display panel.

13. The apparatus of claim 1, wherein the processor is further configured to: Output an instruction for the execution of at least one of the first flushing operation or the second flushing operation.

14. The apparatus of claim 13, wherein, in order to output the instruction for the execution of at least one of the first flushing operation or the second flushing operation, the processor is configured to: The instruction to perform at least one of the first flushing operation or the second flushing operation is stored in at least one of the memory, cache, or buffer.

15. The apparatus of claim 13, wherein, in order to output the instruction for the execution of at least one of the first flushing operation or the second flushing operation, the processor is configured to: Send the instruction to perform at least one of the first flushing operation or the second flushing operation.

16. The apparatus of claim 1, wherein, in order to perform at least one of the first flushing operation or the second flushing operation, the processor is configured to: Based on whether at least one of the first flush operation or the second flush operation is available at the time instance, and based on the indication for the synchronous flush or the indication for the asynchronous flush, at least one of the first flush operation or the second flush operation is consumed at the VSync instance.

17. The apparatus of claim 1, wherein the apparatus is a wireless communication device, the wireless communication device comprising at least one of a transceiver or an antenna coupled to the at least one processor.

18. A method for display processing, the method comprising: The first display processing unit (DPU) or the second DPU receives an instruction for synchronous flushing or an instruction for asynchronous flushing. Determine whether at least one of a first flush operation or a second flush operation is available at a time instance, wherein the first flush operation and the second flush operation are associated with at least one of the first DPU or the second DPU, and wherein the first flush operation and the second flush operation are associated with an exchange of a double-buffered register configuration. as well as Based on whether at least one of the first flushing operation or the second flushing operation is available at the time instance, and based on the indication for the synchronous flushing or the indication for the asynchronous flushing, perform at least one of the first flushing operation or the second flushing operation based on the vertical synchronization (VSync) instance.

19. The method of claim 18, wherein performing at least one of the first flushing operation or the second flushing operation comprises: Perform a handshake between the software associated with at least one of the first DPU or the second DPU and the hardware associated with at least one of the first DPU or the second DPU.

20. The method of claim 19, wherein performing the handshake causes the hardware associated with at least one of the first DPU or the second DPU to exchange the double-buffered register configuration, and clears the flush flag associated with at least one of the first flush operation or the second flush operation.

21. The method of claim 18, wherein obtaining the indication for the synchronization flush, wherein the VSync instance is the next available VSync instance occurring after the time instance, and wherein performing at least one of the first flush operation or the second flush operation comprises: The first flushing operation and the second flushing operation are performed at the next available VSync instance, based on the availability of the first flushing operation and the second flushing operation at the time instance.

22. The method according to claim 21, further comprising: The instruction for the asynchronous flushing is obtained based on the execution of the first flushing operation and the second flushing operation; Determine whether at least one of a third or fourth flush operation is available at a second time instance occurring after the stated time instance, wherein the third and fourth flush operations are associated with at least one of the first or second DPU, and wherein the third and fourth flush operations are associated with a second exchange configured with a second double-buffered register; and The third flushing operation or the fourth flushing operation is performed at a second next available VSync instance based on the availability of the third flushing operation or the fourth flushing operation at the second time instance, wherein the second next available VSync instance is after the next available VSync instance.

23. The method of claim 18, wherein obtaining the instruction for the synchronous flush, wherein the VSync instance is the next available VSync instance where both the first flush operation and the second flush operation are available, and wherein performing at least one of the first flush operation or the second flush operation comprises: Based on the availability of the first flushing operation and the second flushing operation at the time instance, the first flushing operation and the second flushing operation are performed at the next available VSync instance where both the first flushing operation and the second flushing operation are available.

24. The method of claim 18, wherein obtaining the instruction for the asynchronous flush, wherein the VSync instance is the next available VSync instance, and wherein performing at least one of the first flush operation or the second flush operation comprises: The first flushing operation or the second flushing operation is performed at the next available VSync instance if either the first flushing operation or the second flushing operation is available at the next available VSync instance.

25. The method according to claim 24, further comprising: The instruction for the synchronous flushing is obtained based on the execution of the first flushing operation or the second flushing operation; Determine whether at least one of a third or fourth flush operation is available at a second time instance occurring after the stated time instance, wherein the third and fourth flush operations are associated with at least one of the first or second DPU, and wherein the third and fourth flush operations are associated with a second exchange configured with a second double-buffered register; and The third flushing operation or the fourth flushing operation is performed at the second next available VSync instance based on the availability of the third flushing operation or the fourth flushing operation at the second time instance, wherein the second next available VSync instance is after the next available VSync instance.

26. The method of claim 18, wherein the first flushing operation is associated with a first controller of the first DPU, and the second flushing operation is associated with a second controller of the second DPU.

27. The method of claim 18, wherein the first flushing operation is associated with a first controller of the first DPU, and the second flushing operation is associated with a second controller of the first DPU.

28. The method of claim 18, wherein performing at least one of the first flushing operation or the second flushing operation maintains a skew between a first frame displayed on a first display panel and a second frame displayed on a second display panel, wherein at least one of the first DPU or the second DPU is associated with the first display panel and the second display panel.

29. The method of claim 28, wherein at least one of the first flushing operation or the second flushing operation is performed based on performing a variable refresh rate (VRR) update with respect to at least one of the first display panel or the second display panel.

30. A computer-readable medium storing computer-executable code, said computer-executable code causing the processor, when executed by at least one processor, to: The first display processing unit (DPU) or the second DPU receives an instruction for synchronous flushing or an instruction for asynchronous flushing. Determine whether at least one of a first flush operation or a second flush operation is available at a time instance, wherein the first flush operation and the second flush operation are associated with at least one of the first DPU or the second DPU, and wherein the first flush operation and the second flush operation are associated with an exchange configured by a double-buffered register; and Based on whether at least one of the first flushing operation or the second flushing operation is available at the time instance, and based on the indication for the synchronous flushing or the indication for the asynchronous flushing, perform at least one of the first flushing operation or the second flushing operation based on the vertical synchronization (VSync) instance.

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