Chip testing method, device, apparatus, and computer storage medium

Abstract

The application provides a chip testing method, device, equipment and computer storage medium. The chip testing method comprises the following steps: obtaining a test instruction issued by an upper computer; modifying parameters of a test device according to the test instruction to configure a corresponding test mode; and testing one or more chips to be tested connected with the test device according to the test mode to obtain a test result. Through the chip testing method, the reliability and efficiency of chip testing are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of chip research and development, and in particular, to a chip testing method, device, equipment and computer storage medium. BACKGROUND

[0002] Currently, the testing scheme for chips generally adopts a firmware solidification type register configuration mode, that is, the control firmware of the testing device needs to pre-integrate the physical address of the register, the configuration instruction format and the parameter threshold range into the testing device according to the specification parameters of the testing object (chip to be tested).

[0003] In the prior art, the register configuration of the testing device is strongly coupled with the chip specification. When the testing object is replaced by a chip of a different model, different batch or different functional version, the register address mapping rule and configuration parameter requirement of the new chip to be tested are often incompatible with the original firmware. At this time, the technical personnel need to re-write or modify the register modification module code in the firmware, and after compiling and debugging, the firmware is re-programmed to the testing device for testing the new chip to be tested.

[0004] The single firmware re-development, compilation and programming usually consumes several hours to several days. Especially in the multi-variety and small-batch chip testing scenario, frequent firmware iteration and programming will greatly prolong the testing period. The testing device may be damaged due to operation errors during the firmware programming process, which affects the reliability and efficiency of chip testing. SUMMARY

[0005] To solve the above technical problems, the present application provides a chip testing method, device, equipment and computer storage medium.

[0006] To solve the above technical problems, the present application provides a chip testing method, which comprises:

[0007] obtaining a test instruction issued by a host computer;

[0008] modifying parameters of a testing device according to the test instruction to configure a corresponding test mode;

[0009] testing one or more chips to be tested connected with the testing device according to the test mode to obtain a test result.

[0010] The modification of the parameters of the testing device according to the test instruction to configure the corresponding test mode comprises:

[0011] obtaining attribute information represented by a standard format parameter in the test instruction;

[0012] modifying the parameters of the register in the testing device according to the attribute information to realize the configuration of the test mode.

[0013] The register comprises a low 32-bit configuration register, a high 32-bit configuration register, and a data bus mapping register.

[0014] The low 32-bit configuration register is used to control the start or stop of hardware and software training of the low 32-bit storage unit, and the high 32-bit configuration register is used to control the start or stop of hardware and software training of the high 32-bit storage unit.

[0015] The data bus mapping register is used to control the channel mapping mode and the mapping start channel.

[0016] The processing bit width of the test equipment is 64 bits.

[0017] When the test mode is a double-channel test on two chips to be tested with a processing bit width of 32 bits or a single chip to be tested with a processing bit width of 64 bits, the low 32-bit configuration register and the high 32-bit configuration register are configured as a first target value, and the data bus mapping register is configured as a parameter value representing a double-channel mapping mode.

[0018] When the test mode is a single-channel test on the high 32-bit of a chip to be tested with a processing bit width of 64 bits, the low 32-bit configuration register is configured as a second target value, the high 32-bit configuration register is configured as a first target value, the data bus mapping register is configured as a parameter value representing a single-channel mapping mode, and the mapping start channel is configured as a high 32-bit channel.

[0019] The register further comprises a chip address structure configuration register, which is used to represent address structure information of the chip to be tested.

[0020] The method further comprises:

[0021] Constructing a multi-dimensional coordinate system according to the address structure information.

[0022] Obtaining an abnormal physical address reported by a test process.

[0023] Converting the abnormal physical address into a coordinate in the multi-dimensional coordinate system according to a logical address mapping relationship.

[0024] Before testing one or more chips to be tested, the method further comprises:

[0025] Winding one or more chips to be tested respectively to obtain winding attributes of the one or more chips to be tested.

[0026] Comparing the winding attributes with attribute information carried by the test instruction.

[0027] In case of consistent comparison result, start testing one or more of the chips to be tested.

[0028] The winding of the one or more chips to be tested respectively comprises:

[0029] Obtain the theoretical capacity in the attribute information.

[0030] Determine the maximum address range according to the theoretical capacity.

[0031] According to the maximum address range and the preset address interval, read and write in the chip to be tested.

[0032] According to the read and write result, determine the actual capacity of the chip to be tested.

[0033] To solve the above technical problems, the application provides a chip testing device, which comprises:

[0034] An acquisition module is configured to acquire a test instruction issued by an upper computer.

[0035] A modification module is configured to modify parameters of a test device according to the test instruction to configure a corresponding test mode.

[0036] A test module is configured to test one or more chips to be tested connected to the test device according to the test mode, and obtain a test result.

[0037] To solve the above technical problems, the application further provides a computer storage medium for storing program data, which is used to implement the chip testing method.

[0038] Compared with the prior art, the application has the beneficial effects that the parameters of the test device are modified in real time according to the test instruction, the test compatibility of chips with different structures is realized, and when facing the test of chips with different structures, it is not necessary to reprogram the software and modify the hardware, but only to issue the test parameters according to the test instruction, and the test device can modify the corresponding test device according to the test instruction, so as to configure different test modes for different test parameters, and then realize the test of different chips to be tested, and improve the reliability and efficiency of chip testing. BRIEF DESCRIPTION OF DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor. Among them:

[0040] Figure 1 This is a flowchart illustrating the first embodiment of the chip testing method provided in this application;

[0041] Figure 2 This is a schematic diagram of a chip testing architecture provided in this application;

[0042] Figure 3 This is a schematic diagram of the logical address mapping relationship provided in this application;

[0043] Figure 4 This is a schematic diagram of the structure of an embodiment of the chip testing device provided in this application;

[0044] Figure 5 This is a schematic diagram of the structure of an embodiment of the chip testing equipment provided in this application;

[0045] Figure 6 This is a schematic diagram of the structure of an embodiment of the computer storage medium provided in this application. Detailed Implementation

[0046] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0047] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0048] Please see Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of the chip testing method provided in this application.

[0049] The chip testing method of this application is applied to a chip testing device, which can be a server, a terminal device, or a system in which the server and the terminal device cooperate with each other. Accordingly, the various parts of the chip testing device, such as each unit, subunit, module, and submodule, can all be set in the server, all in the terminal device, or separately in the server and the terminal device.

[0050] Furthermore, the aforementioned server can be either hardware or software. When the server is hardware, it can be implemented as a distributed server cluster consisting of multiple servers, or as a single server. When the server is software, it can be implemented as multiple software programs or software modules, such as software or software modules used to provide distributed server functionality, or as a single software program or software module; no specific limitations are made here.

[0051] like Figure 1 As shown, the specific steps are as follows:

[0052] Step S11: Obtain the test command issued by the host computer.

[0053] In this embodiment, the chip testing method is applied to a testing device. Please refer to [link to relevant documentation]. Figure 2 , Figure 2 This is a schematic diagram of a chip testing architecture provided in this application, as shown below. Figure 2 As shown, the chip testing architecture includes a host computer, testing equipment, and the chip to be tested.

[0054] The host computer is a computer used to generate test instructions based on user input, send test instructions to the test equipment, receive the status data of the chip under test returned by the test equipment, analyze whether the chip under test meets the standard, and generate a test report.

[0055] The testing equipment is connected to both the chip under test (DUT) and the host computer. It receives test commands from the host computer and performs tests on the DUT. The DUT is the object of the testing equipment.

[0056] Step S12: Modify the parameters of the test equipment according to the test instructions to configure the corresponding test mode.

[0057] In this embodiment, the parameters of the test equipment are modified in real time according to the test instructions to achieve test compatibility for chips with different structures. When testing chips with different structures, there is no need to re-program the software or modify the hardware. Only the test parameters need to be issued according to the test instructions. The test equipment can be modified according to the test instructions to configure different test modes for different test parameters in the test instructions.

[0058] Furthermore, the step of modifying the parameters of the test device according to the test instruction to configure the corresponding test mode includes: obtaining attribute information represented by standard format parameters in the test instruction; and modifying the parameters of the registers in the test device according to the attribute information to implement the configuration of the test mode.

[0059] In this process, the user inputs relevant information about the chip to be tested, namely attribute information, on the host computer. The attribute information includes information such as the quantity, capacity, and structure of the chip to be tested. The host computer converts the information input by the user into standard format parameters, carries the standard format parameters in the test command, and sends them to the test equipment.

[0060] The host computer supports importing parameter tables of the chip under test. The host computer communicates with the test device through the UART (Universal Asynchronous Receiver / Transmitter) flag register. It periodically reads the data of the first target parameter bit in the UART flag register to check if there is a free position in the transmit queue. If there is a free position, the test command is written into the UART flag register character by character to complete the transmission of the test command.

[0061] The host computer periodically reads the second target parameter bit of the UART flag register to check whether the receive queue is empty. If the receive queue is not empty, it reads the data in the receive queue to receive the data sent by the test device.

[0062] The test equipment receives attribute information represented by standard format parameters; it converts the attribute information into register configuration values, configures the registers in the test equipment, and thus changes the test mode.

[0063] The test modes for configuring test equipment include timing configuration, dynamic configuration, state configuration, and algorithm configuration.

[0064] Timing configuration includes determining the parameters of the timing register, changing the parameters of the timing register to complete the timing configuration of the relevant hardware in the test equipment, and dynamically adjusting the test timing of the test equipment based on the timing register.

[0065] Dynamic configuration involves receiving the address structure information of the chip under test carried in the test command. The test equipment determines the parameters of the chip address structure configuration register based on the address structure information and modifies the parameters of the chip address structure configuration register to adapt to the chip under test with different structures. It does not require reprogramming the software or modifying the hardware. The address structure configuration can be achieved simply by sending the address structure information from the host computer to modify the configuration value of the register.

[0066] Specifically, the address structure configuration register consists of 14 bits, each of which can be configured to be 0 or 1. Bits 0 to 2 represent the column address width of a single chip under test; bits 4 to 6 represent the row address width; bits 8 to 9 represent the number of banks in a single chip under test; and bits 12 to 13 represent the address decoding mode of the memory cells in the chip under test. Specifically, when the configuration value of binary bits 12 to 13 (denoted as the target configuration value) is 00, the address is represented as {Rank, Row, Ba, Col, DW}; when the target configuration value is 01, the address is represented as {Rank, Ba, Row, Col, DW}; when the target configuration value is 10, the address is represented as {Rank, Row, Ba, Col, cs, Col, DW}; and when the target configuration value is 11, the address is represented as {Rank, Ba, Row, Col, cs, Col, DW}.

[0067] Where Rank is the memory bank group, Row is the row address, Bank is the memory bank, Col is the column address, cs is the chip select signal, and DW is the data width.

[0068] In an optional embodiment, a multi-dimensional coordinate system is constructed based on the address structure information; abnormal physical addresses reported during the testing process are obtained; and the abnormal physical addresses are converted into coordinates in the multi-dimensional coordinate system according to the logical address mapping relationship.

[0069] In this embodiment, a multi-dimensional coordinate system is constructed based on address structure information. Specifically, the multi-dimensional coordinate system is constructed based on the address decoding mode. During the testing process, abnormal physical addresses are obtained, and according to the logical address mapping relationship, the abnormal physical addresses are converted into coordinates in the multi-dimensional coordinate system, i.e., converted into logical addresses. Please refer to [link to relevant documentation]. Figure 3 , Figure 3 This is a schematic diagram of the logical address mapping relationship provided in this application. The abnormal physical address corresponding to the abnormal storage unit is represented by 32 bits of binary data, where the 0th bit represents the data width in the logical address, the 1st to 11th bits represent the column address, the 12th to 14th bits represent the storage bank, the 15th to 30th bits represent the row address, and the 31st bit represents the storage bank group.

[0070] The testing equipment has a processing bit width of 64 bits, which can test two 32-bit chips under test simultaneously, or test the high 32 bits and low 32 bits of a single 64-bit chip under test simultaneously, or test the high 32 bits or low 32 bits of a single 32-bit chip under test or a single 64-bit chip under test individually.

[0071] The status configuration is used to configure the test status of the test equipment. The test status is mainly divided into single-channel test and dual-channel test. Single-channel test refers to the test equipment testing a single 32-bit chip under test or a single 64-bit chip under test, specifically the high 32 bits and low 32 bits. Dual-channel test refers to the test equipment testing two 32-bit chips under test or a single 64-bit chip under test, specifically the high 32 bits and low 32 bits, in parallel.

[0072] The registers used to implement state configuration include a low 32-bit configuration register, a high 32-bit configuration register, and a data bus mapping register. The low 32-bit configuration register is used to control whether the hardware and software training of the low 32-bit memory cell is enabled or disabled, and the high 32-bit configuration register is used to control whether the hardware and software training of the high 32-bit memory cell is enabled or disabled.

[0073] Configuration values ​​are written to the lower 32-bit configuration register and the higher 32-bit configuration register to control whether the memory cell corresponding to the chip under test is subjected to hardware training and software training, respectively. When the configuration values ​​written to both the lower 32-bit configuration register and the higher 32-bit configuration register are 1 (first target value), it is a dual-channel test; when the configuration value written to the lower 32-bit configuration register is 1 and the configuration value written to the higher 32-bit configuration register is 0 (second target value), it is a single-channel test, in which case the lower 32 bits of a single 64-bit chip under test can be tested in a single channel; when the configuration value written to the lower 32-bit configuration register is 0 and the configuration value written to the higher 32-bit configuration register is 1, it is a single-channel test of the higher 32 bits of a single 64-bit chip under test.

[0074] The data bus mapping register is used to control the channel mapping mode and the mapping start channel. The channel mapping mode includes dual-channel mapping mode and single-channel mapping mode. In the single-channel test, only the high 32 bits of a single 64-bit chip under test are used for single-channel testing, and the mapping start channel is the high 32-bit channel. In the rest of the test, the mapping start channel is the low 32-bit channel.

[0075] Therefore, in the test mode where dual-channel testing is performed on two 32-bit processing chips or a single 64-bit chip under test, the lower 32-bit configuration register and the higher 32-bit configuration register are configured to a first target value; the data bus mapping register is configured to a parameter value representing the dual-channel mapping mode. In the test mode where single-channel testing is performed on the higher 32 bits of a 64-bit processing chip under test, the lower 32-bit configuration register is configured to a second target value; the higher 32-bit configuration register is configured to the first target value; the data bus mapping register is configured to a parameter value representing the single-channel mapping mode; and the mapping start channel is configured as the higher 32-bit channel.

[0076] The testing equipment incorporates various memory testing algorithms, each applicable to chips with different structures. Users can freely select the identifier of the memory testing algorithm via a host computer and send it to the testing equipment. The testing equipment then selects and executes the corresponding memory testing algorithm based on the identifier, eliminating the need for recompiling and flashing the software.

[0077] Step S13: Test one or more chips to be tested connected to the test equipment according to the test mode, and obtain the test results.

[0078] In an optional embodiment, before testing one or more chips under test, the method further includes: winding one or more chips under test respectively to obtain winding attributes of one or more chips under test; comparing the winding attributes with attribute information carried by the test command; and starting to test one or more chips under test if the comparison results are consistent.

[0079] The step of winding one or more of the chips under test includes: obtaining the theoretical capacity from the attribute information; determining the maximum address range based on the theoretical capacity; performing read and write operations on the chips under test based on the maximum address range and a preset address interval; and determining the actual capacity of the chips under test based on the read and write results.

[0080] In this embodiment of the application, before testing the chip to be tested, the chip to be tested is first wound once to determine whether the chip to be tested connected to the testing equipment is consistent with the chip to be tested sent by the host computer. This avoids the actual test object being inconsistent with the actual object to be tested due to the wrong chip being placed, thus avoiding inaccurate test results.

[0081] If the actual test object is inconsistent with the object intended to be tested, the test will stop and return an error message.

[0082] Specifically, when winding the chip under test, the theoretical capacity is first obtained. The theoretical capacity is the capacity of the chip under test issued by the host computer. The maximum address range is determined according to the theoretical capacity. Reading and writing are performed on the chip under test according to the maximum address range and the preset address interval. The actual capacity of the chip under test is determined according to the read and write results.

[0083] Specifically, starting from the first address, read and write operations are performed every preset address interval (e.g., 16MB) until the read and write range reaches the maximum address range. If the actual capacity of the chip under test is consistent with the theoretical capacity, the data written and read each time should be consistent. If the actual capacity of the chip under test is less than the theoretical capacity, write operations exceeding the actual capacity cannot be completed, and the read data is invalid. Therefore, the actual capacity of the chip under test can be determined based on the read and write results.

[0084] The number of read / write operations N is determined based on the maximum address range and the preset address interval. If the data written and read during the Nth read / write operation are consistent, a second read / write operation is performed at the preset address interval from the memory cell of the Nth read / write operation. If the data written and read are still consistent at this time, it means that the actual capacity of the chip under test is greater than the theoretical capacity. Otherwise, the actual capacity is equal to the theoretical capacity.

[0085] Starting from the beginning address of the maximum address range, specific values ​​are written to the test chip sequentially according to the preset address intervals; after writing specific values ​​to the end address of the maximum address range, data in the chip under test is read sequentially from the beginning address of the maximum address range according to the preset address intervals to obtain multiple first read values; if the multiple first read values ​​are inconsistent with the specific value, it is determined that the theoretical capacity is greater than the actual capacity.

[0086] If the multiple first read values ​​are inconsistent with the specific value, the specific value is written to the target address after the end address; the data at the target address in the chip under test is read to obtain a second read value; if the second read value is consistent with the specific value, it is determined that the theoretical capacity is less than the actual capacity.

[0087] Through the above embodiments, the parameters of the test equipment are modified in real time according to the test instructions, achieving test compatibility for chips with different structures. When testing chips with different structures, there is no need to re-program the software or modify the hardware. Only the test parameters need to be issued according to the test instructions, and the test equipment can be modified accordingly to configure different test modes for different test parameters. This enables the testing of different chips under test, improving the reliability and efficiency of chip testing.

[0088] If the test is successful, a success status is returned to the host computer; if the test fails, a failure status is returned to the host computer, and the logical address of the faulty storage unit is sent back.

[0089] Those skilled in the art will understand that, in the above-described method of the specific implementation, the order in which each step is written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.

[0090] To implement the above chip testing method, this application also proposes a chip testing apparatus, for details please refer to [link / reference needed]. Figure 4 , Figure 4 This is a schematic diagram of an embodiment of the chip testing device provided in this application.

[0091] The chip testing apparatus 500 in this embodiment includes:

[0092] The acquisition module 51 is used to acquire test commands issued by the host computer;

[0093] Modification module 52 is used to modify the parameters of the test equipment according to the test instructions to configure the corresponding test mode;

[0094] The test module 53 is used to test one or more chips to be tested connected to the test device according to the test mode, and obtain test results.

[0095] The aforementioned modification module is also used to obtain attribute information represented by standard format parameters in the test instruction; and to modify the parameters of the registers in the test device according to the attribute information to configure the test mode.

[0096] The registers include a low 32-bit configuration register, a high 32-bit configuration register, and a data bus mapping register. The low 32-bit configuration register is used to control whether the hardware and software training of the low 32-bit memory unit is enabled or disabled. The high 32-bit configuration register is used to control whether the hardware and software training of the high 32-bit memory unit is enabled or disabled. The data bus mapping register is used to control the channel mapping mode and the mapping start channel.

[0097] The testing equipment has a processing bit width of 64 bits. In the test mode, which involves dual-channel testing of two 32-bit processing bit width chips or a single 64-bit processing bit width chip, the lower 32-bit configuration register and the higher 32-bit configuration register are configured with a first target value; the data bus mapping register is configured with a parameter value representing the dual-channel mapping mode. In the test mode, which involves single-channel testing of the higher 32 bits of a 64-bit processing bit width chip, the lower 32-bit configuration register is configured with a second target value; the higher 32-bit configuration register is configured with the first target value; the data bus mapping register is configured with a parameter value representing the single-channel mapping mode; and the mapping start channel is configured as the higher 32-bit channel.

[0098] The register further includes a chip address structure configuration register, which is used to represent the address structure information of the chip under test.

[0099] The chip testing device further includes a construction module, used to construct a multi-dimensional coordinate system based on the address structure information; obtain abnormal physical addresses reported during the testing process; and convert the abnormal physical addresses into coordinates in the multi-dimensional coordinate system according to the logical address mapping relationship.

[0100] The chip testing apparatus further includes a winding module, used to wind one or more chips under test respectively before testing them to obtain winding attributes of one or more chips under test; compare the winding attributes with the attribute information carried by the test command; and start testing one or more chips under test if the comparison results are consistent.

[0101] The aforementioned winding module is also used to obtain the theoretical capacity from the attribute information; determine the maximum address range based on the theoretical capacity; perform read and write operations on the chip under test based on the maximum address range and a preset address interval; and determine the actual capacity of the chip under test based on the read and write results.

[0102] To implement the above chip testing method, this application also proposes a chip testing device, for details please refer to [link / reference needed]. Figure 5 , Figure 5 This is a schematic diagram of an embodiment of the chip testing equipment provided in this application.

[0103] The chip testing device 400 in this embodiment includes a processor 41, a memory 42, an input / output device 43, and a bus 44.

[0104] The processor 41, memory 42, and input / output device 43 are respectively connected to the bus 44. The memory 42 stores program data, and the processor 41 is used to execute the program data to implement the chip testing method described in the above embodiment.

[0105] In this embodiment, processor 41 can also be referred to as a CPU (Central Processing Unit). Processor 41 may be an integrated circuit chip with signal processing capabilities. Processor 41 can also be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The general-purpose processor can be a microprocessor, or processor 41 can be any conventional processor.

[0106] This application also provides a computer storage medium; please refer to the following: Figure 6 , Figure 6This is a schematic diagram of a computer storage medium according to an embodiment of the present application. The computer storage medium 600 stores a computer program 61, which, when executed by a processor, is used to implement the chip testing method of the above embodiment.

[0107] When the embodiments of this application are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0108] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A chip testing method, characterized in that, The chip testing method includes: Obtain test instructions issued by the host computer, wherein the test instructions include attribute information, including the number, capacity and structure of the chips to be tested; The test device parameters are modified according to the test instructions to configure the corresponding test mode. The processing bit width of the test device is 64 bits. The test modes include single-channel test mode and dual-channel test mode. The single-channel test means that the test device tests the high 32 bits / low 32 bits of a single 32-bit chip under test or a single 64-bit chip under test. The dual-channel test means that the test device tests the high 32 bits and low 32 bits of two 32-bit chips under test or a single 64-bit chip under test in parallel. The test results are obtained by testing one or more chips to be tested that are connected to the test equipment according to the test mode.

2. The chip testing method according to claim 1, characterized in that, The step of modifying the parameters of the test equipment according to the test instruction to configure the corresponding test mode includes: Obtain the attribute information represented by standard format parameters in the test instruction; The parameters of the registers in the test device are modified according to the attribute information to configure the test mode.

3. The chip testing method according to claim 2, characterized in that, The registers include a low 32-bit configuration register, a high 32-bit configuration register, and a data bus mapping register; The lower 32-bit configuration register is used to control whether the hardware and software training of the lower 32-bit memory unit is enabled or disabled; the higher 32-bit configuration register is used to control whether the hardware and software training of the higher 32-bit memory unit is enabled or disabled. The data bus mapping register is used to control the channel mapping mode and the starting channel for mapping.

4. The chip testing method according to claim 3, characterized in that, The testing equipment has a processing bit width of 64 bits. In the test mode, dual-channel testing is performed on two chips under test with a processing bit width of 32 bits or a single 64-bit chip under test. The lower 32-bit configuration register and the higher 32-bit configuration register are configured with a first target value; the data bus mapping register is configured with a parameter value representing the dual-channel mapping mode. When the test mode is to perform a single-channel test on the high 32 bits of a chip under test with a processing bit width of 64 bits, the low 32-bit configuration register is configured to the second target value; the high 32-bit configuration register is configured to the first target value; the data bus mapping register is configured to a parameter value representing the single-channel mapping mode; and the mapping start channel is configured as the high 32-bit channel.

5. The chip testing method according to claim 2, characterized in that, The register also includes a chip address structure configuration register, which is used to represent the address structure information of the chip under test; The method further includes: Construct a multi-dimensional coordinate system based on the address structure information; Obtain the physical address of any anomalies reported during the testing process; The abnormal physical address is converted into coordinates in the multidimensional coordinate system based on the logical address mapping relationship.

6. The chip testing method according to claim 1, characterized in that, Before testing one or more chips to be tested, the method further includes: One or more of the chips under test are wound to obtain the winding properties of one or more of the chips under test; Compare the winding properties with the property information carried by the test command; If the comparison results are consistent, testing of one or more of the chips to be tested will begin.

7. The chip testing method according to claim 6, characterized in that, The winding of one or more of the chips under test includes: Obtain the theoretical capacity from the attribute information; Determine the maximum address range based on the theoretical capacity; The chip under test is read and written according to the maximum address range and the preset address interval; The actual capacity of the chip under test is determined based on the read and write results.

8. A chip testing device, characterized in that, The chip testing device includes: The acquisition module is used to acquire test instructions issued by the host computer, wherein the test instructions include attribute information, including the number, capacity and structure of the chips to be tested; The modification module is used to modify the parameters of the test device according to the test instructions to configure the corresponding test mode. The processing bit width of the test device is 64 bits. The test modes include single-channel test mode and dual-channel test mode. The single-channel test means that the test device tests the high 32 bits / low 32 bits of a single 32-bit chip under test or a single 64-bit chip under test. The dual-channel test means that the test device performs parallel testing on the high 32 bits and low 32 bits of two 32-bit chips under test or a single 64-bit chip under test. The testing module is used to test one or more chips to be tested connected to the testing device according to the test mode, and obtain test results.

9. A chip testing device, characterized in that, The chip testing equipment includes a memory and a processor coupled to the memory; The memory is used to store program data, and the processor is used to execute the program data to implement the chip testing method as described in any one of claims 1 to 7.

10. A computer storage medium, characterized in that, The computer storage medium is used to store program data, which, when executed by the computer, is used to implement the chip testing method as described in any one of claims 1 to 7.

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