Soundwire protocol-based synchronization word detection circuit, detection method and chip

Abstract

This invention discloses a synchronization word detection circuit, detection method, and chip based on the Soundwire protocol. The detection circuit includes an initial register and multiple transmission units. Each transmission unit includes multiple registers and selectors spaced apart. The input terminal of the first register of the downstream transmission unit and the second input terminals of all selectors are connected to the output terminal of the last register of the upstream transmission unit. The initial register is used to receive data. Based on the last register of each transmission unit and the output signal of the initial register, it is determined whether it is a synchronization word of a data frame in the Soundwire protocol. According to the synchronization word detection circuit, detection method, and chip based on the Soundwire protocol of this invention, data frame transmission is performed through the initial register and transmission units. The synchronization word of a data frame in the Soundwire protocol can be determined by the last register of each transmission unit and the output of the initial register, thus achieving fast and effective synchronization word detection.

Description

Technical Field

[0001] This invention belongs to the field of synchronization word detection technology, specifically relating to a synchronization word detection circuit, detection method, and chip based on the Soundwire protocol. Background Technology

[0002] MIPI Soundwire is a universal, comprehensive, and scalable digital audio interface protocol developed by the MIPI Audio Working Group (Alliance). It integrates many key features of mobile and PC audio interfaces and can be used to implement audio functions in a variety of devices.

[0003] The Soundwire protocol audio interface consists of one clock line and one or more data lines. The specific number of data lines in the interface is determined by the system bandwidth. For applications where the transmission speed is not particularly high, the Soundwire protocol audio interface only includes two physical signal lines: one clock line and one data line.

[0004] In traditional I2S audio protocol interfaces, the LRCK signal line is used as the frame delimiter, and each frame of data transmitted on the data line has a clear frame data boundary. The Soundwire protocol audio interface does not have a dedicated LRCK frame delimiter like in the I2S protocol interface. Instead, it extracts the frame boundary signal from the data. Therefore, in the Soundwire protocol, the data stream is sent in data frames with a specific organizational structure, and each data frame contains known data bits (data pattern) at a fixed location. This data pattern can be used to anchor the boundary of a frame.

[0005] A schematic diagram of a data frame in the Soundwire protocol is shown below. Figure 1a and Figure 1b As shown, Figure 1a and Figure 1b Two different frame structures are illustrated. Figure 1a It has a 64-row x 4-column frame structure. Figure 1b The frame structure is 50 rows x 8 columns, with command and control words filled in sections 1, 2, and 3, and payload data filled in the other sections. Regardless of the frame structure size, the position of the command and control word section of the data frame is the same, and its size is 48 (rows) x 1 (column).

[0006] The bit structure of the command control word in the data frame is as follows: Figure 2 As shown, an 8-bit static synchronization word is fixed at 10110001. The Soundwire protocol specifies that the data frame is transmitted to the bit stream as follows: Figure 1a and Figure 1bThe Z-shaped dashed line sequence with arrows reduces the impact of command control words on data transmission if several consecutive bit errors occur in the bit stream, but it also makes it difficult to detect frame synchronization words.

[0007] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0008] The purpose of this invention is to provide a synchronization word detection circuit, detection method and chip based on the Soundwire protocol, which can solve the problem of difficult synchronization word detection in data frames in the Soundwire protocol.

[0009] To achieve the above objectives, a specific embodiment of the present invention provides the following technical solution: a synchronization word detection circuit based on the Soundwire protocol, comprising: an initial register and multiple transmission units, each of the transmission units comprising multiple registers and selectors spaced apart, wherein the last position of the transmission unit is a register;

[0010] The output of each selector is connected to the input of an adjacent register, and the first input of the selector is connected to the output of another adjacent register.

[0011] The initial register and multiple transmission units are sequentially connected for data transmission. The input of the initial register is used to sample and receive bit data in the data frame of the Soundwire protocol based on the falling edge of the clock signal. The second input of all selectors of the first transmission unit that receives the data frame sent by the initial register and sends the data frame to the downstream adjacent transmission unit, as well as the input of its first register, are connected to the output of the initial register. The second input of all selectors of the transmission unit that receives the data frame sent by the upstream adjacent transmission unit and sends the data frame to the downstream adjacent transmission unit, as well as the input of its first register, are connected to the output of the last register of the upstream adjacent transmission unit. During the data frame transmission process, the output signal of the last register of each transmission unit and the initial register is used to confirm whether it is a synchronization word of the data frame in the Soundwire protocol.

[0012] In one or more embodiments of the present invention, the initial register and all registers are either falling-edge triggered registers or rising-edge triggers used after inverting the clock.

[0013] In one or more embodiments of the present invention, the synchronization word detection circuit further includes a control circuit, which is used to generate a control code based on the input signal and adjust the control code by an adjustment signal. The control terminal of the selector of each transmission unit is used to receive the control code to control the selection of the selector's path based on the control code.

[0014] In one or more embodiments of the present invention, the selectors between each transmission unit are in one-to-one correspondence, and the corresponding selectors receive the same control code. Under the control of the control code, the selector connects two adjacent registers, or if it is the selector of the first transmission unit, it connects the initial register with the register connected to its output terminal, or if it is the selector of the downstream transmission unit, it connects the last register of the upstream transmission unit with the register connected to its output terminal.

[0015] In one or more embodiments of the present invention, K transmission units are provided, and the selectors of the K transmission units are arranged in N rows * M columns, and the registers of the K transmission units are arranged in X rows * Y columns.

[0016] In one or more embodiments of the present invention, Y is 1 to 8.

[0017] In one or more embodiments of the present invention, X is 7.

[0018] In one or more embodiments of the present invention, seven transmission units are provided, and each transmission unit is provided with seven selectors and eight registers.

[0019] This invention also discloses a synchronization word detection method based on the Soundwire protocol. Based on the aforementioned synchronization word detection circuit, the detection method includes:

[0020] The number of registers that are active is controlled by a selector. The registers are triggered on the falling edge of the clock, and the number of active registers is sufficient to detect 2*m columns of data frames, where m is an integer ≥ 1.

[0021] The row counter increments by 1 every m falling edges of the clock cycle.

[0022] In real time, determine whether the output signal of the last bit register and the initial register of each transmission unit is the synchronization word of the data frame in the Soundwire protocol;

[0023] If the output signal of the last register of each transmission unit and the initial register is still not the synchronization word of the data frame in the Soundwire protocol when the count result of the row counter is the preset value, then the number of working registers is adjusted to detect data frames with different column numbers.

[0024] The present invention also discloses a chip, including the above-mentioned synchronization word detection circuit based on the Soundwire protocol.

[0025] Compared with the prior art, the synchronization word detection circuit, detection method and chip based on the Soundwire protocol of the present invention utilizes the transmission characteristics of data frames of the Soundwire audio protocol, transmits data frames through an initial register and multiple transmission units, and transmits data frames of different structures through the control of a selector. By using the last bit register of each transmission unit and the output of the initial register, it can be confirmed whether it is a synchronization word of the data frame in the Soundwire protocol, thus achieving fast and effective synchronization word detection. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1a This is a schematic diagram of the first structure of frame data in the existing Soundwire protocol.

[0028] Figure 1b This is a schematic diagram of the second structure of frame data in the existing Soundwire protocol.

[0029] Figure 2 This is a schematic diagram of the command control word structure for frame data in the existing Soundwire protocol.

[0030] Figure 3 This is an array diagram corresponding to a 50-row × 16-column data frame in one embodiment of the present invention.

[0031] Figure 4 In one embodiment of the present invention, and Figure 3 The array diagram corresponding to the bits latched by the falling edge of the clock.

[0032] Figure 5 In one embodiment of the present invention, and Figure 4 The array diagram in which the synchronization word of the command control word and the row where the synchronization word is located are located.

[0033] Figure 6 This is a circuit diagram of a synchronization word detection circuit based on the Soundwire protocol in one embodiment of the present invention.

[0034] Figure 7This is a circuit diagram of the control circuit of the synchronization word detection circuit based on the Soundwire protocol in one embodiment of the present invention. Detailed Implementation

[0035] To enable those skilled in the art to better understand the technical solutions in this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this disclosure.

[0036] The terms "coupled," "connected," or "linked" in the specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrical conduction medium, which may have parasitic inductance or capacitance. Indirect connections may also include connections made through other active or passive devices to achieve the same or similar functional purpose, such as connections through switches, follower circuits, or other circuits or components. Furthermore, in the invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another, and do not necessarily require or imply any actual relationship, quantity, or order between these technical features.

[0037] In the detailed description of this specification, reference is made to the accompanying drawings, which form a part thereof, wherein like reference numerals always denote like parts, and wherein exemplary embodiments are shown by way of example that may be implemented. It should be understood that other embodiments may be utilized, and structural or logical changes may be made, without departing from the scope of this disclosure. Therefore, the following detailed description should not be considered limiting.

[0038] The various operations in the specification may be described sequentially as multiple discrete actions or operations in a manner most conducive to understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations must be sequentially related. Specifically, these operations may not be performed in the order presented. The described operations may be performed in a different order than in the described embodiments. Various additional operations may be performed in additional embodiments and / or the described operations may be omitted.

[0039] For the purposes of this disclosure, the phrase “A and / or B” means (A), (B), or (A and B). For the purposes of this disclosure, the phrase “A, B and / or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0040] Various components and devices may be referred to or shown in the singular (e.g., “transistor”, “transistor”, “switch”, etc.) in this document, but only for the convenience of discussion, and any element referred to in the singular may include multiple such elements as taught herein.

[0041] The description uses the phrases "in one embodiment," "in other embodiments," or "in some embodiments," each of which may refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," etc., used with respect to embodiments of this disclosure are synonymous.

[0042] The Soundwire audio protocol interface uses DDR (double data rate) transmission, transmitting one bit of data every half clock cycle and two bits of data every clock cycle. According to the Soundwire audio protocol, the number of columns in a Soundwire data frame is always an even number between 2 and 16, and the first bit of a data frame is always transmitted on the falling edge of the clock. Therefore, all bits of the command control word are transmitted on the falling edge of the clock.

[0043] According to the above characteristics specified in the protocol, all bits in a data frame are divided into two categories: bits transmitted starting from the falling edge and bits transmitted starting from the rising edge. For example... Figure 3 The image shows a 50x16 Soundwire data frame. If A10 corresponds to the first bit of the Soundwire data frame and B507 corresponds to the last bit, then the first column (A10, A20, A30...A500) corresponds to the first column of data in the frame. Each shaded cell corresponds to a bit transmitted on the falling edge, and each blank cell corresponds to a bit transmitted on the rising edge. Figure 4 The diagram shows how all bits transmitted on the falling edge are extracted and grouped into a 50-row × 8-column data frame. In this data frame, all bits are transmitted on the falling edge. According to the Soundwire protocol, the 48-bit command control word is placed in rows 1 to 48 of the first column of the Soundwire data frame, and the static synchronization word in the command control word is bits 25 to 32 of the 48-bit command control word. Figure 5 What is shown is that from Figure 4 The row containing the static synchronization word in the command control word is extracted to form an 8-row × 8-column data frame. A240, A250, A260, A270, A280, A290, A300, and A310 correspond to each bit of the static synchronization word, which is 10110001.

[0044] In order to detect synchronization words, such as Figure 6As shown, an embodiment of the present invention discloses a synchronization word detection circuit based on the Soundwire protocol, including: an initial register A310 and multiple transmission units.

[0045] Each transmission unit includes multiple registers and selectors spaced apart, with the register located at the end of the transmission unit. In one embodiment, the register may also be located at the beginning of the transmission unit. Each register stores one bit. The output of each selector is connected to the input of an adjacent register, and the first input of the selector is connected to the output of another adjacent register.

[0046] The initial register A310 is sequentially connected to multiple transmission units for data transmission. The input of the initial register A310 is used to receive data bits sampled on the falling edge of the clock received from the Soundwire interface. The second input of all selectors of the first transmission unit that receives the bit data of the data frame sent from the initial register A310 and sends the bit data of the data frame to the downstream adjacent transmission unit, as well as the input of its first register, are connected to the output of the initial register A310. The second input of all selectors of the transmission unit that receives the bit data of the data frame sent from the upstream adjacent transmission unit and sends the bit data of the data frame to the downstream adjacent transmission unit, as well as the input of its first register, are connected to the output of the last register of the upstream adjacent transmission unit. During data frame transmission, the output signal of the last register of each transmission unit and the initial register A310 are used to confirm whether it is a synchronization word of the data frame in the Soundwire protocol.

[0047] In one embodiment, the initial register A310 and all registers are falling-edge triggered registers. In other embodiments, rising-edge triggered registers can also be used, but the clock needs to be inverted using an inverter or other circuitry before being used in the rising-edge triggered registers. There are K transmission units, with the selectors for the K transmission units arranged in N rows * M columns, and the registers for the K transmission units arranged in X rows * Y columns. K, N, M, X, and Y are all positive integers. Y is any integer between 1 and 8. X is 7.

[0048] like Figure 7 As shown, the synchronization word detection circuit also includes a control circuit 2. The control circuit 2 is used to generate a control code col_cel<6:0> based on the input signal and to adjust the control code through an adjustment signal. The control terminal of the selector of each transmission unit is used to receive the control code and control the selection of the selector's path based on the control code.

[0049] Each transmission unit has a one-to-one correspondence with its selectors, and the corresponding selectors receive the same control code. Under the control of the control code, the selector connects two adjacent registers, or if it is the selector of the first transmission unit, it connects the initial register A310 with the register connected to its output terminal; if it is the selector of a downstream transmission unit, it connects the last register of the upstream transmission unit with the register connected to its output terminal. The synchronization word detection circuit also includes a receive detection circuit, which is used to receive the output signal of the last register of each transmission unit and the initial register A310 for synchronization word detection.

[0050]

[0051] The table above is the correspondence table in the Soundwire protocol. In this table, the column control corresponds to the adjustment signal, which can be 0~7. The number of columns corresponds to the total number of columns in the data frame (including bits transmitted on the rising and falling edges). The column address corresponds to the number of columns, and the number of columns also corresponds to the adjustment signal. An adjustment signal of 0 can be considered as detecting a data frame structure with 2 columns, and an adjustment signal of 7 can be considered as detecting a data frame structure with 16 columns.

[0052] In one embodiment, such as Figure 6 As shown, taking an example where each transmission unit has 7 selectors and 8 registers, there are 7 transmission units: 2a, 2b, 2c, 2d, 2e, 2f, and 2g. The selectors for these 7 transmission units are arranged in a 7x7 grid, and the registers are arranged in a 7x8 grid. In other embodiments, the number of transmission units, selectors, and registers can be increased or decreased as needed.

[0053] The first transmission unit 1a transmits data to the downstream adjacent transmission unit 1b, transmission unit 1b transmits data to the downstream adjacent transmission unit 1c, and so on, until the downstreammost transmission unit 1g. For example, in transmission unit 1a, selectors are provided between registers A307 and A306, between registers A306 and A305, between registers A305 and A304, between registers A304 and A303, between registers A303 and A302, between registers A302 and A301, and between registers A301 and A300. The first input of each selector is connected to the output of the adjacent register, and the output of each selector is connected to the input of another adjacent register. The remaining transmission units are configured similarly.

[0054] Register A307 is located at the beginning of transmission unit 1a. The input of register A307 and the second input of all selectors in transmission unit 1a are connected to the output of initial register A310 to receive the bits output by initial register A310. Register A297 is located at the beginning of transmission unit 1b. The input of register A297 and the second input of all selectors in transmission unit 1b are connected to the output of register A300, located at the end of transmission unit 1a, to receive the bits output by register A300. Register A287 is located at the beginning of transmission unit 1c. The input of register A287 and the second input of all selectors in transmission unit 1c are connected to the output of register A290, located at the end of transmission unit 1b, to receive the bits output by register A290. And so on. Register A247 is located at the beginning of transmission unit 1g. The input of register A247 and the second input of all selectors in transmission unit 1g are connected to the output of register A250, located at the end of transmission unit 1f, to receive the bits output by register A250.

[0055] The initial register A310 and the last bits of all transmission units 1a, 1b, 1c, 1d, 1e, 1f, and 1g, namely the registers A300, A290, A280, A270, A260, A250, and A240, output the corresponding bits.

[0056] In all transmission units, the control terminal of the selector located in the same column (one-to-one correspondence) receives one control code, and the seven-column selector receives seven control codes col_sel[0], col_sel[1], col_sel[2], col_sel[3], col_sel[4], col_sel[5], and col_sel[6]. The seven-bit input signal causes control circuit 2 to output a seven-bit control code col_cel<6:0>. The seven-bit control code col_cel<6:0> is adjusted by adjusting the input signal. For example, if the adjustment signal is 0, the seven-bit control code col_cel<6:0> is 0000001; if the adjustment signal is 1, the seven-bit control code col_cel<6:0> is adjusted to 0000010; if the adjustment signal is 2, the seven-bit control code col_cel<6:0> is adjusted to 0000100... If the adjustment signal is 6, the seven-bit control code col_cel<6:0> is adjusted to 1000000; if the adjustment signal is 7, the seven-bit control code col_cel<6:0> is adjusted to 0000000.

[0057] If all seven control codes col_sel[0], col_sel[1], col_sel[2], col_sel[3], col_sel[4], col_sel[5], and col_sel[6] are 0, then the first input terminal and the output terminal of all selectors are connected, that is, the adjacent registers on both sides of the selector are connected. When one of the seven control codes is 1, the second input terminal of the selector controlled by that control code is connected to its output terminal. At this time, the bits received by the register connected to the output terminal of that selector are sent from the register connected to the second input terminal of that selector. It can be understood that the selector is switched by the control of the control code that is 1, so that the registers connected to the first input terminal of that selector are shielded, thereby controlling the number of registers that work normally in the circuit.

[0058] If all seven control codes col_sel[0], col_sel[1], col_sel[2], col_sel[3], col_sel[4], col_sel[5], and col_sel[6] are 0, Figure 6 The detection circuit shown can detect a 16-column data frame structure. The initial register A310 receives input data (i.e., the data frame of the Soundwire audio protocol). When the first falling edge of the clock arrives, the initial register A310 works to receive and latch one bit of the data frame. When the rising edge of the clock arrives, the initial register A310 does not work, and the next bit of the data frame will not be received by the initial register A310. When the second falling edge of the clock arrives, the initial register A310 transfers one bit of the previously latched data frame to register A307 for latching. At the same time, the initial register A310 works to receive and latch the next bit of the data frame, and so on. Under the control of the falling edge of the clock, the data frame is transmitted. When registers A240, A250, A260, A270, A280, A290, A300 and the initial register A310 output 10110001, it indicates that the detection circuit has indeed detected a 16-column data frame structure.

[0059] The selector that controls each column can achieve the function of shielding. By adjusting the seven control codes col_sel[6], col_sel[5], col_sel[4], col_sel[3], col_sel[2], col_sel[1], and col_sel[0], the structure of the data frame that the detection circuit can detect can be adjusted. Specifically, for example, if col_sel[6], col_sel[5], col_sel[4], col_sel[3], col_sel[2], col_sel[1], col_sel[0] are 0000001 (just pay attention to the first 1 encountered from right to left, this 1 plays a decisive role, and it doesn't matter whether the signal after this 1 is 1 or 0), then the detection circuit can detect a 2-column data frame structure... If col_sel[6], col_sel[5], col_sel[4], col_sel[3], col_sel[2], col_sel[1], col_sel[0] are 0000100, then the detection circuit can detect a 6-column data frame structure; if col_sel[6], col_sel[5 ... If l[4], col_sel[3], col_sel[2], col_sel[1], and col_sel[0] are 0001000, then the detection circuit can detect 8 columns of data frame structure... If col_sel[6], col_sel[5], col_sel[4], col_sel[3], col_sel[2], col_sel[1], and col_sel[0] are 1000000, then the detection circuit can detect 14 columns of data frame structure; if col_sel[6], col_sel[5], col_sel[4], col_sel[3], col_sel[2], col_sel[1], and col_sel[0] are 0000000, then the detection circuit can detect 16 columns of data frame structure.

[0060] If a detection circuit capable of detecting 10 columns of data frame structure is used to detect data frame structure with other column numbers, it will be impossible to detect because registers A240, A250, A260, A270, A280, A290, A300 and initial register A310 cannot accurately output 10110001. Since it is not known at the beginning how many columns of data frame structure need to be detected, it may be necessary to continuously adjust the seven control codes col_sel[0], col_sel[1], col_sel[2], col_sel[3], col_sel[4], col_sel[5], and col_sel[6] so that registers A240, A250, A260, A270, A280, A290, A300 and initial register A310 can output 10110001, thereby finding the data frame structure synchronization word.

[0061] This invention also discloses a synchronization word detection method based on the Soundwire protocol. Based on the aforementioned synchronization word detection circuit, the detection method includes:

[0062] The number of registers that are active is controlled by a selector. The registers are triggered on the falling edge of the clock, and the number of active registers is sufficient to detect 2*m columns of data frames, where m is an integer ≥ 1.

[0063] The row counter increments by 1 every m falling edges of the clock cycle.

[0064] In real time, determine whether the output signal of the last bit register and the initial register of each transmission unit is the synchronization word of the data frame in the Soundwire protocol;

[0065] If the output signal of the last register of each transmission unit and the initial register is still not the synchronization word of the data frame in the Soundwire protocol when the count result of the row counter is the preset value, then the number of working registers is adjusted to detect data frames with different column numbers.

[0066] Specifically, according to the Soundwire protocol, a Soundwire data frame has a maximum of 256 rows and an even number of columns between 2 and 16. Therefore, the seven control codes during the detection process can be adjusted based on this prerequisite. During detection, since the actual number of rows and columns of the received data frame bitstream is unknown beforehand, the data frame structure is determined through polling. The specific process is as follows: Since the number of columns in a Soundwire data frame is an even number between 2 and 16, the detection circuit can be fixed to detect a data frame structure of 2*m columns (generally, m is initially set to 1). At the start of detection, the built-in row counter is cleared to 0. Every m falling edges of the clock cycle, the row counter is incremented by 1. During detection, the built-in row counter only needs to reach a maximum of 256+x rows to determine whether the current fixed 2*m column data frame has the same number of columns as the data frame represented by the received data bit stream (256+x rows are actually equivalent to (256+x)*m falling edges). x is a redundancy amount that can be 8 or other numbers. Setting x is to prevent the detection from starting from the row where a certain bit of the synchronization word is located. If the number of falling edges is only calculated based on 256 rows, the detection may not be complete in one round. Setting x ensures that the rows where the synchronization word is located are also detected. If the correct synchronization word is not detected after continuously detecting 256+x lines, the detection circuit increases the number of detection columns by adjusting the seven control codes. Under the new column count, it re-detects 256+x lines, polling all possible frame columns from 2 to 16 in this way. If the synchronization word is detected before reaching 256+x lines, the line counter is reset to 0, and detection continues. The next time the correct synchronization word is detected, the number of lines in the built-in line counter between two consecutive correct synchronization word detections represents the actual number of lines in the data frame represented by the received bitstream.

[0067] The present invention also discloses a chip, including the above-mentioned synchronization word detection circuit based on the Soundwire protocol.

[0068] It will be apparent to those skilled in the art that this disclosure is not limited to the details of the exemplary embodiments described above, and that this disclosure can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of this disclosure is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this disclosure. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0069] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A Soundwire protocol based sync word detection circuit, characterized in that, include: An initial register and multiple transmission units, each of the transmission units including multiple registers and selectors spaced apart, with the last position of the transmission unit being a register; The output of each selector is connected to the input of an adjacent register, and the first input of the selector is connected to the output of another adjacent register. The initial register and multiple transmission units are sequentially connected for data transmission. The input of the initial register is used to receive data frames in the Soundwire protocol. The second input of all selectors of the first transmission unit that receives data frames sent from the initial register and sends data frames to the downstream adjacent transmission unit, as well as the input of its first register, are connected to the output of the initial register. The second input of all selectors of the transmission unit that receives data frames sent from the upstream adjacent transmission unit and sends data frames to the downstream adjacent transmission unit, as well as the input of its first register, are connected to the output of the last register of the upstream adjacent transmission unit. During data frame transmission, the output signal of the last register of each transmission unit and the initial register is used to confirm whether it is a synchronization word of the data frame in the Soundwire protocol. Each of the transmission units has a one-to-one correspondence between selectors, and the corresponding selectors receive the same control code. Under the control of the control code, the selector connects two adjacent registers, or if it is the selector of the first transmission unit, it connects the initial register with the register connected to its output terminal, or if it is the selector of the downstream transmission unit, it connects the last register of the upstream transmission unit with the register connected to its output terminal.

2. The Soundwire protocol-based sync word detection circuit of claim 1, wherein, The initial register and all registers are falling-edge triggered registers.

3. The Soundwire protocol-based sync word detection circuit of claim 1, wherein, The synchronization word detection circuit also includes a control circuit, which is used to generate a control code based on the input signal and adjust the control code by an adjustment signal. The control terminal of the selector of each transmission unit is used to receive the control code and control the selection of the selector's path based on the control code.

4. The synchronization word detection circuit based on the Soundwire protocol according to claim 1, characterized in that, There are K transmission units, and the selectors of the K transmission units are arranged in N rows * M columns, and the registers of the K transmission units are arranged in X rows * Y columns.

5. The synchronization word detection circuit based on the Soundwire protocol according to claim 4, characterized in that, The value of Y is 1 to 8.

6. The synchronization word detection circuit based on the Soundwire protocol according to claim 4, characterized in that, The value of X is 7.

7. The synchronization word detection circuit based on the Soundwire protocol according to claim 1, characterized in that, There are 7 transmission units, and each transmission unit is equipped with 7 selectors and 8 registers.

8. A synchronization word detection method based on the Soundwire protocol, characterized in that, Based on the synchronization word detection circuit as described in any one of claims 1 to 7, the detection method includes: The number of registers that are active is controlled by a selector. The registers are triggered on the falling edge of the clock, and the number of active registers is sufficient to detect 2*m columns of data frames, where m is an integer ≥ 1. The row counter increments by 1 every m falling edges of the clock cycle. In real time, determine whether the output signal of the last bit register and the initial register of each transmission unit is the synchronization word of the data frame in the Soundwire protocol; If the output signal of the last register of each transmission unit and the initial register is still not the synchronization word of the data frame in the Soundwire protocol when the count result of the row counter is the preset value, then the number of working registers is adjusted to detect data frames with different column numbers.

9. A chip, characterized in that, Includes the synchronization word detection circuit based on the Soundwire protocol as described in any one of claims 1 to 7.

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