Digital compensation operation circuit and polynomial compensation method thereof

Abstract

This invention discloses a digital compensation operation circuit and its polynomial compensation method, comprising a state control module, a shared operation data link, data selection and routing logic, a first parameter storage module, and a second parameter storage module. The state control module receives clock signals and start signals, and generates a state code that progresses over time and a sub-cycle count value in each compensation cycle. The shared operation data link includes a multiplier, a divider, and several addition and subtraction logic units. The first parameter storage module stores a temperature digital code, preset polynomial coefficients, and operation constants. The second parameter storage module stores intermediate values ​​and operation results for each step of the polynomial compensation method. The data selection and routing logic couples the state control module, the first parameter storage module, the second parameter storage module, and the shared operation data link. In this embodiment, high-precision real-time frequency temperature compensation and control are achieved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a digital compensation operation circuit and its polynomial compensation method. Background Technology

[0002] The clock is the "heart" of digital circuits. Almost all electronic devices in today's society rely on high-precision, stable clock sources, which in turn depend on quartz crystals to generate clock signals with a fixed oscillation frequency. For example... Figure 1 The image shows a Pierce oscillator circuit, a commonly used oscillator circuit in industry. This oscillator consists of an inverting amplifier and a large-value feedback resistor. R F And a quartz crystal resonator and two load capacitors. C L1 , C L2 The circuit is composed of a π-type frequency-selective network. This circuit satisfies the Barkhausen criterion, and the load resonant frequency is... f osc The dependence on the load capacitance can be approximated as follows: ; in, C L This represents the total equivalent capacitance seen at both ends of the crystal. C 0 and C 1 represents the parallel and series capacitance of the quartz crystal. f s The series resonant frequency of a quartz crystal.

[0003] However, quartz crystals are often significantly affected by temperature, exhibiting varying degrees of frequency shift at different temperatures. To obtain high-precision clock signals over a wide temperature range, the industry typically employs temperature-compensated crystal oscillators (TCXOs), which adjust the CL value at different temperatures. L This value ensures that fosc remains stable at the nominal frequency. Based on different compensation methods, existing solutions are divided into three main categories: analog temperature-compensated crystal oscillators (ATCXO), digital temperature-compensated crystal oscillators (DTCXO), and microcontroller temperature-compensated crystal oscillators (MTCXO).

[0004] ATCXOs utilize a thermistor network to generate a compensation voltage to drive a varactor diode. While offering low power consumption, they struggle to precisely match the high-order nonlinear characteristics of the crystal and are susceptible to process variations (PVT), limiting their accuracy in mass production. MTCXOs, on the other hand, can achieve extremely high compensation accuracy through complex floating-point operations, but their milliampere-level power consumption and long startup time prevent them from being universally applicable to electronic devices with low power consumption requirements.

[0005] In contrast, the DTCXO regulates the load capacitance C by switching the capacitor array (CDAC). L This makes it easier to achieve low-power designs. Traditional digital temperature-compensated frequency control chip architectures, such as... Figure 2 As shown, a lookup table (LUT) architecture is used. This involves pre-measuring the frequency deviation of the crystal at various temperature points, calculating the corresponding compensation capacitor control word, and storing this data in on-chip non-volatile memory (NVM, such as EEPROM or Flash). During operation, the circuit retrieves the compensation parameters from the table based on the sampled values ​​from the temperature sensor.

[0006] However, this traditional DTCCXO architecture based on lookup tables requires extremely high temperature resolution to achieve high-precision compensation (e.g., error less than ±5ppm over the entire temperature range). This means the lookup table needs to store a massive amount of calibration data points. This not only occupies a huge chip area and increases manufacturing costs, but also significantly increases the static leakage power consumption of the circuit. Furthermore, the data in the lookup table is "dead data" fixed for specific crystal characteristics. When a crystal batch change causes a slight change in the temperature coefficient (such as the parabolic vertex temperature or curvature constant), the entire lookup table must be retested and reprogrammed, resulting in high production and maintenance costs.

[0007] While some existing improvement schemes attempt to reduce the size of the LUT by introducing interpolation algorithms, they often employ large-scale serial or parallel logic circuits without optimizing the reuse of arithmetic units, resulting in persistently high dynamic power consumption and a large number of logic gates. Therefore, there is an urgent need for a digital temperature compensation technology that abandons large-capacity lookup tables, uses efficient algorithms to perform real-time hardware-based calculation of compensation parameters, and simultaneously meets the requirements of high precision, small area, and ultra-low power consumption. Summary of the Invention

[0008] The purpose of this invention is to overcome the shortcomings of the prior art. This invention provides a digital compensation operation circuit and its polynomial compensation method to achieve high-precision real-time frequency and temperature compensation and control.

[0009] To address the aforementioned technical problems, this invention provides a digital compensation operation circuit, which is a time-division multiplexing architecture, including a state control module, a shared operation data link, data selection and routing logic, a parameter storage module one, and a parameter storage module two. The state control module is used to receive clock signals and start signals, and generate a state code and sub-cycle count value that progress over time in each compensation cycle. The shared computing data link includes a configurable multiplier, a configurable divider, and several addition and subtraction logic units. The parameter storage module is used to store the temperature digital code input from the ADC, preset polynomial coefficients, and operation constants; The parameter storage module 2 is used to store the intermediate values ​​and results of each step of the polynomial compensation method. The data selection and routing logic is used to couple the state control module, the parameter storage module one, the parameter storage module two, and the shared computation data link; The state control module is configured to, based on the sub-cycle count value, control the data selection and routing logic to send the intermediate values ​​of the operation in the parameter storage module two and / or the polynomial coefficients and operation constants of the parameter storage module one to the input end of the shared operation data link in a time-division manner within different clock sub-cycles. Within a single compensation cycle, the multiplier or divider is used sequentially to complete the calculation of temperature normalization, frequency deviation calculation, load resonant frequency calculation, series resonant frequency calculation, and target load capacitance value, and the calculation results are stored in the parameter storage module two.

[0010] Optionally, the shared computing data link adopts a fixed-point number format computing logic, which includes a sign bit, an integer bit, and a fractional bit; the bit width of the fractional bit satisfies a frequency resolution on the order of one million branches. The parameter storage module one and the parameter storage module two pre-store the polynomial coefficients, operation constants and intermediate values ​​in the fixed-point number format.

[0011] Optionally, the state control module consists of a finite state machine and a counter, and the calculation steps of the digital compensation circuit include: When the state control module detects the start signal, it controls the parameter storage module to input the temperature digital code into the shared computing data link, and controls the shared computing data link to convert the temperature digital code into Q17.20 fixed-point number format, and then converts the temperature digital code into a temperature value in the Celsius range by right shift, division operation and subtraction operation in sequence. The shared computation data link performs frequency offset calculation processing at the current temperature based on the nth degree polynomial coefficients of the crystal frequency-temperature characteristics stored in the parameter storage module one, and obtains the frequency offset data at the current temperature; The load resonant frequency at the current temperature is calculated based on the frequency offset data, and the series resonant frequency of the crystal at the current temperature is obtained by calculating the load resonant frequency. The target load capacitance value is obtained by using the series resonant frequency formula based on the Pierce oscillator.

[0012] Optionally, the step of converting the temperature digital code into a temperature value in the Celsius range by sequentially performing right shift, division, and subtraction operations includes: By using the Q17.20 fixed-point number format, shifting it right by 5 bits, and then performing a division operation by a constant 32, the result is subtracted by a constant 45 in the subtractor to convert the temperature digital code into a temperature value in the Celsius range.

[0013] Optionally, the step of calculating the load resonant frequency at the current temperature based on the frequency offset data, and obtaining the series resonant frequency of the crystal at the current temperature through the load resonant frequency, includes: The state control module inputs the decimal places and the nominal frequency to the input terminal of the multiplier during the N+0th sub-cycle. During the (N+1)th sub-cycle, the multiplication result is temporarily stored in the intermediate value of the second parameter storage module, and the frequency offset data at the current temperature is temporarily stored for later use. In the (N+2)th sub-cycle, the nominal frequency and the frequency offset data are added together to obtain the load resonant frequency at the current temperature; The shared computational data link retrieves the scaling factor between the load resonant frequency and the series resonant frequency from the parameter storage module one, and inputs the scaling factor and the load resonant frequency into the multiplier to output the series resonant frequency of the crystal at the current temperature.

[0014] Optionally, the load resonant frequency formula based on the Pierce oscillator uses the series resonant frequency to calculate the target load capacitance value, thereby obtaining the target load capacitance value, including: In the (N+3)th sub-cycle, the state control module inputs twice the load resonant frequency to the dividend terminal of the divider and inputs the series resonant frequency to the divisor terminal of the divider. In the (N+4)th sub-cycle, the first division result output by the divider is subtracted by a fixed constant 2, and the subtraction result is temporarily stored in the intermediate value of the second parameter storage module. In the (N+5)th sub-cycle, the parameter value of the series capacitor is input to the dividend terminal of the divider, the subtraction result is input to the divisor terminal of the divider, and the divider outputs the second division result; In the (N+6)th sub-cycle, the parameter value of the series capacitor is subtracted from the result of the second division to output the target load capacitance value.

[0015] Optionally, the bit width of the temperature digital code is determined by the bit width output of the analog-to-digital converter in the digital temperature compensation frequency control chip used by the digital compensation calculation circuit, to meet the frequency resolution requirement of one part per million. The output bit width of the analog-to-digital converter in the digital temperature compensation frequency control chip, which is used by the digital compensation operation circuit, and the temperature measurement range of the temperature sensor in degrees Celsius are determined sequentially by right shift, division, and subtraction operations.

[0016] Optionally, the operational constants stored in the parameter storage module are generated by the tuning fork quartz crystal in the real-time clock chip. The Pierce oscillator composed of the tuning fork quartz crystal outputs a clock signal with a frequency of 32.768kHz. Its frequency deviation-temperature curve has an n value of 2, a quadratic term coefficient of -0.04, a linear term coefficient of 2, a constant term of -25, and a static capacitance of C0 = 1.3pF and a dynamic capacitance of C1 = 2fF, forming the operational constants.

[0017] In addition, embodiments of the present invention also provide a polynomial compensation method for a digital temperature-compensated frequency control chip, applying the digital compensation arithmetic circuit described above, the method comprising: The input temperature code is processed using a preset formula to obtain the current temperature value corresponding to the Celsius range; Based on the current temperature value, frequency offset calculation is performed using polynomial coefficients to obtain frequency offset data at the current temperature. The load resonant frequency of the Pierce oscillator at the current temperature is calculated based on the frequency offset data at the current temperature. The series resonant frequency at the current temperature is calculated based on the load resonant frequency of the Pierce oscillator at the previous temperature, the parallel capacitance, the series capacitance, and the nominal load capacitance. Using the load resonant frequency as the target frequency, the target load capacitance value is obtained by deriving and calculating the load resonant frequency formula of the Pierce oscillator based on the series resonant frequency at the current temperature and the target frequency.

[0018] Optionally, the frequency offset calculation based on the current temperature value using polynomial coefficients is an nth-degree polynomial of the crystal frequency offset-temperature coefficient in the digital temperature compensation frequency control chip used by the digital compensation operation circuit; the formula for the load resonant frequency of the Pierce oscillator is the relationship between the load resonant frequency and the load capacitance value corresponding to the Pierce oscillator.

[0019] In this embodiment of the invention, the massive lookup table (LUT) storage array in traditional DTCCXOs is abandoned. Compensation parameters are calculated in real time through arithmetic logic. Furthermore, a time-division multiplexing (TDM) architecture is adopted in the circuit implementation, using a state machine to control a single multiplier and divider to work in a time-sharing manner, avoiding the stacking of hardware resources, greatly saving the number of digital logic gates and significantly reducing the chip area. Due to the significant reduction in hardware logic scale and memory read / write operations, the static leakage power consumption of the circuit is significantly reduced. At the same time, the optimized five-step operation process makes the single compensation calculation cycle extremely short, reducing dynamic power consumption, which is suitable for IoT and RTC applications that are extremely sensitive to power consumption. The frequency offset-temperature curve of the crystal is fitted by an nth-order polynomial, which has higher fitting accuracy than the discrete lookup table method. In addition, by modifying the polynomial coefficients in parameter storage module one, it can be adapted to quartz crystals of different batches or different cut angles without redesigning the circuit or burning a large-scale data table, which has strong engineering adaptability. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a structural diagram of a conventional Pierce oscillator in an embodiment of the present invention; Figure 2 This is a traditional digital temperature compensation frequency control chip architecture in the embodiments of the present invention; Figure 3 This is a schematic diagram of the structure of the digital compensation operation circuit in an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of the multiplication and division operation units in an embodiment of the present invention; Figure 5 This is a circuit diagram illustrating the temperature value calculation in an embodiment of the present invention. Figure 6 This is a circuit diagram illustrating the calculation of frequency offset data in an embodiment of the present invention. Figure 7 This is an execution circuit diagram for calculating the target load capacitance value in an embodiment of the present invention; Figure 8 This is a flowchart illustrating a polynomial compensation method for a digital temperature-compensated frequency control chip according to an embodiment of the present invention. Detailed Implementation

[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] Example 1, please refer to Figure 3 , Figure 3 This is a schematic diagram of the structure of the digital compensation operation circuit in an embodiment of the present invention.

[0024] like Figure 3 As shown, the digital compensation operation circuit is a time-division multiplexing architecture, including a state control module, a shared operation data link, data selection and routing logic, parameter storage module one, and parameter storage module two; The state control module is used to receive clock signals and start signals, and generate a state code and sub-cycle count value that progress over time in each compensation cycle. The shared computing data link includes a configurable multiplier, a configurable divider, and several addition and subtraction logic units. The parameter storage module is used to store the temperature digital code input from the ADC, preset polynomial coefficients, and operation constants; The parameter storage module 2 is used to store the intermediate values ​​and results of each step of the polynomial compensation method. The data selection and routing logic is used to couple the state control module, the parameter storage module one, the parameter storage module two, and the shared computation data link; The state control module is configured to, based on the sub-cycle count value, control the data selection and routing logic to send the intermediate values ​​of the operation in the parameter storage module two and / or the polynomial coefficients and operation constants of the parameter storage module one to the input end of the shared operation data link in a time-division manner within different clock sub-cycles. Within a single compensation cycle, the multiplier or divider is used sequentially to complete the calculation of temperature normalization, frequency deviation calculation, load resonant frequency calculation, series resonant frequency calculation, and target load capacitance value, and the calculation results are stored in the parameter storage module two.

[0025] The state control module is the control core of the entire digital compensation operation circuit, consisting of a finite state machine and a sub-cycle counter. The state control module receives the system clock signal (clk, for example, 32.768kHz) and the start signal (start), and generates the state code (state) of the current calculation step and the specific sub-cycle count value (cycle_cnt).

[0026] Parameter storage module one is used to store the 12-bit digital temperature code input from the ADC, the fixed coefficients and operation constants required for polynomial calculation; in this embodiment, the stored parameters include the quadratic term coefficient A2, the linear term coefficient A1, the constant term C, the series resonance-load resonance frequency proportionality coefficient, and the load capacitance calculation constant, etc.

[0027] Parameter storage module two is used to store the intermediate values ​​and results of each step of the polynomial compensation method.

[0028] Shared computation data link: This is the core innovation of this embodiment, aiming to minimize hardware area. This shared computation data link does not employ a pipelined structure, but instead includes a unique configurable multiplier, a unique configurable divider, and several addition and subtraction logic operations. To ensure that the unique configurable multiplier and the unique configurable divider do not expand or lose data precision during the compensation computation cycle, shifting or truncation processing is performed before and after them. The multiplication and division operation units are as follows: Figure 4 As shown.

[0029] The data selection and routing logic is coupled to the state control module, parameter storage module 1, parameter storage module 2, and shared computational data link. The data selection and routing logic is actually a set of multiplexers that dynamically transmit different data (temperature variables, intermediate calculation results, or fixed coefficients) to the input of the multiplier or divider according to the instructions issued by the state control module.

[0030] In this embodiment, to achieve high-precision arithmetic in digital logic while avoiding the significant overhead of a floating-point arithmetic unit, the entire data path uses Q17.20 format fixed-point two's complement for arithmetic operations. That is, the data bit width is 37 bits, where the highest bit is the sign bit, the next 16 bits are the integer bits, and the lower 20 bits are the fractional bits. This format can provide approximately 10... -6 With a computational accuracy on the order of ±1ppm, it fully meets the frequency compensation requirements of DTCXO.

[0031] In the specific implementation of this invention, the shared computation data link adopts the computation logic of fixed-point number format, which includes a sign bit, an integer bit, and a decimal bit; the bit width of the decimal bit satisfies the frequency resolution of one million branches; the parameter storage module one and the parameter storage module two pre-store the polynomial coefficients, operation constants, and intermediate values ​​of the operation in the fixed-point number format.

[0032] In a specific implementation of this invention, the state control module consists of a finite state machine and a counter, and the calculation steps of the digital compensation circuit include: When the state control module detects a start signal, it controls the parameter storage module to input a temperature digital code into the shared computing data link, and controls the shared computing data link to convert the temperature digital code into a Q17.20 fixed-point number format. Then, it sequentially performs right shift, division, and subtraction operations to convert the temperature digital code into a temperature value in the Celsius range. The shared computing data link performs frequency offset calculation processing at the current temperature based on the nth-order polynomial coefficients of the crystal frequency-temperature characteristic stored in the parameter storage module, obtaining frequency offset data at the current temperature. Based on the frequency offset data, it calculates the load resonant frequency at the current temperature, and uses the load resonant frequency to calculate the series resonant frequency of the crystal at the current temperature. Based on the Pierce oscillator's load resonant frequency formula, it uses the series resonant frequency to calculate the target load capacitance value, obtaining the target load capacitance value.

[0033] Furthermore, the step of converting the temperature digital code into a temperature value in the Celsius range by sequentially performing right shift, division, and subtraction operations includes: using the Q17.20 fixed-point number format, shifting right by 5 bits, performing a division operation by a constant 32, and subtracting a constant 45 from the result in the subtractor to convert the temperature digital code into a temperature value in the Celsius range.

[0034] Furthermore, the step of calculating the load resonant frequency at the current temperature based on the frequency offset data, and obtaining the series resonant frequency of the crystal at the current temperature through the load resonant frequency calculation, includes: the state control module inputting the decimal part and nominal frequency to the input terminal of the multiplier during the (N+0)th sub-cycle; temporarily storing the multiplication result in the intermediate value of the second parameter storage module during the (N+1)th sub-cycle, and temporarily storing the frequency offset data at the current temperature for later use; adding the nominal frequency and the frequency offset data during the (N+2)th sub-cycle to obtain the load resonant frequency at the current temperature; and the shared operation data link retrieving the proportional coefficient between the load resonant frequency and the series resonant frequency from the first parameter storage module, and inputting the proportional coefficient and the load resonant frequency into the multiplier to output the series resonant frequency of the crystal at the current temperature.

[0035] Furthermore, the load resonant frequency formula based on the Pierce oscillator uses the series resonant frequency to calculate the target load capacitance value, and obtains the target load capacitance value, including: in the (N+3)th sub-cycle, the state control module inputs twice the load resonant frequency to the dividend terminal of the divider and inputs the series resonant frequency to the divisor terminal of the divider; in the (N+4)th sub-cycle, the first division result output by the divider is subtracted by a fixed constant 2, and the subtraction result is temporarily stored in the intermediate value of the second parameter storage module; in the (N+5)th sub-cycle, the parameter value of the series capacitor is input to the dividend terminal of the divider, the subtraction result is input to the divisor terminal of the divider, and the divider outputs the second division result; in the (N+6)th sub-cycle, the second division result is subtracted from the parameter value of the series capacitor, and the target load capacitance value is output.

[0036] Furthermore, the bit width of the temperature digital code is determined by the bit width output of the analog-to-digital converter in the digital temperature compensation frequency control chip used by the digital compensation operation circuit, satisfying the frequency resolution requirement of one part per million; the bit width is determined by the output of the analog-to-digital converter in the digital temperature compensation frequency control chip used by the digital compensation operation circuit and the temperature measurement range of the temperature sensor in the Celsius domain through right shift, division operation and subtraction operation in sequence.

[0037] Furthermore, the operational constants stored in the parameter storage module are generated by the tuning fork quartz crystal in the real-time clock chip. The Pierce oscillator composed of the tuning fork quartz crystal outputs a clock signal with a frequency of 32.768kHz. Its frequency deviation-temperature curve has an n value of 2, a quadratic term coefficient of -0.04, a linear term coefficient of 2, a constant term of -25, and a static capacitance of C0 = 1.3pF and a dynamic capacitance of C1 = 2fF, forming the operational constants.

[0038] Specifically, in this embodiment, a tuning fork quartz crystal, commonly used in real-time clock chips, is employed. A Pierce oscillator composed of this crystal can output a clock signal at a frequency of 32.768 kHz, and its frequency deviation-temperature curve... n The value is 2, and the coefficient of the quadratic term is... -0.04 The coefficient of the linear term is 2 The constant term is -25 Its static capacitance C 0 =1.3pF Dynamic capacitor C 1 =2fF The aforementioned fixed constants are stored in parameter storage module one in advance for use during the compensation process.

[0039] The digital temperature compensation frequency control chip is used in conjunction with a temperature sensor and analog-to-digital converter to output a 12-bit temperature code. T code Temperature measurement range is-45℃ arrive 83℃ The relationship between the actual temperature and the temperature measurement code is as follows: ; When the state control module of the digital compensation arithmetic circuit detects the start signal, it controls the shared arithmetic data link and data selection and routing logic to begin the first step of calculation: converting the 12-bit temperature code into a Q17.20 format fixed-point number, and then... Figure 5 As shown, a division operation of 32 by right shifting by 5 bits is performed, followed by subtraction of the constant 45, finally yielding the temperature value in the Celsius range. T .

[0040] The second step of the calculation uses the frequency offset-temperature relationship polynomial for quartz crystals: ; Figure 6 The circuit diagram for the execution of the frequency offset-temperature relationship polynomial above shows that, in the first sub-cycle, the temperature value is processed through a shared computation data path and data selection and routing logic. T The input is fed into the unique multiplier input terminal; in the second sub-cycle, the multiplication result is temporarily stored in the intermediate value of the parameter storage module two, that is, the... T 2 The value is temporarily stored for later use; in the third sub-cycle, the coefficient of the quadratic term and... T 2 The input is fed into the unique multiplier input terminal; in the fourth sub-cycle, the multiplication result is temporarily stored in the intermediate value of the parameter storage module two, that is, the result is... A 2 T 2 Store temporarily for later use; in the fifth sub-cycle, sum the coefficients of the linear terms. T The input is fed into the unique multiplier input terminal, which is used for calculation. A 1 T The value; in the sixth sub-cycle A 2 T 2 , A 1 T and constant term C By accumulating the values, the frequency shift at the current temperature can be obtained. ppm .

[0041] Next, we proceed to the third step of the calculation: in the first sub-cycle... ppm The nominal frequency is input to the input terminal of the unique multiplier; in the second sub-cycle, the multiplication result is temporarily stored in the intermediate value of the second parameter storage module, that is, the frequency deviation value at the current temperature is temporarily stored for later use; in the third sub-cycle, the nominal frequency and the frequency deviation value are added together to obtain the load resonant frequency at the current temperature. Next, we proceed to the fourth step of calculation, obtaining the following formula: ; Then, using this formula and the nominal load capacitance value and parallel capacitance... C 0. Series capacitor C 1 can be calculated directly f s and f osc The ratio of the series resonant frequency to the load resonant frequency is pre-stored in parameter storage module one, i.e., the series resonant frequency-load resonant frequency ratio coefficient. In the first sub-cycle of the fourth step calculation, this ratio and the load resonant frequency at the current temperature are input to the input of the unique multiplier; in the second sub-cycle, the series resonant frequency at the current temperature is obtained. f s .

[0042] Finally, the fifth step of calculation yields the following formula: ; The circuit diagram is executed according to the above formula as follows: Figure 7 As shown, in the first sub-cycle, twice the nominal frequency is input to the dividend terminal of the unique divider, and... f s The input is fed into the divisor of the unique divider; in the second sub-cycle, the division result is subtracted by a fixed constant 2, and the subtraction result is temporarily stored in the intermediate value of the second parameter storage module; in the third sub-cycle... C 1. Input the parameter value to the dividend terminal of the unique divider, and input the subtraction result of the second sub-cycle to the divisor terminal of the unique divider; in the fourth sub-cycle, subtract the division result of the third sub-cycle from the... C With a parameter value of 0, the final load capacitance value is obtained. C L .

[0043] A single compensation operation is completed within a complete clock cycle (composed of multiple sub-cycles). The operation process consumes only one multiplier, one divider, and several addition and subtraction logic resources through time-division multiplexing. Furthermore, the entire operation process uses Q17.20 format fixed-point numbers, which meets the high-precision frequency compensation requirement of one part per million.

[0044] In this embodiment of the invention, the massive lookup table (LUT) storage array in traditional DTCCXOs is abandoned. Compensation parameters are calculated in real time through arithmetic logic. Furthermore, a time-division multiplexing (TDM) architecture is adopted in the circuit implementation, using a state machine to control a single multiplier and divider to work in a time-sharing manner, avoiding the stacking of hardware resources, greatly saving the number of digital logic gates and significantly reducing the chip area. Due to the significant reduction in hardware logic scale and memory read / write operations, the static leakage power consumption of the circuit is significantly reduced. At the same time, the optimized five-step operation process makes the single compensation calculation cycle extremely short, reducing dynamic power consumption, which is suitable for IoT and RTC applications that are extremely sensitive to power consumption. The frequency offset-temperature curve of the crystal is fitted by an nth-order polynomial, which has higher fitting accuracy than the discrete lookup table method. In addition, by modifying the polynomial coefficients in parameter storage module one, it can be adapted to quartz crystals of different batches or different cut angles without redesigning the circuit or burning a large-scale data table, which has strong engineering adaptability.

[0045] Example 2, please refer to Figure 8 , Figure 8 This is a flowchart illustrating a polynomial compensation method for a digital temperature-compensated frequency control chip according to an embodiment of the present invention.

[0046] like Figure 8 As shown, a polynomial compensation method for a digital temperature-compensated frequency control chip, employing the digital compensation arithmetic circuit described above, includes: S801: Calculates the input temperature digital code using a preset formula to obtain the current temperature value corresponding to the Celsius range; S802: Based on the current temperature value, perform frequency offset calculation using polynomial coefficients to obtain frequency offset data at the current temperature; S803: Calculates the load resonant frequency of the Pierce oscillator at the current temperature based on the frequency offset data at the current temperature; S804: Calculates the series resonant frequency at the current temperature based on the load resonant frequency, parallel capacitance, series capacitance, and nominal load capacitance of the Pierce oscillator at the previous temperature. S805: Using the load resonant frequency as the target frequency, the target load capacitance value is obtained by deriving and calculating the target load capacitance value based on the series resonant frequency at the current temperature and the target frequency using the load resonant frequency formula of the Pierce oscillator.

[0047] In the specific implementation of this invention, the frequency offset calculation based on the current temperature value using polynomial coefficients is an nth-degree polynomial of the crystal frequency offset-temperature coefficient in the digital temperature compensation frequency control chip used by the digital compensation operation circuit; the formula for the load resonant frequency of the Pierce oscillator is the relationship between the load resonant frequency and the load capacitance value corresponding to the Pierce oscillator.

[0048] Specifically, in this embodiment, the nominal frequency of the quartz crystal oscillator used is 27.12MHz, and the parallel capacitor value is... C 0. Series capacitance value C 1. The frequency offset-temperature relationship is a fifth-order polynomial as follows: ; The digital temperature compensation frequency control chip used is paired with a temperature sensor and analog-to-digital converter that output a 12-bit temperature code (Tcode). The temperature measurement range is -45℃ to 83℃. The formula relating the actual temperature to the measured temperature code is as follows: ; Substitute the raw temperature code to be input into the formula relating the actual temperature and the measured temperature code to obtain the current temperature value in the Celsius range. T Substituting the current temperature value T in the Celsius range into the fifth-order polynomial specific to the quartz crystal used in this embodiment, the frequency deviation at the current temperature is calculated. ppm ; Frequency deviation at the current temperature ppm Use the following formula: ; The parallel oscillation frequency of the Pierce oscillator at the current temperature was calculated.

[0049] The parallel oscillation frequency of the Pierce oscillator at the current temperature f osc Parallel capacitors C 0. Series capacitor C 1 and nominal load capacitance C L_nom Substitute the values ​​into the following formula to solve the problem. The formula is as follows: ; Calculate the series resonant frequency at the current temperature. f s ; Bundle f osc Set the target frequency, namely 27.12MHz, and use the series resonant frequency at the current temperature. f s Substitute the values ​​into the formula to perform the derivation and calculation, where the formula is as follows: ; Derive the target load capacitance value.

[0050] The above method can convert temperature information into load capacitance value, and further adjust the load capacitance of the Pierce oscillator to make the DTCXO output stably within the target frequency range. Furthermore, the method can adapt to different crystal characteristics.

[0051] In this embodiment of the invention, the massive lookup table (LUT) storage array in traditional DTCCXOs is abandoned. Compensation parameters are calculated in real time through arithmetic logic. Furthermore, a time-division multiplexing (TDM) architecture is adopted in the circuit implementation, using a state machine to control a single multiplier and divider to work in a time-sharing manner, avoiding the stacking of hardware resources, greatly saving the number of digital logic gates and significantly reducing the chip area. Due to the significant reduction in hardware logic scale and memory read / write operations, the static leakage power consumption of the circuit is significantly reduced. At the same time, the optimized five-step operation process makes the single compensation calculation cycle extremely short, reducing dynamic power consumption, which is suitable for IoT and RTC applications that are extremely sensitive to power consumption. The frequency offset-temperature curve of the crystal is fitted by an nth-order polynomial, which has higher fitting accuracy than the discrete lookup table method. In addition, by modifying the polynomial coefficients in parameter storage module one, it can be adapted to quartz crystals of different batches or different cut angles without redesigning the circuit or burning a large-scale data table, which has strong engineering adaptability.

[0052] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, which may include: read-only memory (ROM), random access memory (RAM), disk or optical disk, etc.

[0053] Furthermore, the above provides a detailed description of a digital compensation operation circuit and its polynomial compensation method provided by the embodiments of the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A digital compensation arithmetic circuit, characterized in that, The digital compensation operation circuit is a time-division multiplexing architecture, including a state control module, a shared operation data link, data selection and routing logic, parameter storage module one, and parameter storage module two; The state control module is used to receive clock signals and start signals, and generate a state code and sub-cycle count value that progress over time in each compensation cycle. The shared computing data link includes a configurable multiplier, a configurable divider, and several addition and subtraction logic units. The parameter storage module is used to store the temperature digital code input from the ADC, preset polynomial coefficients, and operation constants; The parameter storage module 2 is used to store the intermediate values ​​and results of each step of the polynomial compensation method. The data selection and routing logic is used to couple the state control module, the parameter storage module one, the parameter storage module two, and the shared computation data link; The state control module is configured to, based on the sub-cycle count value, control the data selection and routing logic to send the intermediate values ​​of the operation in the parameter storage module two and / or the polynomial coefficients and operation constants of the parameter storage module one to the input end of the shared operation data link in a time-division manner within different clock sub-cycles. Within a single compensation cycle, the multiplier or divider is used sequentially to complete the calculation of temperature normalization, frequency deviation calculation, load resonant frequency calculation, series resonant frequency calculation, and target load capacitance value, and the calculation results are stored in the parameter storage module two.

2. The digital compensation operation circuit according to claim 1, characterized in that, The shared computing data link adopts fixed-point number format computing logic, which includes a sign bit, an integer bit, and a decimal bit; the bit width of the decimal bit meets the frequency resolution of one million branches. The parameter storage module one and the parameter storage module two pre-store the polynomial coefficients, operation constants and intermediate values ​​in the fixed-point number format.

3. The digital compensation operation circuit according to claim 1, characterized in that, The state control module consists of a finite state machine and a counter, and the operation steps of the digital compensation circuit include: When the state control module detects the start signal, it controls the parameter storage module to input the temperature digital code into the shared computing data link, and controls the shared computing data link to convert the temperature digital code into Q17.20 fixed-point number format, and then converts the temperature digital code into a temperature value in the Celsius range by right shift, division operation and subtraction operation in sequence. The shared computation data link performs frequency offset calculation processing at the current temperature based on the nth degree polynomial coefficients of the crystal frequency-temperature characteristics stored in the parameter storage module one, and obtains the frequency offset data at the current temperature; The load resonant frequency at the current temperature is calculated based on the frequency offset data, and the series resonant frequency of the crystal at the current temperature is obtained by calculating the load resonant frequency. The target load capacitance value is obtained by using the series resonant frequency formula based on the Pierce oscillator.

4. The digital compensation operation circuit according to claim 3, characterized in that, The process of converting the temperature digital code into a temperature value in the Celsius range by sequentially performing right shift, division, and subtraction operations includes: By using the Q17.20 fixed-point number format, shifting it right by 5 bits, and then performing a division operation by a constant 32, the result is subtracted by a constant 45 in the subtractor to convert the temperature digital code into a temperature value in the Celsius range.

5. The digital compensation operation circuit according to claim 3, characterized in that, The step of calculating the load resonant frequency at the current temperature based on the frequency offset data, and obtaining the series resonant frequency of the crystal at the current temperature through the load resonant frequency, includes: The state control module inputs the decimal places and the nominal frequency to the input terminal of the multiplier during the N+0th sub-cycle. During the (N+1)th sub-cycle, the multiplication result is temporarily stored in the intermediate value of the second parameter storage module, and the frequency offset data at the current temperature is temporarily stored for later use. In the (N+2)th sub-cycle, the nominal frequency and the frequency offset data are added together to obtain the load resonant frequency at the current temperature; The shared computational data link retrieves the proportionality coefficient between the load resonant frequency and the series resonant frequency from the parameter storage module one, and inputs the proportionality coefficient and the load resonant frequency into the multiplier to output the series resonant frequency of the crystal at the current temperature.

6. The digital compensation operation circuit according to claim 3, characterized in that, The load resonant frequency formula based on the Pierce oscillator uses the series resonant frequency to calculate the target load capacitance value, including: In the (N+3)th sub-cycle, the state control module inputs twice the load resonant frequency to the dividend terminal of the divider and inputs the series resonant frequency to the divisor terminal of the divider. In the (N+4)th sub-cycle, the first division result output by the divider is subtracted by a fixed constant 2, and the subtraction result is temporarily stored in the intermediate value of the second parameter storage module. In the (N+5)th sub-cycle, the parameter value of the series capacitor is input to the dividend terminal of the divider, the subtraction result is input to the divisor terminal of the divider, and the divider outputs the second division result; In the (N+6)th sub-cycle, the parameter value of the series capacitor is subtracted from the result of the second division to output the target load capacitance value.

7. The digital compensation operation circuit according to claim 3, characterized in that, The bit width of the temperature digital code is determined by the bit width output of the analog-to-digital converter in the digital temperature compensation frequency control chip used by the digital compensation arithmetic circuit, which meets the frequency resolution requirement of one part per million. The output bit width of the analog-to-digital converter in the digital temperature compensation frequency control chip, which is used by the digital compensation operation circuit, and the temperature measurement range of the temperature sensor in degrees Celsius are determined sequentially by right shift, division, and subtraction operations.

8. The digital compensation operation circuit according to claim 1, characterized in that, The operational constants stored in the parameter storage module are generated by the tuning fork quartz crystal in the real-time clock chip. The Pierce oscillator composed of the tuning fork quartz crystal outputs a clock signal with a frequency of 32.768kHz. Its frequency deviation-temperature curve has an n value of 2, a quadratic term coefficient of -0.04, a linear term coefficient of 2, and a constant term of -25. Its static capacitance C0 = 1.3pF and dynamic capacitance C1 = 2fF form the operational constants.

9. A polynomial compensation method for a digital temperature-compensated frequency control chip, characterized in that, The method, employing the digital compensation arithmetic circuit as described in any one of claims 1 to 8, comprises: The input temperature code is processed using a preset formula to obtain the current temperature value corresponding to the Celsius range; Based on the current temperature value, frequency offset calculation is performed using polynomial coefficients to obtain frequency offset data at the current temperature. The load resonant frequency of the Pierce oscillator at the current temperature is calculated based on the frequency offset data at the current temperature. The series resonant frequency at the current temperature is calculated based on the load resonant frequency of the Pierce oscillator at the previous temperature, the parallel capacitance, the series capacitance, and the nominal load capacitance. Using the load resonant frequency as the target frequency, the target load capacitance value is obtained by deriving and calculating the load resonant frequency formula of the Pierce oscillator based on the series resonant frequency at the current temperature and the target frequency.

10. The polynomial compensation method according to claim 9, characterized in that, The frequency offset calculation based on the current temperature value using polynomial coefficients is an nth-degree polynomial of the crystal frequency offset-temperature coefficient in the digital temperature compensation frequency control chip used by the digital compensation operation circuit; the formula for the load resonant frequency of the Pierce oscillator is the relationship between the load resonant frequency and the load capacitance value corresponding to the Pierce oscillator.

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