Crystal Oscillators and Their Phase Noise Suppression Methods

Abstract

This invention provides a crystal oscillator and a method for suppressing phase noise of the same. The crystal oscillator may include a crystal oscillator core circuit, a bias circuit coupled to the output of the crystal oscillator core circuit, a pulse wave buffer coupled to the output of the crystal oscillator core circuit, and a phase noise suppression circuit coupled to the output of the crystal oscillator core circuit. The crystal oscillator core circuit can generate a sine wave. The bias circuit can provide a bias voltage for the sine wave. The pulse wave buffer can generate a pulse wave according to the sine wave. The phase noise suppression circuit can generate a reset signal containing at least one reset pulse for resetting the bias voltage. Furthermore, a reset signal is generated without calibrating at least one reset pulse to the zero-crossing point of the sine wave.

Description

Technical Field

[0001] This invention relates to crystal oscillators, and more particularly to a crystal oscillator and a method for suppressing phase noise therefrom. Background Technology

[0002] For electronic systems such as phase-locked loops (PLLs), a reference clock is essential. More specifically, the phase noise of the reference clock significantly affects the overall performance of the electronic system, thus requiring high performance in terms of phase noise. Generally, the reference clock can be generated by a crystal oscillator, such as a Pierce oscillator or a Colpitts oscillator. The methods and architectures proposed in related technologies significantly increase the additional circuitry required to improve the overall performance of the crystal oscillator (e.g., reduce its phase noise). Therefore, a novel architecture and related methods are needed to reduce the phase noise of the crystal oscillator (more specifically, reduce the phase noise of the reference clock) without introducing any side effects or in a manner that produces fewer side effects. Summary of the Invention

[0003] In view of this, one object of the present invention is to provide a crystal oscillator and a phase noise suppression method thereof to improve the phase noise correlation performance of electronic systems, and in particular to reduce the phase noise output of the reference clock in the crystal oscillator of the electronic system.

[0004] At least one embodiment of the present invention provides a crystal oscillator. The crystal oscillator may include a crystal oscillator core circuit, a bias circuit, a pulse wave buffer, and a phase noise suppression circuit. The crystal oscillator core circuit is used to generate a sine wave. The bias circuit is coupled to the output of the crystal oscillator core circuit to provide a bias voltage for the sine wave. The pulse wave buffer is coupled to the output of the crystal oscillator core circuit to generate a pulse wave based on the sine wave. The phase noise suppression circuit is coupled to the output of the crystal oscillator core circuit to generate a reset signal including at least one reset pulse to provide an AC ground path to the bias voltage noise to reset the bias voltage (e.g., to reset resistive noise on the bias voltage).

[0005] More specifically, a reset signal is generated without calibrating at least one reset pulse to the zero-crossing point of the sine wave.

[0006] At least one embodiment of the present invention provides a phase noise suppression method for a crystal oscillator. The phase noise suppression method may include: generating a sine wave through a crystal oscillation core circuit of the crystal oscillator; providing a bias voltage for the sine wave through a bias circuit; generating a pulse wave according to the sine wave using a pulse wave buffer; and providing an AC ground path for noise on the bias voltage to reset the bias voltage (e.g., to reset resistive noise on the bias voltage). The AC ground path is provided in response to a reset signal generated without calibrating the position of at least one reset pulse to the zero-crossing point of the sine wave.

[0007] The crystal oscillator and phase noise suppression method of the present invention can reduce phase noise without calibrating the timing of the phase noise reset operation, and achieves a significant reduction in the overall cost of phase noise suppression compared to related technologies. Therefore, the present invention can reduce the phase noise of the crystal oscillator (more specifically, reduce the phase noise of the reference clock, such as the pulse wave output from the crystal oscillator) without introducing any side effects or in a manner that produces fewer side effects.

[0008] These and other objects of the invention will undoubtedly become apparent to those skilled in the art after reading the following detailed description of the preferred embodiments shown in the various accompanying drawings. Attached Figure Description

[0009] The invention is illustrated by way of example and not limitation in the accompanying drawings, in which similar reference numerals indicate similar elements. When a particular feature, structure, or characteristic is described in connection with an embodiment, it should be understood that implementing such a feature, structure, or characteristic in connection with other embodiments is within the knowledge of those skilled in the art, whether or not explicitly indicated.

[0010] Figure 1 This is a schematic diagram of a crystal oscillator according to an embodiment of the present invention.

[0011] Figure 2 This is a schematic diagram illustrating how noise from the bias resistor is introduced into the square wave output of the square wave buffer.

[0012] Figure 3 This is a schematic diagram of a crystal oscillator according to an embodiment of the present invention.

[0013] Figure 4 This is a schematic diagram of phase noise suppression using a noise reset pulse according to an embodiment of the present invention.

[0014] Figure 5 It is a crystal oscillator according to an embodiment of the present invention.

[0015] Figure 6 This is an illustration of an embodiment of the present invention. Figure 5 The reset pulse generated by the pulse generator shown.

[0016] Figure 7 This is an illustration of another embodiment of the present invention. Figure 5 The reset pulse generated by the pulse generator shown.

[0017] Figure 8 This is a diagram of a crystal oscillator according to an embodiment of the present invention.

[0018] Figure 9 This is an illustration of an embodiment of the present invention. Figure 8 The reset pulse generated by the pulse generator shown.

[0019] Figure 10 This describes the workflow of a phase noise suppression method for a crystal oscillator according to an embodiment of the present invention. Detailed Implementation

[0020] Certain terms used in the following description and claims refer to specific components. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to a component. It is not intended to distinguish between components with different names but identical functions. In the following description and claims, the terms "comprising" and "including" are used in an open-ended manner and should therefore be interpreted as "including, but not limited to...". Furthermore, the term "coupled" is intended to indicate either an indirect or direct electrical connection. Thus, if one device is coupled to another device, the connection can be either a direct electrical connection or an indirect electrical connection via other devices and connections.

[0021] Figure 1 This is a schematic diagram of a crystal oscillator 10 according to an embodiment of the present invention. The crystal oscillator 10 may include a crystal oscillation core circuit 120, a bias circuit such as a DC bias circuit 140, a bias resistor Rbias, and a pulse wave buffer such as a square wave buffer 160 (denoted as "NBUF" for simplicity). The crystal oscillation core circuit 120 may be as follows: Figure 1The Colpitts oscillator shown includes a crystal slot XTAL (also possibly referred to as a "crystal oscillator (XO)"), capacitors C1 and C2, a transistor, and a current source, but the invention is not limited thereto. For example, in some embodiments, the crystal oscillator core circuit 120 can be replaced by a Pierce oscillator. In this embodiment, a DC bias circuit 140 couples the output of the crystal oscillator 120 through a bias resistor Rbias, and a square wave buffer 160 couples the output of the crystal oscillator 120. For example, the output of the crystal oscillator and the input of the square wave buffer 160 are coupled to a node of the crystal oscillator 10, and the DC bias circuit 140 is coupled to said node through a bias resistor Rbias, wherein the input impedance of said node can be represented by Zin, and Zin is approximately determined by the bias resistor Rbias.

[0022] In this embodiment, the crystal oscillator core circuit 120 is designed to have a high quality factor (e.g., greater than or equal to 100,000) and is configured to generate a sine wave. Figure 1 As shown, the DC bias circuit 140 may include one or more transistors to provide a bias voltage, such as a DC bias voltage VB, for the sine wave. For example, the sine wave is carried at the level of the DC bias voltage VB (more specifically, the sine wave may vary regularly up and down based on the level of the DC bias voltage VB). Furthermore, a pulse wave buffer, such as a square wave buffer 160, may generate a pulse wave, such as a square wave, at the output terminal OUT of the square wave buffer 160 based on the sine wave. For example, the square wave buffer 160 may include an inverter or an inverter chain, wherein the square wave may have a first state (e.g., a first logic value, such as "1") when the level of the sine wave is greater than a threshold value (e.g., an input voltage level threshold) of the square wave buffer 160, and a second state (e.g., a second logic value, such as "0") when the level of the sine wave is less than the threshold value of the square wave buffer 160. In some embodiments, the pulse wave generated by the pulse wave buffer may be a rectangular wave with a duty cycle of 50%, such as a square wave. In some embodiments, the pulse wave generated by the pulse wave buffer can be a rectangular wave with a duty cycle other than 50%. The following description uses a square wave as an example for illustrative purposes only and does not constitute a limitation of the present invention.

[0023] In one embodiment, the bias resistor Rbias contributes a large portion of the phase noise in the square wave. Specifically, the noise contributed by the bias resistor Rbias is positively correlated with the resistance value of Rbias. For example, the higher the resistance value of Rbias, the greater the noise generated. Conversely, the signal power of the sine wave is positively correlated with the resistance value of the bias resistor Rbias. For example, the higher the resistance value of Rbias, the greater the signal power of the sine wave (i.e., the lower the resistance value of Rbias, the greater the sine wave loss). Therefore, there is a trade-off between loss and noise, and the present invention aims to overcome this trade-off.

[0024] Specifically, because the quality factor of the crystal oscillator core circuit 120 is sufficiently high, the thermal noise from the bias resistor Rbias will not significantly affect the signal-to-noise ratio (SNR) of the sinusoidal wave at the output of the crystal oscillator core circuit 120. For example, the crystal oscillator core circuit 120 can filter out most of the noise caused by the bias resistor Rbias at a specific frequency offset (e.g., 100 kHz) relative to the oscillation frequency of the sinusoidal wave. Based on the above description, even if the bias resistor Rbias contributes noise, the phase noise of the sine wave can be very small, for example, -185 dBc / Hz. However, the phase noise at the output OUT of the square wave buffer can be very high (e.g., -165 dBc / Hz).

[0025] To better understand how the noise from the bias resistor Rbias is introduced into the square wave at the output terminal OUT of the square wave buffer 160, please refer to... Figure 2If the bias resistor Rbias does not contribute noise, the sine wave may be carried on a constant level VB, as shown in the waveform labeled "XO Out1" (e.g., a 40MHz sine wave can regularly change upwards and downwards based on a constant level VB), and the pulse width of this square wave may be constant, as shown in the waveform labeled "NBUF Out1". In contrast, if the bias resistor Rbias contributes noise (e.g., it can be modeled as a 100kHz bias noise source), the sine wave may be carried on a varying level VB+ΔV, as shown in the waveform labeled "XO Out2" (e.g., a 40MHz sine wave may change up and down according to the time-varying level of the 100kHz bias noise). Due to the high quality factor of the crystal oscillator core circuit 120, the phase noise of the sine wave does not increase significantly when the noise of the bias resistor Rbias is taken into account. For the square wave, the timing of state transitions (e.g., rising and falling edges) can be significantly affected by variations in the voltage level at the input of the square wave buffer, and the pulse width of the square wave may vary over time, as shown in the circled portion of the waveform labeled "NBUF Out2" (e.g., time-varying phase shift Δt). This results in phase noise in the square wave at the output OUT of the square wave buffer 160. Figure 2 As shown at the bottom, the thin line represents the output of the square wave buffer 160 (with a constant pulse width) without considering the noise of the bias resistor, while the thick line represents the output of the square wave buffer 160 (with a time-varying pulse width) considering the noise of the bias resistor. The difference between these two waveforms can be described by the time-varying phase shift Δt, which can be regarded as the phase noise mentioned above.

[0026] Figure 3This is a schematic diagram illustrating a crystal oscillator 30 according to an embodiment of the present invention. In addition to the crystal oscillator core circuit 120, DC bias circuit 140, bias resistor Rbias, and square wave buffer 160, the crystal oscillator 30 may further include a phase noise suppression circuit 180. The phase noise suppression circuit 180 is coupled to the output of the crystal oscillator core circuit 120 and can be used to generate a reset signal including at least one reset pulse (e.g., one or more pulses, which may be combined and referred to as reset pulses) to reset the bias voltage (e.g., resetting the resistive noise on the bias voltage, such as noise contributed by the bias resistor Rbias) of the sine wave (e.g., by providing an AC ground path for resistive noise on the bias voltage). More specifically, the reset signal is generated without calibrating at least one of the reset pulses to the zero-crossing point of the sine wave, wherein the zero-crossing point of the sine wave may represent a point in time when the sine wave changes across the DC bias voltage VB level. Simulations show that the position of the reset pulse (e.g., the timing of the reset pulse relative to the sine wave phase) does not significantly affect the improvement of phase noise suppression (i.e., the position of the reset pulse is not important, and similar improvements can be obtained at different positions of the reset pulse). Therefore, the reset pulse can be at the zero crossover point or peak of the sine wave output, without the need for complex calibration circuitry regarding the timing of the reset pulse.

[0027] like Figure 3 As shown, the phase noise suppression circuit 180 may include a reset switch 180SW coupled to the output of the crystal oscillator core circuit 120, and may be controlled by the reset signal. Furthermore, the phase noise suppression circuit 180 may also include a pulse generator 180G for generating the reset signal. In this embodiment, the reset switch may be turned on in response to a reset pulse, providing an AC ground path for the resistive noise on the bias voltage to remove the noise on the bias voltage, thereby resetting the bias voltage of the sine wave to a reset level. For example, the reset switch 180SW may be coupled across the bias resistor Rbias. When the reset switch is turned on, the noise generated by the bias resistor Rbias can be reset, and the changing bias voltage level of the sine wave is pulled back to the original voltage level of the DC bias voltage VB, but the invention is not limited thereto.

[0028] To better understand how the phase noise suppression circuit 180 solves the phase noise problem caused by the bias resistor Rbias, please refer to [reference needed]. Figure 4 .like Figure 4The upper half is shown. The waveforms labeled "XO Out2" and "NBUF Out2" represent the sine wave at the output of the crystal oscillator core circuit 120 and the square wave at the output of the square wave buffer 160 when the suggested noise reset pulse is not used (e.g., phase noise suppression circuit 180 is disabled and reset switch 180SW is always off); as Figure 4 As shown in the lower half, the waveforms labeled "XO Out3" and "NBUF Out3" represent the sine wave at the output of the crystal oscillator core circuit 120 and the square wave at the output of the square wave buffer 160 when using the suggested noise reset pulse (e.g., enabling the phase noise suppression circuit 180 and the pulse generator 180G starts outputting reset pulses to periodically turn on the reset switch 180SW). Figure 4 As shown, when the phase noise suppression circuit 180 is disabled, the sine wave can vary up and down based on the time-varying level VB+ΔV, thus the pulse width of the square wave changes over time, resulting in phase noise. In contrast, when the phase noise suppression circuit 180 is enabled and the pulse generator begins outputting reset pulses to the reset switch 180SW (e.g., periodically outputting reset pulses to the reset switch 180SW), the DC bias voltage level of the sine wave is reset in response to the reset pulses, and the pulse width of the square wave can be substantially constant, or the amount of change in the bias level of the sine wave is reduced (e.g., ΔV can be reduced). Therefore, the pulse width of the square wave can be constant or substantially constant, thereby reducing phase noise.

[0029] It should be noted that the resistance value of the bias resistor Rbias and the input capacitance at the output of the crystal oscillator core circuit 120 can be designed to be quite large. A large resistance-capacitance (RC) time constant will prevent the noise in the bias resistor Rbias from having sufficient time to significantly change the level of the sine wave. For example, after the bias voltage level of the sine wave is reset and the reset switch 180SW is turned off again, because the time constant is large enough, the noise in the bias resistor Rbias will not cause an immediate and significant change in the bias voltage level of the sine wave. Moreover, when the accumulated noise causes a slight change in the bias voltage level of the sine wave, the next reset pulse can reset the bias voltage level again. Figure 4As shown. Therefore, the frequency of the reset signal is preferably fast enough to better suppress noise in the bias resistor Rbias, thereby maintaining the bias voltage level of the sine wave. Through simulation, assuming the frequency of the sine wave is 40MHz, a significant improvement in noise correlation performance can be observed when the frequency of the reset signal is 40MHz; further improvement in noise correlation performance can be achieved when the frequency of the reset signal is 400MHz. Therefore, a higher frequency of the reset signal is preferred for better noise correlation performance, but the invention is not limited thereto. In some embodiments, the phase noise suppression circuit 180 may further include a frequency multiplier to generate a signal having a frequency that is N times the frequency of the square wave output from the square wave buffer 160, and accordingly make the frequency of the reset signal N times the frequency of the square wave (e.g., there may be N reset pulses within one period of the sine wave or square wave), where N can be a positive integer greater than or equal to 2. In some embodiments, the frequency of the reset signal may be lower than or equal to the frequency of the sine wave. In some embodiments, the reset pulses may be generated periodically, and the frequency of the reset pulses may be any suitable positive value. In some embodiments, the reset pulse is not generated periodically. For example, the pulse generator 180G may generate the reset pulse randomly, or the occurrence of the reset pulse may be controlled by another controller within the crystal oscillator 30.

[0030] Besides the noise generated by the bias resistor Rbias (referred to as Rbias noise), other factors can affect the SNR of a sine wave, such as the on-time T of the reset pulse. ON (For example, the pulse width of the reset pulse indicates the length of time that the reset switch 180SW is turned on), and the on-resistance R of the reset switch 180SW. ON (For example, the resistance value of reset switch 180SW when reset switch 180SW is on), and the corresponding on-resistance R ON noise (abbreviated as R) ON (Noise). Through calculation, SNR can be expressed as:

[0031]

[0032] The symbol f represents the frequency variable. The symbol R avg The average resistance at the output of the crystal oscillator can be further represented by the on-resistance R. ON The resistance value R of the bias resistor Rbias BIAS And the parameter α represents, where α = T ON / T XO T XO N represents the period of the sine wave output by the crystal oscillator core circuit 120. Rbias (f) and N Ron (f) represent the Rbias noise and R at frequency f, respectively.ON Noise. Assume Rbias noise N Rbias (f) can be reset (e.g., in Rbias noise N). Rbias (f) If it is possible to reset to the same order, consider R. ON and T ON (different combinations of which), the equation shown above can be further arranged as follows:

[0033]

[0034] The symbol k represents the Boltzmann constant. The symbol T represents absolute temperature. The symbol C IN This represents the input capacitor at the output terminal of the crystal oscillator core circuit 120. (Symbol: f) XO R represents the frequency of the sine wave. As shown in the equation above, R ON Noise N Ron (f) may include sample noise and hold noise. Assume the frequency f is much smaller than the frequency f of the sine wave. XO (For example, when f / f) XO When the x-axis is very close to zero, the equation shown above can be further simplified as follows:

[0035]

[0036] As shown in the above equation, to achieve a better SNR, it is best to design a smaller α when resetting the Rbias noise to the same order of magnitude. For example, when the Rbias noise is reset to the same order of magnitude, the SNR of the sine wave may increase when the pulse width of the reset pulse decreases. Therefore, using a very short reset pulse (e.g., a reset pulse with an extremely narrow pulse width) to reset the Rbias noise is an optimized design for the noise-dependent performance of the crystal oscillator 30. In practice, a small α can be implemented using an exclusive-OR (XOR) circuit and a very short delay line, thus benefiting from the small area, low current consumption, and low noise of the delay line. The aforementioned extremely short delay line may include an inverter or a series of inverters, but the invention is not limited thereto. It should be noted that the delay provided by the aforementioned extremely short delay line is not limited to a specific value and can be any delay capable of resetting the sine wave bias voltage level without significantly reducing the SNR, such as 100 picoseconds (ps), 80 ps, ​​etc.

[0037] Figure 5 This is a schematic diagram of a crystal oscillator 50 according to an embodiment of the present invention, wherein the crystal oscillator 50 may be... Figure 3 A modified version or example of the crystal oscillator 30 shown. For example... Figure 5In addition to the reset switch 180SW and pulse generator 180G, the phase noise suppression circuit 180 may also include an AC coupling buffer 180B coupled to the output of the crystal oscillator core circuit 120, used to generate a modified square wave based on the sine wave. In this embodiment, the pulse generator 180G is used to generate a reset signal based on the modified square wave, and the position of the reset pulse on the reset signal is set by the control voltage VB1 on the control terminal of the AC coupling buffer 180B. Specifically, the AC coupling buffer 180B may include a capacitor C3, a resistor RB1, and a buffer circuit 181, wherein the capacitor C3 is coupled between the output of the crystal oscillator core circuit 120 and the input of the buffer circuit 181; the resistor RB1 is coupled between the control terminal of the AC coupling buffer 180B and the capacitor C3. In this embodiment, the capacitor C3 is used to receive the sine wave and generate a modified sine wave. The resistor RB1 is used to control the bias voltage of the modified sine wave to the control voltage VB1, for example, causing the modified sine wave to fluctuate according to the voltage level of the control voltage VB1. The buffer circuit 181 is used to generate a corrected square wave based on the corrected sine wave. In this embodiment, the pulse generator 180G may include a delay unit 182 (which may be the aforementioned extremely short delay line) and an XOR logic circuit 183. The delay unit 182 is used to delay the corrected square wave (e.g., delay by 80 ps) to generate a corrected delayed square wave, and the XOR logic circuit 183 is used to perform an XOR operation on the corrected square wave and the corrected delayed square wave to generate a reset signal. For example, when the bias voltage of the corrected sine wave is corrected in response to the control voltage VB1, the duty cycle of the corrected square wave can be corrected accordingly, thereby changing the position of the reset pulse.

[0038] Assuming the DC bias voltage VB (e.g., the DC bias voltage of the sine wave at the output of the crystal oscillator core circuit 120) is set to 0.8V, the sine wave varies between 2.1V and -0.5V. When the control voltage VB1 is set to a voltage level lower than the DC bias voltage VB (e.g., 0V), the corrected sine wave will fluctuate according to the 0V voltage level, such as... Figure 6 As shown, the reset pulse may occur during a period when the sine wave is below the DC bias voltage VB. When the control voltage VB1 is set equal to the DC bias voltage VB, such as 0.8V, the corrected sine wave may fluctuate according to the 0.8V voltage level. Figure 7 As shown, the reset pulse may be positioned very close to (e.g., slightly later than) the zero-crossing point of the sine wave. Similarly, when the control voltage VB1 is set to a voltage level greater than the DC bias voltage VB (e.g., 1.4V), the corrected sine wave can vary up and down according to the 1.4V voltage level, and the reset pulse can be positioned during the period when the sine wave is higher than the DC bias voltage VB level.

[0039] It should be noted that the reset level of the sinusoidal bias voltage is not limited to the DC bias voltage VB provided by the DC bias circuit 140. Any constant voltage level can be used to reset the bias voltage of the sinusoidal wave. In some embodiments, the buffer circuit 181 can be implemented by an inverter. In some embodiments, the buffer circuit 181 can be implemented by a string of inverters. Furthermore, the size of the AC coupling buffer can be 1 / 10 of the square wave buffer 160, but the invention is not limited thereto.

[0040] Figure 8 This is a schematic diagram of a crystal oscillator 80 according to an embodiment of the present invention, wherein the crystal oscillator 80 may be... Figure 3 A modified version or example of the crystal oscillator 30 is shown. In this embodiment, the pulse generator 180G is used to generate a reset signal based on the square wave at the output terminal OUT. More specifically, the delay unit 182 is used to delay the square wave to generate a delayed square wave, and the XOR logic circuit 183 is used to perform an XOR operation on the square wave and the delayed square wave to generate the reset signal. Figure 8 As shown, the voltage level used to reset the bias voltage of the sine wave can be provided by the DC bias circuit 150, but the invention is not limited thereto. In some embodiments, the DC bias circuits 140 and 150 can provide the same voltage level. In some embodiments, the DC bias circuits 140 and 150 can provide different voltage levels. Based on this architecture, as... Figure 9 As shown, the reset pulse generated by the pulse generator 180G can be close to the zero-crossing point of the sine wave, or more specifically, slightly later than the zero-crossing point of the sine wave.

[0041] Figure 10 This describes the workflow of a phase noise suppression method for a crystal oscillator according to an embodiment of the present invention, wherein the crystal oscillator can be respectively... Figure 3 , Figure 5 and Figure 8 Any one of the crystal oscillators 30, 50, and 80 shown. It should be noted that... Figure 10 This is for illustrative purposes only and is not intended to limit the scope of the invention. In some embodiments, it may be possible to Figure 10 Add, delete, or modify one or more steps in the workflow shown. Additionally, if the same result can be obtained, it is not necessary to follow the steps. Figure 10 The exact order of execution is shown.

[0042] In step 1010, the crystal oscillator can generate a sine wave through the crystal oscillator core circuit (e.g., crystal oscillator core circuit 120).

[0043] In step 1020, the crystal oscillator can provide the bias voltage for the sine wave through the bias circuit.

[0044] In step 1030, the crystal oscillator can generate a square wave based on the sine wave using a square wave buffer.

[0045] In step 1040, the crystal oscillator can generate a reset signal including at least one reset pulse via a phase noise suppression circuit to reset the bias voltage (e.g., to reset the resistive noise on the bias voltage, such as Rbias noise), wherein the reset signal can be generated without calibrating the position of at least one reset pulse to the zero crossover point of the sine wave.

[0046] In summary, this invention provides several embodiments of a crystal oscillator and its phase noise suppression method. These embodiments utilize a very short reset pulse to reset the noise caused by the bias resistor, and more specifically, to reset the bias voltage level interfered with by the noise caused by the bias resistor, thereby reducing the phase noise of the square wave output by the square wave buffer. Furthermore, since the cause of the phase noise introduced into the square wave is not significantly related to the phase of the sine wave (e.g., noise appearing at the zero-crossing point of the sine wave has the same effect on the phase noise of the square wave as noise appearing at other positions / phases of the sine wave), the timing or position of the reset pulse is not important, and calibration regarding the timing or position of the reset pulse can be omitted. Therefore, complex calibration and long delay lines are not required, thus significantly reducing design complexity and overall power consumption.

[0047] Those skilled in the art will readily observe that various modifications and alterations can be made to the apparatus and method while retaining the teachings of the present invention. Therefore, the above disclosure should be construed as being limited only by the scope and limits of the appended claims.

Claims

1. A crystal oscillator, comprising: The core circuit of the crystal oscillator is used to generate a sine wave; A bias circuit, coupled to the output of the crystal oscillator core circuit, is used to provide the bias voltage for the sine wave. A pulse wave buffer, coupled to the output of the crystal oscillator core circuit, is used to generate a pulse wave based on the sine wave; as well as A phase noise suppression circuit, coupled to the output of the crystal oscillator core circuit, is used to provide an AC ground path for the noise on the bias voltage to reset the noise on the bias voltage; The phase noise suppression circuit includes: A reset switch, coupled to the output of the crystal oscillator core circuit, is controlled by a reset signal. The reset switch is turned on in response to the reset signal to provide the AC ground path for the noise on the bias voltage to remove the noise on the bias voltage, and thereby reset the bias voltage of the sine wave to the reset level. The frequency of the reset signal is N times the frequency of the pulse wave, and N is a positive value greater than or equal to 2.

2. The crystal oscillator of claim 1, wherein the signal-to-noise ratio of the sine wave increases when the pulse width of at least one reset pulse of the reset signal decreases.

3. The crystal oscillator as claimed in claim 1, wherein the phase noise suppression circuit further comprises: A pulse generator for generating the reset signal based on the pulse wave, wherein the pulse generator includes: Delay unit, used to delay the pulse wave to generate a delayed pulse wave; and An XOR logic circuit is used to perform an XOR operation on the pulse wave and the delayed pulse wave to generate the reset signal.

4. The crystal oscillator of claim 1, wherein the phase noise suppression circuit further comprises: An AC coupling buffer, coupled to the output of the crystal oscillator core circuit, is used to generate a correction pulse wave based on the sine wave; as well as A pulse generator is used to generate a reset signal containing at least one reset pulse based on the modified pulse wave; wherein the position of the at least one reset pulse on the reset signal is set by a control voltage on the control terminal of the AC coupling buffer.

5. The crystal oscillator of claim 4, wherein the AC coupling buffer comprises: A capacitor, coupled to the output of the core circuit of the crystal oscillator, is used to receive the sine wave and generate a modified sine wave; A resistor, coupled between the control terminal of the AC coupling buffer and the capacitor, is used to control the bias voltage of the modified sine wave to be the control voltage. as well as A buffer circuit is used to generate the corrected pulse wave based on the corrected sine wave.

6. The crystal oscillator of claim 4, wherein the pulse generator comprises: A delay unit is used to delay the corrected pulse wave to generate a corrected delayed pulse wave; as well as An XOR logic circuit is used to perform an XOR operation on the corrected pulse wave and the corrected delayed pulse wave to generate the reset signal.

7. A method for suppressing phase noise in a crystal oscillator, applied to the crystal oscillator according to any one of claims 1-6, comprising: The sine wave is generated by the crystal oscillation core circuit of the crystal oscillator; A bias voltage is provided for this sine wave through a bias circuit; Based on this sine wave, a pulse wave is generated by a pulse wave buffer; as well as Provide an AC ground path to the sine wave to reset the bias voltage.

8. The phase noise suppression method as described in claim 7, wherein providing the AC grounding path comprises: In response to at least one reset pulse of the reset signal, the reset switch is turned on to provide the AC ground path for noise on the bias voltage to remove noise on the bias voltage, thereby resetting the bias voltage of the sine wave to the reset level.

9. The phase noise suppression method as described in claim 8, wherein the frequency of the reset signal is N times the frequency of the pulse wave, and N is a positive value greater than or equal to 2.

10. The phase noise suppression method of claim 8, wherein the signal-to-noise ratio of the sine wave increases when the pulse width of the at least one reset pulse decreases.

11. The phase noise suppression method as described in claim 8, wherein providing the AC grounding path further includes: Delay the pulse wave to generate a delayed pulse wave; as well as The pulse wave and the delayed pulse wave are XORed to generate the at least one reset pulse.

12. The phase noise suppression method as described in claim 8, wherein providing the AC grounding path further includes: Based on the sine wave, a correction pulse wave is generated by the AC coupling buffer; as well as The reset signal is generated by a pulse generator according to the corrected pulse wave; wherein the position of the at least one reset pulse on the reset signal is set by the control voltage on the control terminal of the AC coupling buffer.

13. The phase noise suppression method of claim 12, wherein generating the corrected pulse wave comprises: The capacitor of the AC coupling buffer receives the sine wave and generates a modified sine wave; The bias voltage of the modified sine wave is controlled by the resistor of the AC coupling buffer. as well as The buffer circuit of the AC coupling buffer generates the corrected pulse wave based on the corrected sine wave.

14. The phase noise suppression method of claim 12, wherein generating the reset signal comprises: The modified pulse wave is delayed to generate a modified delayed pulse wave; as well as The reset signal is generated by performing an XOR operation between the corrected pulse wave and the corrected delayed pulse wave.

15. The phase noise suppression method of claim 8, wherein if the at least one reset pulse of the reset signal is not located at the zero-crossing point of the sine wave when the reset signal is generated, it is not necessary to calibrate the position of the at least one reset pulse of the reset signal to the zero-crossing point of the sine wave.

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