A passive crystal oscillator-free gfsk transmitter chip

Abstract

The application belongs to the field of integrated circuit technology design, and relates to a passive and crystal-free GFSK transmitter chip, which comprises a radio frequency energy collection module, a power management module, a clock recovery module and an open-loop modulation transmitter module, the radio frequency energy collection module is used for wireless power supply, the power management module controls a power switch of the transmitter chip according to a power supply voltage value, when the power switch is opened, the power management module supplies power to the open-loop modulation transmitter module, the clock recovery module provides a reference frequency for the open-loop modulation transmitter module, and the open-loop modulation transmitter module multiplies the reference frequency to a radio frequency frequency required for transmission and transmits a data signal. The transmitter chip has the advantages of low power consumption and small size, is suitable for wireless sensor network nodes, and has strong commercial value.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology design and relates to a passive crystal oscillator-free GFSK transmitter chip. Background Technology

[0002] The Internet of Things (IoT) has expanded into home automation, personal health, and industrial monitoring applications, helping people improve efficiency, safety, and quality of life. Wireless communication typically consumes a significant portion of the energy budget for these devices. Industrial monitoring systems, in particular, are highly energy-constrained, generally requiring decades of lifespan, thus necessitating the use of harvestable energy. Relatively long communication distances of tens of meters are needed to cover typical industrial environments with a limited number of base stations, requiring high output power. Generally, these seemingly contradictory specifications can be met with low duty cycles, where sensor nodes transmit at longer packet intervals, reducing average power consumption. This is especially true for many low-bandwidth industrial monitoring applications. For example, sensors monitoring motor health only need to measure every few hours or daily. Similarly, sensors monitoring temperature or the presence of volatile gases only need to communicate when changes occur—a slow process. This has spurred transmitter designs optimized for ultra-low duty cycles.

[0003] Gaussian Frequency Shift Keying (GFSK) is a continuous-phase frequency shift keying modulation technique. It is characterized by ease of implementation, wide applicable bandwidth, strong anti-interference capability, suppression of out-of-band radiation, and compression of signal power. It is widely used in low-data-rate and low-cost personal wireless audio and video transmission systems and modern communication devices, such as Bluetooth and the IEEE 802.11 protocol. Traditional GFSK transmitters use a mixer to multiply the digital signal (after passing through a Gaussian low-pass filter and performing appropriate phase integration) with an orthogonal carrier signal, and then add the results. This process is characterized by high power consumption. Direct modulation, on the other hand, allows the digital signal to be passed through a Gaussian low-pass filter and directly modulated onto the radio frequency carrier. Typically, the modulation signal is applied to the voltage-controlled oscillator of a phase-locked loop frequency synthesizer, resulting in a simpler structure and lower power consumption.

[0004] In the implementation of GFSK direct modulation, to achieve finer frequency resolution to meet the frequency offset requirements of certain protocols, such as Bluetooth (BLE 4.0) which requires a frequency offset of 250kHz, phase-locked loops (PLLs) typically employ fractional frequency division. In fractional PLLs, the quantization noise generated by the Σ-Δ modulator needs to be filtered through the low-pass filter of the PLL feedback loop. By reducing the PLL bandwidth, the impact of quantization noise on the output phase noise can be reduced to a negligible level. However, reducing the PLL bandwidth limits the data rate of the closed-loop modulation; theoretically, the closed-loop modulation data rate should be less than or equal to the loop bandwidth. It is precisely this conflicting bandwidth requirement that complicates the design of low-noise, low-power fractional frequency division PLLs. In research on direct PLL modulation, type I integer frequency division PLLs are gaining increasing appeal in order to improve energy efficiency and data transmission rate. Summary of the Invention

[0005] To address the aforementioned technical problems in the existing technology, this invention proposes a passive, crystal-free GFSK transmitter chip, the specific technical solution of which is as follows:

[0006] A passive, crystal-free GFSK transmitter chip includes: an RF energy harvesting module, a power management module, a clock recovery module, and an open-loop modulation transmitter module. The RF energy harvesting module is used for wireless power supply. The power management module controls the power switch of the transmitter chip according to the power supply voltage value. When the power switch is on, the power management module supplies power to the open-loop modulation transmitter module. The clock recovery module provides a reference frequency for the open-loop modulation transmitter module. The open-loop modulation transmitter module multiplies the reference frequency to the RF frequency required for transmission and transmits the data signal.

[0007] Furthermore, the radio frequency energy harvesting module includes a receiving antenna, a matching network, a rectifier circuit, and a storage capacitor; the power management module includes a voltage monitoring and control circuit, a low-dropout linear regulator, and a bandgap reference circuit; the clock recovery module includes a first-order RC bandpass filter, a multi-stage self-biased amplifier, a pulse generation and shaping circuit, and a multi-stage injection-locked ring oscillator; the open-loop modulation transmitter module is a phase-locked loop circuit, including a phase detector, a master-slave sampling filter, a rail-to-rail buffer, a voltage-controlled oscillator, a true single-phase clock multimode divider, and a non-overlapping clock generator;

[0008] The receiving antenna receives radio frequency energy in the space and connects to the input of the rectifier circuit through a matching network. The two outputs of the rectifier circuit are connected to the storage capacitor and the voltage monitoring and control circuit, respectively. The voltage monitoring and control circuit detects the voltage on the storage capacitor in real time. When the detected voltage is greater than the threshold voltage, a control signal is generated to turn on the power switch. Then, the storage capacitor provides voltage to the low dropout linear regulator and the bandgap reference circuit, thereby powering the open-loop modulation transmitter module. The clock recovery module receives the second-order intermodulation signal generated by the rectifier circuit, filters, amplifies, and shapes the second-order intermodulation signal, and injects it into a multi-stage injection-locked ring oscillator to obtain the required reference frequency. Then, the reference frequency is multiplied to the radio frequency frequency required for transmission through the phase-locked loop of the open-loop modulation transmitter module. When transmitting data, the data to be transmitted is directly loaded onto the voltage-controlled oscillator after passing through a Gaussian filter for transmission.

[0009] Furthermore, the rectifier circuit adopts an N-stage cross-coupled bridge structure and is driven by differential RF input to output the voltage received by the receiving antenna in a voltage-doubled manner. The transistors in the first N / 2 stages of the rectifier circuit use low-threshold NMOS transistors and PMOS transistors, while the transistors in the last N / 2 stages use low-threshold transistors with higher voltage tolerance.

[0010] Furthermore, the voltage monitoring and control circuit adopts a structure based on intrinsic NMOS current reference and current comparator, and embeds a circuit structure for adjusting the voltage threshold value corresponding to the start and stop of the control. The circuit structure consists of an NMOS switch and three PMOS transistors connected in a diode manner, and the PMOS transistors have the same width-to-length ratio.

[0011] Furthermore, the voltage monitoring and control circuit is also connected to a delay circuit, which is used to delay the rising edge of the hysteresis window signal generated by the voltage monitoring and control circuit. The delay circuit is composed of multi-stage inverters and MOS capacitors.

[0012] The voltage monitoring and control circuit includes: NMOS transistors NM0~NM6, PMOS switching transistors PM1~PM4, and three voltage divider circuits, wherein transistors NM0 and NM1 are zero threshold transistors, and the three voltage divider circuits include a first voltage divider circuit, a second voltage divider circuit, and a third voltage divider circuit connected in series, and each voltage divider circuit is composed of PMOS transistors connected in a diode manner.

[0013] The gate of switching transistor PM1 is connected to a delay circuit. The source of switching transistor PM1 is connected to the drain of transistor NM1, the source of switching transistor PM2, the source of switching transistor PM3, the source of switching transistor PM4, and one end of the first voltage divider circuit. The drain of switching transistor PM1 is connected to the drain of transistor NM0. The gate of transistor NM0 is connected to the gate of transistor NM1, the source of transistor NM2, the source of transistor NM3, the source of transistor NM4, the source of transistor NM5, and one end of the third voltage divider circuit. The source of transistor NM0 is connected to the source of transistor NM1, the drain of transistor NM2, and the... The gate of transistor NM3 is connected to the gate of transistor NM3. The drain of transistor NM3 is connected to the drain of switch PM2, the gate of switch PM2, and the gate of switch PM3. The drain of switch PM3 is connected to the gate of switch PM4, the drain of transistor NM4, and the gate of transistor NM5. The drain of transistor NM5 is connected to the drain of switch PM4, the gate of transistor NM6, and the gate of switch PM1. The source of transistor NM6 is connected to the gate of transistor NM4, the intermediate node of the second voltage divider circuit, and the third voltage divider circuit. The drain of transistor NM6 is connected to the intermediate node of the first voltage divider circuit and the second voltage divider circuit.

[0014] Furthermore, the first-order RC bandpass filter is composed of a first-order high-pass filter and a first-order low-pass filter connected in series. The cutoff frequency of the high-pass filter is greater than or equal to the clock recovery frequency, and the cutoff frequency of the low-pass filter is less than or equal to the clock recovery frequency. Therefore, the center frequency of the first-order RC bandpass filter is equal to the clock recovery frequency.

[0015] The multi-stage self-biased amplifier consists of four stages, from the first stage to the fourth stage. The first stage is a common-source stage with a resistive self-biased active load, composed of a PMOS transistor, an NMOS transistor, and a megohm resistor. The source of the PMOS transistor is connected to the power supply voltage, and the source of the NMOS transistor is grounded. The gates of the PMOS and NMOS transistors are connected as the input terminal, and their drains are connected as the output terminal. The resistor is connected between the gate and drain of the PMOS and NMOS transistors to provide DC bias for the common-source stage. The second to fourth stage amplifiers are common-source stages with ordinary active loads. The second and third stage amplifiers further amplify the signal output from the first stage, while the fourth stage amplifier is used to limit the amplitude while amplifying.

[0016] The pulse generation and shaping circuit consists of a delay line and an AND gate. The delay line consists of a multi-stage current-biased inverter circuit.

[0017] The multi-stage injection-locked ring oscillator includes: a current mirror composed of PMOS switches PM5~PM8, three inverters, and three multi-point injected NMOS switches NM7, NM8, and NM9. The width-to-length ratio of the PMOS switches PM5, PM6, PM7, and PM8 is 1:1:1:1, and the width-to-length ratio of the NMOS switches NM7, NM8, and NM9 is 1:1:1. The three inverters are connected end-to-end to form a three-stage ring oscillator. The current mirror replicates the standard current of the bandgap reference circuit. The source of the multi-point injected NMOS is grounded, the drain is connected to the output of the inverter, and the gate is the injection-locked input port.

[0018] Furthermore, the phase detector adopts an XOR gate structure, and a master-slave sampling filter is connected after the phase detector. The master-slave sampling filter includes two NMOS transistor switches S1 and S2, two capacitors C1 and C2, and a first-order RC low-pass filter. The substrate of the NMOS transistor switch is grounded, the gate is the switch control port, and the source and drain are the signal connection ports of the switch. The rail-to-rail buffer is composed of a rail-to-rail operational amplifier. The non-inverting input terminal of the operational amplifier is the input port of the rail-to-rail buffer, and the output terminal of the operational amplifier is shorted to its inverting input terminal to form the output port of the rail-to-rail buffer. The common-mode input voltage range and output voltage range of the rail-to-rail buffer are from the negative power supply voltage to the positive power supply voltage.

[0019] Furthermore, the voltage-controlled oscillator (VCO) is an LC structure, using wire bonding inductors to replace on-chip inductors. The two output terminals of the VCO are respectively connected to two pads, PAD1 and PAD2, for wire bonding. The VCO includes transistors M1-M6, voltage-controlled capacitors D1-D2, and two numerically controlled capacitor arrays. Transistors M5 and M6 provide current to the VCO through a mirror source. Transistors M1-M4 form a cross-coupled transistor. The internode of the series-connected voltage-controlled capacitors D1-D2 is connected to the input control voltage VC. The two numerically controlled capacitor arrays are connected between the two output terminals of the VCO. One numerically controlled capacitor array contains MOM capacitors with large capacitance values, while the other numerically controlled capacitor array contains MOS capacitors with small capacitance values.

[0020] Furthermore, the true single-phase clock multimode divider consists of a 32 / 33 dual-mode prescaler and a programmable divider. The 32 / 33 dual-mode prescaler is composed of a true single-phase clock flip-flop, which uses only a single-phase clock signal to drive the flip-flop circuit. The operating frequency of the programmable divider is reduced to the tens of MHz range and is implemented using standard static logic synthesis.

[0021] Furthermore, the non-overlapping clock generator is composed of two types of gate circuits: NAND gates and inverters. Through the delay function of the gate circuits, the input clock is transformed into a pair of clocks with non-overlapping high and low levels at the same time, which are used as the switching control signals of the master-slave sampling filter.

[0022] Beneficial effects: This invention innovatively constructs a passive crystal-free GFSK transmitter, which achieves wireless power supply through an energy harvesting circuit. Wireless power supply eliminates the need for batteries, thereby eliminating battery costs and avoiding the trouble caused by battery life limitations and battery replacement issues in some special usage environments. The optimized rectifier circuit makes the wireless power supply more sensitive and has a longer range. It can also provide sufficient energy for the system to work normally even in environments with low spatial radio frequency energy density.

[0023] This invention utilizes an i-type phase-locked loop and a master-slave sampling filter circuit to achieve a wide loop bandwidth, thereby shortening the lock-in time of the phase-locked loop. This allows the transmitter to stabilize its output frequency in a shorter time after startup and to operate stably for a longer period under the same energy consumption conditions, thus improving the energy efficiency of wireless power supply. Furthermore, the wide loop bandwidth overcomes the limitation of loop bandwidth on the transmission data rate of direct modulation transmitters, enabling the open-loop modulation transmitter to achieve a data rate of over 2 Mbps.

[0024] This invention uses clock recovery to provide a reference frequency for the phase-locked loop (PLL), eliminating the need for an external crystal oscillator, reducing the size of the node chip, and making the battery-free and crystal-free chip suitable for applications with stringent size requirements. Simultaneously, using wire bonding inductors to replace on-chip inductors reduces the chip area of ​​the voltage-controlled oscillator to 1 / 10 of its original size. This reduction in chip area has significant economic benefits and demonstrates strong commercial value. Furthermore, the use of gold as the bonding wire material results in a high quality factor, which reduces the start-up power consumption of the voltage-controlled oscillator and also lowers the phase noise of the output frequency. Attached Figure Description

[0025] Figure 1 This is an overall system architecture diagram of a passive crystal-free GFSK transmitter chip according to an embodiment of the present invention;

[0026] Figure 2 This is a schematic diagram of the voltage monitoring and control circuit according to an embodiment of the present invention.

[0027] Figure 3 This is a circuit schematic diagram of the clock recovery module according to an embodiment of the present invention.

[0028] Figure 4 This is a circuit diagram of the voltage-controlled oscillator according to an embodiment of the present invention. Detailed Implementation

[0029] To make the objectives, technical solutions, and technical effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0030] like Figure 1 As shown in the illustration, an embodiment of the present invention discloses a passive crystal-free GFSK transmitter chip, comprising an RF energy harvesting module, a power management module, a clock recovery module, and an open-loop modulation transmitter module. The RF energy harvesting module provides wireless power, and the power management module controls the power switch of the transmitter chip based on the supply voltage value. When the power switch is on, the power management module supplies power to the open-loop modulation transmitter module. The clock recovery module provides a reference frequency (Fref) to the open-loop modulation transmitter module, which multiplies the reference frequency to the required RF frequency for transmission and then transmits the data signal.

[0031] The radio frequency energy harvesting module includes a receiving antenna, a matching network, a rectifier circuit, and a storage capacitor (Cstore). The power management module includes a voltage monitor, a low-dropout linear regulator (LDO), and a bandgap reference circuit (BGR). The clock recovery module includes a first-order RC bandpass filter (BPF), a multi-stage self-biased amplifier (AMP), a pulse generator and shaper circuit, and a multi-stage injection-locked ring oscillator. The open-loop modulation transmitter module is a phase-locked loop circuit, including a phase detector, a master-slave sampling filter (MSSF), a rail-to-rail buffer, a voltage-controlled oscillator, a true single-phase clock multimode divider (TSPC), and a non-overlap clock generator.

[0032] The transmitter chip in this embodiment of the invention requires power from radio frequency (RF) energy collected from the environment by an antenna and rectifier circuit within a specific frequency range. This collected energy is stored in a large capacitor. Before the transmitter starts operating, the RF energy harvesting module receives RF energy from the environment via an antenna, primarily from the 900MHz ISM band. The receiving antenna is an on-chip differential antenna, connected to the input of the rectifier circuit via a matching network. The output of the rectifier circuit is connected to a storage capacitor and a voltage monitoring and control circuit. The voltage monitoring and control circuit detects the output voltage at the harvesting end. When the voltage across the storage capacitor exceeds a certain value (a preset threshold), the circuit generates a control signal to open the power switch between the RF energy harvesting module and the open-loop modulation transmitter module. Voltage is then supplied to the low-dropout linear regulator and the bandgap reference circuit through the storage capacitor. The bandgap reference circuit generates a current unaffected by PVT (process, voltage, temperature) to provide a reference current for the charge pump and voltage-controlled oscillator. The bandgap reference circuit also generates a precise voltage to provide a reference voltage for the low-dropout linear regulator, thereby powering the entire open-loop modulation transmitter module. When the open-loop modulation transmitter module consumes some electrical energy after operating for a period of time, and the voltage on the storage capacitor drops to a level insufficient to power the low-dropout linear regulator and bandgap reference circuit, the voltage monitoring and control circuit generates a control signal to turn off the power switch, the phase-locked loop stops working, and the storage capacitor continues to receive the charge collected by the rectifier circuit to prepare for the next system power supply.

[0033] The clock recovery module generates the reference frequency for the open-loop modulation transmitter module by filtering, amplifying, and shaping the second-order intermodulation frequency generated from the power supply frequency and then injecting it into a multi-stage injection-locked ring oscillator. A reference frequency as low as 2MHz and an integer-division phase-locked loop (PLL) are used to reduce the overall power consumption of the transmitter chip and eliminate the effects of fractional spurious signals. The 2MHz reference frequency originates from the second-order intermodulation signal generated by two external power supply frequency sources through a nonlinear rectifier circuit. This signal is bandpass filtered, amplified, and shaped before being injected into the multi-stage injection-locked ring oscillator. The injection-locking method yields a reference frequency with high spectral purity and low jitter. The PLL then multiplies the reference frequency to the required RF frequency for transmission. When data needs to be transmitted, the data is directly passed through a Gaussian filter and loaded onto a voltage-controlled oscillator for transmission. During the data transmission phase, the phase-locked loop is in an open-loop state. The control voltage on the voltage-controlled oscillator is the voltage on the large capacitor after the rail-to-rail buffer. In order to ensure that the control voltage of the voltage-controlled oscillator drifts sufficiently during the data transmission time after the open loop, the capacitor after the rail-to-rail buffer needs to be large enough. The use of the rail-to-rail buffer allows the capacitor to be increased arbitrarily without affecting the loop bandwidth of the phase-locked loop.

[0034] The rectifier circuit employs an N-stage cross-coupled bridge structure and is driven by differential RF input, outputting the voltage received by the receiving antenna as a voltage multiplier. The differential RF input-driven active gate bias mechanism simultaneously achieves low on-resistance and low reverse leakage current, thus realizing high-low energy conversion efficiency. The first N / 2 stages of the rectifier circuit use low-threshold NMOS and PMOS transistors. The use of low-threshold transistors increases the sensitivity of the rectifier circuit, allowing it to output higher voltages even in environments with low RF energy density. The static bias voltage of the transistors in the cross-coupled bridge structure is generated by the rectifier circuit itself. When the voltage amplitude of the RF signal applied to the MOS transistor is less than the threshold voltage of the MOS transistor, the CMOS rectifier circuit driven by differential RF input cannot start operating. When the input voltage is greater than the threshold voltage of the first N / 2 stages of transistors, the voltage of each output node increases with the number of rectification stages. To prevent excessive gate voltage from damaging the NMOS transistors, the transistors in the last N / 2 stages use low-threshold transistors with higher voltage tolerance. Meanwhile, the real part of the rectifier's input impedance decreases as the number of stages increases, making it difficult to match the antenna impedance. Therefore, the value of N can be chosen as a trade-off.

[0035] The voltage monitoring and control circuit employs a current reference and current comparator structure based on intrinsic NMOS transistors, embedding a circuit structure for adjusting the voltage threshold values ​​corresponding to start-up and stop. Typically, this circuit structure consists of an NMOS switch and three voltage divider resistors. To ensure a sufficiently large load resistance at the rectifier circuit output, the series resistance of the voltage divider resistors needs to reach the megaohm level. This enormous resistance value leads to significant chip area consumption and introduces severe thermal noise. To avoid these drawbacks, this invention uses PMOS transistors connected in a diode configuration to replace the resistors for voltage division. Furthermore, to ensure voltage division accuracy, all PMOS transistors used for voltage division have the same aspect ratio, and the voltage division ratio is determined by the proportion of each part of the PMOS transistors. The voltage monitoring and control circuit generates a hysteresis window signal with an adjustable threshold. Simultaneously, it delays the rising edge of the hysteresis window for a period of time via a delay circuit composed of multiple inverters and MOS capacitors. The delay time is adjusted by controlling the width-to-length ratio of the MOS capacitors. Then, the signals before and after the hysteresis window delay are passed through an AND gate to obtain a power-on reset signal (RSTP). This reset signal serves as the reset signal for the digital circuitry in the entire transmitter chip. This circuit structure is robust to PVT variations and power supply ramp time, and its quiescent current is as low as below 80nA.

[0036] like Figure 2As shown, this invention relates to a voltage monitoring and control circuit in a passive crystal-free GFSK transmitter. Zero-threshold NMOS transistors NM0 and NM1 generate a reference current under the control of PMOS switch PM1, functioning as a current reference generator. NMOS transistors NM2 and NM3, along with PMOS switches PM2 and PM3, form two current mirrors to replicate the current generated by the zero-threshold NMOS current reference generator. The voltage at node V2 is determined by both the reference current and the current of NM4. The current of NM4 is determined by NM6 and voltage divider resistors R1, R2, and R3. When the current of NM4 is greater than the reference current, node V2 discharges, causing its voltage to decrease; conversely, when the current of NM4 is less than the reference current, node V2 is charged, causing its voltage to increase. When the input voltage rises from zero, because the threshold of the zero-threshold NMOS is much lower than that of a regular NMOS, the reference current is much larger than the current of NM1. The voltage at node V2 is charged to a high level, causing the inverter composed of PM4 and NM5 to flip, while node V0 remains low. As the input voltage increases further, the voltage across resistor R3 increases, leading to an increase in the gate-source voltage of NM4, and consequently, an increase in the output current. When the NM4 current exceeds the reference current, node V2 discharges to a low level, and the output VO goes high. When VO goes high, transistor NM0 is completely turned off by PM1, and the current generated by the current reference is provided solely by transistor NM1. As the input voltage begins to decrease, the current in NM4 gradually decreases. When the current drops below the reference current, node V2 is charged to a high level, and node V0 goes low. Because the input voltage when node V0 transitions from low to high is greater than the input voltage when node V0 transitions from high to low, a hysteresis window is achieved. The input voltage Vmax when node V0 transitions from low to high and the input voltage Vmin when node V0 transitions from high to low can both be adjusted independently. The ratio of R1, R2 and R3 and the width-to-length ratio of the switching transistor NM6 together determine the magnitude of Vmax and Vmin.

[0037] like Figure 3As shown, the first-order RC bandpass filter consists of a first-order high-pass filter and a first-order low-pass filter connected in series. The cutoff frequency of the high-pass filter is greater than or equal to the clock recovery frequency, and the cutoff frequency of the low-pass filter is less than or equal to the clock recovery frequency. The center frequency of the bandpass filter is equal to the clock recovery frequency. The multi-stage self-biased amplifier is divided into four stages. The first stage amplifier is a common-source stage with a resistive self-biased active load, consisting of a PMOS transistor, an NMOS transistor, and a resistor. The source of the PMOS transistor is connected to the power supply voltage, and the source of the NMOS transistor is grounded. The gates of the PMOS and NMOS transistors are connected as the input terminal, and their drains are connected as the output terminal. A megohm-level resistor is connected between the gates and drains of the PMOS and NMOS transistors to provide DC bias for the common-source stage. The second to fourth stages of the amplifier are common-source stages with ordinary active loads. The second and third stages amplify the signal output from the first stage, while the fourth stage amplifies and limits the signal. The pulse generation and shaping circuit consists of a delay line and an AND gate. The delay line is composed of a multi-stage current-biased inverter circuit. The multi-stage injection-locked ring oscillator consists of a current mirror composed of PMOS switches PM5, PM6, PM7, and PM8, three inverters, and three multi-point injected NMOS switches NM7, NM8, and NM9. The width-to-length ratio of PM5, PM6, PM7, and PM8 is 1:1:1:1, and the width-to-length ratio of NM7, NM8, and NM9 is 1:1:1. The three inverters are connected end-to-end to form a three-stage ring oscillator. The current mirror replicates the standard current of the bandgap reference circuit to control the power consumption of the ring oscillator. The sources of the multi-point injected NMOS switches are grounded, their drains are connected to the output of the inverters, and their gates are the injection-locked input ports.

[0038] The output of a first-order RC bandpass filter is connected to the input port of the first-stage amplifier. The second-order intermodulation signal, outputting at 2MHz from this port, is amplified by the filter and then enters the first-stage self-biased active-load common-source amplifier circuit. It is then amplified by the second and third-stage amplifiers. The fourth-stage amplifier provides limiting, resulting in a square wave signal. This square wave signal then enters a shaping circuit composed of delay lines and AND gates. The delay circuit delays the square wave, and the signals before and after the delay are passed through the AND gates to obtain a narrow pulse signal with a constant frequency and low duty cycle. This narrow pulse signal is then injected into a ring oscillator through the gate of an NMOS transistor. The free-running frequency of this ring oscillator is close to the frequency recovered from the clock. When the ring oscillator receives the injected signal, it no longer oscillates at its free-running frequency but at the injected frequency.

[0039] The phase detector employs an XOR gate structure. A master-slave sampling filter is connected after the phase detector. The master-slave sampling filter consists of two NMOS transistor switches S1 and S2, two capacitors C1 and C2, and a first-order RC low-pass filter. The substrate of the NMOS switches is grounded, the gate is the switch control port, and the source and drain are the signal connection ports of the switches. The rail-to-rail buffer consists of a rail-to-rail operational amplifier. The non-inverting input of the operational amplifier is the input port of the buffer, and the output of the operational amplifier is shorted to its inverting input to form the output port of the buffer. The common-mode input voltage range and output voltage range of the rail-to-rail buffer can range from the negative power supply voltage to the positive power supply voltage.

[0040] like Figure 4 As shown, the voltage-controlled oscillator (VCO) is an LC structure, using wire bonding inductors instead of on-chip inductors. The wire bonding can be made of gold, resulting in a high quality factor. M1-M4 are cross-coupled transistors, and transistors M5 and M6 provide current to the VCO via a mirror source. D1 and D2 are two voltage-controlled capacitors, and VC is the input control voltage. PAD1 and PAD2 are two pads inside the chip, connected to the VCO's output. PAD3 and PAD4 are two pads outside the chip, used to connect the wire bonding for packaging. The wire bonding, made of gold and 1mm long with a diameter of 25µm, has an inductance of approximately 0.8675nH. Two numerically controlled capacitor arrays are connected between the two outputs of the VCO. One array contains MOM capacitors with a larger capacitance, used by AFC to resist PVT variations. The other array contains MOS capacitors with a smaller capacitance, used for data modulation. Baseband data is filtered by a Gaussian filter and then directly controls the MOS capacitor array.

[0041] The true single-phase clock multimode divider consists of a 32 / 33 dual-mode prescaler and a programmable divider. The 32 / 33 dual-mode prescaler is constructed from a true single-phase clock flip-flop, using only a single-phase clock signal to drive the flip-flop circuit, thus avoiding synchronization issues between the two signals. The programmable divider operates at frequencies down to the tens of MHz range and is implemented using standard static logic synthesis. The non-overlapping clock generator consists of NAND gates and inverters. Through the delay function of the gates, it transforms the input clock into a pair of clocks with non-overlapping high and low levels at the same time, which are used as the switching control signals for the master-slave sampling filter.

[0042] In summary, this invention proposes a chip design scheme for a passive crystal-free GFSK transmitter based on i-type phase-locked loop open-loop modulation, featuring low power consumption and small size, suitable for wireless sensor network nodes. This invention uses radio frequency energy harvesting to power the entire chip system, eliminating the need for batteries. This reduces battery pollution and sensor size, while also avoiding the inconvenience of battery replacement in wireless network nodes, improving the user experience. Furthermore, the chip eliminates the need for an external crystal oscillator through clock recovery, employing a reference frequency as low as 2MHz and an integer-division phase-locked loop to reduce system power consumption and eliminate the effects of fractional spurious signals. The clock recovery scheme is compatible with the wireless power supply scheme. The 2MHz reference frequency comes from the second-order intermodulation signal generated by two external power supply frequency sources through a nonlinear rectification circuit. This signal is bandpass filtered, amplified, and shaped before being injected into a ring oscillator. A reference frequency signal with high spectral purity and low jitter is obtained through injection locking. Then, the reference frequency is multiplied to the required radio frequency for transmission using an integer-division phase-locked loop.

[0043] The adopted open-loop modulation scheme of the phase-locked loop (PLL) is suitable for scenarios that do not require continuous communication, such as sensor network nodes. Open-loop modulation overcomes the low data rate disadvantage of closed-loop modulation, enabling transmission data rates of over 2 Mbps and an output frequency range of 2.4 GHz to 2.5 GHz, making it suitable for transmitters of standard protocols such as Bluetooth Low Energy. The voltage-controlled oscillator (VCO) in the PLL uses an LC VCO with bonded wires as inductors, which features high Q-value and small chip area. Compared to on-chip inductors, the chip area of ​​the VCO is reduced to 1 / 10 of the original. At the same time, the high Q-value further reduces the power consumption required for oscillation start-up and also reduces the phase noise of the output frequency, demonstrating strong commercial value.

[0044] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention in any way. Although the implementation process of the present invention has been described in detail above, those skilled in the art can still modify the technical solutions described in the foregoing examples or make equivalent substitutions for some of the technical features. All modifications and equivalent substitutions made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A passive, crystal-free GFSK transmitter chip, characterized in that, include: The system includes a radio frequency energy harvesting module, a power management module, a clock recovery module, and an open-loop modulation transmitter module. The radio frequency energy harvesting module is used for wireless power supply. The power management module controls the power switch of the transmitter chip according to the power supply voltage value. When the power switch is turned on, the power management module supplies power to the open-loop modulation transmitter module. The clock recovery module provides a reference frequency for the open-loop modulation transmitter module. The open-loop modulation transmitter module multiplies the reference frequency to the radio frequency required for transmission and transmits the data signal. The radio frequency energy harvesting module includes a receiving antenna, a matching network, a rectifier circuit, and a storage capacitor; the power management module includes a voltage monitoring and control circuit, a low-dropout linear regulator, and a bandgap reference circuit; the clock recovery module includes a first-order RC bandpass filter, a multi-stage self-biased amplifier, a pulse generation and shaping circuit, and a multi-stage injection-locked ring oscillator; the open-loop modulation transmitter module is a phase-locked loop circuit, including a phase detector, a master-slave sampling filter, a rail-to-rail buffer, a voltage-controlled oscillator, a true single-phase clock multimode divider, and a non-overlapping clock generator; The receiving antenna receives radio frequency energy in the space and connects to the input of the rectifier circuit through a matching network. The two outputs of the rectifier circuit are connected to the storage capacitor and the voltage monitoring and control circuit, respectively. The voltage monitoring and control circuit detects the voltage on the storage capacitor in real time. When the detected voltage is greater than the threshold voltage, a control signal is generated to turn on the power switch. Then, the storage capacitor provides voltage to the low dropout linear regulator and the bandgap reference circuit, thereby powering the open-loop modulation transmitter module. The clock recovery module receives the second-order intermodulation signal generated by the rectifier circuit, filters, amplifies, and shapes the second-order intermodulation signal, and injects it into a multi-stage injection-locked ring oscillator to obtain the required reference frequency. Then, the reference frequency is multiplied to the radio frequency frequency required for transmission through the phase-locked loop of the open-loop modulation transmitter module. When transmitting data, the data to be transmitted is directly loaded onto the voltage-controlled oscillator after passing through a Gaussian filter for transmission.

2. The passive crystal-free GFSK transmitter chip as described in claim 1, characterized in that, The rectifier circuit adopts an N-stage cross-coupled bridge structure and is driven by differential RF input. It outputs the voltage received by the receiving antenna in a voltage-doubled manner. The transistors in the first N / 2 stages of the rectifier circuit use low-threshold NMOS and PMOS transistors, while the transistors in the last N / 2 stages use low-threshold transistors with higher voltage tolerance.

3. The passive crystal-free GFSK transmitter chip as described in claim 1, characterized in that, The voltage monitoring and control circuit adopts a current reference and current comparator structure based on intrinsic NMOS, and embeds a circuit structure for adjusting the voltage threshold value corresponding to the start and stop of the control. The circuit structure consists of an NMOS switch and three PMOS transistors connected in a diode manner, and the PMOS transistors have the same width-to-length ratio.

4. The passive crystal-free GFSK transmitter chip as described in claim 3, characterized in that, The voltage monitoring and control circuit is also connected to a delay circuit, which is used to delay the rising edge of the hysteresis window signal generated by the voltage monitoring and control circuit. The delay circuit is composed of multi-stage inverters and MOS capacitors. The voltage monitoring and control circuit includes: NMOS transistors NM0~NM6, PMOS switching transistors PM1~PM4, and three voltage divider circuits, wherein transistors NM0 and NM1 are zero threshold transistors, and the three voltage divider circuits include a first voltage divider circuit, a second voltage divider circuit, and a third voltage divider circuit connected in series, and each voltage divider circuit is composed of PMOS transistors connected in a diode manner. The gate of switching transistor PM1 is connected to a delay circuit. The source of switching transistor PM1 is connected to the drain of transistor NM1, the source of switching transistor PM2, the source of switching transistor PM3, the source of switching transistor PM4, and one end of the first voltage divider circuit. The drain of switching transistor PM1 is connected to the drain of transistor NM0. The gate of transistor NM0 is connected to the gate of transistor NM1, the source of transistor NM2, the source of transistor NM3, the source of transistor NM4, the source of transistor NM5, and one end of the third voltage divider circuit. The source of transistor NM0 is connected to the source of transistor NM1, the drain of transistor NM2, and the... The gate of transistor NM3 is connected to the gate of transistor NM3. The drain of transistor NM3 is connected to the drain of switch PM2, the gate of switch PM2, and the gate of switch PM3. The drain of switch PM3 is connected to the gate of switch PM4, the drain of transistor NM4, and the gate of transistor NM5. The drain of transistor NM5 is connected to the drain of switch PM4, the gate of transistor NM6, and the gate of switch PM1. The source of transistor NM6 is connected to the gate of transistor NM4, the intermediate node of the second voltage divider circuit, and the third voltage divider circuit. The drain of transistor NM6 is connected to the intermediate node of the first voltage divider circuit and the second voltage divider circuit.

5. A passive, crystal-free GFSK transmitter chip as described in claim 1, characterized in that, The first-order RC bandpass filter is composed of a first-order high-pass filter and a first-order low-pass filter connected in series. The cutoff frequency of the high-pass filter is greater than or equal to the clock recovery frequency, and the cutoff frequency of the low-pass filter is less than or equal to the clock recovery frequency. Therefore, the center frequency of the first-order RC bandpass filter is equal to the clock recovery frequency. The multi-stage self-biased amplifier consists of four stages, from the first stage to the fourth stage. The first stage is a common-source stage with a resistive self-biased active load, composed of a PMOS transistor, an NMOS transistor, and a megohm resistor. The source of the PMOS transistor is connected to the power supply voltage, and the source of the NMOS transistor is grounded. The gates of the PMOS and NMOS transistors are connected as the input terminal, and their drains are connected as the output terminal. The resistor is connected between the gate and drain of the PMOS and NMOS transistors to provide DC bias for the common-source stage. The second to fourth stage amplifiers are common-source stages with ordinary active loads. The second and third stage amplifiers further amplify the signal output from the first stage, while the fourth stage amplifier is used to limit the amplitude while amplifying. The pulse generation and shaping circuit consists of a delay line and an AND gate. The delay line consists of a multi-stage current-biased inverter circuit. The multi-stage injection-locked ring oscillator includes: a current mirror composed of PMOS switches PM5~PM8, three inverters, and three multi-point injected NMOS switches NM7, NM8, and NM9. The width-to-length ratio of the PMOS switches PM5, PM6, PM7, and PM8 is 1:1:1:1, and the width-to-length ratio of the NMOS switches NM7, NM8, and NM9 is 1:1:

1. The three inverters are connected end-to-end to form a three-stage ring oscillator. The current mirror replicates the standard current of the bandgap reference circuit. The source of the multi-point injected NMOS is grounded, the drain is connected to the output of the inverter, and the gate is the injection-locked input port.

6. The passive crystal-free GFSK transmitter chip as described in claim 1, characterized in that, The phase detector adopts an XOR gate structure. A master-slave sampling filter is connected after the phase detector. The master-slave sampling filter includes two NMOS transistor switches S1 and S2, two capacitors C1 and C2, and a first-order RC low-pass filter. The substrate of the NMOS transistor switch is grounded, the gate is the switch control port, and the source and drain are the signal connection ports of the switch. The rail-to-rail buffer is composed of a rail-to-rail operational amplifier. The non-inverting input terminal of the operational amplifier is the input port of the rail-to-rail buffer. The output terminal of the operational amplifier is shorted to its inverting input terminal to form the output port of the rail-to-rail buffer. The common-mode input voltage range and output voltage range of the rail-to-rail buffer are from the negative power supply voltage to the positive power supply voltage.

7. A passive, crystal-free GFSK transmitter chip as described in claim 1, characterized in that, The voltage-controlled oscillator (VCO) is an LC structure, using wire bonded inductors instead of on-chip inductors. The two outputs of the VCO are connected to two pads, PAD1 and PAD2, respectively, for wire bonded package mating. The VCO includes transistors M1-M6, voltage-controlled capacitors D1-D2, and two numerically controlled capacitor arrays. Transistors M5 and M6 provide current to the VCO through a mirror source. Transistors M1-M4 form a cross-coupled transistor. The internode of the series-connected voltage-controlled capacitors D1-D2 is connected to the input control voltage VC. The two numerically controlled capacitor arrays are connected between the two outputs of the VCO. One array contains MOM capacitors with large capacitance, while the other array contains MOS capacitors with small capacitance.

8. A passive, crystal-free GFSK transmitter chip as described in claim 1, characterized in that, The true single-phase clock multimode divider consists of a 32 / 33 dual-mode prescaler and a programmable divider. The 32 / 33 dual-mode prescaler is composed of a true single-phase clock flip-flop, which uses only a single-phase clock signal to drive the flip-flop circuit. The operating frequency of the programmable divider is reduced to the tens of MHz range and is implemented using standard static logic synthesis.

9. A passive, crystal-free GFSK transmitter chip as described in claim 1, characterized in that, The non-overlapping clock generator is composed of two types of gate circuits: NAND gates and inverters. Through the delay function of the gate circuits, the input clock is transformed into a pair of clocks with non-overlapping high and low levels at the same time, which are used as the switching control signals of the master-slave sampling filter.

Images