Timeout interrupt system, method, apparatus, electronic device, and storage medium

Abstract

The application relates to the technical field of computer architecture, and provides a timeout interrupt system, method, device, electronic equipment and storage medium, the system is applied to a chip, the system comprises a command processor and a computing core, the command processor comprises a distribution module and a monitoring module; the distribution module is used for receiving a data packet sent by an external processor, and sending the data packet to the monitoring module and the computing core; the computing core is used for executing the data packet, and sending an execution completion feedback to the monitoring module after the execution is completed; the monitoring module is used for locally establishing a backup record of the data packet, and starting timing monitoring for the backup record; if it is determined that the execution is timed out through monitoring, a timeout interrupt signal is triggered, and the timeout interrupt signal is fed back to the external processor through the distribution module, the crossing from traditional software passive inquiry to hardware active monitoring alarm is realized, the execution state of the hardware can be mastered in real time, the external feedback can be timely given when an exception occurs, and therefore the fault discovery and response delay are greatly shortened.

Description

Technical Field

[0001] This invention relates to the field of computer architecture technology, and more particularly to a timeout interrupt system, method, apparatus, electronic device, and storage medium. Background Technology

[0002] With the development of integrated circuit technology, modern GPUs and artificial intelligence chips are widely used in many industries. To meet computing power demands, a large number of tasks are processed by the chip's computing cores. However, under high load or complex scenarios, the computing cores are prone to unexpected crashes, failing to write back the completed data normally.

[0003] In current GPU designs, software sends instructions to a hardware control unit, which then retrieves the data packets and delivers them to the compute cores for execution. However, after issuing the instructions, the software can only confirm its status by querying a specific memory address after the data packet execution is complete. In this scenario, if the compute core unexpectedly crashes, the data packet cannot be completed correctly, and the software struggles to detect the anomaly in a timely manner. It can only continuously poll or wait, making it difficult to quickly locate the fault and potentially leading to further task issuance and serious system errors. Summary of the Invention

[0004] This invention provides a timeout interrupt system, method, apparatus, electronic device, and storage medium to solve the problem in the prior art that when a computing core unexpectedly hangs, the software cannot detect the abnormality in time, cannot quickly locate the fault, and may continue to issue tasks, causing system errors.

[0005] This invention provides a timeout interrupt system applied to a chip. The system includes a command processor and a computing core. The command processor includes a distribution module and a monitoring module. The distribution module is used to receive data packets sent by an external processor and send the data packets to the monitoring module and the computing core; The computing core is used to execute the data packet and sends execution completion feedback to the monitoring module after execution is completed; The monitoring module is used to establish a backup record of the data packet locally and start timing monitoring for the backup record to monitor the execution time of the calculation and verification of the data packet. If the execution time reflects an execution timeout, a timeout interrupt signal is triggered and fed back to the external processor through the distribution module. If the execution completion feedback is received before the execution timeout, the timing monitoring is stopped.

[0006] According to a timeout interruption system provided by the present invention, the monitoring module includes a storage module, a retrieval module, and a timeout detection module; The storage module includes multiple entries, each entry being used to store the identity identifier of a data packet, a valid status bit indicating the occupancy status of the entry, and a corresponding timer; The retrieval module is used to retrieve target entries in the storage module whose valid status bit is idle, write the identity of the received data packet into the target entry, update the valid status bit of the target entry to occupied status, and start the timer corresponding to the target entry for timing monitoring. The timeout detection module is used to detect the execution duration of each entry in the storage module that is in the occupied state in real time. If the execution duration exceeds the duration threshold, an execution timeout is determined.

[0007] According to a timeout interrupt system provided by the present invention, the distribution module is provided with a port connected to the interrupt line of the timer corresponding to each entry in the storage module, and the interrupt line of the timer corresponding to each entry is connected to the interrupt line of the port in a one-to-one correspondence. The timeout detection module is used to pull high the interrupt line of the corresponding timer to trigger the timeout interrupt signal when a timeout occurs. The distribution module is also used to respond to the timeout interrupt signal, determine the identity of the timed-out data packet based on the interrupt line of the port connected to the high interrupt line of the timer, and feed back the identity as interrupt information to the external processor.

[0008] According to the timeout interruption system provided by the present invention, the monitoring module further includes a completion confirmation module; The completion confirmation module is used to receive the execution completion feedback sent by the computing core, parse the return identifier from the execution completion feedback, compare the return identifier with the identity identifier in each entry in the storage module, and if the comparison is consistent, control the timer of the corresponding entry to reset to stop the timing monitoring, and update the valid status bit of the corresponding entry to the idle state; the return identifier is the identity identifier of the data packet that has been executed.

[0009] According to the timeout interrupt system provided by the present invention, the monitoring module further includes a data packet parsing module; The data packet parsing module is used to receive the data packet sent by the distribution module, parse the identity identifier from the data packet, and send the identity identifier to the retrieval module; The retrieval module is used to sequentially search among multiple entries in the storage module, and the first entry whose valid status bit is idle is selected as the target entry.

[0010] The present invention also provides a timeout interrupt method, applied to a timeout interrupt system as described in any of the preceding claims, the method comprising: Receive data packets sent by an external processor; Execute the data packet; and, A backup record of the data packet is created locally, and timing monitoring is started for the backup record to monitor the execution time of the data packet; If the execution duration reflects an execution timeout, a timeout interrupt signal is triggered and fed back to the external processor; If the data packet is confirmed to have been executed before the execution timeout, then the timing monitoring is stopped.

[0011] According to a timeout interruption method provided by the present invention, the step of establishing a backup record of the data packet locally and starting timing monitoring for the backup record to monitor the execution duration of the data packet includes: The identity identifier is parsed from the data packet; Search for a target entry with an idle status bit among multiple entries, write the identity identifier into the target entry, update the valid status bit of the target entry to the occupied status, and start the timer corresponding to the target entry for timing monitoring to monitor the execution duration of the data packet; each entry is used to store the identity identifier of a data packet, the valid status bit indicating the occupancy status of the entry, and the corresponding timer; If the execution duration reflects an execution timeout, triggering a timeout interrupt signal and feeding it back to the external processor includes: If the execution time exceeds the time threshold, an execution timeout is determined. In the event of a timeout, the interrupt line of the corresponding timer is pulled high to trigger the timeout interrupt signal; In response to the timeout interrupt signal, the identity of the timed-out data packet is determined based on the high interrupt line of the timer, and the identity is fed back to the external processor as interrupt information.

[0012] The present invention also provides a timeout interrupt device, applied to a timeout interrupt system as described in any of the preceding claims, the device comprising: The distribution unit is used to receive data packets sent by an external processor. An execution unit is configured to execute the data packet; and, The monitoring unit is used to establish a backup record of the data packet locally and start timing monitoring for the backup record to monitor the execution time of the data packet; If the execution duration reflects an execution timeout, a timeout interrupt signal is triggered and fed back to the external processor; If the data packet is confirmed to have been executed before the execution timeout, then the timing monitoring is stopped.

[0013] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and running on the processor, wherein the processor, when executing the computer program, implements the timeout interrupt method as described above.

[0014] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the timeout interrupt method as described above.

[0015] The timeout interrupt system, method, apparatus, electronic device, and storage medium provided by this invention construct a collaborative mechanism between the distribution module and the monitoring module within the command processor. By establishing local data packet backup records and independently initiating timing monitoring, it achieves a leap from traditional software passive querying to hardware active monitoring and alarming. It can not only grasp the execution status of hardware in real time with data packets as fine granularity, but also quickly feed back fault information to the external processor through timeout interrupt signals when the computing core encounters abnormal conditions. This greatly shortens the delay in fault detection and response, avoids long-term invalid occupation of hardware resources in abnormal states, and significantly improves the robustness and operating efficiency of the system. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the timeout interrupt system provided by the present invention; Figure 2 This is an overall structural diagram of the timeout interrupt system provided by the present invention; Figure 3 This is a flowchart illustrating the timeout interruption method provided by the present invention; Figure 4 This is a schematic diagram of the timeout interrupt device provided by the present invention; Figure 5 This is a schematic diagram of the structure of the electronic device provided by the present invention.

[0018] Figure label: 110: Distribution module; 120: Monitoring module; 130: Computing core; 121: Storage module; 122: Retrieval module; 123: Timeout detection module; 124: Completion confirmation module; 125: Data packet parsing module; 410: Distribution unit; 420: Execution unit; 430: Monitoring unit; 510: Processor; 520: Communication interface; 530: Memory; 540: Communication bus. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0020] With the rapid development of integrated circuit technology, modern GPU (Graphics Processing Unit) chips and various artificial intelligence chips have been widely used in various industries. In practical applications, to meet the ever-increasing demand for computing power, a large number of tasks are processed within the chip's computing cores. However, under high load or complex scenarios, the computing core may unexpectedly hang during execution. In this case, the computing core cannot continue to execute tasks and therefore cannot write back completed data. Simultaneously, because the software is unaware of the unexpected situation with the computing core, it continues to wait and may even continue to issue new tasks. This prevents the software from detecting the fault in time, resetting, or mitigating the damage, thus severely impacting the GPU's efficiency and the system's stability.

[0021] In current GPU designs, instructions are typically issued from software (an external CPU, or Central Processing Unit) to the microcontroller unit (MCU) in the hardware. The MCU then performs the packet fetching (Pkt) operation and forwards the packet to the downstream GPU core for execution. After configuring the internal hardware registers and issuing instructions, the software's method of obtaining execution status is relatively passive. It can only confirm the completion of the current Pkt by querying data at a specific address in memory after the current packet has been executed. In other words, the computing core only writes the completion status back to memory when the Pkt has successfully completed, allowing the software to perceive the successful completion.

[0022] However, this mechanism has a significant flaw. Because the Command Processor (CP) lacks an active awareness mechanism, when an unexpected situation occurs in the computing core causing the current task (Pkt) to fail to complete normally, it cannot write the completed data back to memory because it did not finish executing properly. At this point, the software cannot detect this abnormal state of "Pkt failing to complete normally" and can only guess the hardware status through continuous polling or long waiting periods. This not only prevents the software from quickly locating the fault, but more seriously, the software may continue to issue new tasks to the computing core without its knowledge, causing serious system-level errors.

[0023] To address this issue, the present invention provides a timeout interrupt system designed to solve the problem in existing technologies where the lack of a hardware-based proactive alarm mechanism leads to software's inability to promptly detect abnormal states of the computing core during data packet execution, resulting in prolonged system stagnation or accumulation of erroneous instructions. By establishing a data packet backup mechanism within the command processor and performing independent timing monitoring, the system can proactively trigger a timeout interrupt signal at the data packet level when the computing core times out, and feed it back to the external processor, thereby ensuring that the software can quickly identify the fault and take appropriate action.

[0024] Figure 1 This is a schematic diagram of the timeout interrupt system provided by the present invention. This system can be applied to various chips containing instruction dispatch and execution architectures, such as GPUs, AI (Artificial Intelligence) chips, and SoCs (System on Chips). Figure 1 As shown, the system includes a command processor and a computing core 130. The command processor includes a distribution module 110 and a monitoring module 120. The distribution module is used to receive data packets sent by external processors and send the data packets to the monitoring module and the computing core; The computing core is used to execute data packets and sends execution completion feedback to the monitoring module after execution is complete; The monitoring module is used to establish a backup record of the data packet locally and start timing monitoring for the backup record to monitor and calculate the execution time of the data packet. If the execution time reflects an execution timeout, a timeout interrupt signal is triggered and fed back to the external processor through the distribution module. If the execution completion feedback is received before the execution timeout, the timing monitoring stops.

[0025] Specifically, in this embodiment of the invention, the timeout interrupt system mainly consists of two core components: a command processor and a computing core. These two components work together to complete task flow and monitoring. The command processor, as the internal management hub of the chip, integrates a distribution module and a monitoring module. The cooperation of these two modules enables proactive monitoring of the data packet execution status. In detail, the workflow of the timeout interrupt system and the coordination mechanism of its components are as follows: First, the distribution module located within the command processor acts as the gateway for the chip's interaction with the outside world. It is responsible for receiving data packets (Pkt) sent by external processors (typically the host CPU or driver software). These data packets are the basic instruction units for hardware-software interaction. Depending on the application scenario, they can be a set of instructions for a frame of image to be rendered, a descriptor for a computational task, or other instructions; this embodiment of the invention does not impose specific limitations on this. After receiving the data packet, the distribution module does not simply transmit it unidirectionally to the computation core as in traditional methods. Instead, it employs a dual-path distribution mechanism: on one hand, it sends the data packet to the computation core, where the core performs actual graphics rendering, logical operations, data transfer, and other execution operations; on the other hand, the distribution module synchronously or in conjunction with this data packet, or the key identity information it contains, sends it to the monitoring module, providing a foundation for subsequent monitoring processes. In terms of specific hardware implementation, this distribution module can be composed of an MCU and related bus logic to ensure the accuracy of the distribution actions.

[0026] Subsequently, after receiving the data packet from the distribution module, the computing core begins to execute the corresponding computing task. Once all instructions in the data packet have been executed, the computing core generates an execution completion feedback and sends it to the monitoring module. This execution completion feedback can manifest as a specific level signal, an interrupt pulse, or a message containing key identification information (such as the data packet's identifier), its purpose being to clearly inform the monitoring module that the task has been completed at the hardware level.

[0027] Meanwhile, the monitoring module, as a hardware monitoring unit independent of the computational logic, immediately creates a backup record of the data packet it receives from the distribution module, or when it receives a data packet or a packet containing critical identity information. This backup record is essentially an "archive" for the task within the monitoring module, allowing the hardware to independently know which tasks are currently in progress. For each backup record, the monitoring module immediately activates a timing monitoring mechanism, for example, by using an internal timer or counter to accumulate clock cycles, thereby monitoring the execution time of the corresponding data packet in real time.

[0028] During timing monitoring, if the execution time exceeds the preset threshold, it indicates a timeout. This typically means the computing core has encountered a deadlock, blockage, or hang in processing the corresponding data packet. In this case, the monitoring module immediately triggers a timeout interrupt signal. This signal, as an anomaly alarm, is fed back to the external processor through the distribution module. This proactive hardware reporting informs the external processor which specific data packet caused the hardware anomaly, allowing for timely intervention. Conversely, if the monitoring module successfully receives execution completion feedback from the computing core before the timeout threshold, it indicates that the corresponding data packet has been executed normally. The monitoring module then stops timing monitoring for the corresponding backup record and releases the corresponding monitoring resources.

[0029] The timeout interrupt system provided by this invention constructs a collaborative mechanism between the distribution module and the monitoring module within the command processor. By establishing local data packet backup records and independently starting timing monitoring, it achieves a leap from traditional software passive querying to hardware active monitoring and alarming. It can not only grasp the execution status of the hardware in real time with data packets as fine granularity, but also quickly feed back fault information to the external processor through timeout interrupt signals when the computing core encounters an abnormal situation. This greatly shortens the delay in fault detection and response, avoids the long-term invalid occupation of hardware resources in abnormal states, and significantly improves the robustness and operating efficiency of the system.

[0030] Based on the above embodiments, the monitoring module includes a storage module 121, a retrieval module 122, and a timeout detection module 123; The storage module includes multiple entries, each of which stores the identifier of a data packet, a valid status bit indicating the occupancy status of the entry, and the corresponding timer; The retrieval module is used to retrieve target entries in the storage module whose valid status bit is in the idle state, write the identity of the received data packet into the target entry, update the valid status bit of the target entry to the occupied state, and start the timer corresponding to the target entry for timing monitoring. The timeout detection module is used to monitor the execution time of each entry in the storage module that is in an occupied state in real time. If the execution time exceeds the time threshold, an execution timeout is determined.

[0031] Specifically, in order to achieve efficient and orderly management of the execution status of data packets, the internal architecture of the monitoring module is specifically configured in this embodiment of the invention; that is, it mainly consists of three parts: a storage module, a retrieval module, and a timeout detection module. Through the collaborative work of these three modules, the entire closed loop from backup establishment to timeout determination is completed.

[0032] Figure 2This is an overall structural diagram of the timeout interrupt system provided by the present invention, as shown below. Figure 2 As shown, the storage module forms the data foundation of the monitoring module; in actual hardware logic, the storage module can be a Pkt-Tab register table or a RAM (Random Access Memory) structure. The storage module is internally divided into multiple entries, each entry being an independent monitoring slot, supporting parallel monitoring of multiple executing data packets. To accurately record the status of each data packet, in this embodiment, each entry contains a specific set of register fields, including fields for recording the data packet's identity (e.g., Pkt sequence-id, used to distinguish different data packets), a valid status bit indicating whether the corresponding entry is currently occupied or available for allocation (e.g., valid), a timer bound to the corresponding entry (e.g., Timer, used to independently record the dwell time of the data packet corresponding to the entry), an entry number (e.g., Index), and a data packet completion status (e.g., Job-done status).

[0033] Based on the aforementioned storage structure, when the monitoring module receives a data packet from the distribution module, the retrieval module immediately begins operation. The primary function of this retrieval module is resource allocation. It iterates through or searches each entry in the storage module to find an entry with a valid status bit set to idle (e.g., valid = 0) as the target entry. Once the target entry is locked, the retrieval module performs a "registration" action: it writes the identifier parsed from the received data packet into the target entry for record-keeping, and simultaneously updates the valid status bit of the target entry from idle to occupied (e.g., setting valid to 1) to prevent the target entry from being repeatedly allocated. At the same time, the retrieval module synchronously starts the timer corresponding to the target entry, beginning timed monitoring. This marks the official start of timing for the data packet at the monitoring level.

[0034] After the timer starts, the monitoring task is handled by the timeout detection module. This module is responsible for polling or scanning in parallel all entries in the storage module whose valid status bits show an occupied state. That is, it monitors the current cumulative value of the timer corresponding to these entries in real time, thereby obtaining the execution duration of each data packet. Subsequently, the timeout detection module compares this real-time obtained execution duration with a preset duration threshold. Once it finds that the execution duration of a data packet corresponding to an entry exceeds the duration threshold, it determines that the execution of the data packet corresponding to that entry has timed out, thereby triggering the subsequent interrupt alarm process.

[0035] In this embodiment of the invention, a storage module containing multiple entries and corresponding retrieval and detection logic are constructed within the monitoring module. Fine-grained monitoring of concurrent data packets is achieved through hardware-based list management. Dynamic allocation and reclamation of monitoring resources are realized using valid status bits. Independent timers ensure the independence and accuracy of monitoring each data packet. This enables the system to process timeout detection tasks of multiple data packets in real time and in parallel without consuming additional software resources, thereby significantly improving the chip's fault tolerance and status awareness efficiency when handling high-concurrency tasks.

[0036] Based on the above embodiments, the distribution module is provided with a port connected to the interrupt line of the timer corresponding to each entry in the storage module, and the interrupt line of the timer corresponding to each entry is connected to the interrupt line of the port one by one. The timeout detection module is used to pull high the interrupt line of the corresponding timer to trigger a timeout interrupt signal when a timeout occurs. The distribution module is also used to respond to timeout interrupt signals. Based on the interrupt line of the port connected to the high-pulled timer interrupt line, it determines the identity of the timed-out data packet and feeds back the identity as interrupt information to the external processor.

[0037] Specifically, to enable independent alarms for each entry, the distribution module has a dedicated port with the number of interrupt lines matching the number of entries in the storage module. In terms of hardware wiring, each entry in the storage module has its own independent timer with a dedicated interrupt line, and the interrupt lines of each entry's timer are physically connected one-to-one with the interrupt lines of the port on the distribution module. This point-to-point hardwired structure establishes the physical foundation for rapid fault signal transmission.

[0038] Based on the aforementioned hardware topology, when the timeout detection module detects that the execution time of a data packet corresponding to a certain entry exceeds the timeout threshold during operation, it determines that the data packet for that entry has timed out, thereby triggering the subsequent interrupt alarm process. It is worth noting here that the alarm action of the timeout detection module does not involve sending complex bus commands, but rather directly pulls the interrupt line of the timer corresponding to that entry high at the physical layer. This level transition directly triggers the timeout interrupt signal, which is instantly transmitted to the corresponding port of the distribution module via the physical connection.

[0039] When responding to this timeout interrupt signal, the distribution module utilizes the determinism of the hardware connection. Specifically, when the distribution module detects which interrupt line on the port is pulled high, it can directly pinpoint which entry in the storage module corresponds to the data packet that caused the timeout. After determining the physical location of the faulty entry (i.e., the entry number index), the distribution module can further read or index the content stored in that entry to determine the identity (Pkt sequence-id) of the data packet that caused the timeout. Subsequently, the distribution module packages this precisely identified identity as interrupt information and sends it to the AIC (Advanced Interrupt Controller). The AIC then feeds back to the external processor via the PCIe (Peripheral Component Interconnect Express) bus interface, thus completing the conversion from physical signal alarm to logical information reporting.

[0040] In this embodiment of the invention, a fast indexing mechanism at the hardware level is constructed by establishing a one-to-one correspondence between the distribution module and the timer corresponding to each entry. This allows for the elimination of the need for software intervention to poll and scan all entries to find the source of the fault when a timeout occurs. Instead, the high level of the physical line directly maps to the specific fault entry and the identity of the corresponding data packet. This not only greatly improves the speed of interrupt response but also enables the external processor to directly obtain precise information about "which data packet is faulty," thus providing a key basis for upper-layer software to perform targeted fault recovery or task reset.

[0041] Based on the above embodiments, the monitoring module further includes a completion confirmation module 124; The completion confirmation module is used to receive the execution completion feedback sent by the computing core, parse the return identifier from the execution completion feedback, compare the return identifier with the identity identifier in each entry in the storage module, and if the comparison is consistent, control the timer of the corresponding entry to reset to stop the timing monitoring, and update the valid status bit of the corresponding entry to the idle state; the return identifier is the identity identifier of the data packet that has been executed.

[0042] Specifically, to improve the closed-loop monitoring mechanism of the system and ensure that monitoring is promptly lifted and monitoring resources are reclaimed after data packets have completed normal execution, this embodiment of the invention further adds a completion confirmation module to the monitoring module. This module can employ Job-done parsing logic in actual circuit design. Its main responsibility is to handle normal business flows that have not experienced execution timeouts; that is, to receive and process execution completion feedback sent by the computing core.

[0043] In detail, once the computing core successfully completes the processing of a data packet, it sends a completion feedback signal back to the monitoring module via the internal bus. This feedback signal inevitably carries information identifying the data packet, namely, the data packet's identifier. Upon receiving this feedback, the completion confirmation module first performs a parsing operation, extracting the return identifier from the completion feedback. This return identifier is essentially the identifier of the completed data packet (i.e., Pktsequence-id), used to prove to the monitoring module "which data packet has been completed."

[0044] Next, the completion confirmation module executes comparison logic to compare or correlate the parsed return identifier with the identity identifiers in each currently occupied entry in the storage module. When a stored identity identifier is found to match the return identifier in an entry (i.e., a match is found), it is confirmed that the data packet corresponding to that entry has been completed. At this point, the completion confirmation module immediately performs a status reset operation on the entry: on the one hand, it controls the timer of the entry to reset, for example, clearing it to zero or stopping the count, thereby stopping the timing monitoring for the data packet and avoiding erroneous triggering of the interruption alarm process due to the timer continuing to run idle; on the other hand, it updates the valid status bit of the entry from occupied to idle (e.g., setting valid to 0), which indicates that the entry has been released and can be reused to receive and monitor subsequently newly distributed data packets.

[0045] In this embodiment of the invention, a completion confirmation module is introduced and a comparison and reset logic is implemented, which realizes the timely cancellation of tasks that are completed normally. This not only ensures that the system can accurately distinguish between the state of execution and completion, preventing false alarms for completed tasks, but more importantly, it realizes the automated recycling of hardware monitoring resources, ensuring that continuous and efficient real-time monitoring of massive data packet streams can be carried out under limited hardware resources.

[0046] Based on the above embodiments, the monitoring module further includes a data packet parsing module 125; The data packet parsing module is used to receive data packets sent by the distribution module, parse out the identity identifier from the data packets, and send the identity identifier to the retrieval module; The retrieval module is used to search sequentially among multiple entries in the storage module, and the first entry with a valid status bit that is in an idle state is selected as the target entry.

[0047] Specifically, in this embodiment of the invention, the monitoring module is further configured with a data packet parsing module. This module is located at the entry point of the monitoring module and is specifically used to interface with the data stream of the distribution module.

[0048] In detail, when the distribution module performs dual-path distribution, the packet parsing module is responsible for receiving the data packets sent by the distribution module. Since the original data packets may contain a large amount of non-monitoring data such as instruction codes and address information, this module needs to perform a key information extraction operation, that is, to parse a unique identifier (Pkt sequence-id) from the data packet. This identifier is the core basis for subsequent tracking of the data packet's status. After parsing, the packet parsing module will directly send the extracted identifier to the retrieval module, providing data input for subsequent entry allocation.

[0049] Upon receiving the identity identifier, the retrieval module allocates resources. Specifically, to ensure deterministic and efficient resource allocation, this embodiment employs a specific search strategy: sequentially searching through multiple entries in the storage module (e.g., from Index 0 to Index n), checking the valid status bit of each entry according to its entry number. During this scan, the retrieval module locks the first entry whose valid status bit is displayed as idle (e.g., valid is 0) and designates it as the target entry. Once the target entry is identified, subsequent operations such as writing the identity identifier, setting the valid status bit, and starting the timer are performed on that target entry.

[0050] In this embodiment of the invention, the parsing process of the data packet parsing module ensures that only critical identity information enters the subsequent monitoring logic, reducing the bandwidth pressure on the internal bus; the sequential retrieval strategy provides a simple, efficient and hardware-easy-to-implement resource management solution, which can quickly find available resources, minimize the delay when establishing backup records, and ensure that the system can still run smoothly under high load.

[0051] The present invention also provides a timeout interrupt method. Figure 3 This is a flowchart illustrating the timeout interrupt method provided by the present invention. This method is applied to timeout interrupt systems as described above, such as... Figure 3 As shown, the method includes: Step 310: Receive data packets sent by an external processor; Step 320, execute the data packet; and, Step 330: Create a backup record of the data packet locally and start timing monitoring for the backup record to monitor the execution time of the data packet; if the execution time reflects an execution timeout, trigger a timeout interrupt signal and send it back to the external processor; if the data packet is confirmed to have been executed before the execution timeout, stop timing monitoring.

[0052] Specifically, the core of this invention lies in achieving real-time perception and anomaly reporting of data packet execution status through a hardware-level parallel monitoring process.

[0053] In detail, during actual operation, the timeout interrupt system first receives the data packet sent by the external processor. During this process, the system's internal distribution module acts as the entry point, obtaining the data packet Pkt to be processed from the external processor (such as the host CPU or driver software). Subsequently, to achieve synchronous business processing and status monitoring, the data packet is distributed to the computing core. The computing core then performs corresponding operations such as graphics rendering, logical operations, and data transfer according to the instructions within the data packet; this is the conventional processing path for the data packet within the chip.

[0054] In parallel with the regular processing path, this data packet also undergoes backup logging and timing monitoring. Specifically, the system's monitoring module creates a local backup record for the data packet and initiates timing monitoring based on this backup record to track the packet's execution duration. At the same time the data packet is sent, the monitoring module allocates a separate entry for the packet in its internal storage, recording the packet's identifier to form a backup record. Once the record is established, it immediately starts the timer bound to that entry, continuously accumulating a count as the clock cycle elapses, thereby quantifying the data packet's residence time or execution duration in the computing core in real time.

[0055] During continuous timing monitoring, this embodiment of the invention also executes different logical branches based on the real-time monitored execution duration. That is, if the execution duration reflects an execution timeout, i.e., when the monitored execution duration exceeds a preset duration threshold, it can be determined that the computing core may have deadlocked or suspended. At this time, a timeout interrupt signal will be immediately triggered and fed back to the external processor through the distribution module. This process typically involves raising the interrupt line of the timer to notify the distribution module, which then reports the interrupt information containing the identity identifier of the corresponding data packet to the external processor, thus realizing hardware-to-software proactive alarm.

[0056] Conversely, if the data packet execution is confirmed to be complete before the timeout, that is, if the monitoring module receives the execution completion feedback from the computing core before the timer value reaches the preset duration threshold, and the feedback signal is confirmed to match the identity identifier in the backup record, then the data packet is determined to have been executed normally. The timer is then reset to stop monitoring, and the valid status bit of the backup record is cleared to free up monitoring resources for subsequent data packets.

[0057] The timeout interrupt method provided by this invention completely changes the inefficient mode of traditional chips relying on software polling to confirm task status by embedding parallel hardware backup and timing monitoring processes in the data packet execution process. It can monitor the hardware execution status around the clock with fine granularity of data packets without occupying software resources. Once the execution times out, it can immediately and proactively feed back accurate fault information to the external processor in the form of an interrupt. This enables the timeout interrupt system to respond to hardware deadlock faults with extremely low latency, thereby greatly improving the maintainability and operational stability of the chip under abnormal operating conditions.

[0058] Based on the above embodiments, in step 330, a backup record of the data packet is established locally, and timing monitoring is started for the backup record to monitor the execution duration of the data packet. If the execution duration reflects an execution timeout, a timeout interrupt signal is triggered and fed back to the external processor, including: Extract the identity identifier from the data packet; The system retrieves the target entry with an idle status bit from multiple entries, writes the identity to the target entry, updates the valid status bit of the target entry to the occupied status, and starts the timer corresponding to the target entry for timing monitoring to monitor the execution duration of the data packet; each entry is used to store the identity of a data packet, the valid status bit indicating the occupancy status of the entry, and the corresponding timer; If the execution time exceeds the time threshold, an execution timeout is determined. In the event of a timeout, pull the corresponding timer's interrupt line high to trigger a timeout interrupt signal; In response to the timeout interrupt signal, the identity of the timed-out data packet is determined based on the high interrupt line of the timer, and the identity is fed back to the external processor as interrupt information.

[0059] Specifically, the process of establishing a backup record of the data packet locally and starting timing monitoring for the backup record to monitor the execution time of the data packet may include: First, the data packets can be parsed to extract their identity identifiers, such as the Pkt sequence-id, thus obtaining the unique credential for the data packet within the system. Then, resource allocation is performed using the storage module within the monitoring module. This storage module is divided into multiple entries, each entry acting as an independent monitoring slot, supporting parallel monitoring of multiple executing data packets simultaneously. To accurately record the status of each data packet, in this embodiment, each entry contains a set of specific register fields, including fields for recording the data packet's identity identifier (such as the Pkt sequence-id, used to distinguish different data packets), a valid status bit indicating whether the corresponding entry is currently occupied or available for allocation (such as valid), a timer bound to the corresponding entry (such as Timer, used to independently record the dwell time of the data packet corresponding to the entry), an entry number (such as Index), and a data packet completion status (such as Job-done status), etc.

[0060] Based on the aforementioned storage structure, when the monitoring module receives a data packet from the distribution module, it iterates through or searches through each entry in the storage module to retrieve an entry with a valid status bit set to idle (e.g., valid is 0) as the target entry. Once the target entry is locked, a "registration" action is performed: the parsed identity is written into the target entry for record-keeping, and the valid status bit of the target entry is updated from idle to occupied (e.g., valid is set to 1) to prevent resource conflicts. The timer corresponding to the target entry is then immediately started for timing monitoring. Through this series of sequential actions, the timeout interrupt system completes real-time tracking of the data packet's execution duration at the hardware level.

[0061] During monitoring, if an anomaly occurs, such as an execution timeout, a timeout interrupt signal is triggered and fed back to the external processor via the distribution module. This process employs a fast response mechanism based on physical connections. Specifically, the monitoring module compares the real-time execution time with a preset timeout threshold. If the execution time of a data packet corresponding to a certain entry exceeds the threshold, the data packet for that entry is deemed to have timed out. Once a timeout is confirmed, the alarm is triggered without relying on complex message communication; instead, a physical operation is directly performed: the interrupt line of the timer corresponding to that entry is pulled high. This high-level action directly triggers the timeout interrupt signal, achieving instantaneous hardware-level alarm.

[0062] Subsequently, the distribution module responds to the timeout interrupt signal and uses the connection between the timer's interrupt line and the port's interrupt line to perform fault backtracking. That is, based on the detected high interrupt line, it can directly reverse-engineer the specific fault entry, thereby reading the content stored in that entry to determine the identity identifier (Pktsequence-id) of the data packet that caused the execution timeout. Finally, the distribution module packages this identity identifier as interrupt information and feeds it back to the external processor via the PCIe bus interface.

[0063] In this embodiment of the invention, by binding the identity of the data packet to a specific entry and the interrupt line, a closed-loop feedback path is constructed from the logical ID to the interrupt line and back to the logical ID. This ensures that when an alarm is triggered by pulling the interrupt line high, the external processor receives not just a general error signal, but precise information containing the exact faulty data packet ID. This greatly improves the diagnostic efficiency and recovery accuracy of the system when dealing with deadlock faults.

[0064] The timeout interrupt device provided by the present invention is described below. The timeout interrupt device described below can be referred to in correspondence with the timeout interrupt method described above.

[0065] Figure 4 This is a schematic diagram of the timeout interruption device provided by the present invention, as shown below. Figure 4 As shown, the device is applied to a timeout interrupt system as described in any of the preceding claims, and the device includes: The distribution unit 410 is used to receive data packets sent by an external processor; Execution unit 420, configured to execute the data packet; and, The monitoring unit 430 is used to establish a backup record of the data packet locally and start timing monitoring for the backup record to monitor the execution time of the data packet; If the execution duration reflects an execution timeout, a timeout interrupt signal is triggered and fed back to the external processor; If the data packet is confirmed to have been executed before the execution timeout, then the timing monitoring is stopped.

[0066] The timeout interrupt device provided by this invention completely changes the inefficient mode of traditional chips relying on software polling to confirm task status by embedding parallel hardware backup and timing monitoring processes in the data packet execution process. It can monitor the hardware execution status around the clock with fine granularity of data packets without occupying software resources. Once the execution times out, it can immediately and proactively feed back accurate fault information to the external processor in the form of an interrupt. This enables the timeout interrupt system to respond to hardware deadlock faults with extremely low latency, thereby greatly improving the maintainability and operational stability of the chip under abnormal operating conditions.

[0067] Based on the above embodiments, the monitoring unit 430 is used for: The identity identifier is parsed from the data packet; Search for a target entry with an idle status bit among multiple entries, write the identity identifier into the target entry, update the valid status bit of the target entry to the occupied status, and start the timer corresponding to the target entry for timing monitoring to monitor the execution duration of the data packet; each entry is used to store the identity identifier of a data packet, the valid status bit indicating the occupancy status of the entry, and the corresponding timer; If the execution time exceeds the time threshold, an execution timeout is determined. In the event of a timeout, the interrupt line of the corresponding timer is pulled high to trigger the timeout interrupt signal; In response to the timeout interrupt signal, the identity of the timed-out data packet is determined based on the high interrupt line of the timer, and the identity is fed back to the external processor as interrupt information.

[0068] Figure 5 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 5 As shown, the electronic device may include: a processor 510, a communications interface 520, a memory 530, and a communication bus 540, wherein the processor 510, the communications interface 520, and the memory 530 communicate with each other through the communication bus 540. The processor 510 may call logical instructions in the memory 530 to execute a timeout interrupt method. This method is applied to the timeout interrupt system described in any of the above embodiments. The method includes: receiving a data packet sent by an external processor; executing the data packet; and establishing a backup record of the data packet locally, and starting timing monitoring for the backup record to monitor the execution duration of the data packet; if the execution duration reflects an execution timeout, triggering a timeout interrupt signal and feeding it back to the external processor; if it is confirmed that the data packet has been executed before the execution timeout, stopping the timing monitoring.

[0069] Furthermore, the logical instructions in the aforementioned memory 530 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0070] On the other hand, the present invention also provides a computer program product, the computer program product comprising a computer program stored on a non-transitory computer-readable storage medium, the computer program comprising program instructions, wherein when the program instructions are executed by a computer, the computer is capable of executing the timeout interrupt method provided by the above methods, the method being applied to a timeout interrupt system as described in any of the above claims, the method comprising: receiving a data packet sent by an external processor; executing the data packet; and establishing a backup record of the data packet locally, and initiating timing monitoring for the backup record to monitor the execution duration of the data packet; if the execution duration reflects an execution timeout, triggering a timeout interrupt signal and feeding it back to the external processor; and stopping the timing monitoring if it is confirmed that the data packet has been executed before the execution timeout.

[0071] In another aspect, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the timeout interrupt method provided by the methods described above. This method is applied to a timeout interrupt system as described in any of the preceding claims. The method includes: receiving a data packet sent by an external processor; executing the data packet; and establishing a backup record of the data packet locally, and initiating timing monitoring for the backup record to monitor the execution duration of the data packet; if the execution duration reflects an execution timeout, triggering a timeout interrupt signal and feeding it back to the external processor; and stopping the timing monitoring if it is confirmed that the data packet has been executed before the execution timeout.

[0072] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0073] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0074] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A timeout interrupt system, characterized in that, Applied to a chip, the system includes a command processor and a computing core, the command processor including a distribution module and a monitoring module; The distribution module is used to receive data packets sent by an external processor and send the data packets to the monitoring module and the computing core; The computing core is used to execute the data packet and sends execution completion feedback to the monitoring module after execution is completed; The monitoring module is used to establish a backup record of the data packet locally and start timing monitoring for the backup record to monitor the execution time of the calculation and verification of the data packet. If the execution time reflects an execution timeout, a timeout interrupt signal is triggered and fed back to the external processor through the distribution module. If the execution completion feedback is received before the execution timeout, the timing monitoring is stopped.

2. The timeout interrupt system according to claim 1, characterized in that, The monitoring module includes a storage module, a retrieval module, and a timeout detection module; The storage module includes multiple entries, each entry being used to store the identity identifier of a data packet, a valid status bit indicating the occupancy status of the entry, and a corresponding timer; The retrieval module is used to retrieve target entries in the storage module whose valid status bit is idle, write the identity of the received data packet into the target entry, update the valid status bit of the target entry to occupied status, and start the timer corresponding to the target entry for timing monitoring. The timeout detection module is used to detect the execution duration of each entry in the storage module that is in the occupied state in real time. If the execution duration exceeds the duration threshold, an execution timeout is determined.

3. The timeout interrupt system according to claim 2, characterized in that, The distribution module is provided with a port connected to the interrupt line of the timer corresponding to each entry in the storage module, and the interrupt line of the timer corresponding to each entry is connected to the interrupt line of the port one by one. The timeout detection module is used to pull high the interrupt line of the corresponding timer to trigger the timeout interrupt signal when a timeout occurs. The distribution module is also used to respond to the timeout interrupt signal, determine the identity of the timed-out data packet based on the interrupt line of the port connected to the high interrupt line of the timer, and feed back the identity as interrupt information to the external processor.

4. The timeout interrupt system according to claim 2, characterized in that, The monitoring module also includes a completion confirmation module; The completion confirmation module is used to receive the execution completion feedback sent by the computing core, parse the return identifier from the execution completion feedback, compare the return identifier with the identity identifier in each entry in the storage module, and if the comparison is consistent, control the timer of the corresponding entry to reset to stop the timing monitoring, and update the valid status bit of the corresponding entry to the idle state; the return identifier is the identity identifier of the data packet that has been executed.

5. The timeout interrupt system according to claim 2, characterized in that, The monitoring module also includes a data packet parsing module; The data packet parsing module is used to receive the data packet sent by the distribution module, parse the identity identifier from the data packet, and send the identity identifier to the retrieval module; The retrieval module is used to sequentially search among multiple entries in the storage module, and the first entry whose valid status bit is idle is selected as the target entry.

6. A timeout interrupt method, characterized in that, Applied to the timeout interrupt system as described in any one of claims 1 to 5, the method comprises: Receive data packets sent by an external processor; Execute the data packet; as well as, A backup record of the data packet is created locally, and timing monitoring is started for the backup record to monitor the execution time of the data packet; If the execution duration reflects an execution timeout, a timeout interrupt signal is triggered and fed back to the external processor; If the data packet is confirmed to have been executed before the execution timeout, then the timing monitoring is stopped.

7. The timeout interruption method according to claim 6, characterized in that, The step of establishing a backup record of the data packet locally and starting timing monitoring for the backup record to monitor the execution duration of the data packet includes: The identity identifier is parsed from the data packet; Search for a target entry with an idle status bit among multiple entries, write the identity identifier into the target entry, update the valid status bit of the target entry to the occupied status, and start the timer corresponding to the target entry for timing monitoring to monitor the execution duration of the data packet; each entry is used to store the identity identifier of a data packet, the valid status bit indicating the occupancy status of the entry, and the corresponding timer; If the execution duration reflects an execution timeout, triggering a timeout interrupt signal and feeding it back to the external processor includes: If the execution time exceeds the time threshold, an execution timeout is determined. In the event of a timeout, the interrupt line of the corresponding timer is pulled high to trigger the timeout interrupt signal; In response to the timeout interrupt signal, the identity of the timed-out data packet is determined based on the high interrupt line of the timer, and the identity is fed back to the external processor as interrupt information.

8. A timeout interruption device, characterized in that, The device, applied to the timeout interrupt system as described in any one of claims 1 to 5, comprises: The distribution unit is used to receive data packets sent by an external processor. An execution unit is configured to execute the data packet; and, The monitoring unit is used to establish a backup record of the data packet locally and start timing monitoring for the backup record to monitor the execution time of the data packet; If the execution duration reflects an execution timeout, a timeout interrupt signal is triggered and fed back to the external processor; If the data packet is confirmed to have been executed before the execution timeout, then the timing monitoring is stopped.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the timeout interrupt method as described in claim 6 or 7.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the timeout interrupt method as described in claim 6 or 7.

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