An abnormal timing processing system and method
The abnormal timing processing system uses D flip-flops and logic gates to generate reporting or shutdown signals of appropriate duration, solving the problem of inappropriate signal duration in integrated circuit chips under abnormal conditions, and realizing flexible processing and accurate identification of abnormalities.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- LEN TECH LTD
- Filing Date
- 2026-05-18
- Publication Date
- 2026-06-19
AI Technical Summary
In abnormal situations, the duration of abnormal signals is either too short or too long, causing the main control chip to be unable to accurately sample or identify the abnormal conditions. Existing technologies are unable to flexibly handle different types of abnormal situations.
Design an abnormal timing processing system, including an abnormal processing circuit and a timing circuit. By combining timing signals and abnormal signals, a reporting signal or a shutdown signal of appropriate duration is generated. D flip-flops and logic gate circuits are used to realize signal delay and control.
It enables flexible handling of different types of anomalies, avoids the problem of excessively short or long duration of reported signals, and ensures that the main control chip accurately samples and identifies abnormal conditions.
Smart Images
Figure CN122240382A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electronic digital data processing, and in particular to an abnormal timing processing system and method. Background Technology
[0002] When designing integrated circuit chips, various abnormal situations are considered. To protect the chip from damage and ensure its normal operation, protection circuits are usually designed, such as over-temperature protection circuits, short-circuit protection circuits, and over-voltage protection circuits.
[0003] Each chip is typically connected to a main control chip (such as an MCU). When an abnormal situation occurs, the chip generates a reporting signal based on the abnormal signal and sends it to the main control chip. If the duration of the reporting signal is too short, the main control chip may not be able to accurately sample the reporting signal. If the duration of the reporting signal is too long, the main control chip may misidentify the abnormal situation, mistakenly believing that the abnormality has persisted when it has actually ended.
[0004] Different types of anomalies require different handling methods. Some anomalies only need to be reported, while others require both reporting and chip shutdown. Therefore, a system capable of flexibly handling both types of anomalies is needed. Summary of the Invention
[0005] This application relates to an abnormal timing processing system, characterized in that it includes an abnormal processing circuit and a timing circuit, wherein the abnormal processing circuit is configured to receive an abnormal signal from a chip, wherein the abnormal signal includes a first type of abnormal signal, the first type of abnormal signal representing an abnormality in the chip that only needs to be reported; the abnormal processing circuit is further configured to receive a timing signal from the timing circuit, and generate a first driving signal based on the timing signal and the abnormal signal, for enabling control of the timing circuit; the timing circuit is configured to generate a timing signal with a preset period according to its clock signal under the enabling control of the first driving signal, and the timing circuit is configured to generate a first reporting signal based on the first driving signal and the timing signal, wherein the effective time of the first reporting signal is one or more times the effective time of the timing signal within one period, based on the relationship between the effective time of the first type of abnormal signal and the effective time of the timing signal within one period.
[0006] Specifically, the abnormal timing processing system proposed in this application is characterized in that the abnormal signal further includes a second type of abnormal signal, which represents an abnormality in the chip that requires both reporting to the main controller and shutting down the chip; the abnormal timing processing system further includes an enable trigger circuit configured to generate a pass signal based on the second type of abnormal signal under the enable control of the first drive signal; the timing circuit is further configured to receive the pass signal and generate a second reporting signal based on the pass signal and the first reporting signal.
[0007] Specifically, the abnormal timing processing system proposed in this application is characterized in that the abnormal processing circuit includes: a first OR gate, whose input terminals are respectively configured to receive the first type of abnormal signal and / or the second type of abnormal signal from the chip; a first NOT gate, whose input terminal is electrically connected to the output terminal of the first OR gate; a first D flip-flop, whose data input terminal is electrically connected to the power supply, whose clock terminal is electrically connected to the output terminal of the first OR gate, and whose main output terminal is electrically connected to the enable trigger circuit and the timing circuit, configured to output the first driving signal; a second D flip-flop, whose data input terminal is electrically connected to the power supply, whose clock terminal is electrically connected to the output terminal of the first NOT gate, and whose main output terminal is electrically connected to the enable trigger circuit and the timing circuit, configured to output the first driving signal; and ... The circuit is configured to output a second drive signal; a second NOT gate, whose input is electrically connected to the timing circuit and configured to receive the timing signal; a first AND gate, one input of which is electrically connected to the main output of the second D flip-flop and the other input of which is electrically connected to the output of the second NOT gate; a third NOT gate, whose input is electrically connected to the output of the first AND gate; a second AND gate, one input of which is electrically connected to the output of the third NOT gate and the other input of which is configured to receive a system enable signal, and whose output is electrically connected to the enable terminals of the first D flip-flop and the second D flip-flop and configured to output a reset signal.
[0008] Specifically, the abnormal timing processing system proposed in this application is characterized in that the enable trigger circuit includes: a fourth NOT gate, the input of which is configured to receive the second type of abnormal signal from the chip; a first resistor, the first end of which is electrically connected to the output of the fourth NOT gate; a first capacitor, the first end of which is electrically connected to the second end of the first resistor, and the second end of which is grounded; a fifth NOT gate, the input of which is electrically connected to the second end of the first resistor; a third D flip-flop, the data input of which is electrically connected to the power supply, the clock input of which is electrically connected to the output of the fifth NOT gate, the main output of which is electrically connected to the timing circuit and configured to output the pass signal, the enable input of which is electrically connected to the abnormal processing circuit and configured to receive the first drive signal, wherein the first resistor and the first capacitor are configured to generate a first delay, the first delay being greater than or equal to the delay of the first D flip-flop itself.
[0009] Specifically, the abnormal timing processing system proposed in this application is characterized in that the timing circuit includes: one or more D flip-flops, the enable terminal of each D flip-flop being electrically connected to the abnormal processing circuit and configured to receive the first driving signal, the inverting output terminal of each D flip-flop being electrically connected to its own data input terminal and the clock terminal of the next D flip-flop, wherein the clock terminal of the first D flip-flop is configured to receive a clock signal; a second OR gate, one input terminal of the second OR gate being electrically connected to the inverting output terminal of the last D flip-flop, the other input terminal being electrically connected to the clock terminal of the last D flip-flop, and the output terminal of the second OR gate being electrically connected to the abnormal processing circuit. The system is configured to output the timing signal; a third AND gate, one input of which is electrically connected to the output of the second OR gate and configured to receive the timing signal, and the other input of which is electrically connected to the exception handling circuit and configured to receive the first drive signal, and the output of which is configured to output the first reporting signal; a fourth AND gate, one input of which is electrically connected to the output of the third AND gate and configured to receive the first reporting signal, and the other input of which is electrically connected to the enable trigger circuit and configured to receive the pass signal, and the output of which is configured to output the second reporting signal.
[0010] In particular, the abnormal timing processing system proposed in this application is characterized in that the number of D flip-flops in the timing circuit is 8.
[0011] Specifically, the abnormal timing processing system proposed in this application is characterized in that, when the effective time of the first type of abnormal signal or the second type of abnormal signal is less than the period of the timing signal, the effective time of the first reporting signal or the second reporting signal is the effective time of the timing signal within one period; when the effective time of the first type of abnormal signal or the second type of abnormal signal is greater than the period of the timing signal, the effective time of the first reporting signal or the second reporting signal is an integer multiple of the effective time of the timing signal within one period.
[0012] In particular, the abnormal timing processing system proposed in this application is characterized in that when the effective time of the first type of abnormal signal or the second type of abnormal signal is greater than a first integer multiple of the timing signal period and less than a second integer multiple of the timing signal period, wherein the first integer multiple is greater than or equal to 1 and the second integer multiple is equal to the first integer multiple plus 1, the effective time of the first reporting signal or the second reporting signal is a second integer multiple of the effective time of the timing signal within one period.
[0013] This application also proposes an electronic device characterized by including the above-described abnormal timing processing system.
[0014] This application also proposes an exception handling method based on the above-mentioned exception timing processing system, characterized in that, when the effective time of the exception signal is less than the period of the timing signal, the effective time of the generated reporting signal is the effective time of the timing signal within one period; when the effective time of the exception signal is greater than the period of the timing signal, the effective time of the generated reporting signal is an integer multiple of the effective time of the timing signal within one period.
[0015] In particular, the anomaly handling method proposed in this application is characterized in that when the effective time of the anomaly signal is greater than the third integer multiple of the timing signal period and less than the fourth integer multiple of the timing signal period, wherein the third integer multiple is greater than or equal to 1 and the fourth integer multiple is equal to the third integer multiple plus 1, the effective time of the generated reporting signal is the fourth integer multiple of the effective time of the timing signal in one period.
[0016] The anomaly timing processing system proposed in this application can generate a reporting signal of appropriate duration based on the duration of the anomaly signal, for reporting to the main control chip, thus avoiding the problems of reporting signals being too long or too short. For anomalies that only need to be reported, the system can generate a reporting signal of appropriate duration. For anomalies that require both reporting and chip shutdown, the system can generate both a reporting signal of appropriate duration and a shutdown signal to shut down the chip, enabling flexible handling of different types of anomalies. Attached Figure Description
[0017] Figure 1 This is an overall schematic diagram of an abnormal timing processing system according to an embodiment of this application; Figure 2 This is an overall schematic diagram of an abnormal timing processing system according to another embodiment of this application; Figure 3 This is a circuit diagram of an exception handling circuit according to an embodiment of this application; Figure 4 This is a circuit diagram of a timing circuit according to an embodiment of this application; Figure 5 This is a waveform diagram of the operation of an exception handling circuit according to an embodiment of this application; Figure 6 This is a circuit diagram of an enable trigger circuit according to an embodiment of this application; Figure 7 This is a waveform diagram of the enable trigger circuit according to an embodiment of this application; Figure 8 This is a waveform diagram of an abnormal timing processing system according to an embodiment of this application; Figure 9This is a waveform diagram of the abnormal timing processing system according to an embodiment of this application. Detailed Implementation
[0018] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0019] In the following detailed description, reference can be made to the accompanying drawings, which form part of this application and illustrate specific embodiments of the present application. In the drawings, similar reference numerals describe substantially similar components in different figures. Specific embodiments of the present application are described in sufficient detail below to enable those skilled in the art to implement the technical solutions of the present application. It should be understood that other embodiments may also be utilized, or structural, logical, or electrical changes may be made to the embodiments of the present application.
[0020] Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus should be considered part of the specification. The lines connecting the units in the accompanying drawings are merely for illustrative purposes, indicating that at least the units at both ends of the line are communicating with each other, and are not intended to prevent unconnected units from communicating. Furthermore, the number of lines between two units is intended to indicate at least the number of signals involved in communication between the two units or at least the number of output terminals, and is not intended to limit communication between the two units to only the signals shown in the figures.
[0021] A transistor can refer to any type of transistor, such as a field-effect transistor (FET) or a bipolar junction transistor (BJT). When a transistor is a field-effect transistor, depending on the channel material, it can be hydrogenated amorphous silicon, metal oxide, low-temperature polycrystalline silicon, organic transistors, etc. Based on whether the charge carriers are electrons or holes, they can be divided into N-type transistors and P-type transistors. The gate of a field-effect transistor is its control electrode; the first electrode can be the drain or source, and the corresponding second electrode can be the source or drain. The gate or control electrode can be the control electrode. When a transistor is a bipolar junction transistor (BJT), the base is its control electrode; the first electrode can be the collector or emitter, and the corresponding second electrode can be the emitter or collector. The base or control electrode can be the control electrode. Transistors can be manufactured using amorphous silicon, polycrystalline silicon, oxide semiconductor, organic semiconductor, NMOS / PMOS, or CMOS processes.
[0022] Figure 1 This is an overall schematic diagram of an abnormal timing processing system according to an embodiment of this application.
[0023] According to one embodiment, the abnormal timing processing system may include an abnormal processing circuit 101, a timing circuit 102, and an enable trigger circuit 103.
[0024] According to one embodiment, an exception handling circuit 101 is electrically connected to a timing circuit 102 and an enable trigger circuit 103. The exception handling circuit 101 is configured to send a first drive signal RP to the timing circuit 102 and the enable trigger circuit 103. The exception handling circuit is also configured to receive a timing signal Time from the timing circuit 102.
[0025] According to one embodiment, a timing circuit 102 is electrically connected to an exception handling circuit 101 and an enable trigger circuit 103. The timing circuit 102 is configured to send a timing signal Time to the exception handling circuit. The timing circuit 102 is also configured to receive a first drive signal RP from the exception handling circuit 101 and a pass signal Pass from the enable trigger circuit 103.
[0026] According to one embodiment, an enable trigger circuit 103 is electrically connected to an exception handling circuit 101 and a timing circuit 102. The enable trigger circuit 103 is configured to receive a first drive signal from the exception handling circuit 101. The enable trigger circuit 103 is also configured to send a pass signal to the timing circuit 102.
[0027] According to one embodiment, the exception handling circuit 101 is configured to receive exception signals from the monitored chip. According to one embodiment, the exception signals may include a first type of exception signal, Fault A, and a second type of exception signal, Fault B, representing two different types of exception states of the chip. Fault B is active when an exception occurs in the chip that requires both reporting and shutdown. Fault A is active when an exception occurs in the chip that only requires reporting.
[0028] According to one embodiment, the timing circuit 102 is configured to start timing upon receiving a valid RP and output a timing signal time.
[0029] According to one embodiment, the exception handling circuit 101 is configured to receive a timing signal Time from the timing circuit 102.
[0030] According to one embodiment, the exception handling circuit 101 is configured to generate a first drive signal RP as an enable signal for the timing circuit 102 and the enable trigger circuit 103 based on Fault A, Fault B, and Time.
[0031] According to one embodiment, the enable trigger circuit 103 is configured to receive a signal Fault B and a signal RP from the exception handling circuit 101, and is configured to delay Fault B and use the delayed signal to generate a pass signal Pass regarding whether to shut down the chip, and send it to the timing circuit 102.
[0032] According to one embodiment, the timing circuit 102 is configured to receive and generate a first reporting signal FLT_CTR and a second reporting signal DIS_EN_SYS based on the RP and Pass signals, and report them to the main control chip (e.g., an MCU, not shown). When FLT_CTR is valid, an abnormal state is reported to the main control chip. When DIS_EN_SYS is valid, an abnormal state is reported to the main control chip and a request is made to shut down the monitored chip. After processing by the abnormality handling circuit 101 and the timing circuit 102, the duration of FLT_CTR and DIS_EN_SYS is neither too short, causing the main control chip to be unable to accurately sample the reporting signal, nor too long, causing the main control chip to deviate in identifying the abnormal state.
[0033] Figure 2 This is an overall schematic diagram of an abnormal timing processing system according to another embodiment of this application.
[0034] According to one embodiment, the abnormal timing processing system may include an abnormal processing circuit 101 and a timing circuit 102.
[0035] According to one embodiment, the exception handling circuit 101 is configured to receive an exception signal from the monitored chip. According to one embodiment, the exception signal may include a first type of exception signal, Fault A. Fault A is valid when an exception occurs in the chip that only needs to be reported.
[0036] According to one embodiment, the exception handling circuit 101 is configured to receive a timing signal Time from the timing circuit 102.
[0037] According to one embodiment, the exception handling circuit 101 is configured to generate a first drive signal RP as an enable signal for the timing circuit 102 based on Fault A and Time.
[0038] Figure 3 This is a circuit diagram of an exception handling circuit according to an embodiment of this application.
[0039] According to one embodiment, the exception handling circuit 101 may include a first OR gate 301. The input of the first OR gate 301 is electrically connected to the monitored chip and configured to receive signals Fault A and Fault B from the chip.
[0040] According to one embodiment, the output of the first OR gate 301 is configured as an output signal FLT_TRI. FLT_TRI is active when either Fault A or Fault B is active, for example, at a high level. FLT_TRI is inactive when both Fault A and Fault B are inactive, for example, at a low level.
[0041] According to one embodiment, the exception handling circuit 101 may further include a first NOT gate 302. The input of the first NOT gate 302 is electrically connected to the output of the first OR gate 301 and is configured to receive the signal FLT_TRI. The output of the first NOT gate 302 is configured to output the inverted signal of FLT_TRI.
[0042] According to one embodiment, the exception handling circuit 101 may further include a first D flip-flop 304. The first D flip-flop 304 may be a rising-edge triggered D flip-flop. The data input terminal (D terminal) of the first D flip-flop 304 is electrically connected to the power supply VDD, and the clock terminal (CLK terminal) is electrically connected to the output terminal of the first OR gate 301, configured to receive the signal FLT_TRI. The main output terminal (Q terminal) of the first D flip-flop 304 is configured to output the signal RP. When FLT_TRI transitions from disabled to active, the signal RP transitions from disabled to active.
[0043] For ease of explanation, in the following text, the data input terminal of the D flip-flop will be referred to as the D terminal, the clock terminal of the D flip-flop will be referred to as the CLK terminal, and the main output terminal of the D flip-flop will be referred to as the Q terminal.
[0044] According to one embodiment, the exception handling circuit 101 may further include a second D flip-flop 303. The second D flip-flop 303 may be a rising-edge triggered D flip-flop. The D terminal of the second D flip-flop 303 is electrically connected to the power supply VDD, and the CLK terminal is electrically connected to the output of the first NOT gate 302, receiving the inverted signal of FLT_TRI. The Q terminal of the second D flip-flop 303 is configured to output a second drive signal FP. When the inverted signal of FLT_TRI changes from inactive to active, the signal FP changes from inactive to active.
[0045] According to one embodiment, the exception handling circuit 101 may further include a second NOT gate 305. The input of the second NOT gate 305 is electrically connected to the timing circuit 102. Figure 2 (Not shown in the diagram) is configured to receive the signal Time from the timing circuit 102. The output of the second NOT gate 305 is configured to output the inverted signal of Time.
[0046] According to one embodiment, the exception handling circuit 101 may further include a first AND gate 306. One input of the first AND gate 306 is electrically connected to the Q terminal of the second D flip-flop 303 and configured to receive the signal FP. The other input of the first AND gate 306 is electrically connected to the output of the second NOT gate 305 and configured to receive the inverted signal of Time. The output of the first AND gate 306 is configured to output the signal Pr.
[0047] According to one embodiment, the exception handling circuit 101 may further include a third NOT gate 307. The input of the third NOT gate 307 is electrically connected to the output of the first AND gate 306 and is configured to receive the signal Pr.
[0048] According to one embodiment, the exception handling circuit 101 may further include a second AND gate 308. One input of the second AND gate 308 is electrically connected to the output of the third NOT gate 307 and configured to receive the inverted signal of Pr. The other input of the second AND gate 308 is configured to receive the system enable signal ON. ON is the enable signal for the entire exception timing handling system, and ON is active when the exception timing handling system is operating. The output of the second AND gate 308 is electrically connected to the enable (EN) terminals of the second D flip-flop 303 and the first D flip-flop 304. The output of the second AND gate 308 is configured to output a reset signal Reset and send it to the EN terminals of the second D flip-flop 303 and the first D flip-flop 304. When Reset is active, the operating states of the second D flip-flop 303 and the first D flip-flop 304 are reset.
[0049] For ease of explanation, the enable terminal of the D flip-flop will be referred to as the EN terminal in the following text.
[0050] Figure 4 This is a circuit diagram of a timing circuit according to an embodiment of this application.
[0051] According to one embodiment, the timing circuit 102 may include one or more D flip-flops.
[0052] According to one embodiment, such as Figure 4 As shown, the timing circuit 102 is illustrated using an example of a timing circuit that includes eight D flip-flops. The timing circuit 102 may also include other numbers of D flip-flops.
[0053] According to one embodiment, such as Figure 4 As shown, the EN terminal of each D flip-flop is configured to receive signals from the exception handling circuit 101. Figure 3 The signal RP (not shown in the diagram). The D terminal of each D flip-flop is electrically connected to its own inverting output terminal (QN terminal).
[0054] For ease of explanation, the inverting output terminal of the D flip-flop will be referred to as the QN terminal in the following text.
[0055] According to one embodiment, the CLK terminal of the fourth D flip-flop 401 is configured to receive a clock signal CLK with a period of T. Except for the fourth D flip-flop 401, the CLK terminals of the other D flip-flops are electrically connected to the QN terminal of the previous D flip-flop. The EN terminal of each D flip-flop is configured to receive a common signal RP, and the Q terminal of each D flip-flop generates and outputs its own output signal.
[0056] According to one embodiment, the timing circuit 102 may further include a second OR gate 409. One input of the second OR gate 409 is electrically connected to the QN terminal of the fifth D flip-flop 407, and the other input is electrically connected to the QN terminal of the sixth D flip-flop 408. The output of the second OR gate 409 is configured to output the signal Time.
[0057] According to one embodiment, the timing circuit 102 may further include a third AND gate 410. One input of the third AND gate 410 is electrically connected to the output of the second OR gate 409 and configured to receive the signal Time, while the other input is configured to receive the signal RP. The output of the third AND gate 410 is configured to output the signal FLT_CTR. FLT_CTR is a reporting signal that will be sent to the main control chip.
[0058] In one embodiment, the period of the clock signal is typically in the microsecond range, for example, 10 microseconds. However, if the duration of the reporting signal FLT_CTR is too short, the main control chip may be unable to accurately sample the signal. Therefore, multiple D flip-flops are configured in the timing circuit 102, with the QN terminal of each D flip-flop electrically connected to the CLK terminal of the next D flip-flop. By extending the period of the clock signal CLK in this way, and then processing the extended signal to generate the reporting signal FLT_CTR, the duration of the reporting signal FLT_CTR can be avoided.
[0059] According to one embodiment, the timing circuit 102 may further include a fourth AND gate 411. One input of the fourth AND gate 411 is electrically connected to the output of the third AND gate 410 and configured to receive the signal FLT_CTR. The other input is configured to receive the pass signal Pass from the enable trigger circuit 103. The output of the fourth AND gate 411 is configured to output the signal DIS_EN_SYS. DIS_EN_SYS is a signal requesting the monitoring chip's reporting to be disabled and will be sent to the main control chip.
[0060] Figure 5 This is a waveform diagram of the operation of an exception handling circuit according to an embodiment of this application.
[0061] According to one embodiment, when RP remains active, such as Figure 5 As shown, QN1 is the signal output from the QN terminal of the fifth D flip-flop 407, and QN2 is the signal output from the QN terminal of the sixth D flip-flop 408. Based on the connection relationship between the fifth D flip-flop 407 and the sixth D flip-flop 408, and the working principle of D flip-flops, the waveforms of QN1 and QN2 can be derived as follows: Figure 5 As shown, the period of QN2 is twice that of QN1.
[0062] According to one embodiment, when RP remains active, based on the operating principle of the second OR gate 409, the waveform of the Time signal can be obtained as follows: Figure 5 As shown. In one cycle of the Time signal, the duration of its active state (e.g., high level) accounts for three-quarters of the entire cycle, while the duration of its inactive state (e.g., low level) accounts for one-quarter of the entire cycle.
[0063] Figure 6 This is a circuit diagram of an enable trigger circuit according to an embodiment of this application.
[0064] According to one embodiment, the enable trigger circuit 103 may include a fourth NOT gate 601. The input of the fourth NOT gate 601 is configured to receive the signal Fault B, and the output is configured to output the inverse signal of Fault B.
[0065] According to one embodiment, the enable trigger circuit 103 may further include a first resistor 602, a fifth NOT gate 603, and a first capacitor 604. One end of the first resistor 602 is electrically connected to the output terminal of the fourth NOT gate 601, and the other end is electrically connected to the input terminal of the fifth NOT gate 603. One end of the first capacitor 604 is electrically connected to the input terminal of the fifth NOT gate 603, and the other end is grounded.
[0066] According to one embodiment, the first resistor 602 and the first capacitor 604 are configured to delay the inverse signal of Fault B, and the output of the fifth NOT gate 603 is configured to output the delayed signal Fault B_D.
[0067] According to one embodiment, the enable trigger circuit 103 may further include a third D flip-flop 605. The D terminal of the third D flip-flop 605 is electrically connected to the power supply VDD, the CLK terminal is electrically connected to the output terminal of the fifth NOT gate 603, configured to receive the signal Fault B_D, the EN terminal is configured to receive the signal RP from the exception handling circuit 101, and the Q terminal is configured to output the signal Pass and send it to the timing circuit 102.
[0068] According to one embodiment, reference Figure 3 When Fault B is valid, FLT_TRI is valid, generating signal RP through the first D flip-flop 304. D flip-flops have a certain delay, defined as D1. That is, after signal FLT_TRI becomes valid, signal RP becomes valid after D1. According to one embodiment, D1 is typically around 1 ns.
[0069] According to one embodiment, reference Figure 6 If Fault B is sent directly to the CLK pin of the third D flip-flop 605, when Fault B becomes active, due to the delay D1, RP has not yet become active. Since the EN pin of the third D flip-flop 605 is configured to receive the signal RP, the third D flip-flop 605 has not yet entered normal operation and cannot generate the signal Pass. Without this module, the effective level of Fault B might be missed due to D1, preventing the signal DIS_EN_SYS from becoming active in time. To avoid this, a first resistor 602 and a first capacitor 604 are used in the enable trigger circuit to generate an RC delay. The RC delay delays the signal Fault B to generate the signal Fault B_D. The delay between Fault B becoming active and Fault B_D becoming active is defined as D2, where D2 > D1. According to one embodiment, the values of the first resistor 602 and the first capacitor 604 can be adjusted so that D2 is between 10ns and 20ns.
[0070] Figure 7 This is a waveform diagram of the enable trigger circuit according to an embodiment of this application.
[0071] According to one embodiment, at time t1, the signal Fault B becomes active. Because the first D flip-flop 304 in the exception handling circuit 101 has a delay, the signal RP becomes active at time t2, which is after t1. The time interval between t1 and t2 is D1.
[0072] According to one embodiment, because an RC delay is provided in the enable trigger circuit 103, the signal Fault B_D becomes active at time t3 after t2. The time interval between t1 and t3 is D2.
[0073] According to one embodiment, at time t3, Fault B_D becomes valid, RP is valid, the third D flip-flop 605 is in normal working state, so Pass becomes valid.
[0074] Figure 8 This is a waveform diagram of the abnormal timing processing system according to an embodiment of this application.
[0075] According to one embodiment, Figure 8 The waveform diagram shown illustrates the generation principle of the reporting signal FLT_CTR. Because both Fault A and Fault B require the generation of the reporting signal FLT_CTR, Figure 8 In the relevant description, the fault signal can be either Fault A or Fault B.
[0076] According to one embodiment, reference Figure 4 The period of the signal CLK is defined as T. C The period of the signal Time is T. T Based on the working principle and connection relationship of the eight D flip-flops and the second OR gate 409, T can be calculated. T =2 8 T C In one cycle of the signal Time, the effective duration T is, for example, the duration of a high level. H =3 / 4T T Failure, for example, the duration T of a low level. L =1 / 4T T .
[0077] According to one embodiment, such as Figure 8 As shown, at time t4, FLT_TRI becomes active. After passing through the first D flip-flop 304 in the exception handling circuit 101, RP becomes active. The EN terminals of the eight D flip-flops in the timing circuit 102 are configured to receive the signal RP. When RP becomes active, the eight D flip-flops enter the working state, and Time becomes active (Time's default state is active). Time and RP pass through the third AND gate 410, making FLT_CTR active.
[0078] According to one embodiment, such as Figure 8 As shown, FLT_TRI becomes invalid at time t5. The time interval between t4 and t5 is less than T. T After passing through the second D flip-flop 303 in the exception handling circuit 101, FP becomes active. However, Time is still high at this time. After processing by the second NOT gate 305, the first AND gate 306, the third NOT gate 307, and the second AND gate 308, Reset remains active. The second D flip-flop 303 and the first D flip-flop 304 are not reset (the second D flip-flop 303 and the first D flip-flop 304 would be reset if Reset fails). Therefore, RP remains active at this time, and FLT_CTR remains active.
[0079] According to one embodiment, such as Figure 8 As shown, at time t6, Time becomes invalid. After processing by the second NOT gate 305, the first AND gate 306, the third NOT gate 307, and the second AND gate 308, the generated signal Reset becomes invalid. Reset is sent to the EN terminals of the second D flip-flop 303 and the first D flip-flop 304, causing the second D flip-flop 303 and the first D flip-flop 304 to be reset, and RP and FP return to their default state, i.e., invalid. The invalidation of RP causes FLT_CTR to also become invalid.
[0080] According to one embodiment, between time t4 and time t6, the effective duration of FLT_CTR is equal to the effective duration of Time in one period, i.e., T. H In other words, when the abnormal timing processing system receives a valid duration less than T... T When an abnormal signal is received, the system will output an effective duration of T. H The reporting signal avoids the problem of the reporting signal being too short.
[0081] According to one embodiment, such as Figure 8 As shown, at time t6, Time becomes inactive, Reset becomes inactive, and RP becomes inactive. The eight D flip-flops in the timing circuit 102 are reset, so after time t6, the Time signal returns to its default state, i.e., becomes active.
[0082] According to one embodiment, such as Figure 8As shown, at time t7, FLT_TRI becomes valid. After passing through the first D flip-flop 304 in the exception handling circuit 101, RP becomes valid. The EN terminals of the eight D flip-flops in the timing circuit 102 are configured to receive the signal RP. When RP becomes valid, the eight D flip-flops enter the working state, making Time valid. Time and RP pass through the third AND gate 410, making FLT_CTR valid.
[0083] According to one embodiment, such as Figure 8 As shown, FLT_TRI becomes invalid at time t8. The time interval between t7 and t8 is greater than T. T This means that the time is greater than one cycle of the timing signal Time. After passing through the second D flip-flop 303 in the exception handling circuit 101, FP becomes valid. However, Time is still valid at this time. After being processed by the second NOT gate 305, the first AND gate 306, the third NOT gate 307, and the second AND gate 308, Reset is still valid. The second D flip-flop 303 and the first D flip-flop 304 have not been reset, so RP is still valid and FLT_CTR is still valid.
[0084] According to one embodiment, such as Figure 8 As shown, at time t9, Time becomes invalid. After processing by the second NOT gate 305, the first AND gate 306, the third NOT gate 307, and the second AND gate 308, the generated signal Reset becomes invalid. Reset is sent to the EN terminals of the second D flip-flop 303 and the first D flip-flop 304, causing the second D flip-flop 303 and the first D flip-flop 304 to be reset, and RP and FP return to their default state, i.e., invalid. The invalidation of RP causes FLT_CTR to also become invalid.
[0085] According to one embodiment, the effective duration of FLT_TRI is greater than T between time t7 and time t9. T 3 times, less than T T The effective duration of FLT_CTR is equal to the effective duration of Time over 4 periods, i.e., 4T. (This is equivalent to 4 times the effective duration of Time over 3 periods, or 4 periods less than Time). H In other words, when the abnormal timing processing system receives a valid duration of aT T to bT T When an abnormal signal occurs (where a and b are both integers, and a≥1, b=a+1), the system will output an effective duration of bT. H The reporting signal avoids the problem of the reporting signal lasting too long.
[0086] According to one embodiment, such as Figure 8As shown, at time t9, Time becomes inactive, Reset becomes inactive, and RP becomes inactive. The eight D flip-flops in the timing circuit 102 are reset, so after time t9, the Time signal returns to its default state, i.e., becomes active.
[0087] Figure 9 This is a waveform diagram of the abnormal timing processing system according to an embodiment of this application.
[0088] According to one embodiment, such as Figure 9 As shown, at times t10 and t11, Fault B changes from invalid to valid. Fault B represents an anomaly that only needs to be reported, so at times t10 and t11, the signal Pass does not become valid.
[0089] According to one embodiment, reference Figure 3 The input of the first OR gate 301 is configured to receive signals Fault A and Fault B. FLT_TRI is valid when either Fault A or Fault B is active. Subsequently, the exception timing processing system generates a reporting signal FLT_CTR. For details, please refer to [link to relevant documentation]. Figure 8 And related explanations.
[0090] According to one embodiment, such as Figure 9 As shown, at time t12, Fault A changes from invalid to valid. Fault A represents an exception that requires both reporting and chip shutdown. After being processed by the enable trigger circuit 103, Fault A causes Pass to change from invalid to valid. The input of the fourth AND gate 411 is configured to receive signals Pass and FLT_CTR. At this time, FLT_CTR is valid, so DIS_EN_SYS changes from invalid to valid.
[0091] According to one embodiment, there is an RC delay between the transition from Fault A to Pass and the transition from Fault A to Pass to Pass. The specific principle behind this delay is explained in [the document / document / etc.]. Figure 6 and Figure 7 The relevant embodiments have been described, therefore in Figure 9 The delay is not shown in the image.
[0092] According to one embodiment, such as Figure 9 As shown, between time t12 and time t13, Pass remains valid, and the changes in DIS_EN_SYS are synchronized with FLT_CTR.
[0093] According to one embodiment, such as Figure 9 As shown, at time t13, Fault A changes from valid to invalid. However, RP is still valid at this time (RP is in...). Figure 9(Not shown in the image). The EN terminal of the third D flip-flop 605 in the enable trigger circuit 103 is configured to receive the signal RP. When RP is valid, the third D flip-flop 605 is not reset, so Pass is still valid at this time.
[0094] According to one embodiment, such as Figure 9 As shown, at time t14, RP becomes inactive (RP at... Figure 9 (Not shown in the diagram) The third D flip-flop 605 in the enable trigger circuit 103 is reset, and Pass becomes disabled. Furthermore, at time t14, FLT_CTR becomes disabled, so DIS_EN_SYS becomes disabled.
[0095] According to one embodiment, the exception timing processing system can generate FLT_TRI based on Fault A or Fault B, and then generate FLT_CTR through subsequent processing for reporting the exception. The exception timing processing system can also generate Pass based on Fault A, and then generate DIS_EN_SYS based on Pass and FLT_CTR for shutting down the chip. In summary, when an exception occurs in the chip, whether the exception only needs to be reported or needs to both be reported and the chip needs to be shut down, the exception timing processing system proposed in this application can handle it flexibly.
[0096] The anomaly timing processing system proposed in this application can generate a reporting signal of appropriate duration based on the duration of the anomaly signal, for reporting to the main control chip, thus avoiding the problems of reporting signals being too long or too short. For anomalies that only need to be reported, the system can generate a reporting signal of appropriate duration. For anomalies that require both reporting and chip shutdown, the system can generate both a reporting signal of appropriate duration and a shutdown signal to shut down the chip, enabling flexible handling of different types of anomalies.
Claims
1. An abnormal timing processing system, characterized in that, Includes exception handling circuitry and timing circuitry, among which, The exception handling circuit is configured to receive exception signals from the chip, wherein the exception signals include a first type of exception signal, which represents an exception that has occurred in the chip that only needs to be reported. The exception handling circuit is further configured to receive a timing signal from the timing circuit and generate a first drive signal based on the timing signal and the exception signal, for enabling control of the timing circuit. The timing circuit is configured to generate a timing signal with a preset period based on its clock signal under the enable control of the first driving signal. The timing circuit is also configured to generate a first reporting signal based on the first driving signal and the timing signal. Based on the relationship between the effective time of the first type of abnormal signal and the effective time of the timing signal within one period, the effective time of the first reporting signal is one or more times the effective time of the timing signal within one period.
2. The abnormal timing processing system according to claim 1, characterized in that, The abnormal signals also include a second type of abnormal signal, which represents an abnormality in the chip that needs to be reported to the main controller and the chip needs to be shut down. The abnormal timing processing system further includes an enable trigger circuit, configured to generate a pass signal based on the second type of abnormal signal under the enable control of the first drive signal; The timing circuit is also configured to receive the pass signal and generate a second reporting signal based on the pass signal and the first reporting signal.
3. The abnormal timing processing system according to claim 2, characterized in that, The exception handling circuit includes: The first OR gate has its inputs configured to receive the first type of abnormal signal and / or the second type of abnormal signal from the chip, respectively. The input terminal of the first NOT gate is electrically connected to the output terminal of the first OR gate; The first D flip-flop has its data input terminal electrically connected to the power supply, its clock terminal electrically connected to the output terminal of the first OR gate, and its main output terminal electrically connected to the enable trigger circuit and the timing circuit, and is configured to output the first drive signal. The second D flip-flop has its data input terminal electrically connected to the power supply, its clock terminal electrically connected to the output terminal of the first NOT gate, and its main output terminal configured to output the second drive signal. The second NOT gate has its input terminal electrically connected to the timing circuit and is configured to receive the timing signal; A first AND gate, one input of which is electrically connected to the main output of the second D flip-flop, and the other input of which is electrically connected to the output of the second NOT gate; The input of the third NOT gate is electrically connected to the output of the first AND gate. The second AND gate has one input electrically connected to the output of the third NOT gate, the other input configured to receive a system enable signal, and its output electrically connected to the enable terminals of the first D flip-flop and the second D flip-flop, configured to output a reset signal.
4. The abnormal timing processing system according to claim 2, characterized in that, The enabling trigger circuit includes: The fourth NOT gate has its input configured to receive the second type of abnormal signal from the chip; The first resistor has its first end electrically connected to the output terminal of the fourth NOT gate; The first capacitor has its first terminal electrically connected to the second terminal of the first resistor, and its second terminal is grounded. The fifth NOT gate has its input terminal electrically connected to the second terminal of the first resistor; The third D flip-flop has its data input electrically connected to the power supply, its clock input electrically connected to the output of the fifth NOT gate, and its main output electrically connected to the timing circuit. It is configured to output the pass signal, and its enable input is electrically connected to the exception handling circuit, configured to receive the first drive signal. The first resistor and the first capacitor are configured to generate a first delay, which is greater than the delay of the first D flip-flop itself.
5. The abnormal timing processing system according to claim 2, characterized in that, The timing circuit includes: One or more D flip-flops, the enable terminal of each D flip-flop is electrically connected to the exception handling circuit and configured to receive the first drive signal, the inverting output terminal of each D flip-flop is electrically connected to its own data input terminal and the clock terminal of the next D flip-flop, wherein the clock terminal of the first D flip-flop is configured to receive a clock signal. The second OR gate has one input electrically connected to the inverting output of the last D flip-flop and the other input electrically connected to the clock output of the last D flip-flop. The output of the second OR gate is electrically connected to the exception handling circuit and is configured to output the timing signal. A third AND gate, one input of which is electrically connected to the output of the second OR gate and configured to receive the timing signal, and the other input of which is electrically connected to the exception handling circuit and configured to receive the first drive signal, and the output of which is configured to output the first reporting signal; The fourth AND gate has one input electrically connected to the output of the third AND gate and configured to receive the first reporting signal. The other input of the fourth AND gate is electrically connected to the enable trigger circuit and configured to receive the pass signal. The output of the fourth AND gate is configured to output the second reporting signal.
6. The abnormal timing processing system according to claim 5, characterized in that, The timing circuit contains eight D flip-flops.
7. The abnormal timing processing system according to claim 2, characterized in that, When the effective time of the first type of abnormal signal or the second type of abnormal signal is less than the period of the timing signal, the effective time of the first reporting signal or the second reporting signal is the effective time of the timing signal within one period; when the effective time of the first type of abnormal signal or the second type of abnormal signal is greater than the period of the timing signal, the effective time of the first reporting signal or the second reporting signal is an integer multiple of the effective time of the timing signal within one period.
8. The abnormal timing processing system according to claim 7, characterized in that, When the effective time of the first type of abnormal signal or the second type of abnormal signal is greater than a first integer multiple of the timing signal period and less than a second integer multiple of the timing signal period, wherein the first integer multiple is greater than or equal to 1 and the second integer multiple is equal to the first integer multiple plus 1, the effective time of the first reporting signal or the second reporting signal is a second integer multiple of the effective time of the timing signal within one period.
9. An electronic device, characterized in that, Includes the abnormal timing processing system described in any one of claims 1-8.
10. An anomaly handling method based on the anomaly timing processing system according to any one of claims 1-8, characterized in that, When the validity period of the abnormal signal is less than the period of the timing signal, the validity period of the generated reporting signal is the validity period of the timing signal within one period; when the validity period of the abnormal signal is greater than the period of the timing signal, the validity period of the generated reporting signal is an integer multiple of the validity period of the timing signal within one period.
11. The anomaly handling method according to claim 10, characterized in that, When the effective time of an abnormal signal is greater than the third integer multiple of the timing signal period and less than the fourth integer multiple of the timing signal period, where the third integer multiple is greater than or equal to 1 and the fourth integer multiple is equal to the third integer multiple plus 1, the effective time of the generated reporting signal is the fourth integer multiple of the effective time of the timing signal within one period.