A matrix reduction operation method, device, equipment, storage medium and product

Abstract

The application discloses a matrix reduction operation method, device and equipment, a storage medium and a product. The method comprises the following steps: reading configuration information of a preset matrix reduction instruction; reading matrix data to be processed according to the configuration information; and calling an arithmetic logic unit at a memory end to execute the matrix reduction instruction on the matrix data based on the configuration information. The embodiment of the application can execute the matrix reduction operation without occupying a register end alu, and provides sufficient register end resources for other tasks.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of artificial intelligence, and in particular to a matrix reduction operation method and device, equipment, a storage medium and a product. BACKGROUND

[0002] Matrix reduction operation refers to calculating a matrix by row or column, which is a scenario requirement in reality. For example, when processing multi-dimensional data, it is usually necessary to perform matrix reduction on the rows or columns of the matrix to extract core information. Traditional matrix reduction operation needs to call a shuffle instruction to implement, but the shuffle instruction cannot directly complete the core operation of matrix reduction and still needs to rely on the arithmetic and logic unit (ALU) at the register end to execute. However, the ALU resource at the register end is limited, and when processing large-scale matrix reduction operation, a large number of register end resources will be occupied, which cannot allocate sufficient register end resources for other tasks, thereby affecting the computing efficiency of other tasks. SUMMARY

[0003] The present application provides a matrix reduction operation method, device, equipment, storage medium and product to solve the problem that a large number of register end resources are occupied in the prior art, which cannot allocate sufficient register end resources for other tasks, thereby affecting the computing efficiency of other tasks.

[0004] To achieve the above-mentioned purpose, the embodiment of the present application provides a matrix reduction operation method, comprising:

[0005] reading the configuration information of a preset matrix reduction instruction;

[0006] reading the matrix data to be processed according to the configuration information;

[0007] based on the configuration information, calling the arithmetic and logic unit at the memory end to execute the matrix reduction instruction on the matrix data.

[0008] As an improvement of the above-mentioned scheme, the configuration information comprises:

[0009] mode, used to indicate the operation type of the matrix reduction instruction;

[0010] data type, used to indicate the data type participating in the operation of the matrix reduction instruction;

[0011] axis, used to indicate the axis dimension of the matrix reduction instruction;

[0012] synchronization flag, used to indicate the end of the operation of the matrix reduction instruction;

[0013] a number of registers, for indicating a number of registers on which the matrix reduction instruction acts;

[0014] a destination, for indicating a storage location of a result of the matrix reduction instruction.

[0015] As an improvement of the above-mentioned scheme, the configuration information further comprises at least one of:

[0016] an absolute value function, for indicating that the matrix reduction instruction enables an absolute value calculation function;

[0017] a cross-register function, for indicating that the matrix reduction instruction enables a cross-register calculation function;

[0018] a descriptor, for indexing a scaling factor, the scaling factor acting on a dequantization operation indicated by the matrix reduction instruction.

[0019] As an improvement of the above-mentioned scheme, the scaling factor is stored in a scaling table, the scaling table being pre-configured by a user or pre-calculated by a core of the processor.

[0020] As an improvement of the above-mentioned scheme, the method further comprises:

[0021] based on the configuration information, invoking a transpose unit at the memory end to execute the matrix reduction instruction on the matrix data.

[0022] As an improvement of the above-mentioned scheme, based on the configuration information, invoking an arithmetic logic unit at the memory end to execute the matrix reduction instruction on the matrix data, comprises:

[0023] sending the matrix data and the configuration information to the arithmetic logic unit, so that the arithmetic logic unit executes the matrix reduction instruction on the matrix data according to the configuration information.

[0024] To achieve the above-mentioned object, the embodiment of the present application further provides a matrix reduction operation device, comprising:

[0025] a first reading module, for reading configuration information of a preset matrix reduction instruction;

[0026] a second reading module, for reading matrix data to be processed according to the configuration information;

[0027] a first operation module, for based on the configuration information, invoking an arithmetic logic unit at the memory end to execute the matrix reduction instruction on the matrix data.

[0028] To achieve the above objectives, this application also provides a matrix reduction operation device, including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor. When the processor executes the computer program, it implements the matrix reduction operation method as described above.

[0029] To achieve the above objectives, embodiments of this application also provide a computer-readable storage medium, the computer-readable storage medium including a stored computer program; wherein, when the computer program is executed, it controls the device where the computer-readable storage medium is located to perform the matrix reduction operation method as described above.

[0030] To achieve the above objectives, embodiments of this application also provide a computer program product, including a computer program / instructions, which, when executed by a processor, implement the matrix reduction operation method as described above.

[0031] Compared with the prior art, the matrix reduction operation method, apparatus, device, storage medium and product provided in this application embodiment reads the configuration information of the preset matrix reduction instruction; reads the matrix data to be processed according to the configuration information; and calls the arithmetic logic unit on the memory side to execute the matrix reduction instruction on the matrix data based on the configuration information. This eliminates the need to occupy the register side ALU to perform matrix reduction operation, and can provide sufficient register side resources for other tasks, thereby improving the computational efficiency of other tasks. Attached Figure Description

[0032] Figure 1 This is a flowchart of a matrix reduction operation method provided in an embodiment of this application;

[0033] Figure 2 This is a structural block diagram of an artificial intelligence chip provided in an embodiment of this application;

[0034] Figure 3 This is a schematic diagram of the register layout provided in an embodiment of this application;

[0035] Figure 4 This is a schematic diagram of an inverse quantization process provided in an embodiment of this application;

[0036] Figure 5 This is a flowchart illustrating the execution of a matrix reduction instruction provided in an embodiment of this application;

[0037] Figure 6 This is a schematic diagram of execution without cross-register functionality provided in an embodiment of this application;

[0038] Figure 7 This is a schematic diagram of enabling cross-register function execution provided in an embodiment of this application;

[0039] Figure 8 This is a structural block diagram of a matrix reduction operation device provided in an embodiment of this application;

[0040] Figure 9 This is a structural block diagram of a matrix reduction operation device provided in an embodiment of this application. Detailed Implementation

[0041] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0042] In the description of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0043] In this application description, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0044] In this application description, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus. The term "based on" means "at least partially based on." The term "according to" means "at least partially according to." The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments." The term "and / or" means at least one of the connected objects, such as A and / or B, indicating three cases: including only A, only B, and both A and B. Unless otherwise stated, the term "multiple" means two or more.

[0045] It is worth noting that this application applies to artificial intelligence chips, which can be graphics processing units (GPUs), general-purpose graphics processing units (GPGPUs), or other AI chips. See also Figure 2 This is a structural block diagram of an artificial intelligence chip provided in an embodiment of this application. The artificial intelligence chip includes a core, a register side, and a memory side. The register side includes registers and an arithmetic logic unit (ALU), and the memory side includes an ALU.

[0046] It's worth noting that a warp has 32 threads, and each thread's Thread Local Register (TLR) is 4 bytes, so a warp's TLR contains 128 bytes of data. From the perspective of a warp's TLR, the row number for each TLR layout is 8; the column number for FP8 and BF8 is 16; the column number for FP16 and BF16 is 8; and the column number for FP32 is 4. Figure 3 Among them, fp8 (8-bit floating point) is an 8-bit floating point number, fp16 (16-bit floating point) is a 16-bit floating point number, fp32 (32-bit floating point) is a 32-bit floating point number, bf8 (8-bit Brain Floating Point) is an 8-bit brain floating point number, bf16 (16-bit Brain Floating Point) is a 16-bit brain floating point number, and r0, r1, r2, and r3 represent register labels respectively.

[0047] See Figure 1 , Figure 1 This is a flowchart of a matrix reduction operation method provided in an embodiment of this application. The matrix reduction operation method includes:

[0048] S1. Read the configuration information of the preset matrix reduction instruction;

[0049] S2. Read the matrix data to be processed according to the configuration information;

[0050] S3. Based on the configuration information, the arithmetic logic unit in memory is invoked to execute the matrix reduction instruction on the matrix data.

[0051] This application embodiment designs a new matrix reduction instruction, which specifies that the memory-side aluu is called to perform matrix reduction. By processing matrix data through this matrix reduction instruction, there is no need to occupy the register-side aluu to perform matrix reduction operations, which can provide sufficient register-side resources for other tasks, thereby improving the computational efficiency of other tasks.

[0052] In one optional embodiment, the configuration information includes:

[0053] The mode is used to indicate the operation type of the matrix reduction instruction;

[0054] Data type, used to indicate the data type involved in the matrix reduction instruction operation;

[0055] Axis, used to indicate the axis dimension on which the matrix reduction command is applied;

[0056] A synchronization flag is used to indicate that the matrix reduction instruction operation has ended;

[0057] The number of registers used to indicate the number of registers affected by the matrix reduction instruction;

[0058] The destination location indicates the storage location of the result of the matrix reduction instruction.

[0059] In this embodiment of the application, the following information is configured for the matrix reduction instruction:

[0060] The mode indicates the operation type of the matrix reduction instruction, representing the type of operation performed on the matrix data. For example, if the indicated operation type is "min", it means finding the minimum value of either row or col in the matrix data. The operation types include:

[0061] min: Find the minimum value of row or col;

[0062] max: Find the maximum value of row or col;

[0063] sum: calculates the sum of row or col;

[0064] avg: Calculates the average of row or col.

[0065] sq: Calculates the squared sum of row or col.

[0066] Data type (dt) is used to indicate the data type involved in the matrix reduction instruction operation, that is, the data type in the matrix reduction instruction operation process, including: fp8, bf8, fp16, bf16, fp32, etc.

[0067] An axis is used to indicate the dimension on which a matrix reduction command applies, including either row or col. This means that the matrix data is reduced based on either row or col. For example, if the indicated axis dimension is row, it means that the matrix data is reduced based on its rows.

[0068] The synchronization flag (sc) is used to indicate the end of the matrix reduction instruction operation. That is, when this flag is received, it means that the current matrix reduction instruction operation has ended.

[0069] The register count (gcnt) indicates the number of registers on which the matrix reduction instruction operates. Specifically, it indicates the number of registers that can be read (input) (i.e., the matrix data to be processed mentioned above) into the memory-side ALU, where the memory-side ALU executes the matrix reduction instruction. Optionally, the register count can be 1, 2, 3, or 4. For example, a register count of 2 indicates that data from 2 registers can be read into the memory-side ALU for the memory-side ALU to execute the matrix reduction instruction.

[0070] The destination location (dst) indicates the storage location of the result of the matrix reduction instruction; if the storage location is a specific register, it means that the result of the matrix reduction instruction will be stored in the corresponding register.

[0071] This application embodiment defines key parameters for matrix reduction operations by configuring the mode, data type, axis, synchronization flag, and destination position of the matrix reduction instruction. This ensures the smooth execution of matrix data reduction operations by the memory-side ALU, improves the flexibility of matrix reduction operations, and adapts to complex business scenarios.

[0072] In one optional embodiment, the configuration information further includes at least one of the following:

[0073] The absolute value function is used to instruct the matrix reduction instruction to enable the absolute value calculation function;

[0074] Cross-register functionality is used to instruct the matrix reduction instruction to enable cross-register computation.

[0075] A descriptor for indexing a scaling factor that acts on the dequantization operation indicated by the matrix reduction instruction.

[0076] This application embodiment configures at least one of the following pieces of information for the matrix reduction instruction:

[0077] The absolute value function (abs) is used to instruct matrix reduction commands to enable absolute value calculation. By adding the absolute value function, not only are the operations on matrix data expanded, but also, without adding additional commands, it enables the matrix data containing negative numbers to first perform absolute value operations, and then perform operations such as min, max, sum, avg, and sq, thus meeting diverse business needs.

[0078] The "cross" function is used to instruct matrix reduction instructions to enable cross-register computation. Related technologies do not consider register layout characteristics; therefore, the shuffle instruction needs to simulate building the matrix layout, requiring multiple calls to the shuffle instruction to achieve matrix reduction. This undoubtedly affects the efficiency of matrix reduction operations. However, the embodiments of this application consider that matrix data will be stored across registers (e.g., ...). Figure 2 This feature enables cross-register operations, allowing matrix reduction to compute row or column data across multiple registers in a single operation. This achieves the same reduction effect without requiring multiple calls to the shuffle instruction, significantly improving computational efficiency. The feature is compatible with min, max, sum, avg, and sq operations in cross-register scenarios, making it more suitable for reducing large-scale matrices.

[0079] The descriptor (desc) is used to index the scaling factor, which operates on the dequantization operation indicated by the matrix reduction instruction. By configuring the descriptor, dequantization operation can be controlled without adding additional instructions or executing at the register level (ALU).

[0080] It should be noted that if dequantization is performed, the original value obtained by dequantization will be used for operations such as min, max, sum, avg, and sq.

[0081] In one specific embodiment, the matrix reduction instruction is: redmatrix.mode.dt[.abs].axis[.cross].sc.gcnt dst, desc.

[0082] mode = {min|max|sum|avg|sq} / / The matrix reduction instruction operates on the following types: min, max, sum, avg, or sq.

[0083] dt = {fp8 / bf8 / fp16 / bf16 / fp32} / / The data types participating in the matrix reduction instruction operation are fp8, bf8, fp16, bf16 or fp32;

[0084] abs = {abs} / / Optional function, absolute value calculation function.

[0085] axis = {row|col} / / The matrix reduction command applies to either the row or col axis.

[0086] cross = {cross} / / Optional function, cross-register calculation function.

[0087] sc = {sync channel} / / Receiving the sync channel indicates that the matrix reduction instruction operation has ended;

[0088] gcnt = {gc1|gc2|gc3|gc4} / / This represents the number of registers as 1, 2, 3, or 4, respectively.

[0089] dst = {tlr} / / The result of the matrix reduction instruction is stored in a register.

[0090] `desc = {descriptor index}` / / Stores the descriptor index, used to index scaling factors. Additionally, the descriptor index can also be used to describe tensor information (such as height, width, and data type `dt`). Users can include the `descriptor index` in the command to index this data.

[0091] In an alternative embodiment, the scaling factor is stored in a scaling table, which is pre-configured by the user or pre-calculated by the processor's kernel.

[0092] It's worth noting that the matrix data may have undergone quantization and is not the original value. It needs to be multiplied by a scaling factor for dequantization (i.e., restoration) to obtain the original value. This scaling factor is stored in a scaling table. The scaling factor can be configured by the user or calculated by the user in the processor kernel.

[0093] It is understandable that in the scaling table, there is a mapping relationship between matrix data and scaling factors. Different rows or different cols will have different scaling factors, and different strides will have different values; this application does not impose specific restrictions. For example, as... Figure 4The scaling factors are arranged by row, and the stride in the column direction is 4, meaning that four columns use one scaling factor to form a scaling table. The data in the first row of register r0 is multiplied by the scaling factor "20" in the first column of the first row of this scaling table to achieve dequantization. The data in the second row of register r0 is multiplied by the scaling factor "5" in the first column of the second row of this scaling table to achieve dequantization. Register r1 is processed similarly, so it will not be described in detail here.

[0094] In an optional embodiment, the method further includes:

[0095] Based on the configuration information, the transpose unit in the memory is invoked to execute the matrix reduction instruction on the matrix data.

[0096] It is worth noting that when the matrix reduction instruction operates on the axis dimension col, in order to simplify the instruction complexity, the existing transpose unit in memory is reused to transpose col and then process it uniformly according to row.

[0097] In a specific embodiment, the execution flow of the matrix reduction instruction is as follows: Figure 5 As shown:

[0098] ① If axis indicates col, then the existing transpose unit in memory is called to transpose col and then process it according to row.

[0099] ② If the command is configured with abs, it means that the absolute value calculation function is enabled, and the absolute value will be calculated.

[0100] ③ If the command is configured with `desc`, it is expected to read the scaling factor from the scaling table and calculate the original value. The scaling factor supports row and col indexing, and is indexed via `desc`. The order of `abs` and `desc` is irrelevant, and the scaling factor is an unsigned type.

[0101] ④ If the instruction is configured with `cross`, it indicates that cross-register computation is enabled. If disabled, the computation range is limited to one register. If enabled, the computation range is not limited to one register and can perform calculations across multiple registers at once.

[0102] ⑤ Based on the mode and dt configured in this instruction, calculate the min, max, sum, avg, and sq of the row data in the register. Specifically, if the cross-register calculation function is enabled, the memory-side ALU can perform calculations across multiple registers, that is, calculate row data across multiple registers, supporting calculations across all registers. If the cross-register calculation function is not enabled, the memory-side ALU cannot perform calculations across multiple registers; each calculation is limited to the row data of one register, that is, calculate the row data of its own register.

[0103] ⑥ The operation result is broadcast to each destination register, or the operation result is stored in its respective destination register.

[0104] Using the matrix reduction instruction "redmatrix.row.fp32.gc2" as an example, let's illustrate processes ④, ⑤, and ⑥. This is a matrix reduction instruction without enabling cross-register computation; it calculates the maximum row value of each of the two registers, limiting the calculation to one register at a time, and writes the result to the respective register. For example... Figure 6 Calculate the maximum value of the row in register r0 and write the result in register r0; calculate the maximum value of the row in register r1 and write the result in register r1.

[0105] The matrix reduction instruction "redmatrix.row.fp32.cross.gc2" is used as an example to illustrate processes ④, ⑤, and ⑥. This is a matrix reduction instruction that enables cross-register computation, calculating the maximum row value across two registers. Each calculation covers both registers, and the result is broadcast to each destination register. For example... Figure 7 Calculate the maximum value of each row in registers r0 and r1, and broadcast the result to registers r0 and r1.

[0106] In an optional embodiment, the step of invoking the arithmetic logic unit in memory to execute the matrix reduction instruction on the matrix data based on the configuration information includes:

[0107] The matrix data and the configuration information are sent to the arithmetic logic unit so that the arithmetic logic unit executes the matrix reduction instruction on the matrix data according to the configuration information.

[0108] In this embodiment, configuration information for matrix data and matrix reduction instructions is sent to the memory-based ALU, enabling the memory-based ALU to process the matrix data according to the configuration information, thereby completing the matrix reduction instructions. This embodiment utilizes the memory-based ALU, eliminating the need to occupy the register-based ALU for matrix reduction operations, thus providing sufficient register resources for other tasks and improving their computational efficiency.

[0109] SeeFigure 8 , Figure 8 This is a structural block diagram of a matrix reduction operation device 10 provided in an embodiment of this application. The matrix reduction operation device 10 includes:

[0110] The first reading module 11 is used to read the configuration information of the preset matrix reduction instruction;

[0111] The second reading module 12 is used to read the matrix data to be processed according to the configuration information;

[0112] The first arithmetic module 13 is used to call the arithmetic logic unit in memory to execute the matrix reduction instruction on the matrix data based on the configuration information.

[0113] Optionally, the configuration information includes:

[0114] The mode is used to indicate the operation type of the matrix reduction instruction;

[0115] Data type, used to indicate the data type involved in the matrix reduction instruction operation;

[0116] Axis, used to indicate the axis dimension on which the matrix reduction command is applied;

[0117] A synchronization flag is used to indicate that the matrix reduction instruction operation has ended;

[0118] The number of registers used to indicate the number of registers affected by the matrix reduction instruction;

[0119] The destination location indicates the storage location of the result of the matrix reduction instruction.

[0120] Optionally, the configuration information may further include at least one of the following:

[0121] The absolute value function is used to instruct the matrix reduction instruction to enable the absolute value calculation function;

[0122] Cross-register functionality is used to instruct the matrix reduction instruction to enable cross-register computation.

[0123] A descriptor for indexing a scaling factor that acts on the dequantization operation indicated by the matrix reduction instruction.

[0124] Optionally, the scaling factor is stored in a scaling table, which is pre-configured by the user or pre-calculated by the processor's kernel.

[0125] Optionally, the matrix reduction operation device 10 further includes:

[0126] The second operation module is used to execute the matrix reduction instruction on the matrix data by calling the transpose unit in the memory based on the configuration information.

[0127] Optionally, the step of calling the memory-based arithmetic logic unit to execute the matrix reduction instruction on the matrix data based on the configuration information includes:

[0128] The matrix data and the configuration information are sent to the arithmetic logic unit so that the arithmetic logic unit executes the matrix reduction instruction on the matrix data according to the configuration information.

[0129] It is worth noting that the working process of each module in the matrix reduction operation device 10 described in this application embodiment can refer to the working process of the matrix reduction operation method described in the above embodiment and achieve the same beneficial effect, and will not be repeated here.

[0130] Furthermore, this application also provides a computer-readable storage medium, which includes a stored computer program; wherein, when the computer program is executed, it controls the device where the computer-readable storage medium is located to perform the matrix reduction operation method as described in any of the above embodiments.

[0131] Furthermore, this application also provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the matrix reduction operation method as described in any of the above embodiments.

[0132] See Figure 9 , Figure 9 This is a structural block diagram of a matrix reduction operation device 20 provided in an embodiment of this application. The matrix reduction operation device 20 includes: a processor 21, a memory 22, and a computer program stored in the memory 22 and executable on the processor 21. When the processor 21 executes the computer program, it implements the steps in the matrix reduction operation method embodiments described above. Alternatively, when the processor 21 executes the computer program, it implements the functions of each module / unit in the various device embodiments described above.

[0133] For example, the computer program may be divided into one or more modules / units, which are stored in the memory 22 and executed by the processor 21 to complete this application. The one or more modules / units may be a series of computer program instruction segments capable of performing specific functions, which describe the execution process of the computer program in the matrix reduction operation device 20.

[0134] The matrix reduction computing device 20 may include, but is not limited to, a processor 21 and a memory 22. Those skilled in the art will understand that the schematic diagram is merely an example of the matrix reduction computing device 20 and does not constitute a limitation on the device. It may include more or fewer components than illustrated, or combine certain components, or use different components. For example, the matrix reduction computing device 20 may also include input / output devices, network access devices, buses, etc.

[0135] The processor 21 can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor. The processor 21 is the control center of the matrix reduction computing device 20, connecting all parts of the matrix reduction computing device 20 via various interfaces and lines.

[0136] The memory 22 can be used to store the computer programs and / or modules. The processor 21 implements various functions of the matrix reduction operation device 20 by running or executing the computer programs and / or modules stored in the memory 22 and calling the data stored in the memory 22. The memory 22 may mainly include a program storage area and a data storage area. The program storage area may store the operating system, at least one application program required for a function (such as sound playback function, image playback function, etc.), etc.; the data storage area may store data created according to the use of the mobile phone (such as audio data, phonebook, etc.). In addition, the memory 22 may include high-speed random access memory, and may also include non-volatile memory, such as hard disk, memory, plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, at least one disk storage device, flash memory device, or other volatile solid-state storage device.

[0137] Wherein, if the modules / units integrated in the matrix reduction operation device 20 are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by the processor 21, it can implement the steps of the various method embodiments described above. Wherein, the computer program includes computer program code, which can be in the form of source code, object code, executable file, or some intermediate form, etc. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drive, portable hard drive, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal, and software distribution medium, etc.

[0138] It should be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Furthermore, in the accompanying drawings of the device embodiments provided in this application, the connection relationships between modules indicate that they have communication connections, which can be specifically implemented as one or more communication buses or signal lines. Those skilled in the art can understand and implement this without any creative effort.

[0139] The above description is the preferred embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications are also considered to be within the scope of protection of this application.

Claims

1. A matrix reduction operation method, characterized in that, include: Read the configuration information of the preset matrix reduction instructions; Based on the configuration information, read the matrix data to be processed; Based on the configuration information, the arithmetic logic unit in memory is invoked to execute the matrix reduction instruction on the matrix data; The configuration information includes: The mode is used to indicate the operation type of the matrix reduction instruction; Data type, used to indicate the data type involved in the matrix reduction instruction operation; Axis, used to indicate the axis dimension on which the matrix reduction command is applied; A synchronization flag is used to indicate that the matrix reduction instruction operation has ended; The number of registers used to indicate the number of registers affected by the matrix reduction instruction; The destination location indicates the storage location of the result of the matrix reduction instruction. The configuration information also includes at least one of the following: The absolute value function is used to instruct the matrix reduction instruction to enable the absolute value calculation function; Cross-register functionality is used to instruct the matrix reduction instruction to enable cross-register computation. A descriptor for indexing a scaling factor that acts on the dequantization operation indicated by the matrix reduction instruction.

2. The matrix reduction operation method as described in claim 1, characterized in that, The scaling factor is stored in a scaling table, which is pre-configured by the user or pre-calculated by the processor's kernel.

3. The matrix reduction operation method as described in claim 1, characterized in that, The method further includes: Based on the configuration information, the transpose unit in the memory is invoked to execute the matrix reduction instruction on the matrix data.

4. The matrix reduction operation method as described in claim 1, characterized in that, The step of calling the memory-based arithmetic logic unit to execute the matrix reduction instruction on the matrix data based on the configuration information includes: The matrix data and the configuration information are sent to the arithmetic logic unit so that the arithmetic logic unit executes the matrix reduction instruction on the matrix data according to the configuration information.

5. A matrix reduction operation device, characterized in that, include: The first reading module is used to read the configuration information of the preset matrix reduction instructions; The second reading module is used to read the matrix data to be processed according to the configuration information; The first arithmetic module is used to execute the matrix reduction instruction on the matrix data by calling the arithmetic logic unit in memory based on the configuration information; The configuration information includes: The mode is used to indicate the operation type of the matrix reduction instruction; Data type, used to indicate the data type involved in the matrix reduction instruction operation; Axis, used to indicate the axis dimension on which the matrix reduction command is applied; A synchronization flag is used to indicate that the matrix reduction instruction operation has ended; The number of registers used to indicate the number of registers affected by the matrix reduction instruction; The destination location indicates the storage location of the result of the matrix reduction instruction. The configuration information also includes at least one of the following: The absolute value function is used to instruct the matrix reduction instruction to enable the absolute value calculation function; Cross-register functionality is used to instruct the matrix reduction instruction to enable cross-register computation. A descriptor for indexing a scaling factor that acts on the dequantization operation indicated by the matrix reduction instruction.

6. A matrix reduction operation device, characterized in that, It includes a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein the processor, when executing the computer program, implements the matrix reduction operation method as described in any one of claims 1 to 4.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes a stored computer program; wherein, when the computer program is executed, it controls the device on which the computer-readable storage medium is located to perform the matrix reduction operation method as described in any one of claims 1 to 4.

8. A computer program product, characterized in that, It includes a computer program / instruction that, when executed by a processor, implements the matrix reduction operation method as described in any one of claims 1 to 4.

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