Database-based memory split combination method, apparatus, device, and medium

Abstract

The application relates to the computer technical field and provides a database-based memory splitting and combining method, device, equipment and medium.The database-based memory splitting and combining method comprises the following steps: obtaining a database of storage units; wherein the database of storage units comprises attribute information of a plurality of storage units; based on design requirements of a target memory, a plurality of splitting schemes of the target memory are generated, each splitting scheme is composed of one or more storage units; the performance indexes of each splitting scheme are evaluated by using the attribute information in the database of storage units; and according to the evaluation results of all splitting schemes, an optimal splitting scheme is determined as a target splitting scheme of the target memory. The database of storage units is established in advance, the attribute information of the storage units can be obtained from the database when the target memory is designed, a plurality of splitting schemes can be quickly generated and evaluated, the optimization of resource utilization is realized, and the design efficiency and flexibility are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, and particularly relates to a database-based memory splitting and combining method, device, equipment and medium. BACKGROUND

[0002] In the current digital information age, memory is a key component of various electronic devices, and its performance and rationality of design directly affect the running efficiency and function implementation of the whole system. The demand for memory in various application scenarios shows a trend of diversification and complication, which brings challenges to the design of memory.

[0003] Traditional memory design methods often lack flexibility and efficiency. When designing a new memory, complex planning and design usually need to be carried out from scratch, which not only consumes a lot of time and effort, but also makes it difficult to fully utilize existing storage resources.

[0004] At the same time, due to the lack of effective management and utilization of storage unit attribute information, it is difficult to quickly and accurately evaluate the performance of different splitting schemes when designing memory splitting and combining. Engineers may need to simulate and test each splitting scheme in detail, which greatly increases the design cycle and cost. Moreover, due to the lack of comprehensive information support, the selected splitting scheme may not be optimal, resulting in the memory not being able to achieve the best state in terms of performance, resource utilization, etc. SUMMARY

[0005] The present application provides a database-based memory splitting and combining method, device, equipment and medium to solve the problem of obvious deficiencies in the efficiency, flexibility and resource utilization of the existing memory design method.

[0006] The present application provides a database-based memory splitting and combining method, comprising: obtaining a database of storage units; wherein the database of storage units includes attribute information of a plurality of storage units; generating a plurality of splitting schemes of a target memory based on the design requirements of the target memory; wherein each splitting scheme is composed of one or more storage units; using the attribute information in the database of storage units to evaluate the performance indicators of each splitting scheme; and determining the optimal splitting scheme as the target splitting scheme of the target memory according to the evaluation results of all splitting schemes.

[0007] According to the memory splitting and combination method based on the database provided in the application, before the database of the storage unit is acquired, the method further comprises: acquiring the storage unit to be stored in the database; generating a name suitable for the database for the storage unit to be stored in the database based on a preset naming rule; wherein the name is an index of the database of the storage unit; the preset naming rule comprises attribute information of different storage units and a comparison relationship between different names; and the storage unit to be stored in the database and the corresponding name are saved to the database of the storage unit.

[0008] According to the memory splitting and combination method based on the database provided in the application, the name comprises a plurality of character segments, and each character segment represents different attribute information; the attribute information comprises one or more of the size, the area, the working frequency, the signal output delay and the power consumption of the storage unit.

[0009] According to the memory splitting and combination method based on the database provided in the application, the performance index of each splitting scheme is evaluated by using the attribute information in the database of the storage unit, which comprises: if the storage unit required by the first splitting scheme does not exist in the database of the storage unit, the missing storage unit is recorded; the update of the database of the storage unit is triggered according to the missing storage unit, and after the missing storage unit is recorded, the performance index evaluation of the first splitting scheme is continued.

[0010] According to the memory splitting and combination method based on the database provided in the application, after the optimal splitting scheme is determined as the target splitting scheme of the target memory according to the evaluation results of all splitting schemes, the method further comprises: generating a corresponding hardware description language code based on the target splitting scheme.

[0011] According to the memory splitting and combination method based on the database provided in the application, after the optimal splitting scheme is determined as the target splitting scheme of the target memory according to the evaluation results of all splitting schemes, the method further comprises: generating a test platform code corresponding to the target memory; performing design verification based on the test platform code; and after the verification is passed, recording the target memory and the corresponding target splitting scheme in the information database of the memory.

[0012] The application further provides a memory splitting and combination device based on a database, which comprises: a database module configured to acquire a database of a storage unit; wherein the database of the storage unit comprises attribute information of a plurality of storage units; a splitting scheme module configured to generate a plurality of splitting schemes of a target memory based on design requirements of the target memory; wherein each splitting scheme is composed of one or more storage units; a performance analysis module configured to evaluate the performance index of each splitting scheme by using the attribute information in the database of the storage unit; and a target splitting scheme module configured to determine an optimal splitting scheme as a target splitting scheme of the target memory according to the evaluation results of all splitting schemes.

[0013] The application also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the database-based memory splitting and combination method according to any one of the above when executing the program.

[0014] The application also provides a non-transitory computer-readable storage medium, which stores a computer program, wherein the computer program is executable on a processor to implement the database-based memory splitting and combination method according to any one of the above.

[0015] The application also provides a computer program product, which comprises a computer program, wherein the computer program is executable on a processor to implement the database-based memory splitting and combination method according to any one of the above.

[0016] The application provides a database-based memory splitting and combination method, device, equipment and medium, the database-based memory splitting and combination method comprises: obtaining a database of a storage unit; wherein the database of the storage unit comprises attribute information of a plurality of storage units; based on a design requirement of a target memory, generating a plurality of splitting schemes of the target memory, each splitting scheme being composed of one or more storage units; using the attribute information in the database of the storage unit, evaluating a performance index of each splitting scheme; and determining an optimal splitting scheme as a target splitting scheme of the target memory according to the evaluation results of all splitting schemes. In this way, the application pre-establishes a database of storage units, and when designing a target memory, attribute information of storage units can be directly obtained from the database, a plurality of splitting schemes can be quickly generated and evaluated, and the optimization of resource utilization is realized, and the efficiency and flexibility of design are improved. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the application or the prior art, the following will briefly introduce the drawings needed in the embodiments or prior art description. Obviously, the drawings in the following description are some embodiments of the application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0018] Figure 1 is one of the flowcharts of the database-based memory splitting and combination method provided by the embodiments of the application.

[0019] Figure 2 is a schematic diagram of a memory design level provided by the embodiments of the application.

[0020] Figure 3 is another flowchart of the database-based memory splitting and combination method provided by the embodiments of the application.

[0021] Figure 4 is a structural schematic diagram of a database-based memory splitting and combining apparatus provided by an embodiment of the present application.

[0022] Figure 5 is a physical structure schematic diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0023] In order to make the objects, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be described clearly and completely below with reference to the drawings in the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0024] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine the different embodiments or examples described in the present specification and the features of the different embodiments or examples without contradiction.

[0025] In the design work of related memories, engineers can split the memory into smaller underlying storage units, such as static random access memory (SRAM), on the basis of ensuring that the design requirements such as timing are met. Then, the design of the memory is realized by reasonably combining these underlying storage units.

[0026] Generally, engineers will split the memory into underlying storage units according to their own experience, and then derive the overall information of the memory according to the related information of the underlying storage units. At the same time, considering factors such as power consumption and area, the appropriate splitting method is selected from a variety of splitting methods. However, with the increasing diversification of memory design requirements, if the parameters are manually input to the compiler and the memory is simply split by experience, the workload will be greatly increased.

[0027] To effectively improve work efficiency, an embodiment of the present application provides a memory splitting and combining method based on a database. The method can automatically complete the splitting operation of the memory and filter out the optimal splitting scheme.

[0028] Referring to Figure 1 , Figure 1 is one of the flowcharts of the memory splitting and combining method based on a database provided by the embodiment of the present application. In the embodiment, the memory splitting and combining method based on a database can include steps S110 to S140, and each step is specifically as follows:

[0029] S110: Obtain a database of storage units; wherein the database of storage units includes attribute information of a plurality of storage units.

[0030] The storage unit is a basic unit for storing data in the memory. The database of storage units is a system for centrally managing the information related to the storage units. It organizes and stores various attribute information of a plurality of storage units, facilitating subsequent query and use.

[0031] In the embodiment, the database of storage units can be established in advance, and the attribute information of the storage units can be recorded in the table of the database. Optionally, the attribute information can include the capacity, read-write speed, power consumption, cost, reliability, etc. of the storage unit.

[0032] By establishing the database of storage units, the embodiment can realize the centralized management and sharing of the attribute information of the storage units, avoiding the need to collect and organize the attribute information of the storage units again each time the target memory is designed, facilitating the quick acquisition of the required information in the subsequent steps, and improving the design efficiency.

[0033] S120: Generate a plurality of splitting schemes of the target memory based on the design requirements of the target memory; wherein each splitting scheme is composed of one or more storage units.

[0034] The target memory is a memory that needs to be constructed according to specific design requirements in the embodiment. The splitting scheme refers to the combination mode of splitting the target memory into one or more storage units according to a preset rule. Different splitting schemes use different numbers and types of storage units to meet the design requirements of the target memory.

[0035] Referring to Figure 2 , Figure 2 is a schematic diagram of the memory design hierarchy provided by the embodiment of the present application.

[0036] The architecture of the memory can be divided into three levels, which are the top layer (memblk), the splitting layer (memwrapper), and the storage unit (sram macro) as the bottom layer.

[0037] The top layer serves as the direct connection level between the memory and external ports, used for external connectivity. The bottom layer of memory cells consists of memory modules in Verilog format generated by the tool. Verilog is a hardware description language used for digital circuit design and verification. Due to the large number of pins in a memory cell, a split layer of the same size as the memory cell can be wrapped around the memory cell to ensure clear and accurate actual pin connections.

[0038] like Figure 2 As shown, the top layer has dimensions of 288×64, and it is divided into 6 storage units, each with the same size of 96×32. The dimensions of the split layers are consistent with the dimensions of the storage units, also 96×32.

[0039] Optionally, the design requirements of the target memory may include storage capacity, read / write speed, etc. In this embodiment, based on the design requirements of the target memory and combined with the attribute information in the database of the storage units, a variety of feasible partitioning schemes can be generated through algorithms.

[0040] This step provides multiple partitioning schemes for the target memory, increasing design flexibility. Different partitioning schemes can meet different design requirements, helping to discover more potential design solutions, improving resource utilization efficiency, and avoiding the limitations that a single scheme might bring.

[0041] S130: Utilize attribute information from the database of the storage unit to evaluate the performance metrics of each partitioning scheme.

[0042] Performance metrics are used to evaluate the merits of each partitioning scheme. Optionally, performance metrics may include storage capacity, read / write speed, power consumption, cost, reliability, etc. By evaluating these performance metrics, the performance of different partitioning schemes can be comprehensively considered.

[0043] In this step, attribute information from the storage unit's database can be used to evaluate the performance metrics of each partitioning scheme. The evaluation process can employ different evaluation methods depending on the specific performance metrics and design requirements. This embodiment, through quantitative evaluation of performance metrics, can objectively describe the performance of each partitioning scheme, thereby improving design efficiency.

[0044] S140: Based on the evaluation results of all partitioning schemes, determine the optimal partitioning scheme as the target partitioning scheme for the target memory.

[0045] In this step, according to the evaluation results of all the split schemes, various performance indicators and design requirements can be comprehensively considered to determine the optimal split scheme. Therefore, the embodiment can ensure that the design scheme of the target memory can realize the optimization of resource utilization on the premise of meeting the design requirements, and by selecting the optimal split scheme, the performance and efficiency of the target memory can be improved.

[0046] In the field of memory design, related methods often rely on repeated manual attempts and simulation tests, which not only prolong the design cycle, but also make it difficult to fully utilize the performance and resource advantages of the memory cells. In view of this situation, the embodiment provides a database-based memory split combination method, which can optimize the design process of the memory. The embodiment can quickly generate and evaluate multiple split schemes by establishing a database of memory cells, and finally obtain the optimal split scheme, thereby fully utilizing the performance and resources of the memory cells in the database and improving the efficiency and flexibility of the design.

[0047] In some embodiments, the step of obtaining the database of memory cells further comprises:

[0048] The memory cells to be stored are obtained, and a naming suitable for the database is generated for the memory cells to be stored based on a preset naming rule. The naming is an index of the database of memory cells. The preset naming rule includes attribute information of different memory cells and a correspondence relationship between different namings. The memory cells to be stored and the corresponding naming are saved to the database of memory cells.

[0049] The process of constructing the database is specifically described in this embodiment. First, the memory cells to be added to the database of memory cells need to be collected. These memory cells can come from different suppliers and different models, and have their own unique performance and attributes.

[0050] Optionally, the memory cell information to be stored can be obtained in various ways, such as extracting data from the product specification of a hardware device, or obtaining detailed technical parameters through an interface with the memory cell manufacturer.

[0051] In addition, the present application also sets a preset naming rule, which specifies how to generate a naming according to the attribute information of the memory cell. This naming will serve as an index of the memory cell in the database, and the purpose is to facilitate quick and accurate positioning and querying of a specific memory cell in the database.

[0052] Specifically, the preset naming rule includes attribute information of different memory cells and a correspondence relationship between different namings.

[0053] For example, assuming that the attributes of a storage unit include capacity, read-write speed, interface type, etc., the naming rule can stipulate that the capacity is represented by a specific letter, the read-write speed is represented by a numerical range, and the interface type is represented by another letter. If a storage unit has a capacity of 1 TB, a read-write speed of 500-600 MB / s, and an interface type of SATA, the generated name according to the rule can be “A5S”.

[0054] When the database needs to record a new storage unit, the database can generate a corresponding name according to the actual attribute information of the storage unit based on the correspondence relationship. After generating the name, the detailed attribute information of the storage unit and the corresponding name are stored in the database. In this way, the database establishes the association between the attributes of the storage unit and the name, facilitating subsequent queries and use.

[0055] In the above embodiment, the name is used as the index of the database. When a specific storage unit needs to be found, the database can quickly locate the corresponding record according to the unique name, reducing the matching time. In addition, the preset naming rule makes the naming of the storage unit consistent and standardized. Through the naming rule, part of the attribute information of the storage unit can be intuitively understood from the name, facilitating the classification and statistics of the storage unit.

[0056] In some embodiments, the name can include multiple character segments, each character segment representing different attribute information; the attribute information includes one or more of the size, area, operating frequency, signal output delay, and power consumption of the storage unit.

[0057] In the present embodiment, the name is composed of multiple character segments, each character segment corresponding to a specific attribute information. For example, the size, area, operating frequency, signal output delay, and power consumption of the storage unit can be represented by specific character segments. This design allows the key attributes of the storage unit to be quickly read from the name without the need to query the detailed records in the database.

[0058] The present embodiment can pre-set the character segment position and coding rule corresponding to each attribute information. For example, it is stipulated that the first character segment of the name represents the size, the second character segment represents the area, and the third character segment represents the operating frequency, etc.

[0059] For each attribute information, a corresponding coding method can be developed. For example, for the size attribute, the letter “S” can be used to represent small size, “M” to represent medium size, and “L” to represent large size; for the operating frequency, a numerical range can be used for coding, such as “1” for 1-100 MHz, “2” for 101-200 MHz, etc.

[0060] The above, the naming manner of specification makes the data in the database more orderly, facilitates the database administrator to manage and maintain. When the data is updated or cleaned, the storage units of different attributes can be more conveniently identified and processed, and the management efficiency of the database is improved.

[0061] Exemplarily, the preset naming rule is as follows:

[0062] [hdrf|uhdrf|hdsr|uhdsr][1|2|s|d]p(fis)[nw]x[nb]m[cm]k[bk](b)[p].

[0063] Wherein, [hdrf|uhdrf|hdsr|uhdsr] represents the information of the storage unit compiler, [1|2|s|d]p represents the interface information, [nw]x[nb] represents the number of words (Words) and bits (Bits) of the memory, m[cm] represents the number of selectors (mux), and k[bk] represents the number of memory banks (bank).

[0064] Specifically, [nw] represents the number of words of the memory, that is, the number of rows of the storage unit; [nb] represents the number of bits of each storage unit, that is, the number of columns of the storage unit. (b) represents whether to support the bit write mask (bit write mask) function, that is, whether the single bit of the storage unit can be written. [p] represents whether to use the pipeline mode (pipeline mode), that is, whether to have the interface with one beat delay output.

[0065] In summary, the preset naming rule can describe the type of storage unit, port characteristics, functional characteristics, storage capacity, multiplexing mode, memory bank division and working mode through a series of character and parameter combinations, which facilitates the compiler to design and configure the memory according to these information.

[0066] The information contained in the naming rule will be described in detail below through a specific example, which is: hdrf2pclb256x128m4k2bp. The specific information contained in the naming is as follows:

[0067] 1. Compiler type: "hdrf" indicates that the used compiler is a high-density RF (High-Density RF) compiler.

[0068] 2. Port configuration: "2p" represents that the memory adopts a dual-port design and has two independent access ports.

[0069] 3. Feature indication: "clb" is a combination of feature indicators, where "c" means that a center decode mode is adopted; "l" means that a low threshold voltage (LVT) peripheral circuit is used; and "b" means that a built-in self-test (BIST) function is enabled.

[0070] 4. Storage capacity: "256x128" describes the storage capacity of the memory, where "256" represents the depth of the memory; and "128" represents the bit width of the memory.

[0071] 5. Multiplexing and banking information: In "m4k2", "m4" means that the number of column multiplexers is 4, and "k2" means that the number of banks is 2.

[0072] 6. Special structure: "bp" means that the memory has two special structures, where "b" represents that a bit write mask structure is supported, and "p" represents that a pipeline mode is provided.

[0073] In other embodiments, other characters other than the above-mentioned characters can be used to represent other characteristic information of the storage units according to actual needs. Since the combinations of such optional characters and corresponding characteristic information are numerous, they are not listed and described one by one here.

[0074] In some embodiments, the step of evaluating the performance indicators of each splitting scheme by using the attribute information in the database of the storage units specifically includes:

[0075] If the storage unit required by the first splitting scheme does not exist in the database of the storage units, the storage unit is recorded as a missing storage unit; and the updating of the database of the storage units is triggered according to the missing storage unit, until the missing storage unit is recorded, and the evaluation of the performance indicators of the first splitting scheme is continued.

[0076] In the present embodiment, the first splitting scheme is defined as a scheme in which the required storage unit does not exist in the database of the storage units. When the performance indicators of the first splitting scheme are evaluated, the storage unit required by the scheme is compared with the existing data in the database of the storage units. If it is found that some storage units cannot be found in the database, these storage units are marked as missing storage units.

[0077] Specifically, when the storage unit corresponding to the scheme is queried in the database, all the storage units involved in the first splitting scheme are traversed, and the storage units are queried in the database according to the identification information (such as the name generated before) of the storage units. If the query result is empty, it is determined that the storage unit is missing.

[0078] When missing storage units are found, an update process of the storage unit database can be automatically triggered to record the attribute information of the missing storage units in the database, so as to ensure that subsequent evaluation work can be carried out smoothly.

[0079] Exemplarily, an update prompt can be sent to inform the database administrator or relevant personnel to collect the attribute information of the missing storage units. After the administrator or the relevant personnel collect the relevant attribute information, the attribute information of the missing storage units is added to the database according to the recording rules of the database.

[0080] After the missing storage units are successfully recorded in the database, the performance indicators of the first splitting scheme are evaluated, the attribute information of all storage units required by the first splitting scheme is reacquired, including the newly recorded storage units. According to the preset evaluation method and algorithm, the performance indicators of the first splitting scheme are calculated and evaluated in combination with the attribute information. The evaluation process comprehensively considers the attribute information of all storage units in the splitting scheme to obtain accurate performance indicator results.

[0081] It should be noted that the storage unit database is a collection of massive information, but it is difficult to comprehensively and synchronously record the information of each storage unit. Moreover, new storage units are constantly emerging, and the database often fails to record all the information of the new storage units. Based on this, the embodiment proposes an effective solution: on the one hand, the missing storage unit information is accurately identified and supplemented in time, so that the attributes of all related storage units can be comprehensively considered when evaluating the performance indicators of the splitting scheme. On the other hand, the database update mechanism is triggered to continuously record the information of new storage units in the database, so that the content of the database is more complete. This not only helps to evaluate the current splitting scheme, but also provides more comprehensive data support for the evaluation of future other memory designs and splitting schemes.

[0082] The above, the method of the embodiment of the application has the ability to automatically process the missing storage unit problem in the splitting scheme, enhances the adaptability of the method, effectively avoids the interruption of the design process caused by the missing storage unit information, and can quickly update the database and continue the evaluation work after the missing information is found, so that the entire design process is more smooth, thereby shortening the design cycle and significantly improving the design efficiency.

[0083] In some embodiments, after determining the optimal splitting scheme as the target splitting scheme of the target memory according to the evaluation results of all splitting schemes, the steps further include:

[0084] Based on the target splitting scheme, a corresponding hardware description language code is generated.

[0085] In the embodiment, after the target splitting scheme is obtained, a corresponding hardware description language code can be further generated for the target splitting scheme.

[0086] The target splitting scheme describes the splitting structure of the target memory, the connection relationship between the parts, the data flow mode and other information. In the embodiment, the abstract scheme content can be accurately expressed in the form of code by generating the hardware description language code.

[0087] The hardware description language code can include Verilog. Verilog is a hardware description language for digital circuit design and verification.

[0088] The embodiment converts the target splitting scheme into the hardware description language code, which provides a basis for subsequent hardware implementation. The code can be processed by a hardware synthesis tool to generate actual hardware circuits.

[0089] In some embodiments, after the optimal splitting scheme is determined as the target splitting scheme of the target memory according to the evaluation results of all splitting schemes, the steps further include:

[0090] A test platform code corresponding to the target memory is generated, design verification is performed based on the test platform code, and after the verification passes, the target memory and the corresponding target splitting scheme are recorded in a memory information library.

[0091] The test platform code is used to simulate various working scenarios of the target memory in actual applications, and to comprehensively test the functions and performance of the target memory under the target splitting scheme. The test platform code can be written according to the interface specification, functional requirements and operation process of the target memory.

[0092] Specifically, the design code of the target memory is jointly simulated with the test platform code. During the simulation, the test platform code inputs excitation signals to the target memory according to the preset test cases, and monitors the output signals of the target memory. By comparing the expected output and the actual output, it is determined whether the target memory meets the design requirements.

[0093] Optionally, the verification content can include functional verification and performance verification. Functional verification is used to check whether the target memory can correctly perform various operations, such as read-write operations, data storage and recovery, etc. Performance verification is used to focus on whether the performance indicators of the target memory, such as read-write speed, storage capacity, power consumption, etc., meet the design requirements.

[0094] In the embodiment, the memory information library is a database that centrally manages and stores various memory design information. Recording the verified target memory and its corresponding target splitting scheme in the information library can provide a reference and reuse for subsequent design work.

[0095] Optionally, the input content can include detailed design information of the target memory, specific parameters of the target splitting scheme, test results, etc.

[0096] In the above, the embodiment can discover and correct errors and defects in the design of the target memory in the design stage in time by generating the test platform code and performing the design verification, avoid problems in the actual manufacturing or application process, and thus improve the reliability and stability of the design. In addition, the target memory and the target splitting scheme that pass the verification are input into the information library, so that the sharing and reuse of the design information can be realized. When a new memory is designed, the designer can refer to the existing design in the information library, reduce repetitive work, and shorten the design cycle.

[0097] Please refer to Figure 3 , Figure 3 is a flowchart of a database-based memory splitting and combining method provided by the embodiment of the application.

[0098] The embodiment proposes a working platform that can automatically split the memory and select the optimal splitting method according to preset conditions. The platform has the following characteristics:

[0099] A bottom layer static random access memory (SRAM) database is constructed; the platform has wide adaptability and can be compatible with memory compilers of any manufacturer; a naming rule based on the bottom layer SRAM is formulated, and the bottom layer SRAM is screened according to the rule. The main working process includes:

[0100] 1. Preparation stage: Establish a database of memory cells.

[0101] Through the user guide provided by the electronic design automation (EDA) tool manufacturer, the main types of SRAM, the bit width range and depth range of each type of SRAM, and other key information can be obtained. Based on these different characteristics, a preset naming rule is constructed. According to the preset naming rule constructed above, a name list of SRAM that can be generated by the current EDA tool can be generated.

[0102] Combined with the name list and the SRAM attributes corresponding to each name, all SRAMs can be generated by using the EDA tool. The key information of these SRAMs is extracted through a script, including length, width, area, clock period, clock-to-output delay (clk2q, signal output delay), and power consumption. Finally, all the extracted information is sorted according to the name list of the SRAM to construct the SRAM information database.

[0103] 2. Generation stage: Selection of memory cells.

[0104] First, the design requirements of the target memory to be generated are determined, such as bit width, depth, working frequency, bitmask, and the like. According to the memory information and the characteristics followed in the SRAM database establishment process, a target memory information table is generated.

[0105] Then, by using a memory splitting and selection algorithm, all possible splitting modes of the target memory can be comprehensively traversed, and multiple splitting schemes can be generated. Considering factors such as frequency, area, and power consumption, the most suitable memory splitting mode and the corresponding underlying SRAM information are selected.

[0106] In addition, in determining the target splitting scheme, the corresponding register transfer level (RTL) code can be generated according to the splitting information, and the underlying SRAM after splitting can be generated. At this point, the memory information generation work is completed.

[0107] It should be noted that if the database has not been completed, the work platform can return the underlying SRAM list under all splitting modes, and after the database is supplemented based on the list, the splitting evaluation operation is performed.

[0108] 3. Verification phase: data verification of the storage unit.

[0109] After determining the target splitting scheme, the testbench code corresponding to the current memory can also be automatically generated for design verification. Specifically, the file list of the memory and the underlying SRAM can be automatically generated, such as the control file (ctl file), the layout data file (gds file), the layout exchange format file (lef file), and the like, and the file quantity and data format are automatically checked.

[0110] After verification, the corresponding data can be transmitted to the memory information library; if the verification fails, the problems existing in the data can be checked, and a new target splitting scheme can be generated.

[0111] In some embodiments, the work platform also has corresponding functional modules to perform different functions, as follows:

[0112] In the SRAM database generation, GmRamList generates a list of SRAM names in the database, GmRamView generates corresponding SRAM data, and GmRelTcc extracts and stores the data to the database.

[0113] In the SRAM selection, GmGenBlk completes splitting and selection according to the memory information table, and returns the SRAM list for completion when the database information is incomplete.

[0114] In the SRAM data verification link, GmSimBlk generates test platform code and performs functional simulation, and GmRelBlk checks the number and format of files and uploads data to the memory information base.

[0115] In some embodiments, the design requirements of the target memory can be presented in the form of a table, as shown in the following example:

[0116]

[0117] wherein NA represents not applicable, No represents non-existent, and L2 cache represents a second-level cache.

[0118] In some embodiments, the final target splitting scheme can be presented in the form of a table, as shown in the following example:

[0119]

[0120] In the foregoing manner, using the working platform, the SRAM database can be constructed in advance, and when generating SRAM, the advantages and disadvantages of different splitting schemes can be directly compared based on the data in the database, without the need to regenerate the data of SRAM under all splitting schemes, thereby effectively saving the time consumed in the Memory design process. At the same time, the working platform supports supplementing the SRAM database in a feedback manner, and also realizes automatic verification and data checking of Memory design. In addition, the working platform has good compatibility and can adapt to EDA tools of different manufacturers, promoting the flow and standardization of Memory design implementation.

[0121] The application also provides a database-based memory splitting and combining device. The database-based memory splitting and combining device provided by the application is described below, and the database-based memory splitting and combining device described below can be mutually referred to the database-based memory splitting and combining method described above.

[0122] Please refer to Figure 4 , Figure 4 is a structural schematic diagram of the database-based memory splitting and combining device provided by the embodiments of the application. In the embodiment, the database-based memory splitting and combining device can include a database module 410, a splitting scheme module 420, a performance analysis module 430, and a target splitting scheme module 440.

[0123] The database module 410 is configured to obtain a database of storage units, wherein the database of storage units includes attribute information of a plurality of storage units.

[0124] The splitting scheme module 420 is configured to generate a plurality of splitting schemes of a target memory based on design requirements of the target memory, wherein each splitting scheme is composed of one or more storage units.

[0125] The performance analysis module 430 is configured to evaluate the performance indicators of each splitting scheme by using the attribute information in the database of the storage unit.

[0126] The target splitting scheme module 440 is configured to determine an optimal splitting scheme as the target splitting scheme of the target memory according to the evaluation results of all the splitting schemes.

[0127] In some embodiments, the database module 410 is further configured to, before obtaining the database of the storage unit, specifically:

[0128] obtain a storage unit to be stored; generate a name suitable for the database for the storage unit to be stored based on a preset naming rule; the name is an index of the database of the storage unit; the preset naming rule includes a comparison relationship between attribute information of different storage units and different names; and save the storage unit to be stored and the corresponding name to the database of the storage unit.

[0129] In some embodiments, the name includes a plurality of character segments, and each character segment represents different attribute information; the attribute information includes one or more of the size, area, working frequency, signal output delay, and power consumption of the storage unit.

[0130] In some embodiments, the performance analysis module 430 is specifically configured to:

[0131] If the storage unit required by the first splitting scheme does not exist in the database of the storage unit, record it as a missing storage unit; trigger the update of the database of the storage unit according to the missing storage unit, and continue to evaluate the performance indicators of the first splitting scheme until the missing storage unit is recorded.

[0132] In some embodiments, after the target splitting scheme module 440 determines the optimal splitting scheme as the target splitting scheme of the target memory according to the evaluation results of all the splitting schemes, the target splitting scheme module 440 is further configured to:

[0133] generate a corresponding hardware description language code based on the target splitting scheme.

[0134] In some embodiments, the database-based memory splitting and combination apparatus further includes a test verification module, and the test verification module is specifically configured to:

[0135] generate a test platform code corresponding to the target memory; perform design verification based on the test platform code; and after the verification is passed, record the target memory and the corresponding target splitting scheme in the information base of the memory.

[0136] In another aspect, the embodiments of the present application also provide an electronic device, please refer to Figure 5 , Figure 5is a schematic diagram of an entity structure of an electronic device provided by an embodiment of the present application, as shown in the figure, the electronic device can include a memory 520, a processor 510, and a computer program stored on the memory 520 and executable on the processor 510. When the processor 510 executes the program, it can implement a database-based memory splitting and combination method, which can include: Figure 5

[0137] obtaining a database of storage units; wherein the database of storage units includes attribute information of a plurality of storage units; generating a plurality of splitting schemes of a target memory based on design requirements of the target memory; wherein each splitting scheme is composed of one or more storage units; evaluating the performance indicators of each splitting scheme using the attribute information in the database of storage units; and determining an optimal splitting scheme as the target splitting scheme of the target memory according to the evaluation results of all splitting schemes.

[0138] Optionally, the electronic device can further include a communication bus 530 and a communications interface 540, wherein the processor 510, the communications interface 540, and the memory 520 can complete mutual communication through the communication bus 530. The processor 510 can invoke the computer program in the memory 520 to execute the database-based memory splitting and combination method provided by the above-mentioned methods.

[0139] In addition, the logical instructions in the memory 520 described above can be implemented in the form of a software functional unit and sold or used as an independent product, which can be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the parts that contribute to the prior art or parts of the technical solutions can be embodied in the form of a software product, which is stored in a storage medium and includes a number of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in the embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.

[0140] On the other hand, the present application also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium, and the computer program can be executed by a processor to enable a computer to execute the database-based memory splitting and combination method provided by the above-mentioned methods, the steps and principles of which have been described in detail in the above-mentioned methods and will not be repeated here.​

[0141] In yet another aspect, the present application also provides a non-transitory computer readable storage medium having stored thereon a computer program, which, when executed by a processor, implements the database-based memory split combination method provided by the above method, the steps and principles of which have been described in detail in the above method and will not be repeated here.

[0142] The non-transitory computer readable storage medium can be any available medium or data storage device that the processor can access, including but not limited to a magnetic memory (such as a floppy disk, a hard disk, a magnetic tape, a magneto-optical disk (MO), etc.), an optical memory (such as a CD, a DVD, a BD, a HVD, etc.), and a semiconductor memory (such as a ROM, an EPROM, an EEPROM, a non-volatile memory (NAND FLASH), a solid state disk (SSD)), etc.

[0143] The device embodiments described above are only schematic, wherein the units illustrated as separate components can or can not be physically separate, and the components illustrated as units can or can not be physical units, i.e., can be located in one place or distributed on a plurality of network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the present embodiment. Those skilled in the art can understand and implement without creative labor.

[0144] From the above description of the embodiments, those skilled in the art can clearly understand that the embodiments can be realized by means of software plus necessary universal hardware platforms, and of course can also be realized by hardware. Based on such understanding, the above technical solutions, essentially or in other words, the part that contributes to the prior art can be embodied in the form of a software product, which can be stored in a computer readable storage medium, such as a ROM / RAM, a magnetic disk, an optical disk, etc., and includes a plurality of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute the methods described in each embodiment or some parts of the embodiments.

[0145] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to some technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A database-based method for splitting and combining memory, characterized in that, include: Obtain the database of the storage unit; wherein the database of the storage unit includes attribute information of multiple storage units; Based on the design requirements of the target memory, multiple partitioning schemes for the target memory are generated; each partitioning scheme consists of one or more memory cells. The performance metrics of each partitioning scheme are evaluated using the attribute information in the database of the storage unit. Based on the evaluation results of all partitioning schemes, the optimal partitioning scheme is determined as the target partitioning scheme for the target memory; The evaluation of performance metrics for each partitioning scheme using attribute information from the database of the storage unit includes: When evaluating the performance of the first partitioning scheme, all storage units involved in the first partitioning scheme are traversed, and the database of the storage unit is queried according to the identification information of the storage unit; if the query result is empty, the storage unit is determined to be missing and recorded as a missing storage unit. The database of the missing storage unit is automatically updated based on the missing storage unit, and an update prompt is issued so that the attribute information of the missing storage unit is entered into the database of the storage unit. After the missing storage unit is successfully entered into the database of the storage unit, the attribute information of all storage units required by the first splitting scheme is retrieved again, and the performance indicators of the first splitting scheme are calculated and evaluated in combination with the attribute information. Also includes: Set a preset naming rule; wherein the preset naming rule is used to specify the naming based on the attribute information of the storage unit.

2. The database-based memory splitting and combining method according to claim 1, characterized in that, Before obtaining the database of the storage unit, the method further includes: Obtain the storage unit to be stored; Based on preset naming rules, a name suitable for the database is generated for the storage unit to be stored; wherein, the name is the database index of the storage unit; the preset naming rules include attribute information of different storage units and the correspondence between different names; The storage unit to be added to the database and its corresponding name are saved to the database of the storage unit.

3. The database-based memory splitting and combining method according to claim 2, characterized in that, The naming includes multiple character segments, each character segment representing different attribute information; The attribute information includes one or more of the following: the size, area, operating frequency, signal output delay, and power consumption of the storage unit.

4. The database-based memory splitting and combining method according to any one of claims 1 to 3, characterized in that, After determining the optimal partitioning scheme as the target partitioning scheme for the target memory based on the evaluation results of all partitioning schemes, the method further includes: Based on the target decomposition scheme, the corresponding hardware description language code is generated.

5. The database-based memory splitting and combining method according to any one of claims 1 to 3, characterized in that, After determining the optimal partitioning scheme as the target partitioning scheme for the target memory based on the evaluation results of all partitioning schemes, the method further includes: Generate test platform code corresponding to the target memory; Design verification was performed based on the test platform code. After successful verification, the target memory and the corresponding target splitting scheme are entered into the memory's information database.

6. A database-based memory splitting and combining device, characterized in that, Using the database-based memory splitting and combining method as described in any one of claims 1 to 5, the database-based memory splitting and combining apparatus includes: A database module is used to obtain the database of a storage unit; wherein the database of the storage unit includes attribute information of multiple storage units; The partitioning scheme module is used to generate multiple partitioning schemes for the target memory based on the design requirements of the target memory; wherein each partitioning scheme consists of one or more memory cells; The performance analysis module is used to evaluate the performance indicators of each partitioning scheme by utilizing the attribute information in the database of the storage unit. The target splitting scheme module is used to determine the optimal splitting scheme as the target splitting scheme for the target memory based on the evaluation results of all splitting schemes.

7. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the database-based memory splitting and combining method as described in any one of claims 1 to 5.

8. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the database-based memory splitting and combining method as described in any one of claims 1 to 5.

9. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the database-based memory splitting and combining method as described in any one of claims 1 to 5.

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