A current domain neuron circuit

Abstract

This invention belongs to the field of integrated circuits, specifically relating to a current-domain neuron circuit. This invention implements a current-domain neuron circuit by paralleling n multi-bit multiplication units and introducing an activation function circuit. Compared to other analog-domain multiply-accumulate operations, current-domain multiply-accumulate operations have the following advantages: high parallelism and scalability (tens, hundreds, or even thousands of current outputs can be easily connected to the same summing node to achieve large-scale parallel multiply-accumulate operations); low power consumption (transistors mainly operate in the subthreshold region, with small drive current and adaptability to lower power supply voltages); and, compared to purely digital schemes, current-domain multiply-accumulate operations have higher energy efficiency in low-precision application scenarios. The current-domain neuron circuit proposed in this invention is particularly suitable for edge computing and IoT devices that require high energy efficiency, and can be applied in fields such as intelligent image sensing and machine vision.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuits, and specifically relates to a current-domain neuron circuit. Background Technology

[0002] With the continuous advancement of artificial intelligence (AI) technology, the energy efficiency requirements of edge AI devices are increasing. In application scenarios such as edge computing where resources and energy budgets are limited, reducing latency, minimizing power consumption, and reducing chip area have become indispensable design goals. At the same time, with the widespread application of deep learning methods, the demand for computing power continues to grow. General-purpose processors, due to the redundant design introduced to maintain programming flexibility and versatility, struggle to provide satisfactory energy efficiency and performance in such scenarios.

[0003] Since the neural networks involved in deep learning methods are composed of interconnected neurons, and the core operation of artificial intelligence accelerators is to implement the functions of neurons, accelerators focusing on the computational characteristics of neural networks have developed rapidly in recent years. These artificial intelligence accelerators are specifically optimized for parallel computing and low-precision linear algebra operations, significantly improving computational throughput and energy efficiency at the cost of some architectural flexibility.

[0004] Early AI accelerators primarily relied on digital signals to implement their functions. In recent years, in addition to purely digital accelerators, the analog-mixed-signal (AMS) approach has received increasing attention. Although this method faces challenges such as noise and device mismatch, it has shown significant potential in accelerating deep neural networks (DNNs). This stems from the unique properties of DNNs compared to general computing: on the one hand, DNNs rely on only a limited number of computational operations; on the other hand, they have a high tolerance for computational accuracy. These characteristics provide ideal implementation conditions for analog-mixed-signal circuits: lower operational complexity and accuracy requirements allow them to better adapt to the inherent process variations in analog circuits. Therefore, the AMS approach excels in energy efficiency, especially at lower precision levels, where its energy efficiency can be significantly higher than that of purely digital solutions.

[0005] In AI accelerators, over 90% of deep learning neural network (DNN) inference computation consists of multiply-accumulate (MAC) operations within neurons, with a single network inference potentially involving billions of MAC operations. Given this dominance, designing energy-efficient MAC units has become a key element in advanced AI accelerator architectures. Meanwhile, activation functions, as an indispensable processing step after the MAC output in neurons, significantly impact the expressive power and performance of neural networks. Activation functions introduce nonlinearity into the network, enabling it to learn complex patterns and features, thus enhancing the model's expressive power. However, different activation functions (such as ReLU, Sigmoid, or Tanh) introduce varying computational overhead and energy efficiency impacts in hardware implementation. Therefore, while optimizing MAC units, it is often necessary to incorporate high-efficiency integration schemes of activation functions into the overall design considerations to construct a complete neuron structure, further improving the accelerator's energy efficiency while ensuring model accuracy. Summary of the Invention

[0006] To address the problems or shortcomings of the aforementioned purely digital solutions and to solve the issue of low energy efficiency in existing neuron circuits, this invention provides a current-domain neuron circuit.

[0007] The technical solution provided by this invention is as follows:

[0008] A current-domain neuron circuit includes a current-domain multi-bit multiplication unit circuit and an activation function circuit.

[0009] The current-domain multi-bit multiplication unit circuit has n units, n≥1. Its function is to convert the unsigned multi-bit digital input feature value signal and the unsigned multi-bit digital weight signal into analog current signals, multiply the current values ​​of the two analog current signals and divide by the scaling factor I. REF Then, it is output in the form of analog current.

[0010] Scale factor I REF It also serves as the least significant bit (LSB) in the conversion of multi-bit digital input feature signals and multi-bit digital weight signals into analog current signals; the current value of the multi-bit digital input feature signal converted into an analog current signal is I. X The current value of a multi-bit digital weighted signal converted into an analog current signal is I. W The output current of the multi-bit multiplication unit circuit is I CELL This indicates that its value is:

[0011] .

[0012] n current-domain multi-bit multiplication units are connected in parallel to form a current-domain multi-bit multiply-accumulate circuit, which accumulates the output currents of the n parallel current-domain multi-bit multiplication units.

[0013] The activation function circuit compares the output current of the current-domain multi-bit multiply-accumulate circuit with a set bias current: if the bias current is greater than the output current of the current-domain multi-bit multiply-accumulate circuit, the final output current of the neuron circuit is set to zero; otherwise, the final output current of the neuron circuit is the sum of the output current of the current-domain multi-bit multiply-accumulate circuit and the negative of the set bias current. This activation function circuit functions identically to the ReLU activation function.

[0014] The activation function circuit sets the two bias currents I. B and I TH I after subtracting the two bias currents TH - I B with I CELL By comparing the magnitudes, the output current I of the activation function circuit is obtained. OUT Its value is:

[0015] .

[0016] The current-domain multi-bit multiplication unit provided by this invention, by connecting several current-domain multi-bit multiplication units in parallel, can obtain the multiplied and accumulated current value, in I... SUM This indicates that the current value is activated by the function circuit and then compared with the current value I. TH - I B By comparison, the complete neuron function can be realized. Assuming the number of multiplication units is n, and i takes values ​​from n, the final output current value I is obtained. OUTF It can be represented as:

[0017] .

[0018] Furthermore, the aforementioned current-domain neuron circuits are applied to energy-efficient edge computing and IoT devices.

[0019] In summary, this invention realizes a current-domain neuron circuit by paralleling n multi-bit multiplication units and introducing an activation function circuit. Compared to other analog-domain multiply-accumulate operations, current-domain multiply-accumulate operations offer advantages such as: high parallelism and scalability (tens, hundreds, or even thousands of current outputs can be easily connected to the same summing node, achieving large-scale parallel multiply-accumulate operations); low power consumption (transistors mainly operate in the subthreshold region, resulting in small drive current and adaptability to lower power supply voltages); and higher energy efficiency in low-precision applications compared to purely digital schemes. Therefore, the current-domain neuron circuit proposed in this invention has promising applications in edge computing and IoT devices that demand high energy efficiency, especially in fields such as intelligent image sensing and machine vision. Attached Figure Description

[0020] Picture 1 The circuit diagram of the current-domain multi-bit multiplication unit is shown in the embodiment.

[0021] Picture 2 The activation function circuit diagram is shown in the example.

[0022] Picture 3 The circuit diagram of the current domain neuron is shown in the embodiment.

[0023] Picture 4 This is a comparison chart of the output current of the activation function circuit and the ReLU activation function curve in the embodiment. Detailed Implementation

[0024] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0025] A current-domain neuron circuit includes a current-domain multi-bit multiplication unit circuit and an activation function circuit.

[0026] The current-domain multi-bit multiplication unit circuit is used to perform the conversion of unsigned multi-bit digital input feature value signals and unsigned multi-bit digital weight signals into analog current signals, and to perform multiplication operations between two analog current signals.

[0027] In this embodiment, taking an example where both the input feature value and the weight signal are 2 bits, refer to... Picture 1 The specific circuit composition consists of one current source I0, six NMOS transistors N0-N5, seven PMOS transistors P0-P6, and four switches S0-S3. The circuit connection method and specific functions are as follows:

[0028] The positive terminal of current source I0 is connected to the power supply potential VDD, and the negative terminal is connected to the gate and drain of transistor N0. N0 forms five current mirrors with N1 to N5 respectively, copying the current value of I0 to the corresponding transistors (N1 to N5) according to the width-to-length ratio between N1 to N5 and N0. Among them, the source of N0 is grounded to the potential GND, and its gate is connected to the gate of N3 and one end of switches S0 to S4; switches S0 and S1 are controlled by the 2-bit digital input feature value signal X<1:0> respectively, with one end connected to the gate of N3, and the other end of switches S0 and S1 are connected to the gates of N1 and N2 respectively; switches S2 and S3 are controlled by the 2-bit digital weight signal W<1:0> respectively, with one end connected to the gate of N3, and the other end of switches S2 and S3 are connected to the gates of N4 and N5 respectively; the sources of N1 to N5 are all grounded to the potential GND, where the width-to-length ratio of N2, N3, and N5 is the same as that of N0, and the width-to-length ratio of N1 and N4 is twice that of N0.

[0029] The specific function of this circuit is to convert the 2-bit digital input feature value signal X<1:0> into an analog current signal I. X The 2-bit digital weighted signal W<1:0> is converted into an analog current signal I. W Among them, the current value I0 of the current source is... REF As the least significant bit (LSB) in the conversion from digital signal to analog current signal, therefore I X and I W Four current values ​​are available: 3I REF 2I REF I REF 0.

[0030] P1 through P4 all operate in the subthreshold region, and their width-to-length ratios are the same. Specifically, the source of P1 is connected to the power supply potential VDD, and its gate and drain are shorted and connected to the drains of N1 and N2. The gate of P2 is connected to the gate of P1, its drain to the drain of N3, and its source to the drain of P0 and the source of P3. The gate and drain of P3 are shorted and connected to the drains of N4 and N5. The gate of P4 is connected to the gate of P3, its source is connected to the power supply potential VDD, and its drain outputs the output current I of the multi-bit multiplication unit circuit. CELL The drain of P5 is connected to the gates of P3 and P4, and the source is connected to the drain of P6. The source of P6 is connected to the power supply potential VDD. The gates of P5 and P6 are connected to the digital input characteristic value signal X<1:0>, which determines whether the gate of P4 is pulled up to the power supply potential VDD.

[0031] The specific function of this part of the circuit is to utilize the current-voltage characteristics of the subthreshold region and the circuit connection structure to... X and I W Multiply and divide by the scaling factor I REF The output is the calculated current. Specifically, a MOSFET operating in the subthreshold region has the following current-voltage relationship:

[0032]

[0033] Among them, V gs It is the gate-source voltage, V bs It is the body source voltage, V ds It is the drain-source voltage, I d0 It is the leakage current under zero bias. It is thermal voltage. It is the subthreshold slope factor. In this invention, the PMOS body source is shorted, V bs =0, and V ds Much greater than V T Therefore, the current-voltage relationship of transistors P1 to P4 can be simplified as follows:

[0034]

[0035] Therefore, the gate-source voltage V gs It can be represented as: .

[0036] From the circuit connection relationship of transistors P1 to P4, we can obtain: .

[0037] In this invention, P1 to P4 have the same width-to-length ratio, and can be considered as I d0 And since k is the same, based on the subthreshold current-voltage characteristics of P1~P4 and the circuit connection structure, we can obtain:

[0038]

[0039] And because , , , The current of P4 transistor can be obtained:

[0040]

[0041] from As can be seen from the expression, the current-domain multi-bit multiplication unit circuit realizes the current-domain multiplication operation between the input feature value and the weight signal, and divides by the scaling factor I. REF It should be noted that when X<1:0> is 00, i.e., I... X When the current is 0 nA, transistor P2 is turned off, and I d2 When the current is 0 nA, the current of P4 no longer follows the above formula. Therefore, P6 and P7 need to be added to ensure that when X<1:0> is 00, the gate of P4 is pulled up to the power supply potential VDD, thereby enabling the output current of P4 to I. CELL The value is 0 nA.

[0042] The activation function circuit is used to implement the ReLU activation function. This circuit compares the current value I... TH - I B with I CELL The value is used to obtain the output current I of the multiplication unit. OUT Its value can be expressed as:

[0043]

[0044] Reference Picture 2 The specific circuit composition of this embodiment consists of two current sources I1 and I2, six NMOS transistors N6 to N11, five PMOS transistors P7 to P11, and one buffer B0. The circuit connection method and specific functions are as follows:

[0045] Current source I1 has its positive terminal connected to the power supply potential VDD and its negative terminal connected to the source of transistor P10. Current source I2 has its positive terminal connected to the drain of transistor P7 and its negative terminal connected to ground potential GND. P7 and P8, P7 and P9, N6 and N7, and N8 and N9 form four sets of current mirror circuits. Specifically, the gates of P7, P8, and P9 are connected, and their sources are all connected to the power supply potential VDD. The drain of P8 is connected to the drain of N6, and the drain of P9 is connected to the drain of N8. The gates of N6 and N7 are connected, and the gates of N8 and N9 are connected. Their sources are all connected to ground potential GND. The drain of N6 is connected to the drain of N11, the drain of N7 is connected to the drain of P10, and the drain of N9 is connected to the drain of P11. P11, N10, and N11 are switching transistors controlled by an externally input digital signal RST, and the gates of P11, N10, and N11 are all connected to the RST signal. The source of P11 is connected to the negative terminal of current source I1, and its drain is connected to the drain of N9; the source of N10 is grounded to GND, and its drain is connected to the output terminal of buffer B0; the source of N11 is connected to the input terminal of buffer B0, and its drain is connected to the drains of N6 and P8. Buffer B0 enhances the driving capability of P10, and its output is connected to the gate of P10. The source of P10 is connected to the output current I of the n current-domain multi-bit multiplication unit circuit. CELL (i.e., the drain of the current domain multi-bit multiplication unit circuit P4), the drain is connected to the drain of N7.

[0046] The specific function of the circuit is as follows:

[0047] When signal RST is high, P11 is off, and N10 and N11 are on, at which point P10 is on. P7 and P8, and N6 and N7 convert the current source I2 to the value I. TH and current value I CELL With current source I1 current value I B The sum is copied onto the same branch.

[0048] When RST changes from high to low, P11 is turned on, and N10 and N11 are turned off; if When the output of buffer B0 is high, P10 is turned off. At this time, the activation function circuit outputs current I. OUT =0. If The output of buffer B0 is low, and P10 remains on. At this time, the activation function circuit outputs current. Combining the two cases where RST is low, the output current of the activation function circuit can be expressed as:

[0049]

[0050] This expression is the same as the ReLU activation function expression, and it implements the activation function functionality on the circuit.

[0051] The overall current-domain neuron circuit diagram in this embodiment combines n current-domain multi-bit multiplication units and activation function circuits. For example... Picture 3 As shown, by connecting the output current branches of n current-domain multi-bit multiplication unit circuits in parallel, n analog input characteristic value current signals can be processed. and n analog weighted current signals The corresponding multiplication and summation are performed to obtain the current after multiplication and summation:

[0052]

[0053] This current value is processed by the activation function circuit and the current value By comparison, the multiplication unit's output current can be accumulated, and the ReLU activation function can be implemented, thus constructing a complete neuron circuit in the current domain. The final output current value... It can be represented as:

[0054]

[0055] To verify the functionality of the current-domain multi-bit multiplication unit and activation function circuit provided in this invention, the circuit was simulated and evaluated using Virtuoso simulation software. The simulation environment was: 180nm CMOS process, power supply voltage 1.8V.

[0056] Simulations of the current-domain multi-bit multiplication unit were performed to evaluate whether the circuit achieved its multiplication function by comparing the actual and theoretical calculation results. The simulation process combined 16 different combinations of unsigned 2-bit digital input characteristic value signals X<1:0>, and set... (1LSB) The functionality of the current-domain multi-bit multiplication unit circuit was verified, and the simulation results are shown in Table 1:

[0057] Table 1: Operation results of the current-domain multi-bit multiplication unit circuit

[0058] X<1:0> W<1:0> ideal result Actual results of the law 00 00 0 nA 0.022 nA 00 01 0 nA 0.022 nA 00 10 0 nA 0.022 nA 00 11 0 nA 0.022 nA 01 00 0 nA 0.667 nA 01 01 50 nA 57.53 nA 01 10 100 nA 113.5 nA 01 11 150 nA 169.1 nA 10 00 0 nA 1.402 nA 10 01 100 nA 110.8 nA 10 10 200 nA 212.8 nA 10 11 300 nA 309.5 nA 11 00 0 nA 2.244 nA 11 01 150 nA 164.3 nA 11 10 300 nA 307.9 nA 11 11 450 nA 440.6 nA

[0059] Comparing the ideal and actual multiplication results in Table 1, it can be found that under 16 combinations, the difference between the two does not exceed 20 nA, which is less than... (50 nA) will not have a significant impact on subsequent data processing (such as the conversion of analog current signals to digital signals).

[0060] The simulation of the activation function circuit evaluates whether the circuit achieves its activation function functionality by testing whether the actual output current matches the ReLU activation function expression. The simulation sets X<1:0> to 01 and W<1:0> to 11. Set to 50nA Set to 200nA, scan in 5nA steps within the range of 0nA to 450nA. Values ​​are determined by plotting the different values ​​when the RST signal is low. Output current at the specified value The current value curve is obtained and compared with the ReLU function curve to verify the correctness of the activation function circuit. The simulation results are as follows: Picture 4 As shown in the figure, the output current of the activation function circuit basically matches the ReLU function curve, indicating that the circuit function is correct.

Claims

1. A current-domain neuron circuit, characterized in that: Includes current-domain multi-bit multiplication unit circuit and activation function circuit; The current domain multi-bit multiplication unit circuit has n, n≥1, which is to convert the unsigned multi-bit digital input characteristic value signal and the unsigned multi-bit digital weight signal into an analog current signal, multiply the current values of the two analog current signals, and divide by the scale factor I REF Output in the form of an analog current Scale factor I REF It also serves as the least significant bit (LSB) in the conversion of multi-bit digital input feature signals and multi-bit digital weight signals into analog current signals; the current value of the multi-bit digital input feature signal converted into an analog current signal is I. X The current value of a multi-bit digital weighted signal converted into an analog current signal is I. W The output current of the multi-bit multiplication unit circuit is I CELL This indicates that its value is: n current-domain multi-bit multiplication unit circuits are connected in parallel to obtain a current-domain multi-bit multiply-accumulate circuit, which accumulates the output currents of the n parallel current-domain multi-bit multiplication units. The activation function circuit compares the output current of the current domain multi-bit multiply-accumulate circuit with the set bias current: if the bias current value is greater than the output current value of the current domain multi-bit multiply-accumulate circuit, the final output current value of the neuron circuit is set to zero. Conversely, the final output current value of the neuron circuit is the sum of the output current value of the current domain multi-bit multiply-accumulate circuit and the inverse of the set bias current value. The activation function circuit sets two bias currents I B and I TH , the difference between the two bias currents I TH - I B is compared with I CELL , and the output current I OUT of the activation function circuit is obtained, and the value is: 。 2. The current-domain neuron circuit as described in claim 1, characterized in that: The current-domain multi-bit multiplication unit circuit includes one current source I0, six NMOS transistors N0 to N5, seven PMOS transistors P0 to P6, and four switches S0 to S3. The positive terminal of current source I0 is connected to the power supply potential VDD, and the negative terminal is connected to the gate and drain of transistor N0. N0 forms five current mirrors with N1 to N5 respectively, copying the current value of I0 to the corresponding transistors N1 to N5 according to the width-to-length ratio between N1 to N5 and N0. Among them, the source of N0 is grounded to the potential GND, and the gate is connected to the gate of N3 and one end of switches S0 to S4. Switches S0 and S1 are controlled by the 2-bit digital input feature value signal X<1:0> respectively, with one end connected to the gate of N3, and the other end of switches S0 and S1 are connected to the gates of N1 and N2 respectively. Switches S2 and S3 are controlled by the 2-bit digital weight signal W<1:0> respectively, with one end connected to the gate of N3, and the other end of switches S2 and S3 are connected to the gates of N4 and N5 respectively. The sources of N1 to N5 are all grounded to the potential GND, where the width-to-length ratio of N2, N3, and N5 is the same as that of N0, and the width-to-length ratio of N1 and N4 is twice that of N0. Among them, the current value I of current source I0 REF As the least significant bit (LSB) in the conversion of digital signals into analog current signals; P1 through P4 all operate in the subthreshold region and have the same width-to-length ratio. Specifically, the source of P1 is connected to the power supply potential VDD, and its gate and drain are shorted and connected to the drains of N1 and N2. The gate of P2 is connected to the gate of P1, its drain to the drain of N3, and its source to the drain of P0 and the source of P3. The gate and drain of P3 are shorted and connected to the drains of N4 and N5. The gate of P4 is connected to the gate of P3, its source is connected to the power supply potential VDD, and its drain outputs the output current I of the multi-bit multiplication unit circuit. CELL The drain of P5 is connected to the gates of P3 and P4, and the source is connected to the drain of P6. The source of P6 is connected to the power supply potential VDD. The gates of P5 and P6 are connected to the digital input characteristic value signal X<1:0>. The signal X<1:0> determines whether the gate of P4 is pulled up to the power supply potential VDD.

3. The current-domain neuron circuit as described in claim 1, characterized in that: The activation function circuit includes two current sources I1 and I2, six NMOS transistors N6 to N11, five PMOS transistors P7 to P11, and one buffer B0. Current source I1 has its positive terminal connected to the power supply potential VDD and its negative terminal connected to the source of transistor P10; current source I2 has its positive terminal connected to the drain of transistor P7 and its negative terminal connected to ground potential GND; P7 and P8, P7 and P9, N6 and N7, and N8 and N9 form four sets of current mirror circuits; among them, the gates of P7, P8, and P9 are connected, and their sources are all connected to the power supply potential VDD, the drain of P8 is connected to the drain of N6, and the drain of P9 is connected to the drain of N8; the gates of N6 and N7 are connected, the gates of N8 and N9 are connected, and their sources are all connected to ground potential GND, the drain of N6 is connected to the drain of N11, and the drain of N7 is connected to the drain of P10. N9's drain is connected to P11's drain; P11, N10, and N11 are switching transistors controlled by the externally input digital signal RST, and the gates of P11, N10, and N11 are all connected to the RST signal; P11's source is connected to the negative terminal of current source I1, and its drain is connected to N9's drain; N10's source is grounded to GND, and its drain is connected to the output terminal of buffer B0; N11's source is connected to the input terminal of buffer B0, and its drain is connected to the drains of N6 and P8; the output terminal of buffer B0 is connected to P10's gate; P10's source is connected to the output current I of n current-domain multi-bit multiplication unit circuits. CELL The drain is connected to the drain of N7; When signal RST is high, P11 is off, and N10 and N11 are on. At this time, P10 is on; P7 and P8, N6 and N7 will convert the current source I2 to the current value I. TH and current value I CELL With current source I1 current value I B The sum is copied onto the same branch; When RST changes from high to low, P11 is turned on, and N10 and N11 are turned off; if When the output of buffer B0 is high, P10 is turned off. At this time, the activation function circuit outputs current I. OUT =0; if When the output of buffer B0 is low, P10 remains on; at this time, the activation function circuit outputs current. Combining the two cases where RST is low, the output current of the activation function circuit can be expressed as: 。 4. The current-domain neuron circuit as described in claim 1, characterized in that: It is used in high-energy-efficiency edge computing and IoT devices.

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