PCB circuit board edge size detection method and system based on image recognition

Abstract

The application relates to the technical field of image recognition, and provides a PCB (Printed Circuit Board) edge size detection method and system based on image recognition. The method comprises the following steps: a plurality of PCB units are spliced into integrated spliced boards; after being conveyed to a detection station, panoramic images are collected by an industrial camera triggered by a light sensor; after image preprocessing, a Canny contour recognition is adopted to generate a binary image; multi-dimensional size measurement is performed, and a CAD drawing is compared to locate an out-of-tolerance coordinate; the out-of-tolerance coordinate is converted into a physical coordinate, a defective unit is recognized and marked; the defective unit is independently scrapped when the board is separated, and a non-defective PCB board is output. The application solves the technical problem that in the traditional PCB spliced board production, after the board is separated, the whole board is scrapped due to the inability to accurately locate the defective unit in the post-processing stage, achieves the technical effect that the accurate positioning of the defective unit is realized through optical detection and coordinate conversion, the defective unit is independently scrapped in combination with the board separation process, the post-processing efficiency of the board separation is improved, and the production cost is reduced.

Description

Technical Field

[0001] This application relates to the field of image recognition technology, specifically to a method and system for detecting the edge dimensions of PCB circuit boards based on image recognition. Background Technology

[0002] Printed circuit boards (PCBs) in mass production typically employ a "paneling-processing-separation" process. Integrating multiple PCB units onto the same panel significantly improves turnaround efficiency for mounting, reflow soldering, and testing. However, edge geometry parameters such as the panel's outer contour, process edge width, and V-cut slots or bridging spacing between adjacent units directly affect subsequent separation quality, assembly fit, and yield control. Especially in high-density and precision manufacturing scenarios, dimensions often require sub-millimeter tolerances; any minute deviation can be amplified into batch defects or rework / scrap after separation.

[0003] Existing inspection methods mainly include: manual caliper / projector sampling inspection, offline coordinate measuring machine (CMM) point measurement, and AOI inspection focusing on circuits / pads. The first two are mostly sampling inspections, with limited coverage and cycle time, and it is difficult to achieve full-area, continuous edge contour measurement of the entire panel; AOI focuses on graphic / welding defect identification, and has limited ability to detect the dimensions of the outer contour and process edges. In particular, it lacks a linkage mechanism for accurate identification of defect units in the panel process and independent scrapping of separate panels, making it difficult to achieve "panel efficiency improvement" and "panel cost reduction" simultaneously. Summary of the Invention

[0004] This application provides a PCB circuit board edge size detection method and system based on image recognition, aiming to solve the technical problem of the entire board being scrapped in the post-processing stage of traditional PCB panel production due to the inability to accurately locate defective units.

[0005] The first aspect of this application discloses a method for edge dimension detection of PCB circuit boards based on image recognition. The method includes: splicing multiple PCB units on a PCB panel plane to form an integrated panel; conveying the integrated panel to an inspection station via a conveyor belt, and triggering a high-resolution industrial camera to acquire an image of the panel using a light sensor to obtain a panoramic image of the panel; preprocessing the panoramic image of the panel, and then using the Canny edge detection algorithm to identify the outer contour of the PCB to generate a binary edge image; performing multi-dimensional dimension measurement on the binary edge image to obtain multi-dimensional dimension data, and then using CAD design drawings to calculate the deviation of each item of the multi-dimensional dimension data to locate the coordinates of N out-of-tolerance image points; converting the coordinates of the N out-of-tolerance image points into N physical coordinates of the panel, and then identifying defective PCB units on the integrated panel; based on the defective PCB unit identification, independently scrapping the defective units during the panel separation process, and outputting a defect-free PCB unit board.

[0006] Another aspect of this application discloses a PCB circuit board edge dimension detection system based on image recognition. The system includes: a single-unit splicing module: multiple PCB units are spliced ​​together on a PCB panel plane to form an integrated panel; an image acquisition module: after the integrated panel is conveyed to the inspection station via a conveyor belt, a high-resolution industrial camera is triggered by a light sensor to acquire an image, obtaining a panoramic image of the panel; an edge detection module: after preprocessing the panoramic image of the panel, the Canny edge detection algorithm is used to identify the outer contour of the PCB and generate a binary edge image; a deviation calculation module: after performing multi-dimensional dimension measurement on the binary edge image to obtain multi-dimensional dimension data, the deviation of the multi-dimensional dimension data is calculated item by item using CAD design drawings to locate the coordinates of N out-of-tolerance points; a defect unit identification module: after converting the coordinates of the N out-of-tolerance points into N panel physical coordinates, deviation defect unit identification is performed, and defective PCB units are marked on the integrated panel; and an independent scrapping module: based on the defective PCB unit markings, the defective units are independently scrapped during the panel separation process, and defect-free PCB unit boards are output.

[0007] One or more technical solutions provided in this application have at least the following technical effects or advantages:

[0008] The aforementioned image recognition-based PCB edge dimension detection method first splices multiple PCB units onto the same plane to form a panel, which is then transported to the inspection station via a conveyor belt. An industrial camera, triggered by a light sensor, captures a panoramic image of the panel. After image preprocessing, the Canny edge detection algorithm is used to identify the panel's outer contour and generate a binarized edge image. Based on this, multi-dimensional dimensional measurements are performed on the image, and the results are compared item by item with CAD design drawings to calculate deviations and locate out-of-tolerance points. These out-of-tolerance points are then mapped to the panel's physical coordinates to identify and mark defective PCB units. Finally, during the board separation process, the marked defective units are independently scrapped, ensuring that the output consists entirely of qualified, defect-free PCB units. This achieves automated detection and sorting of defective units in panel production, reducing the overall board scrap rate.

[0009] The above description is merely an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, specific embodiments of this application are given below. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a flowchart illustrating a PCB circuit board edge size detection method based on image recognition in one embodiment.

[0012] Figure 2 This is an architecture diagram of a PCB circuit board edge size detection system based on image recognition in one embodiment.

[0013] Figure labeling: 11 Single unit splicing module, 12 Image acquisition module, 13 Edge detection module, 14 Deviation calculation module, 15 Defect unit identification module, 16 Independent scrap module. Detailed Implementation

[0014] This application provides a PCB circuit board edge size detection method and system based on image recognition, which solves the technical problem of the entire board being scrapped in the post-processing stage of traditional PCB panel production due to the inability to accurately locate defective units.

[0015] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0016] It should be noted that the terms “comprising” and “having”, and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or server that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or modules that are not explicitly listed or that are inherent to such process, method, product, or device.

[0017] Example 1, as Figure 1 As shown, this application provides a PCB circuit board edge size detection method based on image recognition, the method comprising:

[0018] Multiple PCB units are spliced ​​together on the PCB panel to form an integrated panel.

[0019] In this embodiment, during PCB mass production, a single PCB unit is typically not processed individually. Instead, several PCB units of the same size and shape are assembled on the same PCB panel plane in a preset array. The PCB panel plane is aligned and fixed using uniform reference positioning holes and process borders, ensuring that each unit has a stable and repeatable relative positional relationship in a two-dimensional coordinate system. The assembly method can be a matrix arrangement, staggered rows and columns, or other regular arrays. A certain gap is reserved between the units to facilitate subsequent separation using V-cut slots or stamp holes. The panel typically has process borders around its perimeter for arranging positioning holes, optical alignment marks, and process fixture interfaces for easy transfer and clamping. Through this assembly, multiple PCB units are combined into an integrated panel, providing a unified inspection object and a stable geometric reference for subsequent dimensional inspection.

[0020] After the integrated panel is conveyed to the inspection station via a conveyor belt, a high-resolution industrial camera is triggered by a light sensor to acquire an image, resulting in a panoramic image of the panel.

[0021] In one embodiment, after the integrated panel is assembled, it is conveyed to a designated inspection station via a conveyor belt. When the integrated panel arrives at the inspection station, a light sensor triggers a high-resolution industrial camera to acquire an image. The light sensor ensures that the timing of the inspection is synchronized with the specific position of the panel, thereby guaranteeing that image acquisition is performed when the panel is accurately positioned. The connection between the light sensor and the camera is typically established via an electrical triggering mechanism, which precisely controls the camera's shooting timing to prevent panel misalignment or missing image information. Once triggered, the high-resolution industrial camera captures every detail of the panel surface, including edges, holes, and any minor defects that may exist, forming a high-resolution panoramic image of the panel. This image serves as the basis for subsequent image processing and dimensional inspection, ensuring that subsequent edge recognition and dimensional measurement can be performed accurately.

[0022] Furthermore, this application also includes:

[0023] The high-resolution industrial camera is installed perpendicular to the inspection station, wherein the optical axis of the lens of the high-resolution industrial camera coincides with the normal of the panel plane of the inspection station; the high-resolution industrial camera is pre-deployed with a multi-angle ring LED light source; the high-resolution industrial camera is electrically connected to the light sensor through a trigger signal line, forming a closed-loop acquisition and control loop with a position synchronization accuracy of ≤±0.1mm.

[0024] Preferably, the high-resolution industrial camera is vertically mounted on the inspection station, ensuring that the optical axis of the camera lens coincides with the normal of the panel plane. This mounting method helps ensure that the high-resolution industrial camera captures the panel vertically from directly above, avoiding any viewing angle deviation and thus obtaining an accurate panoramic image of the panel. To ensure image acquisition quality under different lighting conditions, the high-resolution industrial camera is also equipped with a pre-deployed multi-angle ring LED light source. This multi-angle ring LED light source solves the problem of reflection interference that may occur on the panel surface through a combination of coaxial light and diffuse reflection light. The coaxial light provides direct and uniform illumination, which can clearly illuminate the panel surface; while the diffuse reflection light reduces the reflection interference caused by the inconsistent angle between the light source and the panel surface through the reflection effect. Especially for the metal parts of the panel surface, it can effectively eliminate image blurring or distortion caused by high light reflection. This light source configuration not only improves the contrast and clarity of the image, but also ensures that all parts of the panel, especially the edge areas, can maintain a clear imaging effect under different lighting conditions. During the inspection process, the optical sensor and the high-resolution industrial camera are electrically connected via trigger signal lines, forming a precise synchronous control loop. Whenever the optical sensor detects that the panel has reached a designated position, it triggers the high-resolution industrial camera to acquire an image, ensuring that each image acquisition occurs at the moment when the panel's position is most stable, thus avoiding image data errors caused by positional deviations. This closed-loop acquisition control loop precisely controls the synchronization of the high-resolution industrial camera and the conveyor belt, ensuring a positional accuracy within ±0.1mm. This precise synchronous control loop not only improves the system's reliability but also enhances the automation and accuracy of the inspection, enabling the entire production line to operate efficiently while maintaining accurate inspection results.

[0025] After preprocessing the panoramic image of the PCB panel, the Canny edge detection algorithm is used to identify the outer contour of the PCB and generate a binarized edge image.

[0026] In one embodiment, after obtaining the panoramic image of the PCB panel, the image is first preprocessed, including lens distortion correction and grayscale processing, to make the outer contour edges of the PCB more obvious and enhance the separability of edge features. Then, the Canny edge detection algorithm is used to identify the outer contour of the PCB in the preprocessed panoramic image of the PCB panel to obtain a binary edge image. In this binary edge image, the outer contour and key structural edges of the PCB are displayed as white pixels, while non-edge areas are displayed as black pixels, thereby clearly distinguishing the edges from the background, simplifying the calculation of subsequent multi-dimensional size measurement and deviation analysis, and improving the accuracy and efficiency of detection.

[0027] Furthermore, this application provides a method for preprocessing the panoramic image of the PCB panel, then using the Canny edge detection algorithm to identify the outer contour of the PCB and generate a binarized edge image. The method includes:

[0028] A two-dimensional coordinate system is established with the panelization process angle as the origin to perform lens distortion correction on the panoramic image of the panelization, and the panelization correction image is output. The panelization correction image is then processed into grayscale to obtain a panelization grayscale image. The Canny edge detection algorithm is used to identify the outer contour of the PCB in the panelization grayscale image to generate the binarized edge image.

[0029] Preferably, when processing the panoramic image of the panel, a two-dimensional coordinate system is first established using the process corner of the panel (such as the lower left or upper right corner, usually a reference corner point agreed upon during design) as the origin. This coordinate system serves as a unified spatial reference for the image, accurately mapping the positional relationships of each PCB unit on the panel and providing a unified benchmark for subsequent dimensional measurements and defect location. Subsequently, based on this two-dimensional coordinate system, lens intrinsic parameters (focal length, principal point coordinates) and distortion coefficients (radial distortion, tangential distortion) are calculated using a calibration algorithm (such as OpenCV's checkerboard calibration method). Then, a distortion model (such as the Brown-Conrady model) is used to perform a reverse mapping of the image, eliminating distortion effects and ensuring that straight edges in the image remain true straight lines after correction. This outputs a corrected panel image consistent with the actual panel geometry, guaranteeing the accuracy of subsequent edge detection and dimensional calculations. Next, the obtained panel correction image is converted to grayscale. This is done by weighted summation of the RGB channels based on human eye color sensitivity (e.g., formula: Gray = 0.299 × R + 0.587 × G + 0.114 × B), where Gray is the grayscale value, and R, G, and B are the pixel values ​​of the red, green, and blue channels, respectively. This weighted summation converts the panel correction image into a grayscale image, reducing color interference and allowing edge detection to rely solely on brightness changes, thus improving the separability of edge features. Then, the Canny edge detection algorithm is applied to the grayscale image to identify the PCB outer contour. The Canny algorithm first calculates the gradient magnitude and direction of each pixel in the grayscale image through gradient operations, thereby identifying areas of rapid brightness change, i.e., potential edge locations. Then, non-maximum suppression is performed to remove non-edge points along the gradient direction, preserving the finest and most continuous edge lines. Finally, through dual threshold detection and edge connection, strong edges and the weak edges connected to them are preserved to form a complete outer contour edge, thus obtaining the final binarized edge image. In this binarized edge image, the outer contour of the PCB and the edges of key structures are displayed as white pixels, and the background is displayed as black pixels, clearly marking the contour of each PCB unit, providing a reliable foundation for subsequent multi-dimensional dimension measurement, deviation calculation and defect location.

[0030] After performing multidimensional size measurement on the binarized edge image to obtain multidimensional size data, the deviation of the multidimensional size data is calculated item by item using CAD design drawings to locate the image coordinates of N out-of-range points.

[0031] In one embodiment, after obtaining the binarized edge image, the outline of each PCB unit is first measured in multiple dimensions. That is, the dimensional information of each key geometric feature is extracted from the binarized edge image, including the total length and width of the panel, the width of the process edge, etc. Then, the obtained multidimensional dimensional data is compared with the standard design dimensions and tolerance values ​​in the corresponding CAD design drawings item by item. The coordinates of N out-of-tolerance points are accurately located from the binarized edge image, providing accurate image references for subsequent defect unit identification, deviation type classification and production scrapping.

[0032] Furthermore, this application provides a method for calculating the deviation of each item of the multidimensional dimension data after performing multidimensional dimension measurement on the binarized edge image to locate the image coordinates of N out-of-range points using CAD design drawings. The method includes:

[0033] Multidimensional size measurement is performed on the binarized edge image based on subpixel edge fitting to obtain multidimensional size data, which includes the total length and width of the panel, the width of the process edge, and the V-cut slot spacing matrix between adjacent panels. Based on the composition of the multidimensional size data, a multidimensional standard tolerance threshold is retrieved from the CAD design drawings. The deviation of the multidimensional size data is calculated using the mapping of the multidimensional standard tolerance threshold to obtain multiple discrete outliers. Spatial coordinate fusion of the multiple discrete outliers is performed based on spatial clustering to output the image coordinates of the N outlier points.

[0034] Preferably, after extracting the binarized edge image, sub-pixel edge fitting processing is first performed on the binarized edge image. In this process, a continuous gray-level variation model is constructed in the neighborhood of the pixel-level edge (e.g., a 3x3 or 5x5 area) using gray-level interpolation (such as bilinear interpolation, cubic spline interpolation), moment calculation, or surface fitting. By finding the extreme points or inflection points of this model, the precise position of the edge can be calculated. This position can be between two physical pixels. For example, the actual position of the edge is at pixel coordinates (100.35, 50.78), thereby improving the positioning accuracy of the edge point from the pixel level to the sub-pixel level and improving the accuracy of size measurement. Next, based on the fitted edge contour, the length and width are obtained by fitting the minimum bounding rectangle of the panel's outer contour, serving as the overall length and width of the panel. The process edge width is obtained by measuring the lateral / vertical width of the reserved process edge area (used for production clamping) on ​​the panel's edge. For the V-cut grooves used for board separation in the panel, the center-to-center distance between the V-cut grooves of every two adjacent PCB units is calculated, forming a V-cut groove spacing matrix between adjacent boards (e.g., a two-dimensional array of M×N, where M and N are the number of rows and columns of the panel). The calculated total panel length and width, process edge width, and V-cut groove spacing matrix between adjacent boards are uniformly stored to form multi-dimensional dimensional data. Then, based on the composition of the multi-dimensional dimensional data indicators, the corresponding design dimensions and their tolerance thresholds are retrieved from the CAD design drawings to construct a standard tolerance threshold library. Using this standard tolerance threshold library as a benchmark, the deviation of each measured multi-dimensional dimensional data item is calculated. If the deviation between the measured value and the design value exceeds the corresponding tolerance range, the location is determined to be a discrete outlier, and the coordinates of the discrete outlier are recorded. Finally, to avoid misjudgments due to measurement errors or single noise points, spatial clustering analysis was performed on all the obtained discrete anomalies. Specifically, using a set neighborhood scale, the spatial distribution of discrete anomalies was density-based, merging neighboring anomalies belonging to the same physical region into clusters, thus forming N representative out-of-tolerance image coordinates. This process realizes a complete detection chain from sub-pixel level measurement to tolerance comparison, and then to anomaly clustering and fusion. This ensures detection accuracy while avoiding false detections caused by single discrete anomalies, providing a reliable basis for subsequent defect identification and process analysis.

[0035] Furthermore, this application provides a method for fusing the spatial coordinates of the multiple discrete outliers based on spatial clustering to output the image coordinates of the N outlier points. The method includes:

[0036] Using a preset density radius as the neighborhood scale, the density reachability of the multiple discrete outliers is determined to obtain multiple candidate core points. Using the multiple candidate core points as seed points, the multiple discrete outliers are traversed through a cluster expansion generation algorithm to aggregate density reachable points, resulting in N candidate clusters. The mean coordinates within the N candidate clusters are calculated, and the mean coordinates of the N fused clusters are output as the image coordinates of the N outlier points.

[0037] Optionally, after obtaining multiple discrete outliers, a pre-defined density radius is acquired and used as a neighborhood scale to measure the spatial density between outliers. Then, with each discrete outlier as the center, the number of other outliers within its neighborhood scale is calculated using Euclidean distance. If the number of points in the neighborhood of a discrete outlier exceeds the density of core points, the discrete outlier is identified as a candidate core point. These candidate core points represent locations where actual deviations may be concentrated. Next, using these candidate core points as seed points, outliers reachable by their density are recursively traversed, and all points within the neighborhood of the density radius are aggregated step-by-step, gradually expanding to form a cluster. In this way, multiple spatially independent clustering regions are divided, resulting in N candidate clusters. Each candidate cluster contains a group of spatially close discrete outliers with similar deviation characteristics. Then, the coordinates of discrete outliers within each candidate cluster are averaged. Specifically, the average of the x and y coordinates of all points within the cluster is calculated to obtain the fused cluster mean coordinates for each candidate cluster. These fused cluster mean coordinates effectively reflect the overall deviation characteristics of the cluster and reduce single-point noise interference. Finally, the obtained N fused cluster mean coordinates are output as N out-of-tolerance point image coordinates to represent the truly existing out-of-tolerance areas in the mosaic image. Through this process, stable and accurate deviation locations can be extracted from a large number of discrete outliers, effectively improving the reliability and executability of the detection results.

[0038] After converting the N out-of-tolerance image coordinates into N panel physical coordinates, deviation defect units are identified, and defective PCB units are marked on the integrated panel.

[0039] In one embodiment, after obtaining the image coordinates of N out-of-tolerance points, the Zhang Zhengyou calibration method is first used to control a high-resolution industrial camera to take multi-angle pictures of a standard calibration board (such as a checkerboard panel with known size markings). The pixel coordinates of the checkerboard corner points in the image and their corresponding physical coordinates are extracted. The camera's intrinsic parameter matrix (focal length, principal point coordinates) and distortion coefficients are calculated. Then, through at least four sets of pixel-physical coordinate correspondences of non-collinear corner points, the perspective transformation matrix is ​​solved using the least squares method. By substituting the image coordinates of the N out-of-tolerance points into the perspective transformation matrix, bilinear interpolation is used to calculate the N panel physical coordinates. These panel physical coordinates can accurately reflect the actual distribution of dimensional deviations on the panel. Subsequently, based on pre-set panel division rules, the entire panel is divided into unit regions, and it is determined which specific PCB unit each out-of-tolerance point belongs to. If an out-of-tolerance point exists in a certain unit region, the unit is identified as a deviation defect unit, and the corresponding PCB unit is marked as defect on the panel. This helps to quickly identify defective units in subsequent board separation stages and can also be associated with production batch data in subsequent process traceability.

[0040] Furthermore, this application provides a method for identifying deviation defect units after converting the N out-of-tolerance image coordinates into N panel physical coordinates, and then identifying defective PCB units on the integrated panel. The method includes:

[0041] Based on predefined unit grid division rules, the physical coordinates of the N panels are projected onto the integrated panel to perform PCB unit area mapping and locate P target defective units; machine-readable markings are engraved at the non-functional area boundaries of the P target defective units to generate the defective PCB unit identifier.

[0042] Preferably, after obtaining the physical coordinates of N panels, the entire integrated panel is first divided into unit grids according to predefined unit grid division rules. These unit grid division rules are predefined based on CAD design drawings and manufacturing process requirements, and can accurately divide the entire panel area into multiple rectangular or polygonal unit grids. Each grid corresponds to the physical location and boundary range of a single PCB unit. Through this division, a clear mapping relationship between unit areas can be established on the panel. Subsequently, the obtained N panel physical coordinates are projected one by one into the divided unit grids and associated with the corresponding PCB units. If a PCB unit contains one or more out-of-tolerance point coordinates, this PCB unit will be identified as a target defect unit. Through this projection and mapping process, P target defect units with dimensional anomalies can be located. Subsequently, to avoid affecting electrical performance and functional areas, these target defective units are marked with defects. That is, at the boundary of the non-functional area of ​​the PCB unit (usually the edge of the panelization process or the reserved non-circuit area), machine-readable marking technology, such as laser marking of QR codes, barcodes, or dot matrix, is used to mark these target defective units, thereby generating defective PCB unit markings. These markings can be quickly read by automatic identification equipment in subsequent board separation and inspection stages, accurately distinguishing defective units from qualified units, preventing defective units from flowing into subsequent processes, and thus effectively improving the quality control capabilities of the production process.

[0043] Based on the defective PCB unit identifier, the defective unit is independently scrapped during the integrated panelization and separation process, and a defect-free PCB unit board is output.

[0044] In one embodiment, after establishing defective PCB unit identification, the defective PCB units are identified from the integrated panel based on these identifications. The integrated panel is then processed into individual units using a V-cut cutter, punching machine, or laser depaneling machine. When the depaneling equipment reaches the area containing a PCB unit with a defective identification, an independent scrapping process is triggered. This means the PCB unit is directly removed from the scrap channel or defective product collection bin, or it is individually picked up and moved into a scrap container during the robotic arm sorting stage. The remaining unidentified, qualified PCB units are output to the finished product channel according to normal procedures, forming defect-free, qualified PCB units. This process avoids the production capacity waste caused by scrapping entire boards and ensures that only defect-free PCB units are output, achieving the technical effect of improving production yield and secondary production efficiency.

[0045] Furthermore, this application also includes:

[0046] Based on the physical coordinates of the N panels, deviation types are identified, and N dimensional deviation types are output. Based on the physical coordinates of the N panels and the N dimensional deviation types, root cause analysis of process failures is performed to locate the faulty process step. Based on the faulty process step and the defective PCB unit identifier, the process parameters of the defective production batch are traced back.

[0047] Preferably, the deviations corresponding to the physical coordinates of each panel are first identified by type. That is, the multi-dimensional dimensional data is compared with the design values, and the deviations are classified according to their direction and numerical characteristics. For example, if the deviations mainly occur in the total length and width of the panel, they are identified as overall dimensional deviations; if they are concentrated in the width of the process edge, they are identified as process edge processing deviations; if there are abnormalities in the V-cut slot spacing between adjacent PCBs, they are identified as cutting / splicing deviations. After identification, the dimensional deviation type corresponding to each deviation point is output. Subsequently, based on the N panel physical coordinates and N dimensional deviation types, the root cause analysis of process failures is performed according to the process failure mapping rule library to locate the faulty process link. For example, overall dimensional deviations usually originate from the lamination or panel design stage, process edge deviations may be related to the punching / milling process, and abnormal V-cut slot spacing often corresponds to insufficient precision of the depaneling machine or cutting equipment. Subsequently, based on the identified faulty process step and defective PCB unit identifier, production data from the Manufacturing Execution System (MES) is retrieved to trace back the corresponding production batch's process parameters. For example, process data such as the equipment number, tool life, cutting speed, lamination pressure, and panelization parameters used in that batch are extracted. This method not only pinpoints the batch that caused the defect but also allows for further analysis of potential process anomaly trends, providing a basis for subsequent process optimization and quality improvement.

[0048] Furthermore, this application provides a method for identifying deviation types based on the physical coordinates of the N panels and outputting N dimensional deviation types, the method comprising:

[0049] A pixel physical space transformation matrix is ​​constructed based on a standard calibration board; the pixel physical space transformation matrix is ​​used to perform millimeter-level physical coordinate mapping of the N out-of-tolerance image coordinates to obtain the N panel physical coordinates; based on the N panel physical coordinates, N panel design values ​​are retrieved from the CAD design drawing, and the deviation direction is determined according to the N panel physical coordinates and the N panel design values, outputting N deviation direction labels; the N panel physical coordinates are retrieved and matched with a preset functional area position feature library to classify out-of-tolerance deviations, obtaining the N size deviation types, and then the deviation direction labels and N size deviation types are associated.

[0050] Optionally, based on a standard calibration board, a perspective transformation matrix is ​​calculated using the Zhang Zhengyou calibration method. This perspective transformation matrix is ​​then used as a pixel physical space transformation matrix to convert the image pixel coordinates to actual physical coordinates. Subsequently, using this pixel physical space transformation matrix, the coordinates of N out-of-tolerance image points are converted into millimeter-precision mosaic physical coordinates, resulting in N mosaic physical coordinates. Then, based on these N mosaic physical coordinates, the mosaic design value for each point is retrieved from the corresponding CAD design drawing; that is, the corresponding theoretical dimensions and position data. The mosaic physical coordinates are then combined with the mosaic design values ​​to determine the deviation direction for each point, and a deviation direction label is generated for each out-of-tolerance point to identify whether the deviation is horizontal, vertical, or diagonal. Then, the physical coordinates of the N panelizations are matched with a pre-established functional area location feature library to determine the PCB functional area where each out-of-tolerance point is located, such as the pad area, via area, process edge, or V-cut slot area. Based on the functional area matching results, each out-of-tolerance point is categorized to obtain the specific dimensional deviation type of each out-of-tolerance point (such as overall dimensional deviation of the pad area, width deviation of the process edge of the pad area, and V-cut slot spacing deviation of the pad area). Finally, the deviation direction label of each out-of-tolerance point is associated with the corresponding dimensional deviation type to form a complete deviation information description, providing basic data for subsequent process fault diagnosis.

[0051] Furthermore, this application provides a method for analyzing the root causes of process failures based on the N physical coordinates of the panels and the N dimensional deviation types, and for locating the faulty process step. The method includes:

[0052] Using a preset neighborhood radius as the clustering scale, the physical coordinates of the N panels are clustered by defect region density to generate M spatially independent defect regions. Based on the coverage relationship of the M spatially independent defect regions to the N dimensional deviation types, M dominant deviation types are statistically output. Using the M dominant deviation types and the M spatially independent defect regions as two-dimensional matching conditions, M candidate fault links are matched and output in a preset process fault mapping rule library. After performing cross-regional correlation deviation combination on the M candidate fault links, upstream common process links are traced and the faulty process links are bound.

[0053] Optionally, firstly, using a preset neighborhood radius as the clustering scale, defect region density clustering analysis is performed on the obtained N panel physical coordinates. The density reachability relationship between the panel physical coordinates is determined using the same method described above, grouping spatially close points with related deviation properties into the same cluster, thus generating M spatially independent defect regions. Each spatially independent defect region corresponds to a concentrated abnormal area on the PCB panel. Subsequently, the N dimensional deviation types are mapped to the M spatially independent defect regions according to the N panel physical coordinates. The deviation type with the highest frequency in each spatially independent defect region is statistically analyzed to obtain M dominant deviation types. These dominant deviation types are used to reflect the main dimensional anomaly characteristics of the region. Then, each spatially independent defect region and its corresponding dominant deviation type are used as two-dimensional matching conditions, matched against a preset process fault mapping rule library, outputting M candidate fault steps, i.e., process steps or processes that may lead to defects in the region. Then, to further pinpoint the source of the fault, a cross-regional correlation analysis was performed on the M candidate fault stages. If the dominant deviation types of multiple defective areas were correlated—for example, if positive length deviations simultaneously appeared on both the left and right sides of the panel—it was determined to be a cross-regional correlation deviation. Finally, these cross-regional correlation deviations were traced back through the entire process flow (e.g., from lamination to panel separation) to identify upstream common process stages. For example, the simultaneous occurrence of positive length deviations in multiple areas might be due to uneven lamination pressure causing overall substrate shrinkage, which in turn leads to subsequent panel separation dimensional deviations. By linking the results of the cross-regional correlation analysis with the candidate fault stages, the final faulty process stage (e.g., "uneven lamination pressure") was determined, providing a basis for process optimization, production quality improvement, and defect batch tracing.

[0054] In summary, the embodiments of this application have at least the following technical effects:

[0055] In this embodiment, multiple individual PCB units are first spliced ​​together on a PCB panel to form an integrated panel. Then, the integrated panel is conveyed to an inspection station via a conveyor belt, where a high-resolution industrial camera is triggered by a light sensor to acquire a panoramic image of the panel. After preprocessing the panoramic image, the Canny edge detection algorithm is used to identify the PCB's outer contour, generating a binarized edge image. Further, multi-dimensional dimensional measurements are performed on the binarized edge image to obtain multi-dimensional dimensional data. Then, CAD design drawings are used to calculate the deviations of each item in the multi-dimensional dimensional data, locating the coordinates of N out-of-tolerance points. Next, the coordinates of these N out-of-tolerance points are converted into N physical coordinates of the panel, and defective PCB units are identified and marked on the integrated panel. Finally, based on the defective PCB unit markings, the defective units are independently scrapped during the panel separation process, resulting in a defect-free PCB unit board. These technologies collectively solve the technical problem of scrapping the entire board in the post-processing stage of traditional PCB panel production due to the inability to accurately locate defective units. They achieve the technical effect of accurately locating defective units through optical detection and coordinate transformation, and independently scrapping defective units during the panel separation process, thereby improving the efficiency of post-processing and reducing production costs.

[0056] Example 2 is based on the same inventive concept as the image recognition-based PCB circuit board edge size detection method in the foregoing examples, such as... Figure 2 As shown, this application provides a PCB circuit board edge size detection system based on image recognition, the system comprising:

[0057] Single-unit splicing module 11: Multiple PCB units are spliced ​​together on the PCB panel plane to form an integrated panel; Image acquisition module 12: After the integrated panel is conveyed to the inspection station via a conveyor belt, a high-resolution industrial camera is triggered by a light sensor to acquire images and obtain a panoramic image of the panel; Edge detection module 13: After preprocessing the panoramic image of the panel, the Canny edge detection algorithm is used to identify the outer contour of the PCB and generate a binary edge image; Deviation calculation module 14: After performing multi-dimensional size measurement on the binary edge image to obtain multi-dimensional size data, the deviation of the multi-dimensional size data is calculated item by item using CAD design drawings to locate the coordinates of N out-of-tolerance points; Defect unit identification module 15: After converting the coordinates of the N out-of-tolerance points into N panel physical coordinates, deviation defect unit identification is performed, and defective PCB units are marked on the integrated panel; Independent scrapping module 16: According to the defective PCB unit markings, the defective units are independently scrapped during the panel separation process of the integrated panel, and defect-free PCB unit boards are output.

[0058] Furthermore, the image acquisition module 12 is also used to perform the following methods:

[0059] The high-resolution industrial camera is installed perpendicular to the inspection station, wherein the optical axis of the lens of the high-resolution industrial camera coincides with the normal of the panel plane of the inspection station; the high-resolution industrial camera is pre-deployed with a multi-angle ring LED light source; the high-resolution industrial camera is electrically connected to the light sensor through a trigger signal line, forming a closed-loop acquisition and control loop with a position synchronization accuracy of ≤±0.1mm.

[0060] Furthermore, the edge detection module 13 is also used to perform the following method:

[0061] A two-dimensional coordinate system is established with the panelization process angle as the origin to perform lens distortion correction on the panoramic image of the panelization, and the panelization correction image is output. The panelization correction image is then processed into grayscale to obtain a panelization grayscale image. The Canny edge detection algorithm is used to identify the outer contour of the PCB in the panelization grayscale image to generate the binarized edge image.

[0062] Furthermore, the deviation calculation module 14 is also used to perform the following method:

[0063] Multidimensional size measurement is performed on the binarized edge image based on subpixel edge fitting to obtain multidimensional size data, which includes the total length and width of the panel, the width of the process edge, and the V-cut slot spacing matrix between adjacent panels. Based on the composition of the multidimensional size data, a multidimensional standard tolerance threshold is retrieved from the CAD design drawings. The deviation of the multidimensional size data is calculated using the mapping of the multidimensional standard tolerance threshold to obtain multiple discrete outliers. Spatial coordinate fusion of the multiple discrete outliers is performed based on spatial clustering to output the image coordinates of the N outlier points.

[0064] Furthermore, the deviation calculation module 14 is also used to perform the following method:

[0065] Using a preset density radius as the neighborhood scale, the density reachability of the multiple discrete outliers is determined to obtain multiple candidate core points. Using the multiple candidate core points as seed points, the multiple discrete outliers are traversed through a cluster expansion generation algorithm to aggregate density reachable points, resulting in N candidate clusters. The mean coordinates within the N candidate clusters are calculated, and the mean coordinates of the N fused clusters are output as the image coordinates of the N outlier points.

[0066] Furthermore, the defective unit identification module 15 is also used to perform the following method:

[0067] Based on predefined unit grid division rules, the physical coordinates of the N panels are projected onto the integrated panel to perform PCB unit area mapping and locate P target defective units; machine-readable markings are engraved at the non-functional area boundaries of the P target defective units to generate the defective PCB unit identifier.

[0068] Furthermore, the independent scrapping module 16 is also used to perform the following method:

[0069] Based on the physical coordinates of the N panels, deviation types are identified, and N dimensional deviation types are output. Based on the physical coordinates of the N panels and the N dimensional deviation types, root cause analysis of process failures is performed to locate the faulty process step. Based on the faulty process step and the defective PCB unit identifier, the process parameters of the defective production batch are traced back.

[0070] Furthermore, the independent scrapping module 16 is also used to perform the following method:

[0071] A pixel physical space transformation matrix is ​​constructed based on a standard calibration board; the pixel physical space transformation matrix is ​​used to perform millimeter-level physical coordinate mapping of the N out-of-tolerance image coordinates to obtain the N panel physical coordinates; based on the N panel physical coordinates, N panel design values ​​are retrieved from the CAD design drawing, and the deviation direction is determined according to the N panel physical coordinates and the N panel design values, outputting N deviation direction labels; the N panel physical coordinates are retrieved and matched with a preset functional area position feature library to classify out-of-tolerance deviations, obtaining the N size deviation types, and then the deviation direction labels and N size deviation types are associated.

[0072] Furthermore, the independent scrapping module 16 is also used to perform the following method:

[0073] Using a preset neighborhood radius as the clustering scale, the physical coordinates of the N panels are clustered by defect region density to generate M spatially independent defect regions. Based on the coverage relationship of the M spatially independent defect regions to the N dimensional deviation types, M dominant deviation types are statistically output. Using the M dominant deviation types and the M spatially independent defect regions as two-dimensional matching conditions, M candidate fault links are matched and output in a preset process fault mapping rule library. After performing cross-regional correlation deviation combination on the M candidate fault links, upstream common process links are traced and the faulty process links are bound.

[0074] It should be noted that the order of the embodiments described above is for descriptive purposes only and does not represent the superiority or inferiority of the embodiments. Furthermore, the above description focuses on specific embodiments of this specification. The processes depicted in the accompanying drawings do not necessarily require a specific or sequential order to achieve the desired results. In some implementations, multitasking and parallel processing are possible or may be advantageous.

[0075] The above description is only a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0076] This specification and accompanying drawings are merely illustrative examples of this application and are intended to cover any and all modifications, variations, combinations, or equivalents within the scope of this application. Clearly, those skilled in the art can make various alterations and modifications to this application without departing from its scope. Therefore, if such modifications and modifications fall within the scope of this application and its equivalents, this application intends to include such modifications and modifications.

Claims

1. A method for detecting the edge dimensions of a PCB circuit board based on image recognition, characterized in that, The method includes: Multiple individual PCB units are spliced ​​together on a PCB panel to form an integrated panel; After the integrated panel is conveyed to the inspection station via a conveyor belt, a high-resolution industrial camera is triggered by a light sensor to acquire an image and obtain a panoramic image of the panel. After preprocessing the panoramic image of the PCB panel, the Canny edge detection algorithm is used to identify the outer contour of the PCB and generate a binarized edge image. After performing multidimensional size measurement on the binarized edge image to obtain multidimensional size data, CAD design drawings are used to calculate the deviation of each item of the multidimensional size data and locate the image coordinates of N out-of-range points. After converting the N out-of-tolerance image coordinates into N panel physical coordinates, deviation defect units are identified, and defective PCB units are marked on the integrated panel. Based on the defective PCB unit identifier, the defective unit is independently scrapped during the integrated panelization and board separation process, and a defect-free PCB unit board is output. The method further includes: Based on the physical coordinates of the N panels, the deviation type is identified, and N dimensional deviation types are output. Based on the N physical coordinates of the panels and the N dimensional deviation types, a root cause analysis of the process failure is performed to locate the faulty process step. The process parameters of the defective production batch are traced back based on the faulty process step and the defective PCB unit identifier.

2. The PCB circuit board edge size detection method based on image recognition as described in claim 1, characterized in that, After preprocessing the panoramic image of the PCB panel, the Canny edge detection algorithm is used to identify the outer contour of the PCB to generate a binarized edge image. The method includes: A two-dimensional coordinate system is established with the panel process angle as the origin to perform lens distortion correction on the panoramic image of the panel and output the panel correction image; By converting the corrected image of the mosaic panel to grayscale, a grayscale image of the mosaic panel is obtained. The Canny edge detection algorithm is used to identify the outer contour of the PCB in the grayscale image of the panel to generate the binarized edge image.

3. The PCB circuit board edge size detection method based on image recognition as described in claim 1, characterized in that, After performing multidimensional size measurement on the binarized edge image to obtain multidimensional size data, the method uses CAD design drawings to calculate the item-by-item deviation of the multidimensional size data and locate the image coordinates of N out-of-range points. The method includes: Multidimensional size measurement is performed on the binarized edge image based on subpixel edge fitting to obtain multidimensional size data, wherein the multidimensional size data includes the total length and width of the panel, the width of the process edge, and the V-cut groove spacing matrix between adjacent panels; Based on the composition of the multidimensional dimensional data, retrieve the multidimensional standard tolerance threshold from the CAD design drawings; The deviation of the multidimensional size data is calculated by using the multidimensional standard tolerance threshold mapping to obtain multiple discrete outliers; Spatial clustering is used to fuse the spatial coordinates of the multiple discrete outliers, and the image coordinates of the N outliers are output.

4. The PCB circuit board edge size detection method based on image recognition as described in claim 3, characterized in that, The method involves fusing the spatial coordinates of the multiple discrete outlier points based on spatial clustering to output the image coordinates of the N outlier points. Using a preset density radius as the neighborhood scale, the core point density reachability relationship is determined for the multiple discrete anomalies to obtain multiple candidate core points; Using the multiple candidate core points as seed points, the multiple discrete outlier points are traversed through the cluster expansion generation algorithm to aggregate density reachable points, resulting in N candidate clusters; The mean coordinates within each of the N candidate clusters are calculated, and the mean coordinates of the N fused clusters are output as the coordinates of the N out-of-range point images.

5. The PCB circuit board edge size detection method based on image recognition as described in claim 1, characterized in that, Based on the physical coordinates of the N panels, deviation types are identified, and N dimensional deviation types are output. The method includes: Construct a pixel physical space transformation matrix based on a standard calibration board; The pixel physical space transformation matrix is ​​used to perform millimeter-level physical coordinate mapping of the N out-of-range image coordinates to obtain the N panel physical coordinates; Based on the physical coordinates of the N panels, retrieve the design values ​​of the N panels from the CAD design drawing, and determine the deviation direction based on the physical coordinates of the N panels and the design values ​​of the N panels, and output the N deviation direction labels; The physical coordinates of the N panels are retrieved and matched with the preset functional area position feature library to classify the deviations of the excess points. After obtaining the N size deviation types, the deviation direction label and the N size deviation types are associated.

6. The PCB circuit board edge size detection method based on image recognition as described in claim 1, characterized in that, Based on the N physical coordinates of the panels and the N dimensional deviation types, a root cause analysis of process failures is performed to locate the faulty process step. The method includes: Using a preset neighborhood radius as the clustering scale, the physical coordinates of the N panels are clustered by defect region density to generate M spatially independent defect regions. Based on the coverage relationship of the M spatially independent defect regions to the N dimensional deviation types, M dominant deviation types are statistically output; Using the M dominant deviation types and M spatially independent defect regions as two-dimensional matching conditions, and in a pre-set process fault mapping rule library, M alternative fault links are matched and output. After combining the cross-regional correlation deviations of the M candidate fault links, the upstream common process links are traced and the faulty process links are linked.

7. The PCB circuit board edge size detection method based on image recognition as described in claim 1, characterized in that, After converting the N out-of-tolerance image coordinates into N panel physical coordinates, deviation defect unit identification is performed, and defective PCB units are identified on the integrated panel. The method includes: Based on predefined unit grid division rules, the physical coordinates of the N panels are projected onto the integrated panel to perform PCB single-unit area mapping and locate P target defect units; Machine-readable markings are imprinted on the non-functional area boundaries of the P target defective units to generate the defective PCB unit identifier.

8. The PCB circuit board edge size detection method based on image recognition as described in claim 1, characterized in that, Also includes: The high-resolution industrial camera is installed perpendicular to the inspection station, wherein the optical axis of the lens of the high-resolution industrial camera coincides with the normal of the panel plane of the inspection station. The high-resolution industrial camera is pre-deployed with a multi-angle ring LED light source. The high-resolution industrial camera is electrically connected to the optical sensor via a trigger signal line, forming a closed-loop acquisition and control circuit with a position synchronization accuracy of ≤ ±0.1mm.

9. A PCB circuit board edge dimension detection system based on image recognition, characterized in that, The system is used to execute the PCB circuit board edge size detection method based on image recognition as described in any one of claims 1-8, and the system comprises: Single-unit splicing module: Multiple PCB units are spliced ​​together on the PCB panel plane to form an integrated panel; Image acquisition module: After the integrated panel is conveyed to the inspection station via a conveyor belt, a high-resolution industrial camera is triggered by a light sensor to acquire images and obtain a panoramic image of the panel; Edge detection module: After preprocessing the panoramic image of the panel, the Canny edge detection algorithm is used to identify the outer contour of the PCB and generate a binarized edge image; Deviation calculation module: After performing multi-dimensional size measurement on the binarized edge image to obtain multi-dimensional size data, the module uses CAD design drawings to calculate the deviation of each item of the multi-dimensional size data and locate the image coordinates of N out-of-range points; Defect Unit Identification Module: After converting the N out-of-tolerance image coordinates into N panel physical coordinates, the module identifies deviation defect units and marks the defective PCB units on the integrated panel. Independent scrapping module: Based on the defective PCB unit identifier, the defective unit is independently scrapped during the integrated panelization and board separation process, and a defect-free PCB unit board is output.

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