Semiconductor device

Abstract

The purpose of the present invention is to provide a semiconductor device capable of suppressing a change in the responsiveness of a switching element even if the driving capability for driving the switching element is changed. A semiconductor device (1) according to an embodiment of the present invention is provided with: an IGBT (121); a state detection unit (113) that detects the operating state of the IGBT (121); a switching time adjustment unit (111) that adjusts the switching time of the IGBT (121) on the basis of the operating state detected by the state detection unit (113); and a drive current adjustment unit (112) that adjusts a drive current (Idv) for driving the IGBT (121) on the basis of the operating state detected by the state detection unit (113).

Description

Technical Field

[0001] This invention relates to a semiconductor device having a switching element. Background Technology

[0002] Patent documents 1 to 3 disclose the following technology: when a switching element is turned on or off, the driving capability used to drive the switching element is changed according to the load current supplied by the switching element to the load.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2016-158361

[0006] Patent Document 2: Japanese Patent Application Publication No. 2020-136874

[0007] Patent Document 3: International Publication No. 2017 / 150036 Summary of the Invention

[0008] The problem the invention aims to solve

[0009] When the drive capability of a switching element is varied according to the load current, the drive capability is set to be higher as the load current increases. Therefore, the rate of change of voltage (dv / dt) of the switching element during turn-on or turn-off becomes higher. As such, when the drive capability of the switching element is varied according to the load current, the responsiveness of the switching element changes, thus increasing the likelihood that the operation of the device with this switching element will become unstable.

[0010] The object of the present invention is to provide a semiconductor device that can suppress changes in the responsiveness of a switching element even when the driving capability used to drive the switching element is changed.

[0011] Solution for solving the problem

[0012] To achieve the above objectives, a semiconductor device according to one aspect of the present invention includes: a switching element; a state detection unit that detects an operating state of the switching element; a switching time adjustment unit that adjusts the switching time of the switching element based on the operating state detected by the state detection unit; and a drive current adjustment unit that adjusts the drive current for driving the switching element based on the operating state detected by the state detection unit.

[0013] The effects of the invention

[0014] According to one aspect of the invention, even if the driving capability used to drive the switching element is changed, the change in the responsiveness of the switching element can be suppressed. Attached Figure Description

[0015] Figure 1 This is a block diagram illustrating an example of the general structure of a semiconductor device according to a first embodiment of the present invention.

[0016] Figure 2 This is a graph showing the relationship between load current and voltage change rate of a switching element in the prior art.

[0017] Figure 3 This is a graph showing the relationship between load current and conduction time of a switching element in the prior art.

[0018] Figure 4 This is a diagram illustrating a semiconductor device according to a first embodiment of the present invention, and is a timing diagram schematically showing an example of the operating waveform when the switching element is turned on.

[0019] Figure 5 This is a block diagram (1) illustrating an example of the general structure of a semiconductor device according to a second embodiment of the present invention.

[0020] Figure 6 This is a block diagram (2) illustrating an example of the general structure of a semiconductor device according to a second embodiment of the present invention.

[0021] Figure 7 This is a diagram illustrating a semiconductor device according to a second embodiment of the present invention, and is a timing diagram schematically showing an example of the operating waveform when the switching element is turned on.

[0022] Figure 8 This is a block diagram illustrating an example of the general structure of a semiconductor device according to a third embodiment of the present invention.

[0023] Figure 9 This is a block diagram (1) illustrating an example of the general structure of a semiconductor device according to a fourth embodiment of the present invention.

[0024] Figure 10 This is a block diagram (2) illustrating an example of the general structure of a semiconductor device according to a fourth embodiment of the present invention.

[0025] Figure 11 This diagram illustrates a semiconductor device according to a fourth embodiment of the present invention, and is a timing diagram schematically showing the input signal and the output signal output from the switching time adjustment unit. Detailed Implementation

[0026] The embodiments of the present invention illustrate apparatuses and methods for embodying the technical concept of the present invention. The technical concept of the present invention does not define the material, shape, structure, or arrangement of structural components as described below. The technical concept of the present invention can be modified in various ways within the technical scope defined by the claims.

[0027] [First Implementation]

[0028] use Figures 1 to 4 The semiconductor device of the first embodiment of the present invention will be described below. The semiconductor device of this embodiment and the embodiments described below can, for example, be applied to an intelligent power module (IPM) that integrates a semiconductor chip having a power semiconductor element (e.g., an insulated gate bipolar transistor) for power conversion and an integrated circuit for driving or protecting the semiconductor chip into a single package. Hereinafter, "insulated gate bipolar transistor" will sometimes be abbreviated as "IGBT" (Insulated Gate Bipolar Transistor).

[0029] 1-1. Structure of a semiconductor device:

[0030] use Figure 1 The outline structure of the semiconductor device in this embodiment will be explained. Figure 1 This is a block diagram illustrating an example of the general structure of the semiconductor device 1 according to this embodiment.

[0031] like Figure 1 As shown, the semiconductor device 1 includes a semiconductor control circuit 11 and a semiconductor element 12. The semiconductor element 12 has an IGBT 121 and a state detection element 122. The semiconductor element 12 may also have a freewheeling diode connected in reverse parallel with the IGBT 121. The semiconductor element 12 is, for example, composed of a semiconductor chip in which the IGBT 121 and the state detection element 122 are formed.

[0032] In this way, semiconductor device 1 includes IGBT 121 (an example of a switching element). The operating state of IGBT 121 includes, for example, the level of current supplied by IGBT 121 to the load device (not shown) that is being driven, or the temperature at which IGBT 121 is operating. Therefore, the state detection element 122 may be, for example, a current detection element that detects the current flowing in IGBT 121, or a temperature detection element that detects the temperature of IGBT 121.

[0033] When the semiconductor device 1 is, for example, a power conversion device and the IGBT 121 forms the upper arm of the power conversion device, the load device is connected to the emitter of the IGBT 121. Conversely, when the IGBT 121 forms the lower arm of the power conversion device, the load device is connected to the collector of the IGBT 121. The gate of the IGBT 121 is connected to the gate input terminal Tgi provided on the semiconductor element 12. The output terminal of the state detection element 122 is connected to the detection terminal Tdo provided on the semiconductor element 12.

[0034] like Figure 1 As shown, the semiconductor control circuit 11 includes a switching time adjustment unit 111, a drive current adjustment unit 112, and a status detection unit 113. Therefore, the semiconductor device 1 includes the switching time adjustment unit 111, the drive current adjustment unit 112, and the status detection unit 113. The semiconductor control circuit 11 is an integrated circuit for drive protection functions used to drive or protect the IGBT 121.

[0035] The input terminal of the state detection unit 113 is connected to the detection signal input terminal Tdi provided in the semiconductor control circuit 11. The detection signal input terminal Tdi is connected to the detection terminal Tdo provided in the semiconductor element 12. Therefore, the state detection unit 113 uses, for example, the detection signal Sos input from the state detection element 122 to detect the operating state of the IGBT 121. The state detection unit 113 outputs a state detection signal Sosd detected using the detection signal Sos.

[0036] The switching time adjustment unit 111 has two input terminals. One of these input terminals is connected to the signal input terminal Tic provided in the semiconductor control circuit 11, and the other of these input terminals is connected to the output terminal of the state detection unit 113. The switching time adjustment unit 111 adjusts the switching time of the IGBT 121 according to the operating state of the IGBT 121 detected by the state detection unit 113. The switching time adjustment unit 111 adjusts the switching time according to the signal level of the state detection signal Sosd input from the state detection unit 113. Although details will be described later, when the state detection unit 113 detects that the IGBT 121 is in a predetermined operating state, the switching time adjustment unit 111 delays the input signal Sin input via the signal input terminal Tic by a predetermined time before outputting it. Thus, by delaying the input signal Sin by a predetermined time by the switching time adjustment unit 111, the semiconductor device 1 can make the switching time approximately the same length regardless of the operating state of the IGBT 121.

[0037] The drive current adjustment unit 112 has two input terminals. One of these input terminals is connected to the output terminal of the switching time adjustment unit 111, and the other input terminal is connected to the output terminal of the state detection unit 113. The drive current adjustment unit 112 adjusts the drive current Idv for driving the IGBT 121 based on the operating state of the IGBT 121 detected by the state detection unit 113. The drive current adjustment unit 112 also adjusts the drive current Idv based on the signal level of the state detection signal Sosd input from the state detection unit 113. When the IGBT 121 is in an operating state where the input signal Sin is delayed by a predetermined time in the switching time adjustment unit 111, the drive current adjustment unit 112 adjusts the amount of drive current Idv to, for example, increase. Therefore, the semiconductor device 1 can suppress changes in the responsiveness of the IGBT 121 independently of the amount of load current supplied by the IGBT 121 to the load device.

[0038] 1-2. Operation of semiconductor devices:

[0039] Reference Figure 1 And use Figures 2 to 4 The operation of the semiconductor device 1 in this embodiment will be explained. Furthermore, the problems with the prior art will also be explained during the explanation of the operation of the semiconductor device 1. Figures 2 to 4 In this context, the operating state of the IGBT will be illustrated using the current flowing through the IGBT (i.e., the load current supplied by the IGBT to the load) as an example.

[0040] Figure 2 This is a graph illustrating an example of the relationship between the load current and the rate of voltage change when an IGBT is turned on. Figure 2 The horizontal axis of the graph shown represents the load current, and the vertical axis represents the voltage change rate (dv / dt).

[0041] When the load current is low, for example, less than 15% of the rated current Icr, the IGBT is driven with low drive capability compared to a normal current where the load current is greater than, for example, 15% of the rated current Icr but less than 100%. In this case, such as Figure 2 As shown, the voltage change rate of the IGBT decreases at low current compared to normal current.

[0042] Figure 3 This is a graph illustrating an example of the relationship between load current and conduction time in an IGBT. Figure 3 The horizontal axis of the graph shown represents the load current, and the vertical axis represents the conduction time.

[0043] When the load current is low, for example, less than 15% of the rated current Icr, the IGBT is driven with low drive capability compared to a normal current where the load current is greater than, for example, 15% of the rated current Icr but less than 100%. In this case, such as Figure 3 As shown, the conduction time of the IGBT becomes longer at low current compared to the normal current.

[0044] Although the diagram is omitted, when driving the IGBT with the same drive capability at low current as at normal current, the IGBT's voltage change rate increases sharply as the load current decreases. Therefore, when driving the IGBT with the same drive capability at low current as at normal current, the IGBT's tolerance to noise signals decreases, thus increasing the likelihood of malfunction. Therefore, as... Figure 2 As shown, the driving capability of the IGBT is reduced at low current compared to normal current, thereby reducing the possibility of malfunction.

[0045] However, if used Figure 3 As explained, when driving an IGBT with reduced drive capability at low current compared to normal current, the conduction time at low current becomes longer. As the IGBT's conduction time changes accordingly with the load current, its responsiveness also changes, thus increasing the likelihood of unstable operation in devices equipped with IGBTs. Therefore, it is difficult to simultaneously suppress malfunctions caused by a decrease in the IGBT's tolerance to noise signals and reduce operational instability caused by changes in the IGBT's responsiveness.

[0046] Figure 4 This is a timing diagram schematically showing a portion of the operating waveforms of the IGBT 121 included in the semiconductor device 1 of this embodiment and a conventional IGBT when they are turned on. Figure 4 The upper part of the image shows the operating waveforms of the IGBT 121 and previous IGBTs. Figure 4 The middle section shows the operating waveform of a previous IGBT. Figure 4 The lower part of the image shows the operating waveform of the IGBT121. Figure 4 In this context, "Sin" represents the input signal to the semiconductor control circuit 11 or a conventional semiconductor control circuit. Figure 4 In this context, "Ic" represents the collector current (i.e., the load current supplied to the load device) of the IGBT 121 or previous IGBTs. Figure 4 In this context, "Sdy" represents the delayed signal obtained by delaying the input signal.

[0047] In addition, Figure 4 The upper part of the diagram shows the... Figure 2 and Figure 3The diagram illustrates the operating waveforms when the drive current at low current conditions is used to drive the IGBT 121 or a conventional IGBT. Figure 4 The middle part of the diagram shows the... Figure 2 and Figure 3 The diagram illustrates the operating waveform of a conventional IGBT driven by a drive current under normal operating conditions. Figure 4 The lower part of the diagram shows adjusting the switching time and in Figure 2 and Figure 3 The diagram illustrates the operating waveform when the drive current is used to drive the IGBT 121 under normal operating conditions. Figure 4 In the operating waveform shown from the upper to the lower part, the DC voltage applied to IGBT 121 or a conventional IGBT, the emitter-collector voltage when IGBT 121 or a conventional IGBT is in the off state, the load impedance, and the load current supplied to the load are set to be common. Additionally, in Figure 4 In the lower part of the action waveform shown, to be consistent with Figure 4 The upper part of the IGBT 121 is driven by a driving current that is twice that of the upper part.

[0048] like Figure 4 As shown in the upper and middle sections, in conventional IGBTs, the switching time ton1 at normal current is, for example, 90% of the switching time ton0 at low current. The peak current during collector current Ic overshoot at normal current is significantly larger than the peak current during collector current Ic overshoot at low current by an amount equivalent to the shorter switching time. Therefore, compared to low current, the tolerance of conventional IGBTs to noise signals is reduced at normal current. Figure 4 In this context, the time from when the input signal Sin is input until the collector current Ic reaches 90% of the target value is set as the switching time of IGBT 121 or conventional IGBTs.

[0049] In the semiconductor device 1 of this embodiment, the switching time adjustment unit 111 (see reference) Figure 1 For example, when the current is low, the input signal Sin is output to the drive current adjustment unit 112 without delay. Therefore, as... Figure 4 As shown in the upper part, the switching time of IGBT 121 in this embodiment is the same as that of conventional IGBTs, which is switching time ton0.

[0050] On the other hand, in the semiconductor device 1 of this embodiment, the switching time adjustment unit 111 outputs the input signal Sin to the drive current adjustment unit 112 in a delayed manner, for example, during normal current operation. Therefore, as Figure 4As shown in the lower part, in the IGBT 121 of this embodiment, when the input time of the delayed signal Sdy, which serves as the trigger for providing the drive current Idv, is taken as a reference, the switching time of the IGBT 121 is the switching time ton1, which is approximately the same length as the switching time of a conventional IGBT. However, the delayed signal Sdy is a signal obtained by delaying the input signal Sin by a delay time Tdy in the switching time adjustment unit 111. Therefore, the switching time ton3 of the IGBT 121 under normal current is approximately the same length as the switching time ton0 of the IGBT 121 under low current.

[0051] In this way, in semiconductor device 1, the voltage change rate of IGBT 121 is larger at normal current compared to low current. Therefore, the rise time from the start of providing drive current Idv to the collector current Ic of IGBT 121 reaching the target value is shortened. Semiconductor device 1 compensates for this shortened rise time by adjusting the delay time of the input signal Sin to match the voltage change rate of IGBT 121 according to each load current, thereby improving the tolerance of the input signal Sin to noise signals and suppressing the decrease in the responsiveness of IGBT 121.

[0052] Furthermore, regarding IGBT 121, the switching time becomes slower when the operating temperature increases. Therefore, when the operating state of IGBT 121 is at its operating temperature, the switching time adjustment unit 111 is configured to adjust the switching time in such a way that the higher the operating temperature, the shorter the delay time.

[0053] As described above, the semiconductor device 1 of this embodiment includes: an IGBT 121; a state detection unit 113 that detects the operating state of the IGBT 121; a switching time adjustment unit 111 that adjusts the switching time of the IGBT 121 according to the operating state detected by the state detection unit 113; and a drive current adjustment unit 112 that adjusts the drive current Idv for driving the IGBT 121 according to the operating state detected by the state detection unit 113.

[0054] With such a structure, the semiconductor device 1 can suppress changes in the responsiveness of the switching element even if the driving capability used to drive the switching element is changed.

[0055] [Second Implementation]

[0056] use Figures 5 to 7 The semiconductor device of the second embodiment of the present invention will be described below.

[0057] 2-1. Structure of a semiconductor device:

[0058] use Figure 5 and Figure 6 The outline structure of the semiconductor device 2 in this embodiment will be explained. Figure 5 and Figure 6 This is a block diagram illustrating an example of the general structure of the semiconductor device 2 according to this embodiment. Figure 5 The diagram omitting a detailed illustration of the drive current adjustment unit 212 included in the semiconductor device 2. Figure 6 The specific structure of the delay time adjustment circuit 211AC included in the semiconductor device 2 is omitted from the illustration. Regarding the semiconductor device 2 of this embodiment, structural elements that perform the same functions as the structural elements of the semiconductor device 1 of the first embodiment are labeled with the same reference numerals, and their descriptions are omitted.

[0059] like Figure 5 and Figure 6 As shown, the semiconductor device 2 of this embodiment includes a semiconductor control circuit 21 and a semiconductor element 22. The semiconductor element 22 includes an IGBT 221 and a current sensing element 222. Therefore, the semiconductor device 2 includes an IGBT 221 (an example of a switching element) and a current sensing element 222. The current sensing element 222 detects a sensing current Is used to detect the load current IL supplied by the IGBT 221 to the load. The semiconductor element 22 may also have a freewheeling diode connected in reverse parallel with the IGBT 221. The semiconductor element 22 is, for example, composed of a semiconductor chip on which the IGBT 221 and the current sensing element 222 are formed.

[0060] The semiconductor control circuit 21 included in the semiconductor device 2 includes a switching time adjustment unit 211, a drive current adjustment unit 212, and a status detection unit 213. The semiconductor control circuit 21 is an integrated circuit for drive protection functions that drives or protects the IGBT 221.

[0061] The state detection unit 213 detects the operating state of the IGBT 221. The state detection unit 213 includes a current detection unit 213ID, which detects the magnitude of the load current IL corresponding to the probe current Is detected by the current sensing element 222 to determine the operating state of the IGBT 221. The current detection unit 213ID includes: a current-to-voltage conversion circuit 213a (an example of a conversion circuit) that converts the probe current Is into a probe voltage Vs; and a buffer circuit 213b that outputs the probe voltage Vs output from the current-to-voltage conversion circuit 213a as a current detection signal Ss having a signal level corresponding to the magnitude of the load current IL.

[0062] The current-to-voltage conversion circuit 213a has a resistor element R213. One terminal of the resistor element R213 is connected to the detection signal input terminal Tdi. The other terminal of the resistor element R213 is connected to the reference potential terminal (e.g., ground terminal) of the semiconductor control circuit 21. The current-to-voltage conversion circuit 213a outputs the voltage generated between the two terminals of the resistor element R213 as the detection voltage Vs as the voltage generated by the detection current Is flowing from the current detection element 222 to the buffer circuit 213b. The buffer circuit 213b is constructed, for example, by an operational amplifier. One terminal of the resistor element R213 is connected to the non-inverting input terminal (+) of the buffer circuit 213b. The inverting input terminal (-) of the buffer circuit 213b is connected to the output terminal of the buffer circuit 213b. Therefore, the buffer circuit 213b functions as a voltage follower circuit, outputting a current detection signal Ss with the same voltage level as the detection voltage Vs.

[0063] The switching time adjustment unit 211 includes a NOT gate 211a, a transistor 211b, a delay time adjustment circuit 211AC, a buffer circuit 211e, and a NOT gate 211f.

[0064] The input terminal of NOT gate 211a is connected to the signal input terminal Tic provided in the semiconductor control circuit 21. The output terminal of NOT gate 211a is connected to transistor 211b. Transistor 211b is, for example, an N-type MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The output terminal of NOT gate 211a is connected to the gate of transistor 211b. The source of transistor 211b is connected to the reference potential terminal (e.g., ground terminal) of the semiconductor control circuit 21. The drain of transistor 211b is connected to the delay time adjustment circuit 211AC.

[0065] The input terminal of the NOT gate 211f is connected to the output terminal of the buffer circuit 213b. The output terminal of the NOT gate 211f is connected to the delay time adjustment circuit 211AC. The NOT gate 211f inverts the signal level of the current detection signal Ss input from the buffer circuit 213b and outputs it to the delay time adjustment circuit 211AC.

[0066] The delay time adjustment circuit 211AC adjusts the delay time of the input signal Sin input from an external source (e.g., a control device (not shown) that controls the semiconductor control circuit 21) based on the signal level of the current detection signal Ss input from the current detection unit 213ID. The delay time adjustment circuit 211AC includes a variable constant current source 211c, a delay time changing unit 211d, and a buffer circuit 211e.

[0067] The variable constant current source 211c operates using the power supply used to drive the delay time adjustment circuit 211AC. The output terminal of the NOT gate 211f is connected to the current control terminal of the variable constant current source 211c. The variable constant current source 211c outputs a constant current of different values ​​based on the signal level (e.g., voltage level) of the current detection signal Ss input from the buffer circuit 213b. More specifically, the variable constant current source 211c outputs a constant current of different values ​​based on the signal level (e.g., voltage level) of the current detection signal Ss input from the buffer circuit 213b and inverted by the NOT gate 211f. The variable constant current source 211c, for example, has the same structure as the variable constant current source 212VC provided in the drive current adjustment unit 212, described later. The lower the signal level of the inverted signal input from the NOT gate 211f (i.e., the higher the signal level of the current detection signal Ss), the smaller the constant current value output by the variable constant current source 211c. In addition, the higher the signal level of the inverted signal input to the variable constant current source 211c from the NOT gate 211f (i.e., the lower the signal level of the current detection signal Ss), the larger the output constant current value.

[0068] The output terminal of the variable constant current source 211c is connected to the drain of the transistor 211b and the delay time adjustment unit 211d. The delay time adjustment unit 211d has a resistor R211d and a capacitor C211d. The delay time adjustment circuit 211AC adjusts the delay time of the input signal Sin by using the amount of current input from the variable constant current source 211c to the delay time adjustment unit 211d and a time constant determined by the resistance value of the resistor R211d and the capacitance value of the capacitor C211d. This time constant is a fixed value; therefore, the delay time adjustment circuit 211AC outputs a delayed signal Sdy obtained by delaying the input signal Sin according to the current value of the output current Iout output from the variable constant current source 211c.

[0069] One terminal of the resistor R211d, located in the delay time changing section 211d, is connected to the output terminal of the variable constant current source 211c and the drain of the transistor 211b. The other terminal of the resistor R211d is connected to one electrode of the capacitor C211d. The other electrode of the capacitor C211d is connected to the reference potential terminal (e.g., ground terminal) of the semiconductor control circuit 21. The input terminal of the buffer circuit 211e is connected to the output terminal of the delay time changing section 211d (the connection between the other terminal of the resistor R211d and one electrode of the capacitor C211d). The buffer circuit 211e, like the buffer circuit 213b, forms a voltage follower circuit. The output terminal of the buffer circuit 211e is connected to the input terminal of the drive current adjustment section 212. Thus, the buffer circuit 211e outputs the delayed signal Sdy input from the delay time changing section 211d to the drive current adjustment section 212 without changing the signal level.

[0070] The higher the signal level (i.e., voltage level) of the current detection signal Ss input from the current detection unit 213ID to the variable constant current source 211c, the smaller the output current Iout. Conversely, the lower the signal level (i.e., voltage level) of the current detection signal Ss input from the current detection unit 213ID to the variable constant current source 211c, the larger the output current Iout. In other words, the smaller the load current IL supplied by the IGBT 221 to the load device, the larger the output current Iout of the variable constant current source 211c. Conversely, the larger the load current IL supplied by the IGBT 221 to the load device, the smaller the output current Iout of the variable constant current source 211c.

[0071] When the input signal Sin switches from a low level to a high level, transistor 211b changes from an on state to an off state, thus disconnecting the output terminal of the variable constant current source 211c from the reference potential terminal. Consequently, the output current Iout from the variable constant current source 211c flows to the delay time changing unit 211d, and the delay signal Sdy output from the delay time changing unit 211d rises. The rise time of the delay signal Sdy depends on the value of the output current Iout from the variable constant current source 211c; the larger the current value, the shorter the rise time of the delay signal Sdy.

[0072] Furthermore, when the signal level of the input signal Sin switches from high to low, transistor 211b changes from an off state to an on state, thus connecting the output terminal of the variable constant current source 211c to the reference potential terminal. As a result, the output current Iout from the variable constant current source 211c flows to the reference potential terminal. Simultaneously, the capacitor C211d provided in the delay time changing unit 211d discharges, and the delayed signal Sdy output from the delay time changing unit 211d decreases. The greater the amount of output current Iout flowing from the variable constant current source 211c to the reference potential terminal, the faster the charge charged in capacitor C211d is removed, and therefore, the shorter the discharge time of capacitor C211d. Therefore, the greater the amount of current, the shorter the fall time of the delayed signal Sdy. The delay time changing unit 211d functions to generate a delayed signal Sdy that is delayed relative to the input signal Sin, and also functions to suppress oscillations generated in the output current Iout from the variable constant current source 211c.

[0073] The moment the signal level of the input signal Sin switches is the input moment of the input signal Sin. The drive current adjustment unit 212 generates the drive current Idv by the input delay signal Sdy. Therefore, the time from when the input signal Sin is input to the switching time adjustment unit 211 to when the drive current adjustment unit 212 outputs the delay signal Sdy to start providing the drive current Idv to the IGBT 221 is the delay time. The moment when the drive current Idv is started to be provided to the IGBT 221 is, for example, the time when the current value of the collector current (i.e., the load current IL) flowing in the IGBT 221 reaches 10% of the target value.

[0074] In this way, the switching time adjustment unit 211 delays the input signal Sin based on the magnitude of the load current IL detected by the current detection unit 213ID. Therefore, the switching time adjustment unit 211 adjusts the switching time of the IGBT 221 according to the magnitude of the load current IL detected by the current detection unit 213ID as the operating state of the IGBT 221. Furthermore, the variable constant current source 211c provided in the delay time adjustment circuit 211AC can continuously change the amount of the output current Iout according to the continuous change in the signal level (i.e., voltage level) of the current detection signal Ss input from the current detection unit 213ID. Therefore, the switching time adjustment unit 211 continuously adjusts the switching time according to the change in the detected current Is.

[0075] like Figure 6As shown, the drive current adjustment unit 212 includes an operational amplifier 212a, transistors 212b, 212c, 212e, 212f, 212g, and a resistor element 212d. Transistor 212c is, for example, an N-type MOSFET, and transistors 212b, 212e, 212f, and 212g are, for example, P-type MOSFETs.

[0076] A current mirror circuit 212CM is formed by transistors 212e and 212f. The source of transistor 212e is connected to the power supply terminal that provides power for driving the gate drive circuit 212DC. The drain of transistor 212e is connected to the gates of transistors 212e and 212f, and the drain of transistor 212c.

[0077] The source of transistor 212f is connected to a power supply terminal that provides power for driving the gate drive circuit 212DC. The drain of transistor 212f is connected to the source of transistor 212g. The drain of transistor 212g is connected to a reference potential terminal (e.g., ground terminal) of the semiconductor control circuit 21. The gate of transistor 212g is connected to the output terminal of the switching time adjustment unit 211 (specifically, the output terminal of the buffer circuit 211e). The connection between the drain of transistor 212f and the source of transistor 212g is connected to the current output terminal Toc. The connection between the drain of transistor 212f and the source of transistor 212g is the output terminal of the drive current adjustment unit 212.

[0078] A variable constant current source 212VC is constructed from operational amplifier 212a, transistors 212b and 212c, and resistor 212d. The non-inverting input terminal (+) of operational amplifier 212a, which serves as the current control terminal of the variable constant current source 212VC, is connected to the output terminal of current detection unit 213ID. The inverting input terminal (-) of operational amplifier 212a is connected to the source of transistor 212c and one terminal of resistor 212d. The output terminal of operational amplifier 212a is connected to the gate of transistor 212c and the source of transistor 212b. The drain of transistor 212b is connected to the reference potential terminal (e.g., ground) of semiconductor control circuit 21. The gate of transistor 212b is connected to the output terminal of switching time adjustment unit 211 (specifically, the output terminal of buffer circuit 211e). The other terminal of resistor 212d is connected to the reference potential terminal (e.g., ground) of semiconductor control circuit 21.

[0079] The variable constant current source 212VC controls the transistor 212c so that a constant current flows from the current mirror circuit 212CM, corresponding to the voltage level of the current detection signal Ss input to the non-inverting input terminal (+) of the operational amplifier 212a.

[0080] When the delay signal Sdy input from the switching time adjustment unit 211 is high, transistor 212b is off. Therefore, the variable constant current source 212VC operates by causing a constant current corresponding to the voltage level of the current detection signal Ss to flow into transistor 212c. Conversely, when the delay signal Sdy input from the switching time adjustment unit 211 is high, transistor 212g is off. Therefore, the current mirror circuit 212CM outputs the current corresponding to the current flowing from the variable constant current source 212VC into transistor 212c as the drive current Idv (i.e., the gate current) to the gate of IGBT 221.

[0081] The output voltage of operational amplifier 212a changes according to the voltage level of the current detection signal Ss. Therefore, the drive current Idv changes according to the voltage level of the current detection signal Ss. The current detection signal Ss is a signal obtained by converting the detection current Is detected by current detection element 222 into a current-to-voltage signal; therefore, the current detection signal Ss changes according to the change in the detection current Is. The detection current Is is a continuously changing current. Therefore, the drive current adjustment unit 212 continuously adjusts the drive current Idv according to the change in the detection current Is.

[0082] The voltage level of the current detection signal Ss output from the current detection unit 213ID is based on the magnitude of the load current IL supplied by the IGBT 221 to the load device. Therefore, the drive current adjustment unit 212 can supply a drive current Idv to the gate of the IGBT 221 corresponding to the magnitude of the load current IL supplied by the IGBT 221 to the load device. In this way, the drive current adjustment unit 212 adjusts the drive current Idv for driving the IGBT 221 according to the magnitude of the load current IL detected by the current detection unit 213ID as the operating state of the IGBT 221.

[0083] Furthermore, the drive current adjustment unit 212 begins to provide drive current Idv to IGBT 221 by receiving a delay signal Sdy from the switching time adjustment unit 211. Therefore, the drive current adjustment unit 212 provides drive current Idv to IGBT 221 that is delayed relative to the input time of the input signal Sin, based on the current value of the load current IL provided by IGBT 221 to the load device. In this way, the drive current adjustment unit 212 has a gate drive circuit 212DC (an example of a drive circuit), which, when a delay signal Sdy obtained by delaying the input signal Sin is input from the delay time adjustment circuit 211AC, drives IGBT 221 with a drive current Idv of a current magnitude corresponding to the signal level of the current detection signal Ss.

[0084] 2-2. Operation of semiconductor devices:

[0085] Reference Figure 5 and Figure 6 And use Figure 7 The operation of the semiconductor device 2 in this embodiment will be explained. Figure 7 This is a timing diagram that schematically shows a portion of the operating waveform of semiconductor device 2. Figure 7 In this context, "Sin" indicates the input signal input to the switching time adjustment unit 211. Figure 7 In this context, "Sinv" represents the inverted signal output from the NOT gate 211a provided in the switching time adjustment section 211. Figure 7 In this context, "Sdy" represents the delayed signal output from the delay time adjustment circuit 211AC. Figure 7 In this context, "IL" represents the load current supplied by the IGBT 221 to the load device.

[0086] like Figure 7 As shown, when the input signal Sin rises, the inverting signal Sinv falls. When the voltage level of the inverting signal Sinv becomes lower than the threshold voltage of transistor 211b, transistor 211b becomes off, and therefore, the output current Iout from the variable constant current source 211c flows to the delay time changing section 211d. As a result, the signal level of the delay signal Sdy rises.

[0087] When the load current IL supplied by IGBT 221 to the load device is at its minimum within the available range (i.e., when the target value is at its minimum), the signal level of the current sensing signal Ss is at its minimum within the variable range. Therefore, the amount of output current Iout from the variable constant current source 211c provided in the delay time adjustment circuit 211AC is at its maximum within the variable range. Thus, as Figure 7 As shown in the waveform Sdyn, the delayed signal Sdy becomes the signal that rises fastest within a variable range and is delayed by a delay time Tdyn relative to the input signal Sin. When the voltage level of the delayed signal Sdy becomes higher than the threshold voltage of transistors 212b and 212g, transistors 212b and 212g become off, and therefore, the drive current Idv flows to the gate of IGBT 221.

[0088] At this time, the signal level of the current detection signal Ss is at its lowest within the variable range. Therefore, the current flowing from the variable constant current source 212VC of the gate drive circuit 212DC to the transistor 212c in the drive current adjustment unit 212 is at its minimum within the variable range. Therefore, the current supply capability of the drive current adjustment unit 212 is at its lowest. Figure 7As shown in the lower waveform ILn, the rise time of the load current IL is the longest within the variation range. As a result, the switching time of the IGBT 221 at low current is called the switching time SWT.

[0089] As the load current IL of the IGBT 221 gradually increases, the signal level of the current sensing signal Ss increases. Therefore, as... Figure 7 As shown in the waveform Sdyx, the delayed signal Sdy becomes the slowest rising signal within its variable range, delayed by a delay time Tdyx relative to the input signal Sin. The delay time Tdyx is the longest time within the variable range of the delayed signal Sdy.

[0090] At this time, the signal level of the current detection signal Ss is at its highest within the variable range. Therefore, the current flowing from the variable constant current source 212VC of the gate drive circuit 212DC in the drive current adjustment unit 212 to the transistor 212c is at its maximum within the variable range. Therefore, the current supply capability of the drive current adjustment unit 212 is at its highest. Figure 7 As shown in the lower waveform ILx, the rise time of the load current IL is the shortest within the variation range. As a result, the switching time of the IGBT 221 at normal current is the same as that at low current, which is called the switching time SWT.

[0091] like Figure 7 As shown by the bidirectional arrows, the rise time of the delayed signal Sdy changes continuously according to the continuous change of the load current IL (i.e., the continuous change of the signal level of the current sensing signal Ss). Therefore, the switching time of the IGBT 221 also changes continuously according to the continuous change of the load current IL (i.e., the continuous change of the signal level of the current sensing signal Ss).

[0092] As described above, the semiconductor device 2 of this embodiment includes: an IGBT 221; a state detection unit 213 that detects the operating state of the IGBT 221; a switching time adjustment unit 211 that adjusts the switching time of the IGBT 221 according to the operating state detected by the state detection unit 213; and a drive current adjustment unit 212 that adjusts the drive current Idv for driving the IGBT 221 according to the operating state detected by the state detection unit 213.

[0093] With such a structure, the semiconductor device 2 can suppress changes in the responsiveness of the switching element even if the driving capability used to drive the switching element is changed.

[0094] [Third Implementation Method]

[0095] use Figure 8 The semiconductor device of the third embodiment of the present invention will be described below. Figure 8This is a block diagram illustrating an example of the general structure of the semiconductor device 3 according to this embodiment. Regarding the semiconductor device 3 of this embodiment, structural elements that perform the same functions and effects as the structural elements of the semiconductor device 2 of the second embodiment described above are labeled with the same reference numerals and their descriptions are omitted.

[0096] 3-1. Structure of a semiconductor device:

[0097] like Figure 8 As shown, the semiconductor device 3 of this embodiment includes a semiconductor control circuit 31 and a semiconductor element 22. The semiconductor control circuit 31 includes a switching time adjustment unit 311, a drive current adjustment unit 312, and a status detection unit 313.

[0098] The status detection unit 313 has a current detection unit 313ID, which detects the magnitude of the load current IL corresponding to the detection current Is detected by the current detection element 222 to determine the operating status of the IGBT 221.

[0099] The current detection unit 313ID includes: a current-to-voltage conversion circuit 313a (an example of a conversion circuit) that converts the detected current Is into a detected voltage Vs; and a comparator 313b that outputs a current detection signal Ss with a signal level based on a comparison result obtained by comparing the detected voltage Vs output from the current-to-voltage conversion circuit 313a with a reference voltage Vr. Furthermore, the current detection unit 313ID includes a reference voltage generation circuit 313c that generates the reference voltage Vr.

[0100] The current-to-voltage conversion circuit 313a includes a resistive element R313. The current-to-voltage conversion circuit 313a outputs the voltage generated between the two terminals of the resistive element R313 as a detected voltage Vs as a current generated by the flow of the detected current Is input from the current sensing element 222 to the comparator 313b. The current-to-voltage conversion circuit 313a has the same structure as the current-to-voltage conversion circuit 213a in the second embodiment described above, except that the output destination of the detected voltage Vs is the comparator 313b.

[0101] The reference voltage generation circuit 313c is, for example, composed of a DC voltage source. The positive terminal of the reference voltage generation circuit 313c is connected to the input terminal of the comparator 313b, and the negative terminal of the reference voltage generation circuit 313c is connected to the reference potential terminal (e.g., ground terminal) of the semiconductor control circuit 31.

[0102] Comparator 313b is constructed, for example, by an operational amplifier. The non-inverting input terminal (+) of comparator 313b is connected to the output terminal of current-to-voltage conversion circuit 313a (specifically, one terminal of resistor R313). The inverting input terminal (-) of comparator 313b is connected to the positive side of reference voltage generation circuit 313c. Comparator 313b outputs a low-level current detection signal Ss when the probe voltage Vs is lower than the reference voltage Vr. Conversely, comparator 313b outputs a high-level current detection signal Ss when the probe voltage Vs is higher than the reference voltage Vr.

[0103] When the sensing current Is increases, the sensing voltage Vs increases. The larger the load current IL, the larger the sensing current Is. Therefore, comparator 313b outputs a low-level current detection signal Ss when the load current IL is smaller than the current corresponding to the reference voltage Vr. Comparator 313b outputs a high-level current detection signal Ss when the load current IL is larger than the current corresponding to the reference voltage Vr. The current corresponding to the reference voltage Vr is the current that serves as the boundary between the current at low current (described in the first embodiment above) and the current at normal current. For example, the current corresponding to the reference voltage Vr is 15% of the rated current of the IGBT 221.

[0104] The switching time adjustment unit 311 has an AND gate 311a and a delay time adjustment circuit 311b.

[0105] One input terminal of AND gate 311a is connected to the signal input terminal Tic provided in the semiconductor control circuit 31, and the other input terminal of AND gate 311a is connected to the output terminal of the state detection unit 313 (more specifically, the output terminal of comparator 313b). AND gate 311a outputs an operation signal to the delay time adjustment circuit 311b, which is the result of performing a logical multiplication operation between the signal level of the input signal Sin input via the signal input terminal Tic and the signal level of the current detection signal Ss output from the comparator 313b.

[0106] The delay time adjustment circuit 311b, located in the switching time adjustment unit 311, adjusts the delay time of the input signal Sin, which is input from an external source (e.g., a control device (not shown) that controls the semiconductor control circuit 31), based on the signal level of the current detection signal Ss input from the comparator 313b.

[0107] When the current detection signal Ss is at a low level, AND gate 311a outputs a constant low-level operational signal to the delay time adjustment circuit 311b. When the current detection signal Ss is at a high level, AND gate 311a outputs an input signal Sin to the delay time adjustment circuit 311b. A high level for the current detection signal Ss output from comparator 313b indicates a large load current IL (as explained in the first embodiment above, the target value of the load current IL is the current value at normal current). Therefore, when the load current IL is large, the input signal Sin is input to the delay time adjustment circuit 311b. On the other hand, when the load current IL is small (as explained in the first embodiment above, the target value of the load current IL is the current value at low current), a constant low-level operational signal is input to the delay time adjustment circuit 311b. Therefore, when the load current IL is large, the delay time adjustment circuit 311b outputs a delayed signal Sdy obtained by delaying the input signal Sin. When the load current IL is small, the delay time adjustment circuit 311b directly outputs a low-level constant operational signal.

[0108] The drive current adjustment unit 312 includes a gate drive circuit 312DC. When a delayed signal Sdy, obtained by delaying the input signal Sin, is input from the delay time adjustment circuit 311b, the gate drive circuit 312DC drives the IGBT 221 with a drive current Idv of an amount corresponding to the signal level of the current detection signal Ss. The gate drive circuit 312DC has multiple current supply units (a first current supply unit 312-1 and a second current supply unit 312-2), which selectively supply the drive current Idv to the IGBT 221 according to the signal level of the current detection signal Ss.

[0109] like Figure 8As shown, the first current supply unit 312-1, located in the gate drive circuit 312DC, is selected to supply drive current Idv1 to the IGBT 221 at least when the current detection signal Ss has a signal level indicating that the probe voltage Vs is lower than the reference voltage Vr. In this embodiment, an input signal Sin is input to the first current supply unit 312-1, but the current detection signal Ss is not input. Therefore, the first current supply unit 312-1 starts supplying drive current Idv1 to the IGBT 221 when the input signal Sin is input. On the other hand, the first current supply unit 312-1 supplies drive current Idv1 to the IGBT 221 not only when the current detection signal Ss has a signal level indicating that the probe voltage Vs is lower than the reference voltage Vr, but also when the current detection signal Ss has a signal level indicating that the probe voltage Vs is higher than the reference voltage Vr.

[0110] The second current supply unit 312-2 is selected to supply a drive current Idv2 to the IGBT 221 when the current detection signal Ss has a signal level indicating that the probe voltage Vs is higher than the reference voltage Vr. More specifically, when the current detection signal Ss has a signal level indicating that the probe voltage Vs is higher than the reference voltage Vr, the IGBT 221 provides a large target value load current IL (the load current at normal current as described in the first embodiment above) to the load device. Therefore, the second current supply unit 312-2 outputs a drive current Idv2 to the gate of the IGBT 221, enabling the IGBT 221 to provide a large target value load current IL to the load device.

[0111] The first current supply unit 312-1 provides a drive current Idv1 to the gate of the IGBT 221 when an input signal Sin is input. The second current supply unit 312-2 provides a drive current Idv2 to the gate of the IGBT 221 when a delay signal Sdy is input. A drive current Idv, obtained by combining the drive currents Idv1 and Idv2, is provided to the gate of the IGBT 221.

[0112] In this embodiment, for example, the second current supply unit 312-2 provides the IGBT 221 with a drive current Idv2 that is larger in value than that of the first current supply unit 312-1. Therefore, the turn-on time of the IGBT 221 when provided with drive current Idv2 is shorter than when provided with drive current Idv1. The first current supply unit 312-1 provides the drive current Idv1 to the IGBT 221 based on the input of the input signal Sin. Conversely, the second current supply unit 312-2 provides the drive current Idv2 to the IGBT 221 based on the input of the delay signal Sdy obtained by adjusting the delay time using the delay time adjustment circuit 311b of the switching time adjustment unit 311. Therefore, the start-on time of the IGBT 221 when provided with drive current Idv2 is later than when provided with drive current Idv1. As a result, the switching time of IGBT 221 is almost the same when the drive current Idv1 is provided to the gate of IGBT 221 as drive current Idv, and when the drive current Idv obtained by combining drive current Idv1 and drive current Idv2 is provided to the gate of IGBT 221. Therefore, semiconductor device 3 can suppress changes in the responsiveness of IGBT 221 when the drive capability for driving IGBT 221 is only drive current Idv1, and when the drive capability is obtained by combining drive currents Idv1 and Idv2.

[0113] 3-2. Operation of semiconductor devices:

[0114] use Figure 4 and Figure 8 The operation of the semiconductor device 3 in this embodiment will be explained below. The operation of the semiconductor device 3 in this embodiment will be explained using the IGBT 221 being turned on as an example.

[0115] When the IGBT 221 provides a small target value of load current IL to the load device (the load current at low current as described in the first embodiment above), the probe voltage Vs is lower than the reference voltage Vr. Therefore, when the semiconductor control circuit 31 receives the input signal Sin, the first current supply unit 312-1 provides a drive current Idv1 to the gate of the IGBT 221, while the second current supply unit 312-2 does not provide a drive current Idv2 to the gate of the IGBT 221. Thus, as Figure 4 As shown in the upper part, the switching time of IGBT 221 is the switching time ton0.

[0116] When the IGBT 221 provides a large target value of load current IL (the load current during normal operation as described in the first embodiment above) to the load device, the probe voltage Vs is higher than the reference voltage Vr. Therefore, when the semiconductor control circuit 31 receives the input signal Sin, the delay signal Sdy is output from the delay time adjustment circuit 311b to the second current supply unit 312-2. Thus, the first current supply unit 312-1 provides a drive current Idv1 to the gate of the IGBT 221, and the second current supply unit 312-2 provides a drive current Idv2 to the gate of the IGBT 221. Therefore, as... Figure 4 As shown in the lower part, although the conduction time of IGBT 221 is shortened, the timing of the load current IL (i.e. the collector current of IGBT 221) flowing out is delayed by the delay time Tdy of the delayed signal Sdy relative to the input signal Sin. Therefore, the switching time of IGBT 221 is the switching time ton0.

[0117] In this way, semiconductor device 3 can suppress the change in the responsiveness of IGBT 221 caused by the amount of current IL of load current of IGBT 221.

[0118] As described above, the semiconductor device 3 of this embodiment includes: an IGBT 221; a state detection unit 313 that detects the operating state of the IGBT 221; a switching time adjustment unit 311 that adjusts the switching time of the IGBT 221 according to the operating state detected by the state detection unit 313; and a drive current adjustment unit 312 that adjusts the drive current Idv for driving the IGBT 221 according to the operating state detected by the state detection unit 313.

[0119] With such a structure, the semiconductor device 3 can suppress changes in the responsiveness of the switching element even if the driving capability used to drive the switching element is changed.

[0120] [Fourth Implementation Method]

[0121] use Figures 9 to 11 The semiconductor device of the fourth embodiment of the present invention will be described below. Figure 9 and Figure 10 This is a block diagram illustrating an example of the general structure of the semiconductor device 4 according to this embodiment. Figure 9 The specific structure of the drive current adjustment unit 412 is omitted from the illustration. Figure 10 The specific structure of the delay time adjustment circuit 411AC is omitted from the illustration. Regarding the semiconductor device 4 of this embodiment, structural elements that perform the same functions as the structural elements of the semiconductor devices 1, 2, and 3 of the first to third embodiments described above are marked with the same reference numerals and their descriptions are omitted.

[0122] 4-1. Structure of a semiconductor device:

[0123] like Figure 9 and Figure 10 As shown, the semiconductor device 4 of this embodiment includes a semiconductor control circuit 41 and a semiconductor element 22. The semiconductor control circuit 41 includes a switching time adjustment unit 411, a drive current adjustment unit 412, and a status detection unit 313. The status detection unit 313 includes a current detection unit 313ID. The status detection unit 313 and the current detection unit 313ID in this embodiment have the same structure as those in the third embodiment described above. Furthermore, the voltage value of the reference voltage Vr in this embodiment can be set to the same value as the reference voltage Vr in the third embodiment described above, or it can be set to a different value.

[0124] The switching time adjustment unit 411 includes a NOT gate 211a, a transistor 211b, a delay time adjustment circuit 411AC, and a buffer circuit 211e. The delay time adjustment circuit 411AC includes a constant current source 411a and delay time changing units 211d and 411b.

[0125] The delay time change unit 411b includes a transistor 411b-1 and a capacitor C411b. The transistor 411b-1 is, for example, an N-type MOSFET. The gate of the transistor 411b-1 is connected to the output terminal of the comparator 313b provided in the current detection unit 313ID. Thus, the transistor 411b-1 is controlled to be in an on / off state by the signal level of the current detection signal Ss input from the comparator 313b.

[0126] The delay time changer 411b is connected between the delay time changer 211d and the buffer circuit 211e. Capacitor C411b is arranged in parallel with capacitor C211d downstream of the delay time changer 211d. When transistor 411b-1 is in the off state, capacitor C411b is disconnected from the wiring between capacitor C211d and the buffer circuit 211e. On the other hand, when transistor 411b-1 is in the on state, capacitor C411b is connected in parallel with capacitor C211d. Therefore, when transistor 411b-1 becomes on, the capacitance of the capacitor formed between the wiring from the output terminal of the constant current source 411a to the buffer circuit 211e and the reference potential terminal (e.g., ground terminal) of the semiconductor control circuit 41 increases by an amount equivalent to the capacitance of capacitor C411b.

[0127] The constant current source 411a operates using the power supply used to drive the delay time adjustment circuit 411AC. The output terminal of the constant current source 411a is connected to the drain of the transistor 211b and the delay time adjustment section 211d. Therefore, when the input signal Sin is at a low level, the output current Iout of the constant current source 411a flows to the reference potential terminal (e.g., ground terminal) of the semiconductor control circuit 41 and hardly flows to the delay time adjustment section 211d. On the other hand, when the input signal Sin is at a high level, the output current Iout of the constant current source 411a hardly flows to the reference potential terminal of the semiconductor control circuit 41 and flows to the delay time adjustment section 211d.

[0128] In semiconductor device 4, unlike semiconductor device 2 in the second embodiment described above, the output current Iout output from constant current source 411a is constant. Therefore, when transistor 411b-1 is in the on state, the rise time delay of delay signal Sdy corresponds to the capacitance of capacitor C411b. Transistor 411b-1 is controlled to be on / off by current detection signal Ss. In other words, transistor 411b-1 is controlled to be on / off according to the change in detected current Is. When transistor 411b-1 is in the off state, the capacitor C211d is charged by the output current Iout output from constant current source 411a. On the other hand, when transistor 411b-1 is in the on state, the capacitors C211d and C411b are charged by the output current Iout output from constant current source 411a. Therefore, when transistor 411b-1 is in the ON state, compared to when transistor 411b-1 is in the OFF state, the delayed signal Sdy is difficult to rise, and thus the delay time becomes longer.

[0129] In this way, the delay time adjustment circuit 411AC controls the transistor 411b-1 from the off state to the on state or vice versa according to the change of the probe current Is, thereby enabling the stepwise change of the delay time of the delay signal Sdy. Therefore, the switching time adjustment unit 411 adjusts the switching time of the IGBT 221 stepwise according to the change of the probe current Is.

[0130] The on / off state of transistor 411b-1 is controlled based on the amount of load current IL supplied by IGBT 221 to the load device (not shown). Therefore, the delay time changing unit 411b can selectively output a delayed signal Sdy obtained by delaying the input signal Sin by different lengths of delay time according to the amount of load current IL.

[0131] In this way, the delay time adjustment circuit 411AC adjusts the delay time of the input signal Sin input from an external source (e.g., a control device (not shown) that controls the semiconductor control circuit 41) based on the signal level of the current detection signal Ss input from the comparator 313b.

[0132] like Figure 10 As shown, the drive current adjustment unit 412 includes a gate drive circuit 412DC. The gate drive circuit 412DC includes a constant current source 412CC, a current mirror circuit 412CM, a first current supply unit 412-1, and a second current supply unit 412-2. Thus, the gate drive circuit 412DC has multiple current supply units, including a first current supply unit 412-1 and a second current supply unit 412-2.

[0133] The constant current source 412CC includes an operational amplifier 212a, transistors 212b and 212c, a resistor element 212d, and a DC voltage generation unit 412a. Unlike the variable constant current source 212VC in the second embodiment described above, the constant current source 412CC has a DC voltage generation unit 412a. The DC voltage generation unit 412a is, for example, a DC voltage source, with its positive terminal connected to the non-inverting input terminal (+) of the operational amplifier 212a. Therefore, the operational amplifier 212a outputs an output voltage to the gate of the transistor 212c that is approximately the same as the voltage generated by the DC voltage generation unit 412a. Thus, the constant current source 412CC can cause a constant current corresponding to the output voltage of the operational amplifier 212a to flow into the transistor 212e of the current mirror circuit 412CM.

[0134] The current mirror circuit 412CM includes transistors 212e, 212f, and 412b. In the semiconductor device 4, transistors 212f and 412b have different transistor sizes, allowing transistor 412b to carry a larger current flow compared to transistor 212f. Transistor 212f also constitutes the first current supply section 412-1, and transistor 412b also constitutes the second current supply section 412-2.

[0135] The first current supply unit 412-1 includes transistors 212f and 212g. In this embodiment, transistors 212f and 212g operate in the same manner as in the second embodiment described above. Therefore, when a high-level delayed signal Sdy is input from the switching timing adjustment unit 411 to transistor 212g, the first current supply unit 412-1 provides a drive current Idv1 to the gate of the IGBT 221. On the other hand, when a low-level delayed signal Sdy is input from the switching timing adjustment unit 411 to transistor 212g, the first current supply unit 412-1 does not provide a drive current Idv1 to the gate of the IGBT 221, but instead allows the drive current Idv1 to flow to the reference potential terminal (e.g., ground terminal) of the semiconductor control circuit 41.

[0136] Whether the first current supply unit 412-1 provides a drive current Idv1 to the gate of the IGBT 221 is controlled by the signal level of the delay signal Sdy (i.e., the signal level of the input signal Sin), rather than by the signal level of the current detection signal Ss. The first current supply unit 412-1 is selected to provide the drive current Idv1 to the IGBT 221 at least when the current detection signal Ss has a signal level indicating that the probe voltage Vs is lower than the reference voltage Vr. Additionally, the first current supply unit 412-1 also provides the drive current Idv1 to the IGBT 221 when the current detection signal Ss has a signal level indicating that the probe voltage Vs is higher than the reference voltage Vr. Regarding the current detection signal Ss, a low signal level indicates that the probe voltage Vs is lower than the reference voltage Vr, and a high signal level indicates that the probe voltage Vs is higher than the reference voltage Vr.

[0137] The second current supply unit 412-2 includes transistors 412b and 412c. Transistor 412b is, for example, a P-type MOSFET, and transistor 412c is, for example, an N-type MOSFET. Transistors 412b and 412c are connected in series between a power supply terminal that provides power for driving the gate drive circuit 412DC and a current output terminal Toc provided in the semiconductor control circuit 41. The source of transistor 412c is connected to the connection point between transistors 212f and 212g (i.e., the output terminal of the drive current Idv1) and the current output terminal Toc. The gate of transistor 412c is connected to the output terminal of comparator 313b.

[0138] Therefore, when the second current supply unit 412-2 inputs a high-level current detection signal Ss from the current detection unit 313ID to the transistor 412c, it provides a drive current Idv2 to the gate of the IGBT 221. On the other hand, when the second current supply unit 412-2 inputs a low-level current detection signal Ss from the current detection unit 313ID to the transistor 412c, it does not provide a drive current Idv2 to the gate of the IGBT 221, but instead allows the drive current Idv2 to flow to the reference potential terminal (e.g., ground terminal) of the semiconductor control circuit 41.

[0139] In this way, the second current supply unit 412-2 is controlled to be on / off by the signal level of the current detection signal Ss. Therefore, the second current supply unit 412-2 is selected to supply drive current Idv2 to IGBT 221 when the current detection signal Ss has a signal level indicating that the probe voltage Vs is higher than the reference voltage Vr.

[0140] The first current supply unit 412-1 provides a drive current Idv1 to the IGBT 221 regardless of the relationship between the reference voltage Vr and the detection voltage Vs. Conversely, the second current supply unit 412-2 provides a drive current Idv2 to the IGBT 221 only when the detection voltage Vs is higher than the reference voltage Vr. That is, when the detection voltage Vs is lower than the reference voltage Vr (when the signal level of the current detection signal Ss is low), the gate drive circuit 412DC selects only the first current supply unit 412-1. Conversely, when the detection voltage Vs is higher than the reference voltage Vr (when the signal level of the current detection signal Ss is high), the gate drive circuit 412DC selects both the first current supply unit 412-1 and the second current supply unit 412-2. The gate drive circuit 412DC combines the drive currents Idv1 and Idv2 to obtain the current Idv, which is then provided to the gate of the IGBT 221 as the drive current Idv. Therefore, the gate drive circuit 412DC has multiple current supply units (i.e., the first current supply unit 412-1 and the second current supply unit 412-2), which selectively supply drive current Idv to IGBT 221 according to the signal level of the current detection signal Ss.

[0141] The drive current adjustment unit 412 supplies drive current Idv to the gate of IGBT 221 only through the first current supply unit 412-1, or through both the first current supply unit 412-1 and the second current supply unit 412-2, according to the changes in the reference voltage Vr and the detection voltage Vs, i.e., the changes in the detection current Is. Therefore, the drive current adjustment unit 412 adjusts the drive current Idv in a stepwise manner according to the changes in the detection current Is.

[0142] In this embodiment, for example, the second current supply unit 412-2 provides the IGBT 221 with a drive current Idv2 that is larger in value than the first current supply unit 412-1. Therefore, when the drive current Idv2 is provided to the IGBT 221, the conduction time of the IGBT 221 is shorter than when the drive current Idv1 is provided to the IGBT 221.

[0143] As described above, the drive current adjustment unit 412 includes a gate drive circuit 412DC. When a delayed signal Sdy, obtained by delaying the input signal Sin, is input from the delay time adjustment circuit 411AC, the gate drive circuit 412DC drives the IGBT 221 with a drive current Idv of a current magnitude corresponding to the signal level of the current detection signal Ss. The delayed signal Sdy is such that, compared to the case where the signal level of the current detection signal Ss is low, when the signal level of the current detection signal Ss is high, the delayed signal Sdy has a longer delay time relative to the input signal Sin. Therefore, compared to the case where only the first current supply unit 412-1 provides the drive current Idv to the IGBT 221, when both the first current supply unit 412-1 and the second current supply unit 412-2 provide the drive current Idv to the IGBT 221, the delay time of the delayed signal Sdy input to the gate drive circuit 412DC is longer.

[0144] Therefore, the switching time of IGBT 221 is almost the same when the drive current Idv1 is provided to the gate of IGBT 221 as drive current Idv, and when the drive current Idv obtained by combining drive current Idv1 and drive current Idv2 is provided to the gate of IGBT 221. Thus, semiconductor device 4 can suppress changes in the responsiveness of IGBT 221 when the drive capability for driving IGBT 221 is only drive current Idv1, and when the drive capability is obtained by combining drive currents Idv1 and Idv2.

[0145] 4-2. Operation of semiconductor devices:

[0146] Reference Figure 9 and Figure 10 And use Figure 11 The operation of the semiconductor device 4 in this embodiment will be explained. Figure 11 This is a timing diagram that schematically shows a portion of the operating waveform of semiconductor device 4. Figure 11 In this context, "Sdy" represents the delayed signal output from the delay time adjustment circuit 411AC. Figure 11 In this context, "Sin" indicates the input signal input to the switching time adjustment unit 411. Figure 11 In this context, "IL" represents the load current supplied by the IGBT 221 to the load device.

[0147] When the IGBT 221 provides a small target value of load current IL to the load device (the load current at low current as described in the first embodiment above), the probe voltage Vs is lower than the reference voltage Vr. Therefore, when a delayed signal Sdy that is delayed by a delay time Tdy1 relative to the input signal Sin is input to the drive current adjustment unit 412, the first current supply unit 412-1 provides a drive current Idv1 to the gate of the IGBT 221, while the second current supply unit 412-2 does not provide a drive current Idv2 to the gate of the IGBT 221. Thus, as Figure 11 As shown in the upper part, the switching time of IGBT 221 is the switching time ton0.

[0148] When the IGBT 221 provides a large target value of load current IL (the load current during normal operation as described in the first embodiment above) to the load device, the probe voltage Vs is higher than the reference voltage Vr. Therefore, when a delayed signal Sdy, which is delayed by a delay time Tdy2 longer than the low current duration, is input to the drive current adjustment unit 412, the first current supply unit 412-1 starts providing drive current Idv1 to the IGBT 221 at a time later than the low current duration. Furthermore, when the probe voltage Vs is higher than the reference voltage Vr, the transistor 412c is in the on state, therefore, the second current supply unit 412-2 also starts providing drive current Idv2. Therefore, the on-time of the IGBT 221 is shorter than during the low current duration. As a result, as... Figure 11 As shown in the lower part, the switching time of IGBT 221 is the same as the switching time ton0 when the current is low.

[0149] In this way, semiconductor device 4 can suppress the change in the responsiveness of IGBT 221 caused by the amount of current IL of load current of IGBT 221.

[0150] As described above, the semiconductor device 4 of this embodiment includes: an IGBT 221; a state detection unit 313 that detects the operating state of the IGBT 221; a switching time adjustment unit 411 that adjusts the switching time of the IGBT 221 according to the operating state detected by the state detection unit 313; and a drive current adjustment unit 412 that adjusts the drive current Idv for driving the IGBT 221 according to the operating state detected by the state detection unit 313.

[0151] With such a structure, the semiconductor device 4 can suppress changes in the responsiveness of the switching element even if the driving capability used to drive the switching element is changed.

[0152] The present invention is not limited to the above-described embodiments and can be modified in various ways.

[0153] In the semiconductor devices 1, 2, 3, and 4 of the first to fourth embodiments described above, the example of the IGBT being turned on was used as an example; however, the present invention is not limited thereto. The semiconductor devices 1, 2, 3, and 4 can also achieve the same effect when the IGBT is turned off.

[0154] The semiconductor devices 3 and 4 of the third and fourth embodiments described above can change the drive current Idv supplied to the gate of the IGBT 221 in two stages. However, by setting a predetermined number of current detection units and current supply units, it is possible to change it in three or more stages.

[0155] In the semiconductor devices 3 and 4 of the third and fourth embodiments described above, a drive current Idv1 is provided to the gate of the IGBT 221 from the first current supply units 312-1 and 412-1 even under normal current conditions. However, the present invention is not limited to this. The first current supply units 312-1 and 412-1 may also be configured not to provide current to the gate of the IGBT 221 under normal current conditions. In this case, the second current supply units 312-2 and 412-2 need to be configured to provide a drive current Idv2 to the gate of the IGBT 221 that is larger in quantity than that of the first current supply units 312-1 and 412-1.

[0156] The scope of this invention is not limited to the illustrated and described exemplary embodiments, but also includes all embodiments that achieve the same effect as the purpose of this invention. Furthermore, the scope of this invention is not limited to the combination of features defined by the claims, but can be defined by all desired combinations of specific features among all the disclosed features.

[0157] Explanation of reference numerals in the attached figures

[0158] 1, 2, 3, 4: Semiconductor devices; 11, 21, 31, 41: Semiconductor control circuits; 12, 22: Semiconductor elements; 111, 211, 311, 411: Switching time adjustment unit; 112, 212, 312, 412: Drive current adjustment unit; 113, 213, 313: Status detection unit; 121, 221: IGBT; 122: Status detection element; 211AC, 311b, 411AC: Delay time adjustment circuit; 211c, 212VC: Variable constant current source; 211d, 411b: Delay time changing unit; 211e, 213b: Buffer circuit; 212CM, 412CM: Current mirror circuit; 21 2DC, 312DC, 412DC: Gate drive circuit; 213a, 313a: Current-to-voltage conversion circuit; 213ID, 313ID: Current detection unit; 222: Current sensing element; 311a: AND gate; 312-1, 412-1: First current supply unit; 312-2, 412-2: Second current supply unit; 313b: Comparator; 313c: Reference voltage generation circuit; Idv, Idv1, Idv2: Drive current; IL: Load current; Is: Sensing current; Sin: Input signal; Sos: Sensing signal; Sosd: Status detection signal; Ss: Current detection signal; Vr: Reference voltage; Vs: Sensing voltage.

Claims

1. A semiconductor device comprising: Switching elements; The status detection unit detects the operating status of the switching element; A switching time adjustment unit adjusts the switching time of the switching element based on the operating state detected by the state detection unit; and The drive current adjustment unit adjusts the drive current used to drive the switching element based on the operating state detected by the state detection unit.

2. The semiconductor device according to claim 1, wherein, It includes a current sensing element that detects a sensing current used to detect the load current supplied by the switching element to the load. The state detection unit includes a current detection unit, which detects the magnitude of the load current corresponding to the detection current detected by the current detection element to determine the operating state. The switching time adjustment unit adjusts the switching time of the switching element based on the magnitude of the load current detected by the current detection unit as the operating state. The drive current adjustment unit adjusts the drive current used to drive the switching element based on the magnitude of the load current detected by the current detection unit as the operating state.

3. The semiconductor device according to claim 2, wherein, The switching time adjustment unit continuously adjusts the switching time according to the change in the detection current. The drive current adjustment unit continuously adjusts the drive current according to the changes in the detection current.

4. The semiconductor device according to claim 2 or 3, wherein, The current detection unit has: A conversion circuit that converts the probe current into a probe voltage; as well as A buffer circuit outputs the probe voltage from the conversion circuit as a current detection signal with a signal level corresponding to the magnitude of the load current. The switching time adjustment unit includes a delay time adjustment circuit, which adjusts the delay time of an externally input signal based on the signal level of the current detection signal input from the current detection unit. The drive current adjustment unit has a drive circuit that drives the switching element with a drive current of a magnitude corresponding to the signal level of the current detection signal when a delay signal obtained by delaying the input signal is input from the delay time adjustment circuit.

5. The semiconductor device according to claim 2, wherein, The switching time adjustment unit adjusts the switching time in stages according to the changes in the detection current. The drive current adjustment unit adjusts the drive current in stages according to the changes in the detection current.

6. The semiconductor device according to claim 2 or 5, wherein, The current detection unit has: A conversion circuit that converts the probe current into a probe voltage; as well as A comparator whose output is a current-sensing signal with a signal level based on a comparison result obtained by comparing the detected voltage output from the conversion circuit with a reference voltage. The switching time adjustment unit includes a delay time adjustment circuit, which adjusts the delay time of an externally input signal based on the signal level of the current detection signal input from the comparator. The drive current adjustment unit has a drive circuit that drives the switching element with a drive current of a magnitude corresponding to the signal level of the current detection signal when a delay signal obtained by delaying the input signal is input from the delay time adjustment circuit.

7. The semiconductor device according to claim 6, wherein, The drive circuit has multiple current supply units, which selectively supply the drive current to the switching element according to the signal level of the current detection signal.

8. The semiconductor device according to claim 7, wherein, The plurality of current supply units have: A first current supply unit is selected to supply the drive current to the switching element at least when the current detection signal has a signal level indicating that the detection voltage is lower than the reference voltage. as well as The second current supply unit is selected to supply the drive current to the switching element when the current detection signal has a signal level indicating that the detection voltage is higher than the reference voltage.

9. The semiconductor device according to claim 8, wherein, The first current supply unit also supplies the drive current to the switching element when the current detection signal has a signal level indicating that the detection voltage is higher than the reference voltage.

10. The semiconductor device according to claim 9, wherein, The second current supply unit provides the switching element with a drive current that is larger than that provided by the first current supply unit.

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