Analog circuit implementation method and device based on unified probabilistic graph computation architecture, equipment and medium

Abstract

The application discloses a simulation circuit implementation method and device based on a unified probability graph calculation architecture, equipment and a medium, comprising: establishing a unified signal model based on the common characteristics of baseband signal processing tasks; the unified signal model is characterized as a unified probability graph model; the initialization probability of the variable node state value in the unified probability graph model is obtained; a storage and calculation integrated characteristic device is set, the storage and calculation integrated characteristic device comprises an initial input array, an iterative calculation array and a result output array, wherein the node state values of the initial input array, the iterative calculation array and the result output array are configured based on the unified probability graph model; the driving vector is obtained as the input of the initial input array based on the initialization probability, the iterative calculation array is used to complete the iterative calculation of the mutual message transmission between the variable nodes and the check nodes in the unified probability graph model, when the iteration stopping condition is met, the result output array outputs the processing result, and the baseband signal processing task is completed.

Description

TECHNICAL FIELD

[0001] The application relates to a simulation circuit implementation method, device and equipment based on a unified probabilistic graph calculation architecture and a medium, and relates to the technical field of signal processing. BACKGROUND

[0002] Constrained by extreme working environments, extreme equipment working conditions and other extreme conditions, the energy supply of a large number of edge communication terminals is limited, which greatly limits the terminal baseband signal processing energy consumption.

[0003] In view of the extremely low power consumption signal processing requirement, the existing signal baseband processing architecture faces challenges in processing method and hardware architecture: first, the existing signal processing unit "independent optimization, linear combination" mode is difficult to solve the huge difference between the processing algorithms of each unit, and the baseband power consumption is nonlinearly coupled with the time and space dimension elements of each processing unit, so that local unit module optimization cannot achieve global energy efficiency optimization. Second, the existing baseband signal processing algorithm usually relies on digital circuit implementation, including traditional computers, MCUs, FPGAs, CMOS special integrated circuits and the like. The signal processing process involves a large number of discrete fixed-point number operations, and the energy efficiency of the communication baseband based on the traditional digital circuit is seriously restricted by the random memory access power consumption cost and the energy consumption caused by the discrete fixed-point number operation in the digital domain. The existing digital circuit processing paradigm cannot fundamentally realize the energy efficiency breakthrough. SUMMARY

[0004] The application aims to at least solve one of the technical problems in the prior art. To this end, in order to solve the above problems, the application aims to provide an analog circuit implementation method, device, equipment and medium based on a unified probabilistic graph calculation architecture with extremely low power consumption.

[0005] In order to achieve the above application purpose, the technical scheme adopted by the application is:

[0006] In a first aspect, the application provides an analog circuit implementation method based on a unified probabilistic graph calculation architecture, comprising:

[0007] establishing a unified signal model based on the common features of baseband signal processing tasks;

[0008] characterizing the unified signal model as a unified probabilistic graph model;

[0009] obtaining the initialization probability of the variable node state value in the unified probabilistic graph model;

[0010] setting a storage and calculation integrated characteristic device, the storage and calculation integrated characteristic device comprising an initial input array, an iterative calculation array and a result output array, wherein the node state values of the initial input array, the iterative calculation array and the result output array are configured based on the unified probabilistic graph model;

[0011] The driving vector is obtained based on the initialization probability as an input of the initial input array, the iterative calculation array is used to complete the iterative calculation of the message passing between the variable nodes and the check nodes in the unified probabilistic graph model, and the result output array outputs a processing result when an iteration stopping condition is met, thereby completing the baseband signal processing task.

[0012] In some possible implementation manners, a unified signal model is established based on the common features of the baseband signal processing tasks, and the unified signal model is as follows: wherein, x is an unknown variable, y is an observation variable, A is a given association mapping matrix between x and y, n is an unknown disturbance noise, x is a certain unknown variable, y is a certain observation variable, A is a column number of the association mapping matrix A is a row number of the association mapping matrix . .

[0013] In some possible implementation manners, the unified probabilistic graph model includes variable nodes, check nodes and undirected edges, and the undirected edges are used to connect the variable nodes and the check nodes that have a connection relationship.

[0014] The variable nodes represent unknown variables.

[0015] The check nodes represent the coupling relationship among the unknown variables, the observation variables and the association mapping matrix, and are provided with a probability configuration function based on the association mapping matrix, and are used to describe the differentiated constraint rules among the baseband signal processing tasks.

[0016] In some possible implementation manners, the message passing from the check node to the variable node is as follows:

[0017]

[0018] wherein, x is a state included in the variable node, is a message passed from the check node i to the variable node j about a state value of the variable node j , is a message passed from the check node to the variable node about a state value of the variable node , is a probability configuration function of ​represents the message passed from the variable node i with connection to the check node j to the check node all combinations of variable node states taking values represents the message passed from the variable node i with connection to the check node j to the check node all combinations of variable node states taking values represents the value of the element in the candidate vector constructed by the th undirected edge, represents the value of the corresponding element in the candidate vector, corresponding to the variable node represents the value of the corresponding element in the candidate vector, corresponding to the variable node represents the value taken from the set of variable node indices i with connection to the check node , represents the message passed from the variable node to the check node about ,

[0019] The message passing from the variable node to the check node is:

[0020]

[0021] wherein, represents the message passed from the variable node to the check node about , is the message passed from the check node to the variable node j about the variable node j state taking value .

[0022] In some possible implementations, the configuration and calculation process of the initial input array are as follows:

[0023] The configuration scale of the initial input array is , is the number of variable node states, is the number of candidate vectors;

[0024] The input of the initial input array is an input voltage proportional to the initialization probability of the state value of the variable node:

[0025] ;

[0026] Based on the input voltage, the calculation performed by the initial input array is:

[0027] ;

[0028] The column output current of the initial input array is:

[0029]

[0030] The node state value corresponding to the node of the column of the initial input array is:

[0031]

[0032] Where e represents the e-th element from top to bottom, represents the value satisfying The corresponding voltage input row index, specifically, the value of the element in the candidate vector of all variable nodes connected to the check node i is selected as The corresponding variable node is j The value of the node is set to 1 if it exists, otherwise it is set to 0; 1 indicates that the node is in a low configuration and can be turned on, 0 indicates that the node is in a high resistance state and is not turned on, the value 1 corresponds to the row voltage that can be accumulated, and the output current is output at the output end.

[0033] In some possible implementation manners, the iterative calculation array includes a first iterative sub-array, a second iterative sub-array, and an external input sub-array, wherein the configuration and calculation process of the iterative calculation array are as follows:

[0034] The first iterative sub-array is used to complete message passing from the check node to the variable node, and the scale is set to ; the output of the initial input array is connected to the column input end of the first iterative sub-array to start iteration, and when The value of , the calculation performed by the first iterative sub-array is:

[0035]

[0036] At the beginning of iteration, the row input voltage of the first iterative sub-array is:

[0037]

[0038] The element order in the column output current arrangement vector corresponding to the first iterative sub-array is:

[0039] ​​

[0040] wherein, ;

[0041] The node state value corresponding to the column of nodes where the first iteration subarray is located is:

[0042]

[0043] wherein, represents the value of the node state value of the node corresponding to the column of nodes where the first iteration subarray is located. The voltage input row index corresponding to the column of nodes where the first iteration subarray is located, specifically, the value of the element in the candidate vector of all variable nodes connected with the check node i corresponding to the column of nodes where the first iteration subarray is located is The variable node corresponding to the column of nodes where the first iteration subarray is located is j The value of the node state value of the node corresponding to the column of nodes where the first iteration subarray is located. The value of the node state value of the node corresponding to the column of nodes where the first iteration subarray is located. The value of the node state value of the node corresponding to the column of nodes where the first iteration subarray is located. The value of the node state value of the node corresponding to the column of nodes where the first iteration subarray is located. k When e=1, the state value of the node is set to 1, 1 represents that it can be turned on, and 0 represents that it cannot be turned on; e represents the e-th element from top to bottom.

[0044] The second iteration subarray and the external input subarray are used to complete message passing of the variable node to the check node, wherein: the size of the second iteration subarray is , the size of the external input subarray is , the column of the second iteration subarray and the external input subarray corresponds to the row voltage input, the row corresponds to the current readout, and the rows of the second iteration subarray and the external input subarray are concatenated.

[0045] The column voltage value of the external input of the external input subarray is:

[0046]

[0047] wherein, ;

[0048] The second iteration subarray and the external input subarray jointly complete the calculation as:

[0049]

[0050] The output of the second iteration subarray and the external input subarray is:

[0051]

[0052] ​The relationship between the row input of the first iteration sub-array and the output of the second iteration sub-array and the external input sub-array is:

[0053]

[0054] The node state value corresponding to the row output of the second iteration sub-array is configured as:

[0055]

[0056] wherein, represents a combination of all variable node states satisfying corresponding to the column index, and the specific meaning is to select all variable nodes i connected with the check node j whose values are If exists, the node value is configured as 1, and if does not exist, the node value is configured as 0, 1 indicates that it can be turned on, and 0 indicates that it cannot be turned on; e represents the e-th array node from left to right.

[0057] The node state value corresponding to the row output of the external input sub-array is configured as:

[0058]

[0059] wherein, represents a combination of all variable node states satisfying corresponding to the column index, and the specific meaning is to select all variable nodes i connected with the check node j whose values are If exists, the node value is configured as 1, and if does not exist, the node value is configured as 0, 1 indicates that it can be turned on, and 0 indicates that it cannot be turned on; e represents the e-th array node from left to right.

[0060] In some possible implementations, the iteration stop condition is satisfied, and the result output array is used to output the processing result, wherein the configuration of the result output array is calculated as:

[0061] The configuration scale of the result output array is , and the row of the result output array is concatenated with the row of the first iteration sub-array.

[0062] The result output array is completed by calculation:

[0063] ​​​​

[0064] The column output current corresponding to the output array of the results is:

[0065]

[0066] The node state values ​​corresponding to the columns of nodes in the output array are:

[0067]

[0068] in, Specifically, it means selecting variable nodes. j All connected verification nodes i The value of the middle is of ,like If it exists, the node value is configured to 1; if If a node does not exist, its value is set to 0. 1 indicates that the node is conductive, 0 indicates that it is not conductive, and e represents the e-th element from the top.

[0069] Secondly, the present invention also provides an analog circuit implementation device based on a unified probabilistic graphical computing architecture, comprising:

[0070] The signal model building unit is configured to establish a unified signal model based on the common characteristics of baseband signal processing tasks;

[0071] A probabilistic graphical construction unit is configured to characterize the unified signal model as a unified probabilistic graphical model;

[0072] The probability initialization unit is configured to obtain the initial probability of the state values ​​of the variable nodes in the unified probabilistic graphical model.

[0073] The in-memory computing device configuration unit is configured to set up an in-memory computing integrated feature device, which includes an initial input array, an iterative calculation array, and a result output array, wherein the node state values ​​of the initial input array, the iterative calculation array, and the result output array are configured based on the unified probabilistic graphical model.

[0074] The iterative calculation unit is configured to obtain the driving vector based on the initialization probability as the input of the initial input array. The iterative calculation array is used to complete the iterative calculation of mutual message passing between variable nodes and test nodes in the unified probabilistic graphical model. When the iteration stopping condition is met, the result output array outputs the processing result to complete the baseband signal processing task.

[0075] In a third aspect, the present application provides an electronic device, comprising: at least one processor; and a memory connected with the processor in communication; wherein the memory stores instructions executable by the processor, and the instructions are executed by the processor to enable the processor to perform the method.

[0076] In a fourth aspect, the present application provides a computer readable storage medium storing one or more programs, the one or more programs comprising instructions for causing a computer to perform the method.

[0077] The present application has the following characteristics: 1. Low power consumption: the present application makes full use of the memory and computing integrated characteristic devices such as memristor, and loads the static variables in the probability graph calculation process into the memory and computing integrated characteristic devices such as memristor to overcome the energy consumption caused by memory access in the iteration process, and converts the traditional discrete digital operation into current, voltage and other continuous physical variable operation, avoiding the energy consumption caused by digital domain discrete fixed-point number operation, and fundamentally improving the energy efficiency; 2. Small area: the memory and computing integrated characteristic devices such as memristor used in the present application are very small, and the occupied area is several tenths of the traditional cmos circuit. In summary, the present application can be widely applied in signal processing. BRIEF DESCRIPTION OF DRAWINGS

[0078] Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The accompanying drawings are included to provide a description of the preferred embodiments and are not intended to limit the scope of the present application. Throughout the drawings, like reference numerals will be used to designate like components. In the drawings:

[0079] Figure 1 Baseband signal multitasking diagram for embodiments of the present application;

[0080] Figure 2 Unified representation of differentiated baseband signal processing tasks based on probability graph theory for embodiments of the present application;

[0081] Figure 3 Analog circuit principle diagram based on unified probability graph calculation architecture for embodiments of the present application;

[0082] Figure 4 Connection relationship between check nodes and each variable node in the probability graph model for embodiments of the present application. DETAILED DESCRIPTION

[0083] It is to be understood that the terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises", "comprising", "includes", "including" and "has" are inclusive and therefore specify the presence of stated features, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring their performance in the particular order in which they are described, unless specifically identified as an order dependent step. It is also to be understood that additional or alternative steps can be employed.

[0084] To solve the problem that it is difficult to adapt to low-power application environment in baseband signal processing method. The analog circuit implementation method, device, equipment and medium based on unified probability graph calculation architecture provided by the application include establishing a unified signal model based on the common characteristics of baseband signal processing tasks; the unified signal model is represented as a probability graph model; the initialization probability of the state value of the variable node in the probability graph model is obtained; a storage and calculation integrated characteristic device is set, the storage and calculation integrated characteristic device includes an initial input array, an iterative calculation array and a result output array, wherein the node state values of the initial input array, the iterative calculation array and the result output array are configured based on the unified probability graph model, the driving vector is obtained as the input of the initial input array based on the initialization probability, the iterative calculation array is used to complete the iterative calculation of the message transmission between the variable nodes and the check nodes in the probability graph model, and when the iteration stopping condition is met, the result output array outputs the processing result, and the baseband signal processing task is completed. Therefore, the traditional discrete digital operation is converted into continuous physical variable operation such as current and voltage, the energy consumption caused by the digital domain discrete fixed-point number operation is avoided, and the energy efficiency is fundamentally improved.

[0085] Example embodiments of the present application will be described herein below with reference to the accompanying drawings. While example embodiments of the present application are illustrated in the drawings, it is understood that the present application can be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present application to those skilled in the art.

[0086] Embodiment one: the embodiment provides a unified probability graph calculation architecture, comprising:

[0087] S1, based on the common characteristics of baseband signal processing tasks, a unified signal model is established.

[0088] In this embodiment, the baseband signal processing tasks include channel decoding, channel detection, channel estimation, multi-antenna detection and image recognition, etc. For example, but not limited to.

[0089] Specifically, as shown in Figure 1 , the baseband signal processing tasks in this embodiment include: Task1: multi-antenna detection task; Task2: channel decoding task; Task3: channel estimation task; Task4: multi-user identification task.

[0090] As shown in Figure 2 , based on the common characteristics of baseband signal processing tasks, a unified signal model is established as: , wherein, is an unknown variable, is an observation variable, is a given and is the association mapping matrix between is an unknown disturbance noise.

[0091] It should be noted that when facing different baseband signal processing tasks, the parameters of the unified signal model represent different meanings, for example: in the multi-antenna detection task: is a multi-antenna channel feature matrix, is a to-be-estimated transmission symbol, is a multi-antenna mixed signal observed at the receiving end, is continuous, is continuous, is an unknown discrete variable; in the channel decoding task: is a code word check matrix, is a to-be-estimated transmission bit, is a bit sequence received at the receiving end, is discrete, is continuous, is an unknown discrete variable; in the channel estimation task: is a pilot structure matrix, is a to-be-estimated communication channel, is a pilot signal observed at the receiving end, is continuous, is an unknown continuous variable; in the multi-user detection task, is a sensing matrix, is a terminal activation state of a device, is a multi-user superimposed signal observed at the receiving end, is continuous, is continuous, is an unknown continuous variable.

[0092] S2. Based on the unified probability graph theory, the unified signal model is represented as a unified probability graph model.

[0093] In this embodiment, as Figure 2 As shown, the unified probabilistic graphical model includes multiple variable nodes, multiple check nodes, and multiple undirected edges. Undirected edges connect variable nodes and check nodes that have a connection relationship. Each variable node corresponds to an association mapping matrix. A column vector in which each verification node uniquely corresponds to an association mapping matrix. A row vector in a matrix. For example, the incidence matrix. The Middle i Row vector representation , for No. i Line number j Column elements, representing validation nodes. i With variable nodes j The relationship between them, if the association mapping matrix middle If the element is 1, then the variable node i With verification node j If there is a connection relationship, such as an association mapping matrix of If the element is 0, then the variable node... i With verification node j No connection exists.

[0094] Furthermore, based on the preceding formal transformation, each signal processing problem in the baseband signal processing task is transformed into a problem of estimating unknown variables based on observed variables and correlation patterns. The signal state of a certain task is the set of values ​​for the state of the variable to be estimated. Specifically, in this embodiment, it is assumed that there are K states, denoted as follows: , For example, in a decoding scenario, K states represent the values ​​of the transmitted bits. In LDPC decoding, K=2. u 1=1, u 2=0.

[0095] Specifically, in the unified probabilistic graphical model of this embodiment, variable nodes represent unknown variables. , of which each Belongs to the state set space Its cardinality (number of elements) is Verification nodes represent the coupling relationships between unknown variables, observed variables, and the correlation mapping matrix.

[0096] In this embodiment, the unified probabilistic graphical model further includes constructing a probability configuration function. i Probability configuration function for each verification node This is used to characterize the differences in probabilistic iterative messages from the check node to the variable node in different baseband signal processing tasks. A probabilistic configuration function is constructed based on different tasks. They are all different, the verification node and the probability configuration function The quantities are in a one-to-one correspondence. Specifically, the probability allocation function... Essentially, it represents a given correlation mapping matrix. With unknown variables After about the observed variables The posterior probability satisfies It is used to characterize the differentiated constraint rules between tasks. The core objective of unified probabilistic graphical computation is to maximize the posterior probability, i.e. The variable to be estimated is passed Obtain, among which, Represents the set of states of a variable node.

[0097] Furthermore, this embodiment effectively addresses the problem of significant algorithmic differences between communication signal processing elements / units by fusing and representing signal processing elements and unifying the inference architecture, thus laying a mathematical model foundation for joint power consumption optimization across elements. Appropriate probability configuration functions are set during specific signal processing. It can achieve flexible switching of baseband signal processing functions, and the probability configuration function can be adjusted according to different baseband processing tasks. They are also different. The following examples illustrate different baseband processing tasks, but are not limited to these:

[0098] Multi-antenna detection task Configured as follows:

[0099] ;

[0100] Channel estimation task Configured as follows:

[0101] ;

[0102] Channel decoding task Configured as follows:

[0103] ;

[0104] in, Indicates the noise variance. H represents the received signal, and H represents the matrix transpose. Represents the association mapping matrix The first in row vectors This indicates the remainder calculation. This indicates that the remainder is inverted.

[0105] S3, Obtain the initial probability of the state value of the variable node.

[0106] In this embodiment, based on the received signal Calculate the corresponding variable node The initial probability value is obtained by saving the likelihood ratio. ,in, Given an association mapping matrix With unknown variables After about the observed variables The posterior probability, Given an association mapping matrix With unknown variables After about the observed variables The posterior probability.

[0107] S4. Calculate message passing from the verification node to the variable node.

[0108]

[0109] in, For verification nodes i To variable node j Passing information about variable nodes j The state value is The message (essentially representing the verification node) i To variable node j The message about the first j Variables about The confidence level is the posterior probability. This represents the states contained in the variable node; For probability configuration function Take the logarithm. for The probability configuration function. Indicates and verifies the node i Connected China satisfies of j The corresponding variable node is related to the validation. i (with connections), and variable nodes j Values The combination of all variable node states. Indicates the first The candidate vector constructed from the nth undirected edge element values

[0110] Indicates and verifies the node iThere are connections, except for variable nodes. j The combination of all variable node states except for It is a set The vector has M There are 1 candidate vectors, where the candidate vectors are unknown variables. One of the elements,

[0111] Indicates and verifies the node i Connected and variable nodes j Values The combination of all variable node states, express From the verification node i A set of indexes of variable nodes with connections Take the value from; This represents the element value corresponding to the variable node in the candidate vector. express From the verification node i A set of indexes of variable nodes with connections Take the value from the middle.

[0112] Represents variable nodes To the verification node The message conveyed about The message. At the start of the first iteration, .

[0113] S5. Calculate message passing from the verification node to the variable node.

[0114]

[0115] in, Represents variable nodes j To the verification node The message conveyed about Messages (essentially variable nodes) j to the inspection point i The message about the first j Variables about The confidence level is the prior probability. For verification nodes To variable node j Passing information about variable nodes j The state value is The news.

[0116] S6. Repeat S4 to S5. Stop iterating if the maximum set number of iterations is reached, and obtain the probability of each state value in each variable node:

[0117] ;

[0118] Then, based on the established judgment conditions The received symbol is obtained, where, .

[0119] The following detailed implementation of the analog circuit based on the unified probabilistic graphical computing architecture described above is illustrated through specific embodiments. This embodiment transforms each signal processing problem in the baseband signal processing task into a problem of estimating unknown variables based on observed variables and correlation patterns. Each verification node... i To variable node j The mutual message passing process is all calculated on the in-memory computing device. The in-memory computing device in this embodiment is only used as an example for illustration, and is not limited to this.

[0120] like Figure 3 As shown, the memristor array used in this embodiment includes an initial input array, an iterative calculation array, and a result output array. The node state values ​​of the initial input array, iterative calculation array, and result output array are configured based on a unified probabilistic graphical model. The specific implementation process is as follows:

[0121] (1) The configuration and calculation process of the initial input matrix is ​​as follows:

[0122] The initial input array size is configured as follows: , For the correlation mapping matrix The number of columns; For the association mapping matrix the number of rows, The number of states of the variable node is . , Represents a set (Indicates the relationship with the verification node) i There are connections, except for variable nodes. j Candidate vectors in the combination of all variable node states except those of other variables The number of.

[0123] The initial input to the input array is a voltage proportional to the initial probability of the variable node state values, as follows:

[0124]

[0125] Based on the above input voltage, the initial input array performs the following calculations:

[0126] ;

[0127] The initial input array output current sequence is:

[0128]

[0129] in, .

[0130] The initial input matrix is ​​for The value corresponding to the node in the column is:

[0131]

[0132] in, Indicates satisfaction of The corresponding voltage input row index, specifically, selects the node belonging to the test node. i The elements in the candidate vectors of all connected variable nodes take values ​​of The corresponding variable node is j of If a value exists, the corresponding value for that node is set to 1; otherwise, it is set to 0. `e` represents the `e`th element from the top. 1 indicates the memristor array node is in a low-impedance configuration and can conduct; 0 indicates the memristor array node is in a high-impedance configuration and cannot conduct. The row voltage corresponding to a value of 1 can be accumulated, outputting current at the output terminal, equivalent to... The calculations in the process.

[0133] (2) The iterative computation array includes a first iterative subarray, a second iterative subarray, and an external input subarray. The configuration and computation process of the iterative computation array are as follows:

[0134] The first iteration subarray is used to complete message passing from the check node to the variable node, and its size is set to... .

[0135] Specifically, during the first iteration, the row input voltage of the first iteration subarray is 0, and the column output of the initial input array is connected to the column input of the first iteration subarray to start the iteration. x l Values u k At that time, the complete operation in the first iteration subarray is:

[0136]

[0137] During iteration, the row input voltage corresponding to the first iteration subarray is:

[0138]

[0139] The element order in the column output current arrangement vector corresponding to the first iteration subarray is:

[0140]

[0141] in, .

[0142] The first iteration subarray contains the columns of nodes ( The corresponding node state value is:

[0143]

[0144] in, Indicates satisfaction of The corresponding voltage input row index, specifically, selects the node belonging to the test node. i The elements in the candidate vectors of all connected variable nodes take values ​​of The corresponding variable node is j of The previous iteration of the value input to all test nodes of Does it exist? If it does, the value of the node is 1; if it does not exist, the value of the node is 0. A special case is when... k When =1, the state value of this node is set to 1; e represents the e-th element from top to bottom, 1 indicates that the memristor array node is in a low configuration and can conduct, 0 indicates a high impedance state and cannot conduct. The row voltage corresponding to the value 1 can be accumulated, and the output current is output at the output terminal, which is equivalent to The calculations in the process.

[0145] The second iteration subarray and the external input subarray are used to complete message passing from the variable node to the verification node, and are used to calculate the row input of the first iteration subarray, specifically:

[0146] The size of the second iteration subarray is The size of the external input subarray is Unlike the first iterative subarray, the second iterative subarray and the external input subarray have columns corresponding to row voltage inputs and rows corresponding to current readouts. The output of the first iterative subarray needs to undergo a current-to-voltage conversion when it reaches the input of the second iterative subarray. Conversely, the output of the second iterative subarray needs to undergo a current-to-voltage conversion when it reaches the input of the first iterative subarray.

[0147] The input to the external input subarray is directly supplied by an external voltage. The external input voltage of the external input subarray is:

[0148]

[0149] in, .

[0150] The second iteration subarray and the external input subarray together complete the calculation as follows:

[0151]

[0152] The common output of the second iteration subarray and the external input subarray is:

[0153]

[0154] The relationship between the input of the first iteration subarray and the common output of the second iteration subarray and the external input subarray is as follows:

[0155]

[0156] Second iteration subarray row output The corresponding node value configuration is as follows:

[0157]

[0158] in, Indicates satisfaction of The corresponding column index, its specific meaning, is selected in relation to the validation node. i Connected and variable nodes j Values The combination of all variable node states ,like If it exists, the node value is configured to 1; if If a node does not exist, its value is set to 0; 'e' represents the e-th array node from left to right.

[0159] External input subarray row output The corresponding node status value is configured as follows:

[0160]

[0161] Where e represents the e-th array node from left to right. Indicates satisfaction of The corresponding column index, its specific meaning, is selected in relation to the validation node. i Connected and variable nodes j Values The combination of all variable node states ,like If it exists, the node value is configured to 1; if If the node does not exist, its value is configured to 0.

[0162] (3) The output array is the output result generation matrix, with a size of The rows of the output array are concatenated with the rows of the first iterative subarray.

[0163] In this embodiment, the result output array is used to complete the calculation formula. , equivalent to:

[0164]

[0165] The order of elements in the column output current arrangement vector corresponding to the output array is as follows:

[0166]

[0167] for The node state values ​​corresponding to the nodes in the column are:

[0168]

[0169] in, Specifically, it means selecting variable nodes. j All connected verification nodes i The value of the middle is of ,like If it exists, the node value is configured to 1; if If it does not exist, the node value is configured to 0; e represents the e-th element from top to bottom.

[0170] It should be noted that the node state values ​​in all the above subarrays are configured before the iteration. After a certain number of iterations, the output of the result array obtains the final decision result based on the preset decision conditions. ,in .

[0171] Furthermore, different candidate variables can be constructed based on different baseband signal processing tasks. To more clearly illustrate the content of this invention, the content of the candidate vectors is explained using a decoding task as an example:

[0172] like Figure 4 As shown, in this embodiment, for any verification node In a probabilistic graphical model, the target variable nodes connected to the verification node, as well as the target undirected edges, can be determined. For example... Figure 3 As shown, when When the value is 3, the target variable nodes connected by the 3rd verification node are the 2nd, 3rd, and 4th variable nodes, respectively. At this time, the number of undirected edges in the target node is... The value is 3. Each target undirected edge is an undirected edge connecting the 3rd verification node to the 2nd, 3rd, and 4th variable nodes, respectively. The internal order of each target undirected edge among all target undirected edges is 1, 2, and 3.

[0173] The target character includes 0 and 1. At this point... The result is 3. Multiple candidate vectors are constructed by permuting and combining the three target characters. The number of candidate vectors is 2^3 (K=2), or 8 candidate vectors: (0,0,0), (0,0,1), (0,1,0), (0,1,1), (1,0,0), (1,0,1), (1,1,0), and (1,1,1). It's understood that the number of elements in the candidate vectors is the same as the number of undirected edges in the target vectors. The first, second, and third target characters in the candidate vectors are then associated with the target variable nodes connected by the undirected edges in order 1, 2, and 3, respectively. In other words, the first, second, and third target characters in the candidate vectors are associated with the second, third, and fourth variable nodes, respectively. The internal order of the target undirected edges is determined by the following steps. The first, second, and third target undirected edges are traversed sequentially. Upon reaching each target undirected edge, the eight candidate vectors are divided into first and second candidate vectors. For example, when traversing the third target undirected edge... If the value is 3, and the third element of a candidate vector is 1, then it is determined as the first candidate vector; if the third element of a candidate vector is 0, then it is determined as the second candidate vector. The first candidate vectors in this case include (0, 0, 1), (0, 1, 1), (1, 0, 1), and (1, 1, 1), while the second candidate vectors include (0, 0, 0), (0, 1, 0), (1, 0, 0), and (1, 1, 0). Each of the first and second candidate vectors mentioned above is then used as a candidate vector to be processed. For example, when the first candidate vector (0, 1, 1) is taken as the candidate vector to be processed, a zero vector (0, 0, 0, 0, 0, 0) with a total number of elements equal to the total number of variable nodes (6) is first constructed. The first, second, and third target characters in the first candidate vector are associated with the second, third, and fourth variable nodes, respectively. Therefore, in this embodiment, the second, third, and fourth zero elements in the zero vector can be replaced with the first, second, and third target characters in the first candidate vector, respectively, to obtain the corresponding processed first candidate vector (0, 0, 1, 1, 0, 0). At this point, when this embodiment traverses to the third target undirected edge, it can obtain four processed first candidate vectors and four processed second candidate vectors based on this target undirected edge.

[0174] Example 2: Following the method for implementing analog circuits based on a unified probabilistic graph computation architecture provided in Example 1, this example provides an apparatus for implementing analog circuits based on a unified probabilistic graph computation architecture. The apparatus provided in this example can implement the method for implementing analog circuits based on a unified probabilistic graph computation architecture as described in Example 1. This apparatus can be implemented through software, hardware, or a combination of both. For ease of description, this example is described by dividing the functionality into various units. Of course, in implementation, the functions of each unit can be implemented in one or more software and / or hardware components. For example, the apparatus may include integrated or separate functional modules or units to execute the corresponding steps in the methods of Example 1. Since the apparatus in this example is basically similar to the method example, the description process of this example is relatively simple. For relevant details, please refer to the description in Example 1. The example of the apparatus for implementing analog circuits based on a unified probabilistic graph computation architecture provided by this invention is merely illustrative.

[0175] Specifically, the present invention also provides an analog circuit implementation device based on a unified probabilistic graphical computing architecture, comprising:

[0176] The signal model building unit is configured to establish a unified signal model based on the common characteristics of baseband signal processing tasks;

[0177] The probabilistic graphical building unit is configured to represent a unified signal model as a unified probabilistic graphical model.

[0178] The probability initialization unit is configured to obtain the initial probabilities of the state values ​​of variable nodes in the unified probabilistic graphical model.

[0179] The in-memory computing device configuration unit is configured to set up in-memory computing characteristic devices, which include an initial input array, an iterative calculation array, and a result output array. The node state values ​​of the initial input array, iterative calculation array, and result output array are configured based on a unified probabilistic graphical model.

[0180] The iterative computation unit is configured to use the driving vector obtained from the initialization probability as the input to the initial input array. The iterative computation array is used to complete the iterative computation of mutual message passing between variable nodes and test nodes in the unified probabilistic graphical model. When the iteration stopping condition is met, the result output array outputs the processing result, thus completing the baseband signal processing task.

[0181] Example 3: This example provides an electronic device corresponding to the analog circuit implementation method based on the unified probabilistic graph computing architecture provided in Example 1. The electronic device can be an electronic device for a client, such as a mobile phone, laptop, tablet computer, desktop computer, etc., to execute the method of Example 1.

[0182] Example 4: This example provides a computer-readable storage medium for storing one or more programs, the one or more programs including computer instructions, which, when executed by a computer, cause the computer to perform the method provided in Example 1 above.

[0183] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In the description of this specification, the terms "a preferred embodiment," "furthermore," "specifically," "in this embodiment," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the embodiments in this specification. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described can be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0184] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for implementing analog circuits based on a unified probabilistic graphical computing architecture, characterized in that, include: Based on the common characteristics of baseband signal processing tasks, a unified signal model is established; The unified signal model is represented as a unified probabilistic graphical model; Obtain the initial probabilities of the variable node state values ​​in the unified probabilistic graphical model; A memory computing device is configured, comprising an initial input array, an iterative computation array, and a result output array, wherein the node state values ​​of the initial input array, the iterative computation array, and the result output array are configured based on the unified probabilistic graphical model. The driving vector obtained based on the initialization probability is used as the input of the initial input array. The iterative calculation array is used to complete the iterative calculation of mutual message passing between variable nodes and verification nodes in the unified probabilistic graphical model. When the iteration stopping condition is met, the result output array outputs the processing result to complete the baseband signal processing task.

2. The analog circuit implementation method according to claim 1, characterized in that, Based on the common characteristics of baseband signal processing tasks, a unified signal model is established as follows: ,in, For unknown variables, For observed variables, For given and The correlation mapping matrix between them This is unknown disturbance noise. Each is a certain unknown variable. For each of the observed variables, For the correlation mapping matrix The number of columns, For the correlation mapping matrix number of rows.

3. The analog circuit implementation method according to claim 2, characterized in that, The unified probabilistic graphical model includes variable nodes, verification nodes, and undirected edges, wherein the undirected edges are used to connect the variable nodes and the verification nodes that have a connection relationship. The variable nodes represent unknown variables; The verification node represents the coupling relationship between the unknown variable, the observed variable, and the correlation mapping matrix, and is set with a probability configuration function based on the correlation mapping matrix to characterize the differentiated constraint rules between baseband signal processing tasks.

4. The analog circuit implementation method according to claim 3, characterized in that, The message passing from the verification node to the variable node is as follows: in, For each state contained in a variable node, For verification nodes To variable node Passing information about variable nodes The state value is The news, For probability configuration function Take the logarithm. for The probability configuration function, Indicates and verifies nodes Connected and variable nodes Values The combination of all variable node states; Indicates and verifies nodes i Connected and variable nodes Values The combination of all variable node states, Indicates the first The candidate vector constructed from the nth undirected edge Each element value Represents the variable nodes in the candidate vector The corresponding element value, Represents the variable nodes in the candidate vector The corresponding element value, express From the verification node A set of indexes of variable nodes with connections Take the value from the middle. Represents variable nodes To the verification node The message conveyed about The message; The message passing from the variable node to the verification node is as follows: in, Represents variable nodes To the verification node The message conveyed about The news, For verification nodes To variable node Passing information about variable nodes The state value is The news.

5. The analog circuit implementation method according to claim 4, characterized in that, The configuration and calculation process of the initial input array is as follows: The initial input array configuration size is , The number of states of the variable node. The number of candidate vectors; The input to the initial input array is an input voltage that is proportional to the initialization probability of the state values ​​of the variable nodes: ； Based on the input voltage, the initial input array performs the following calculations: ； The column output current of the initial input array is: The node state values ​​corresponding to the columns of nodes in the initial input array are: Where e represents the e-th element from the top. Indicates satisfaction of The corresponding voltage input row index, specifically, indicates the selection of the node belonging to the verification node. The elements in the candidate vectors of all connected variable nodes take values ​​of The corresponding variable node is of If the value exists, the value corresponding to the node is set to 1; otherwise, it is set to 0. 1 indicates that the node is in a low-impedance state and can be turned on, while 0 indicates that the node is in a high-impedance state and cannot be turned on. The row voltage corresponding to the value of 1 can be accumulated and output current at the output terminal.

6. The analog circuit implementation method according to claim 5, characterized in that, The iterative computation array includes a first iterative subarray, a second iterative subarray, and an external input subarray. The configuration and computation process of the iterative computation array are as follows: The first iterative subarray is used to complete the message passing from the verification node to the variable node, and its size is set to... The output of the initial input array is connected to the column input of the first iterative subarray to initiate iteration. x l Values u k At that time, the calculation performed by the first iterative subarray is as follows: At the start of the iteration, the row input voltage of the first iterative subarray is: The element order in the column output current arrangement vector corresponding to the first iterative subarray is: in, ; The node state values ​​corresponding to the columns of nodes in the first iterative subarray are: in, Indicates satisfaction of The corresponding voltage input row index, specifically, indicates the selection of the node belonging to the verification node. The elements in the candidate vectors of all connected variable nodes take values ​​of The corresponding variable node is of The value of the previous iteration input to all verification nodes of If a node exists, its value is 1; otherwise, its value is 0. A special case exists when... k When =1, the state value of this node is set to 1, where 1 indicates that it can conduct and 0 indicates that it cannot conduct; e represents the e-th element from top to bottom; The second iterative subarray and the external input subarray are used to complete the message passing from the variable node to the verification node, wherein: the size of the second iterative subarray is... The size of the external input subarray is The columns of the second iterative subarray and the external input subarray correspond to the row voltage input, and the rows correspond to the current readout, and the rows of the second iterative subarray and the external input subarray are connected in series; The column voltage values ​​of the external inputs of the external input subarray: in, ; The second iterative subarray and the external input subarray together perform the calculation as follows: The common output of the second iterative subarray and the external input subarray is: The relationship between the row input of the first iterative subarray and the common output of the second iterative subarray and the external input subarray is as follows: The node state values ​​corresponding to the output of the second iterative subarray row are configured as follows: in, Indicates satisfaction of The corresponding column index, specifically, refers to the selection and verification of nodes. Connected and variable nodes Values The combination of all variable node states ,like If it exists, the node value is configured to 1; if If a node does not exist, its value is configured as 0, where 1 indicates that it can conduct and 0 indicates that it cannot conduct; e represents the e-th array node from left to right. The node state value corresponding to the row output of the external input subarray is configured as follows: in, Indicates satisfaction of The corresponding column index, its specific meaning, is selected in relation to the validation node. Connected and variable nodes Values The combination of all variable node states ,like If it exists, the node value is configured to 1; if If a node does not exist, its value is configured as 0, where 1 indicates that the node can conduct and 0 indicates that it cannot conduct; e represents the e-th array node from left to right.

7. The analog circuit implementation method according to claim 6, characterized in that, If the iteration stopping condition is met, the result output array is used to output the processing results, wherein the configuration and calculation of the result output array are as follows: The configuration size of the result output array is The rows of the result output array are concatenated with the rows of the first iterative subarray; The result output array completes the calculation as follows: The column output current corresponding to the output array of the results is: The node state values ​​corresponding to the columns of nodes in the output array are: in, Specifically, it means selecting variable nodes. All connected verification nodes The value of the middle is of ,like If it exists, the node value is configured to 1; if If a node does not exist, its value is set to 0. 1 indicates that the node is conductive, 0 indicates that it is not conductive, and e represents the e-th element from the top.

8. An analog circuit implementation device based on a unified probabilistic graphical computing architecture, characterized in that, include: The signal model building unit is configured to establish a unified signal model based on the common characteristics of baseband signal processing tasks; A probabilistic graphical construction unit is configured to characterize the unified signal model as a unified probabilistic graphical model; The probability initialization unit is configured to obtain the initial probability of the state values ​​of the variable nodes in the unified probabilistic graphical model. The in-memory computing device configuration unit is configured to set up an in-memory computing integrated feature device, which includes an initial input array, an iterative calculation array, and a result output array, wherein the node state values ​​of the initial input array, the iterative calculation array, and the result output array are configured based on the unified probabilistic graphical model. The iterative calculation unit is configured to obtain the driving vector based on the initialization probability as the input of the initial input array. The iterative calculation array is used to complete the iterative calculation of mutual message passing between variable nodes and verification nodes in the unified probabilistic graphical model. When the iteration stopping condition is met, the result output array outputs the processing result to complete the baseband signal processing task.

9. An electronic device, characterized in that, include: At least one processor; And a memory communicatively connected to the processor; wherein the memory stores instructions executable by the processor, the instructions being executed by the processor to enable the processor to perform the method according to any one of claims 1-7.

10. A computer-readable storage medium for storing one or more programs, characterized in that, One or more programs include computer instructions for causing a computer to perform the method according to any one of claims 1-7.

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