FPGA-based PCM acquisition and coding device dynamic framing IP core and method

Abstract

The application discloses a dynamic framing IP core and method of a PCM sampling and coding device based on FPGA. The IP core comprises a register access module, a DNA authorization module, a sampling frame processing module, a framing control module and a PCM coding module. The method comprises the following steps: performing parameter configuration on the IP core register; verifying an authorization key by the DNA authorization module; receiving and buffering sampling frames in parallel by the sampling frame processing module, and assembling PCM frame data; and performing PCM coding according to the code type configured by the register. The application has the advantages of strong generality and high flexibility of frame format, high deployment efficiency, support for predefinition and fast dynamic switching of three frame formats, support for 32-way parallel framing of sampling frames, support for common PCM code type output, all functions accessible through register access without additional logic, adoption of a standard AXI-Lite interface for the register interface, and integration of the DNA authorization function.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of digital telemetry, and particularly relates to an FPGA-based PCM acquisition and coding device dynamic framing IP core and method. BACKGROUND

[0002] The PCM acquisition and coding device is an important component in a modern digital telemetry system, and its core function is to complete acquisition and reception of multiple analog and digital signals, and frame formation according to a specific format to form a transmittable PCM code stream signal.

[0003] The existing PCM acquisition and coding device frame format is generally a fixed frame format, which has been fixed at the time of code design. Any slight change in the frame format, such as adding a measurement channel, requires re-designing the code, re-combining, layout and programming into the FPGA. This way has insufficient flexibility and expandability. When the task requirement changes, the software needs to be re-developed, causing the project cycle to be lengthened. In a flight test task, the measurement parameters of interest often change dynamically with the task stage, and the PCM frame format also has different frame formats at different stages of the flight test. The fixed frame format is difficult to adapt to such dynamic requirements. SUMMARY

[0004] Therefore, the primary purpose of the present application is to provide an FPGA-based PCM acquisition and coding device dynamic framing IP core and method to solve the problems of insufficient flexibility and expandability in the prior art.

[0005] Another purpose of the present application is to provide a corresponding method that can switch the PCM frame format in real time and dynamically without reconfiguring the FPGA code.

[0006] To achieve the above purpose, the technical solution of the present application is as follows:

[0007] In a first aspect, the present application provides an FPGA-based PCM acquisition and coding device dynamic framing IP core, comprising a register access module, an acquisition frame processing module, a framing control module, a PCM coding module and a DNA authorization module.

[0008] The acquisition frame processing module, the framing control module, the PCM coding module and the DNA authorization module are all connected with the register access module, the acquisition frame processing module is connected with the framing control module, and the framing control module is connected with the PCM coding module.

[0009] The registers of the register access module include a frame format 1 channel register group, a frame format 2 channel register group, a frame format 3 channel register group, a scrambling channel register group, an idle fill word register group, a frame format register group and a control register group.

[0010] The acquisition frame processing module includes 32 processing units with the same structure, the input interface of the processing unit is a standard AXI4-Stream slave interface, and the signal group of the interface includes TVALID, TREADY, TDATA and TLAST;

[0011] The register interface of the FPGA-based PCM acquisition and encoding device dynamic framing IP core is a standard AXI4-Lite interface.

[0012] Further, the acquisition frame processing module is used for receiving and buffering acquisition frames and generating to-be-framed data; the framing control module is used for framing the to-be-framed data according to a set frame format to generate a binary code stream; the PCM encoding module is used for encoding frame data; the DNA authorization module is used for verifying whether a DNA authorization key configured by a host is correct; and the register access module is used for setting a frame format, a working mode and running parameters.

[0013] The frame format 1 channel register group is used for describing the content of each channel of the frame format 1; the frame format 2 channel register group is used for describing the content of each channel of the frame format 2; the frame format 3 channel register group is used for describing the content of each channel of the frame format 3; the scrambling channel register group is used for defining the scrambling corresponding to each channel; the idle fill word register group is used for defining the character filled when a channel is idle; the frame format register group is used for describing a subframe synchronization code group, a subframe length, a subframe length and frame format selection; and the control register group is used for controlling the running state of the IP core and PCM encoding code type control.

[0014] In a second aspect, based on the same aspect, the application further provides a method of a FPGA-based PCM acquisition and encoding device dynamic framing IP core, including the following steps:

[0015] S1, after the system is powered on, a host performs parameter configuration on IP core registers through an AXI4-Lite access bus interface;

[0016] S2, a DNA authorization module verifies whether a DNA authorization key configured by a host is correct, and generates an authorization state signal;

[0017] S3, an acquisition frame processing module receives and buffers acquisition frames in parallel, waits for a channel gating signal of a framing control module, and if the FIFO corresponding to the channel is not empty, reads one byte of acquisition frame data from the FIFO;

[0018] S4, the framing control module reads a channel descriptor from a channel register, generates a channel descriptor sequence, and assembles PCM frame data according to the channel descriptor sequence;

[0019] S5, the PCM encoding module encodes the binary code stream generated in step S4 according to the code type configured by the register.

[0020] Further, in step S1, the host configures the IP core register through AXI4-Lite access bus interface, including:

[0021] S11, the host writes a reset command to the IP core reset control register to perform soft reset operation;

[0022] S12, the host writes the configuration parameters into the corresponding register in turn through AXI4-Lite bus transaction according to the pre-defined register mapping table;

[0023] S13, the host writes a start command to the IP core start control register.

[0024] Further, in step S12, the configuration parameters written into the register include frame format parameters, channel definition parameters and PCM encoding parameters.

[0025] Further, in step S2, the DNA authorization module verifies whether the DNA authorization key configured by the host is correct to generate an authorization state signal, including:

[0026] S21, the DNA authorization module reads the device DNA code by calling the DEVICE_DNA primitive provided by the FPGA and stores it into the DNA code register;

[0027] S22, the DNA authorization module encrypts the 57 or 96-bit DNA code into a 32-bit local key A through the AES encryption algorithm;

[0028] S23, the host reads the DNA code register to obtain the DNA code of the current FPGA, queries the key library to find the matching key B, and writes the key B into the DNA authorization key register;

[0029] S24, the DNA authorization module compares the local key A with the key B, and if they are consistent, generates an authorization success state flag signal.

[0030] Further, in step S3, the received acquisition frame includes:

[0031] S31, it is judged whether the DNA authorization state is successful, if yes, the acquisition frame reception is started, otherwise, it is idle and waits;

[0032] S32, the received acquisition frame data and the frame tail flag TLAST signal are stored into FIFO1;

[0033] S33, when a complete acquisition frame is received, the complete acquisition frame is transferred to FIFO2.

[0034] S34, if the channel gating signal sent by the framing control module is received, firstly judge whether FIFO2 is empty, if not empty, read a byte of data and assign it to DBuf1 register; otherwise, do not read FIFO2.

[0035] Further, in step S4, the PCM frame is assembled, including:

[0036] S41, judge the DNA authorization state, if the authorization is successful, start the framing operation, otherwise idle and wait;

[0037] S42, read the frame format register group value, get the current frame format to be executed, and the sub-frame synchronization code group, sub-frame length and sub-frame length;

[0038] S43, read the scrambling channel register group, idle character register group value;

[0039] S44, judge the current selected frame format, start from the first register of the frame format channel register group, read the channel register in turn to generate the channel descriptor sequence;

[0040] S45, according to the channel descriptor sequence, start the assembly of PCM frame channel data;

[0041] S46, frame format dynamic switching: when the value of frame format selection register is detected to change, the current PCM frame assembly will not be interrupted, but at the moment of generating the next frame synchronization starting point, the new frame format configuration is used to assemble the subsequent PCM frame;

[0042] S47, when the accumulated length of the read channel descriptor sequence and the sub-frame length are consistent, it means that the assembly of a PCM frame is completed;

[0043] S48, according to steps S44~S46, the PCM frame assembly operation is circularly performed;

[0044] S49, the PCM framed data is converted into parallel serial to generate binary code stream.

[0045] Further, in step S45, the assembly of PCM frame channel data includes:

[0046] S451, insert synchronization code;

[0047] S452, gate and read the data of the corresponding FIFO in the acquisition frame processing module;

[0048] S453, insert frame count and checksum fixed information;

[0049] S454, inserting idle fill characters when data is missing, scrambling to form PCM frame byte data.

[0050] Further, in step S5, PCM encoding, comprising:

[0051] Encoding the binary code stream into a set of PCM code types, including NRZ-L, NRZ-M, NRZ-S, BiΦ-L, BiΦ-M and BiΦ-S.

[0052] Compared with the prior art, the FPGA-based PCM encoder and decoder dynamic framing IP core and method has the following beneficial effects:

[0053] The frame format is defined by a configurable register group, overcoming the defects of fixed frame format, re-designing and burning FPGA code, realizing software-level dynamic switching of frame format, greatly improving flexibility and deployment efficiency; the frame format is highly universal, supporting 3 kinds of frame format pre-definition and fast dynamic switching; supporting 32-way acquisition frame parallel framing; supporting common PCM code type output; all functions can be accessed through registers, without additional logic; the register interface adopts a standard AXI-Lite interface, enabling the IP core to seamlessly interface with various host processors supporting the standard protocol, improving the universality and integrability of the IP core; integrating a DNA authorization function to protect the IP core property. BRIEF DESCRIPTION OF DRAWINGS

[0054] The drawings constituting a part of the present application are used to provide a further understanding of the present application, the illustrative embodiments of the present application and the description thereof are used to explain the present application, and do not constitute an improper limitation on the present application. In the drawings:

[0055] Figure 1 The PCM encoder and decoder function block diagram described in the embodiments of the present application;

[0056] Figure 2 The framing IP core structure block diagram described in the embodiments of the present application;

[0057] Figure 3 The data processing flowchart of the processing unit 1 (PE1) described in the embodiments of the present application;

[0058] Figure 4 The framing control module workflow diagram described in the embodiments of the present application;

[0059] Figure 5 The DNA authorization module workflow diagram described in the embodiments of the present application;

[0060] Figure 6 The IP core overall workflow diagram described in the embodiments of the present application. DETAILED DESCRIPTION

[0061] It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0062] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element indicated must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second" and the like are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" and the like can explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0063] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium, or it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood through specific circumstances.

[0064] The present application will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0065] The FPGA-based PCM acquisition and encoder dynamic framing IP core includes a register access module, an acquisition frame processing module, a framing control module, a PCM encoding module and a DNA authorization module; the acquisition frame processing module, the framing control module, the PCM encoding module and the DNA authorization module are all connected with the register access module; the acquisition frame processing module is connected with the framing control module, and the framing control module is connected with the PCM encoding module.

[0066] The method of the FPGA-based PCM acquisition and encoder dynamic framing IP core includes the following steps:

[0067] S1, after the system is powered on, the host performs parameter configuration on the IP core register through the AXI4-Lite access bus interface;

[0068] S2. The DNA authorization module verifies whether the DNA authorization key configured on the host is correct and generates an authorization status signal.

[0069] S3. The acquisition frame processing module receives the buffered acquisition frames in parallel and waits for the channel selection signal from the frame control module. If the FIFO corresponding to the channel is not empty, one byte of acquisition frame data is read from the FIFO.

[0070] S4. The framing control module reads the channel descriptor from the channel register, generates a channel descriptor sequence, and then assembles PCM frame data according to the channel descriptor sequence. The assembly operation includes: inserting a synchronization code, selecting and reading the data of the corresponding FIFO in the acquisition frame processing module, inserting frame counting and checksum fixing information, inserting idle padding characters when data is missing, scrambling to form PCM frame byte data, and converting the byte data string to generate a binary code stream.

[0071] S5. The PCM encoding module performs PCM encoding on the binary code stream generated in step S4 according to the code pattern configured in the register.

[0072] Specifically as follows:

[0073] I. Overall Design of PCM Data Acquisition and Editing System

[0074] like Figure 1 As shown in the diagram, the PCM data acquisition and editing unit is divided into three parts: the host unit, the acquisition unit, and the framing IP core. The host unit initializes and configures the framing IP core and controls it in real time by accessing registers. The acquisition unit acquires, quantizes, and encodes the measured parameters (such as engineering telemetry parameters like temperature and voltage, images, audio, and load data) to form digital acquisition frame data output. The framing IP core, according to the register configuration, enables dynamic framing of up to 32 acquisition frames and outputs the PCM bitstream.

[0075] II. Top-level Design of the Framed IP Core

[0076] like Figure 2 The diagram shows the block structure of the framing IP core. This core enables dynamic framing of up to 32 acquisition frames. The IP core mainly comprises five modules: a register access module; an acquisition frame processing module; a framing control module; a PCM encoding module; and a DNA licensing module.

[0077] Real-time PCM frame assembly refers to the sequential assembly of PCM frame data from each channel under the control of the channel descriptor. This includes five assembly operations: synchronization code group generation, data gating and FIFO read enable, fixed field insertion, idle data filling, and scrambling.

[0078] The frame synchronization code group generation operation refers to generating a full frame / sub-frame synchronization code according to the descriptor indication; the channel gating and reading FIFO enabling operation refers to selecting a corresponding channel from the acquisition frame processing module as a multiplexer according to the acquisition frame channel information in the channel descriptor, and reading a byte of data from the FIFO of the channel; the fixed field insertion operation refers to inserting fixed information such as a frame counter and a check code; the idle data filling operation refers to filling with idle filling characters preset in an idle character register to ensure the integrity and continuity of the PCM frame when the channel descriptor requires reading the acquisition frame data of a channel, but the FIFO of the channel is empty; and the scrambling operation refers to scrambling the PCM frame that has been assembled according to the channel, that is, performing a bit XOR operation between the original channel content and the corresponding channel scrambling code to generate new channel data, so as to improve the randomness of the data.

[0079] When the frame format is dynamically switched, the frame format is not immediately switched. The framing control module monitors the value of the frame format selection register in real time, and when it is detected that the value changes, the module does not interrupt the PCM frame that is currently being assembled, but continues to complete the assembly of the current frame. At the moment when the next frame synchronization starting point is generated, the new frame format configuration is used to start assembling the subsequent PCM frame, so as to ensure the integrity and continuity of the PCM frame when the frame format is switched.

[0080] III. Register access module

[0081] The register access module provides a standard AXI4-Lite bus slave interface for receiving a frame format configuration parameter set and a running parameter issued by an external host (such as an embedded CPU) and safely storing the same. The configuration parameter set defines complete PCM frame format information. The module is the basis for the entire IP core to be configurable and dynamically reconfigurable.

[0082] The register interface of the framing IP core adopts a standard AXI4-Lite bus interface, which has the advantage that the register can be conveniently accessed whether the host is on the PS side or the PL side.

[0083] As shown in Tables 1 to 7, the registers describe the necessary information of the frame format, and other modules work according to the respective related register values, wherein Table 1 describes the frame format 1 channel register group, Table 2 describes the frame format 2 channel register group, Table 3 describes the frame format 3 channel register group, Table 4 describes the scrambling code channel register group, Table 5 describes the idle filling word register group, Table 6 describes the frame format register group, and Table 7 describes the control and status register group.

[0084] The frame format 1 channel register group is used to describe the content of each channel of frame format 1; the frame format 2 channel register group is used to describe the content of each channel of frame format 2; the frame format 3 channel register group is used to describe the content of each channel of frame format 3; the scrambling channel register group is used to define the scrambling corresponding to each channel; the idle fill word register group is used to define the character filled when the channel is idle; the frame format register group is used to describe the sub-frame synchronization code group, the sub-frame length, the sub-frame length and the frame format selection; the control register group is used to control the running state of the IP core and the PCM encoding type control.

[0085] Table 1

[0086]

[0087] Table 2

[0088]

[0089] Table 3

[0090]

[0091] Table 4

[0092]

[0093] Table 5

[0094] Register Address Description 0x1000 Frame Format 1 Capture Frame 0 Idle Characters 0x1001 Frame Format 1 Capture Frame 1 Idle Characters …… 0x101E Frame Format 1 Capture Frame 30 Idle Characters 0x101F Frame Format 1 Capture Frame 31 Idle Characters 0x1020 Frame Format 2 Capture Frame 0 Idle Characters 0x1021 Frame Format 2 Capture Frame 1 Idle Characters …… 0x103E Frame Format 2 Capture Frame 30 Idle Characters 0x103F Frame Format 2 Capture Frame 31 Idle Characters 0x1040 Frame Format 3 Capture Frame 0 Idle Characters 0x1041 Frame Format 3 Capture Frame 1 Idle Characters …… 0x105E Frame Format 3 Capture Frame 30 Idle Characters 0x105F Frame Format 3 Capture Frame 31 Idle Characters

[0095] Table 6

[0096]

[0097] Table 7

[0098]

[0099] The host configures the IP core register parameters through the AXI4-Lite access bus interface, as follows:

[0100] 1. The host writes a reset command to the IP core reset control register to perform a soft reset operation; the operation places all main logic (including the acquisition frame processing module, the framing control module, and the PCM encoding module) in a determined initial state except the register access module in the IP core, and clears all FIFO, resets the state machine and the counter;

[0101] 2. The host writes configuration parameters into corresponding registers in sequence through transactions of AXI4-Lite bus according to a predefined register mapping table; the configuration process follows a specific logical order to ensure that the IP core has complete and consistent frame format information before starting, which specifically includes: configuring frame format parameters, channel definition parameters and PCM encoding parameters;

[0102] 3. The host writes a start command into the IP core start control register. The rising edge of the write signal serves as a trigger event, making the frame format selection value configured in step 2 take effect formally, and at the same time activating the framing control module. The IP core then starts receiving acquisition frames and dynamically assembling and encoding PCM frames according to the configured frame format.

[0103] Four, acquisition frame processing module

[0104] The acquisition frame processing module includes 32 parallel channels, each channel is implemented by a processing element (PE, Process Element), and each processing element is composed of an asynchronous FIFO1 and a synchronous FIFO2, which are used to receive acquisition frames from different clock domains and different data sources, solve the cross-clock domain problem, provide data buffering, and at the same time, the module also provides the empty / full state flags of each FIFO to the framing control module. For the framing control module, the 32 processing elements are abstracted into 32 channels, and when framing data is needed, a read enable signal of the channel is generated, and the acquisition frame processing module takes out one byte of data from the FIFO of the corresponding processing element.

[0105] The input interface of the processing element is an AXI4-Stream interface, including Tvalid, Tready, Tdata and Tlast signals. Tvalid indicates that the host sends a valid transmission, Tready indicates that the slave can receive a transmission in the current period, and when Tvalid and Tready are both valid, the data is received by the slave. Tdata indicates the payload data of the transmission, and Tlast indicates the boundary of a frame, which is aligned with the frame tail. In this way, the specific data content does not need to be concerned during reception, greatly improving the universality.

[0106] As shown in Figure 3 the data processing flow of processing element 1 (PE1) is:

[0107] 1. Determine the DNA authorization state, if the authorization is successful, start acquisition frame reception, otherwise idle and wait;

[0108] 2. Store the received data and frame tail flag Tlast into the asynchronous FIFO1 in PE1;

[0109] 3. After receiving a complete acquisition frame, store the complete acquisition frame in the synchronization FIFO2 in PE1;

[0110] 4. Wait for the channel selection signal from the framing control module;

[0111] 5. If a channel selection signal is received from the framing control module, first check if FIFO2 is empty. If it is not empty, read one byte of data and assign it to the DBuf1 register; otherwise, do not perform a read operation on FIFO2.

[0112] V. Frame Control Module

[0113] The framing control module is the control center of the IP core. This module periodically and incrementally reads the channel descriptors, which are essentially microprograms or lookup tables that explicitly define the data to be assembled for each channel within a complete PCM frame cycle. Under the precise control of the channel descriptors, real-time assembly of PCM frames is achieved, and finally, a binary code stream is generated through parallel-to-serial conversion.

[0114] like Figure 4 As shown, the workflow of the framing control module is as follows:

[0115] 1. Determine the DNA authorization status. If authorization is successful, begin the framing operation; otherwise, wait idly.

[0116] 2. Read the frame format register group value to obtain the frame format of the current frame assembly to be performed, as well as frame format synchronization information such as subframe synchronization code group, subframe length, and subframe length;

[0117] 3. Read the values ​​of the scrambling channel register group and the idle character register group;

[0118] 4. Determine the currently selected frame format, and starting from the first register in the channel register group for that frame format, read the channel registers step by step to generate a channel descriptor sequence;

[0119] 5. Based on the channel descriptor sequence, begin assembling PCM frame channel data, including frame synchronization code group generation, channel gating and FIFO reading, fixed field insertion, idle data filling and scrambling assembly operations, and finally generate PCM frame data;

[0120] 6. When the cumulative length of the channel descriptor sequence read is consistent with the subframe length, it indicates that the assembly of a PCM frame has been completed;

[0121] 7. Repeat steps 4-6 to perform the PCM frame assembly operation;

[0122] 8. Perform parallel-to-serial conversion on the PCM framed data to generate a binary bitstream.

[0123] Six, PCM encoding module

[0124] The PCM encoding module is used for PCM encoding of the framed binary code stream to generate the required modulation code type; the PCM encoding module encodes the binary data according to the code type configured by the register, supports six code types, which are NRZ-L, NRZ-M, NRZ-S, BiΦ-L, BiΦ-M, and BiΦ-S, respectively.

[0125] Seven, DNA authorization module

[0126] The DNA authorization module is responsible for verifying the correctness of the authorization key configured by the host, and generating an authorization state signal, which directly controls the running state of the IP core. The authorization authentication is based on the unique DNA identification of the chip, and verifies whether the key is exclusively for the current FPGA hardware through the AES encryption algorithm. Each FPGA of Xilinx has a unique ID, called Device DNA, which is fixed in the eFuse register of the chip during FPGA chip production and has a non-modifiable attribute.

[0127] As shown in Figure 5 The workflow of the DNA authorization module, the DNA authorization module reads the device DNA code by calling the DEVICE_DNA primitive provided by the FPGA (such as the DNA_PORT of the Xilinx platform), and stores it in the DNA code register. At the same time, the module encrypts the 57-bit / 96-bit DNA code into a 32-bit local key A through the AES encryption algorithm (the AES encryption algorithm uses the AES-128 standard, where the plaintext, AES key, and ciphertext are all 128-bit data. Since the AES-128 algorithm itself is public, the security of the encryption process depends entirely on the AES key. According to the padding scheme defined in the encryption message syntax standard (PKCS#7), the original 57-bit or 96-bit DNA code is expanded to 128-bit plaintext. The AES key is pre-set by the IP developer to be 128-bit fixed value. After the plaintext is encrypted by AES-128, 128-bit ciphertext data is generated, and finally the lower 32 bits of the ciphertext are intercepted as the DNA authorization key.), the host reads the DNA code register to obtain the DNA code of the current FPGA, queries the key library to find the matching key B, and writes the key B into the DNA authorization key register, the module compares the local key A with the host key B, and generates an authorization flag signal when they are consistent, and the framing control module can only work normally when authorized.

[0128] As shown in Figure 6 The overall workflow of the method of the dynamic framing IP core of the FPGA-based PCM encoder and decoder:

[0129] 1. System initialization and configuration phase

[0130] After the system is powered on, the host configures the parameters of each register in the IP core through the standard AXI4-Lite bus interface. This step completes the basic settings such as frame format definition, synchronization code setting, scrambling configuration, idle character definition, and lays the foundation for subsequent dynamic framing.

[0131] 2. Authorization verification phase

[0132] The DNA authorization module starts the verification process: first, read the unique device DNA identification of the FPGA chip, generate the local key A through the AES encryption algorithm; at the same time, the host provides the corresponding authorization key B; through the consistency of the two, complete the hardware authorization verification. Only after the authorization is successful, the core function module of the IP core will be activated.

[0133] 3. Data acquisition and processing phase

[0134] After the authorization is passed, the acquisition frame processing module starts to work. The 32 parallel processing units receive the acquisition data through the AXI4-Stream interface, and after two-level FIFO buffering (asynchronous FIFO1 solves the cross-clock domain problem, and synchronous FIFO2 stores the complete acquisition frame), provide a stable and continuous data source for the framing module.

[0135] 4. Dynamic framing core phase

[0136] The framing control module is the core of the IP core, and works according to the following sub-processes:

[0137] 4.1 Read the currently effective frame format configuration;

[0138] 4.2 Generate the corresponding channel descriptor sequence;

[0139] 4.3 Assemble the PCM frame according to the sequence (including synchronization code insertion, data gating, fixed field insertion, idle filling and scrambling operation);

[0140] 4.4 Complete the parallel-to-serial conversion and generate the binary code stream.

[0141] 5. Encoding output phase

[0142] The PCM encoding module encodes the binary code stream into the specified PCM code type (such as NRZ-L, BiΦ-M, etc.) according to the code type configured by the register, and finally outputs the PCM code stream that meets the telemetry standard.

[0143] 6. Dynamic switching mechanism

[0144] During operation, the host can trigger frame format switching by modifying the frame format selection register. The framing control module will seamlessly switch to the new frame format after completing the assembly of the current frame, ensuring the integrity and continuity of the output bitstream.

[0145] Embodiment One: Phase-wise Dynamic Switching of PCM Frames in a Certain Aircraft Telemetry System

[0146] In this embodiment, the aircraft telemetry system needs to collect and transmit different sets of parameters in different phases of its flight (takeoff, cruise, reentry), so three different PCM frame formats are required.

[0147] Frame Format 1 (Takeoff Phase): Focus on monitoring engine parameters, short frame length, contains a large number of high-frequency sampled temperature and pressure channels.

[0148] Frame Format 2 (Cruise Phase): Focus on monitoring navigation and environmental parameters, medium frame length, contains attitude, GPS positioning, etc.

[0149] Frame Format 3 (Reentry Phase): Focus on monitoring aerodynamic heat and structural parameters, long frame length, contains heat flux, overload, etc.

[0150] Initialization Configuration Phase:

[0151] After the system is powered on, the host (such as the CPU in a computer) configures the IP core through the AXI4-Lite bus as follows:

[0152] 1. Write the detailed definitions of the three frame formats to the channel register groups of frame formats 1, 2, and 3. For example, define the 0-15 channels of frame format 1 as engine temperature 1-16, and the 16-31 channels as pressure 1-16, etc.

[0153] 2. Write the synchronization codes, subframe lengths, and subframe lengths corresponding to the three frame formats to the frame format register group;

[0154] 3. Write the default fill value (such as 0x55) of each channel when there is no data to the idle fill word register group;

[0155] 4. Write the pre-defined scrambling sequence to the scrambling channel register group;

[0156] 5. Configure the PCM code type field of the control register group to NRZ-L.

[0157] DNA Authorization Phase:

[0158] 1. The host reads the DNA code register to obtain a 96-bit device unique identifier;

[0159] 2. The host computer queries the corresponding authorization key B from the pre-stored key library according to the identification, and writes the authorization key B into the DNA authorization key register;

[0160] 3. The DNA authorization module in the IP core reads the device DNA code by calling the FPGA primitive, and generates the local key A by the AES encryption algorithm;

[0161] 4. The module compares the key A with the key B, and generates an authorization success signal if they are consistent. After that, the framing control module and the acquisition frame processing module are allowed to start.

[0162] Running and dynamic switching stage:

[0163] 1. Initial running: the host computer starts the IP core through the control register, and sets the frame format selection register to "0x01", selecting frame format 1. The framing control module starts reading the engine data from the corresponding channels (such as 0-15 channels) of the acquisition frame processing module according to the definition of frame format 1, assembles and outputs the PCM code stream of the take-off stage.

[0164] 2. Triggering and dynamic switching: the aircraft enters the cruising stage. The host computer only needs to write "0x02" into the frame format selection register, and the framing control module will not immediately respond to this change. It will continue to complete the entire PCM frame based on frame format 1 that is currently being assembled, ensuring the integrity of the frame structure. After assembling the last channel of the frame, the module automatically switches to the definition of frame format 2 when the next frame period starts. At this time, it starts reading data from different channels (such as navigation data channels) of the acquisition frame processing module, assembles and outputs the PCM code stream of the cruising stage. This process does not require FPGA reconstruction, achieving a nanosecond-level speed switch;

[0165] 3. Data buffering and fault tolerance: during the framing process, if the framing control module enables a certain acquisition channel (such as a certain image data channel in the cruising stage), but the FIFO of the channel is empty (possibly due to data processing delay), the module will automatically take the preset idle character for the channel from the idle character register group and fill it into the current channel, ensuring the continuity of the PCM code stream and preventing the loss of a single channel from causing an entire frame error.

[0166] Beneficial effect verification:

[0167] The embodiment clearly shows how the application achieves real-time, dynamic and seamless switching of complex PCM frame formats through simple register configuration. This solves the core problem of "poor flexibility of fixed frame format and the need to redesign the code for changes" in the background art, greatly shortens the task cycle, and improves the adaptability and reliability of the system.

[0168] The above merely provides the preferred embodiment of the present application, and is not used to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A dynamic framing IP core for a PCM data acquisition and editing system based on FPGA, characterized in that: It includes a register access module, a data acquisition frame processing module, a frame control module, a PCM encoding module, and a DNA licensing module; The acquisition frame processing module, the frame assembly control module, the PCM encoding module, and the DNA authorization module are all connected to the register access module. The acquisition frame processing module is connected to the frame assembly control module, and the frame assembly control module is connected to the PCM encoding module. The registers of the register access module include a frame format 1 channel register group, a frame format 2 channel register group, a frame format 3 channel register group, a scrambling code channel register group, a free padding word register group, a frame format register group, and a control register group. The acquisition frame processing module includes 32 identical processing units. The input interface of the processing unit is a standard AXI4-Stream slave interface, and its signal groups include TVALID, TREADY, TDATA and TLAST. The register interface of the dynamic framing IP core of the FPGA-based PCM data acquisition and editing unit is the standard AXI4-Lite interface. The acquisition frame processing module is used to receive and buffer acquisition frames and generate data to be assembled into frames; the frame assembly control module is used to assemble the data to be assembled into frames according to the set frame format and generate a binary code stream; the PCM encoding module is used to encode the frame data; the DNA authorization module is used to verify whether the DNA authorization key configured on the host is correct; the register access module is used to set the frame format, working mode and operating parameters. The Frame Format 1 channel register group is used to describe the content of each channel in Frame Format 1; the Frame Format 2 channel register group is used to describe the content of each channel in Frame Format 2; the Frame Format 3 channel register group is used to describe the content of each channel in Frame Format 3; the scrambling code channel register group is used to define the scrambling code corresponding to each channel; the idle padding word register group is used to define the characters filled when a channel is idle; the frame format register group is used to describe the subframe synchronization code group, subframe length, subframe length, and frame format selection; the control register group is used to control the IP core operating status and PCM encoding pattern control.

2. A method for dynamic framing IP core of a PCM acquisition and editing device based on FPGA, applied to the dynamic framing IP core of a PCM acquisition and editing device based on FPGA as described in claim 1, characterized in that: Includes the following steps: S1. After the system is powered on, the host accesses the bus interface through AXI4-Lite to configure the parameters of the IP core registers; S2. The DNA authorization module verifies whether the DNA authorization key configured on the host is correct and generates an authorization status signal. S3. The acquisition frame processing module receives the buffered acquisition frames in parallel and waits for the channel selection signal from the frame control module. If the FIFO corresponding to the channel is not empty, one byte of acquisition frame data is read from the FIFO. S4. The framing control module reads the channel descriptor from the channel register, generates a channel descriptor sequence, and then assembles the PCM frame data according to the channel descriptor sequence. S5. The PCM encoding module performs PCM encoding on the binary code stream generated in step S4 according to the code pattern configured in the register.

3. The method for dynamic framing IP core of FPGA-based PCM acquisition and editing unit according to claim 2, characterized in that: In step S1, the host configures the IP core registers via the AXI4-Lite bus interface, including: S11. The host writes a reset command to the IP core reset control register to perform a soft reset operation. S12. The host writes the configuration parameters into the corresponding registers sequentially through transactions on the AXI4-Lite bus according to the predefined register mapping table. S13. The host writes a startup command to the IP core startup control register.

4. The method for dynamic framing IP core of FPGA-based PCM acquisition and editing unit according to claim 3, characterized in that: In step S12, the configuration parameters written to the register include frame format parameters, channel definition parameters, and PCM encoding parameters.

5. The method for dynamic framing IP core of FPGA-based PCM acquisition and editing unit according to claim 2, characterized in that: In step S2, the DNA authorization module verifies whether the DNA authorization key configured on the host is correct and generates an authorization status signal, including: S21. The DNA authorization module reads the device DNA code by calling the DEVICE_DNA primitive provided by the FPGA and stores it in the DNA code register. S22, the DNA authorization module uses the AES encryption algorithm to encrypt the 57 or 96-bit DNA code into a 32-bit local key A; S23. The host reads the DNA code register to obtain the DNA code of the current FPGA, queries the key library, finds the matching key B, and writes key B into the DNA authorization key register. S24. The DNA authorization module compares local key A with key B. If they match, it generates an authorization success status signal.

6. The method for dynamic framing IP core of FPGA-based PCM acquisition and editing unit according to claim 2, characterized in that: In step S3, receiving the acquisition frame includes: S31. Determine the DNA authorization status. If authorization is successful, start receiving acquisition frames; otherwise, wait idle. S32. Store the received acquisition frame data and frame end flag TLAST signal into FIFO1; S33. After receiving a complete acquisition frame, transfer the complete acquisition frame to FIFO2; S34. If a channel selection signal is received from the framing control module, first determine whether FIFO2 is empty. If it is not empty, read one byte of data and assign it to the DBuf1 register; otherwise, do not perform the FIFO2 read operation.

7. The method for dynamic framing IP core of FPGA-based PCM acquisition and editing unit according to claim 2, characterized in that: In step S4, assembling the PCM frame includes: S41. Determine the DNA authorization status. If authorization is successful, start the framing operation; otherwise, wait idly. S42. Read the frame format register group value to obtain the frame format of the current frame group to be executed, as well as the subframe synchronization code group, subframe length and subframe length; S43. Read the values ​​of the scrambling channel register group and the idle character register group; S44. Determine the currently selected frame format, and start reading the channel registers step by step from the first register in the frame format channel register group to generate a channel descriptor sequence. S45. Based on the channel descriptor sequence, begin assembling the PCM frame channel data; S46, Frame format dynamic switching: When a change in the value of the frame format selection register is detected, the assembly of the current PCM frame will not be interrupted. Instead, at the moment when the next frame synchronization start point is generated, the new frame format configuration will be used to assemble the subsequent PCM frames. S47. When the cumulative length of the channel descriptor sequence read is consistent with the subframe length, it indicates that the assembly of a PCM frame has been completed. S48. Perform PCM frame assembly operations cyclically according to steps S44~S46. S49. Perform parallel-to-serial conversion on the PCM framed data to generate a binary code stream.

8. The method for dynamic framing IP core of FPGA-based PCM acquisition and editing unit according to claim 7, characterized in that: In step S45, the assembly of PCM frame channel data includes: S451, Insert synchronization code; S452. Select and read the data of the corresponding FIFO in the acquisition frame processing module; S453, Insert frame counting and checksum fixing information; S454. When data is missing, insert a filler character and scramble it to form PCM frame byte data.

9. The method for dynamic framing IP core of FPGA-based PCM acquisition and editing unit according to claim 2, characterized in that: In step S5, PCM encoding includes: The binary bitstream is encoded into a set PCM code pattern, which includes NRZ-L, NRZ-M, NRZ-S, BiΦ-L, BiΦ-M, and BiΦ-S.

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