Silicon controlled rectifier device and preparation method thereof

Abstract

The invention provides a silicon controlled rectifier device and a preparation method thereof, and belongs to the technical field of semiconductor protection devices, and the device comprises a substrate, a first epitaxial layer and a second epitaxial layer which are sequentially arranged from bottom to top; the isolation groove extends downwards into the substrate; the first transistor and the second transistor are formed in the second epitaxial layer of the first area, grid electrodes and drain electrodes of the first transistor and the second transistor are interconnected, the grid electrode of the first transistor is connected with the input port and the source electrode of the first transistor through a first resistor, and the grid electrode of the second transistor is connected with the source electrode of the second transistor through a second resistor; the first diode is formed in the first epitaxial layer of the second region, the anode is connected with the grounding end, and the cathode is connected with the source electrode of the second transistor; the anode of the second diode is connected with the grounding end, and the cathode is connected with the grid of the first transistor. The device has the advantages that due to the existence of the first diode, the device has high maintaining voltage, and the latch-up phenomenon can be avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor protection devices, in particular to a silicon controlled rectifier device and a preparation method thereof. BACKGROUND

[0002] Electro-Static Discharge (ESD) is a ubiquitous physical phenomenon that can occur between any two objects. Its causes mainly include friction, collision and electric induction between objects, and can enter the internal of electrical equipment through various ways such as human contact, metal mechanical equipment contact and electromagnetic field. Electro-Static Discharge has the characteristics of fast discharge speed and high instantaneous voltage, which causes great harm to the normal work of integrated circuits in electrical equipment, and even burns out the integrated circuits, thereby making the entire electrical equipment unable to work normally. With the development trend of integrated circuits towards ultra-miniaturization, ultra-high integration and multi-function, integrated circuits become more and more sensitive to electro-static discharge. Therefore, how to effectively protect integrated circuits from electro-static discharge has become an important problem to be solved in the electronic field.

[0003] Silicon Controlled Rectifier (SCR) is a device commonly used for ESD protection, which has excellent ability to release static electricity. Compared with traditional diodes, triodes and field effect transistors, silicon controlled rectifiers have the advantages of strong current discharge capacity, high discharge efficiency per unit area, small on-resistance, strong robustness and high protection level due to their unique positive feedback mechanism, and can achieve high electro-static protection level with small chip area on semiconductor planar process.

[0004] However, the traditional SCR device usually shows a low holding voltage. The holding voltage is too low to easily cause latch-up and damage the subsequent circuit. At the same time, when the protection object is a high-speed data port, the capacitance of the protection device is required to be as small as possible to avoid abnormality such as packet loss of high-speed signals during transmission, and the traditional SCR device is difficult to meet this actual demand. SUMMARY

[0005] In order to solve the above technical problems, the present application provides a silicon controlled rectifier device, and on the other hand, a preparation method of the silicon controlled rectifier device.

[0006] The technical problems solved by the present application can be realized by the following technical solutions:

[0007] A silicon controlled rectifier device, comprising:

[0008] a substrate comprising, from bottom to top, a substrate with a first conductivity type, a first epitaxial layer with the first conductivity type, and a second epitaxial layer with a second conductivity type;

[0009] an isolation groove extending downward from an upper surface of the second epitaxial layer into the substrate to divide the substrate into a first region and a second region;

[0010] a first transistor and a second transistor formed in the second epitaxial layer of the first region, gates and drains of the first transistor and the second transistor being interconnected, a gate of the first transistor being connected to an input port and a source of the first transistor through a first resistance, a gate of the second transistor being connected to a source of the second transistor through a second resistance;

[0011] a first diode formed in the first epitaxial layer of the second region, an anode of the first diode being connected to a ground terminal, and a cathode of the first diode being connected to the source of the second transistor;

[0012] a second diode, an anode of the second diode being connected to the ground terminal, and a cathode of the second diode being connected to the gate of the first transistor.

[0013] Preferably, further comprising:

[0014] a third diode formed in the second epitaxial layer of the second region, an anode of the third diode being connected to the source of the second transistor, and a cathode of the third diode being connected to the cathode of the first diode.

[0015] Preferably, further comprising:

[0016] a first well region with the second conductivity type formed in the second epitaxial layer of the first region, a first implant region with the second conductivity type and a second implant region with the first conductivity type being formed in the first well region, and the first implant region and the second implant region being connected to the input port;

[0017] a second well region with the first conductivity type formed in the second epitaxial layer of the first region, a third implant region with the second conductivity type and a fourth implant region with the first conductivity type being formed in the second well region;

[0018] a plurality of shield regions with the second conductivity type, implant energies of the plurality of shield regions being different, and each of the shield regions being connected to the first well region and the second well region, respectively;

[0019] The second implantation region, the first well region, the shielding region, the second epitaxial layer and the second well region constitute the first transistor, the first well region, the shielding region, the second epitaxial layer, the second well region and the third implantation region constitute the second transistor, the parasitic resistance of the first well region serves as the first resistance, and the parasitic resistance of the second well region serves as the second resistance.

[0020] Preferably, the first diode comprises:

[0021] One or more first buried layers with the second conductivity type are formed in the first epitaxial layer of the second region.

[0022] Preferably, the first diode further comprises:

[0023] A second buried layer with the first conductivity type is formed in the first epitaxial layer of the second region; wherein the first buried layer is formed in the second buried layer, or the second buried layer and the first buried layer are arranged alternately in sequence, and the junction depth of the second buried layer is greater than the junction depth of the first buried layer.

[0024] Preferably, the second diode is composed of the first epitaxial layer and the second epitaxial layer, and the reverse breakdown voltage of the second diode is greater than the reverse breakdown voltage of the first diode.

[0025] Preferably, further comprising:

[0026] A third well region with the second conductivity type is formed in the second epitaxial layer of the second region, and a fifth implantation region with the second conductivity type is formed in the third well region.

[0027] Preferably, the third diode comprises:

[0028] A sixth implantation region with the first conductivity type is formed in the second epitaxial layer of the second region.

[0029] Preferably, the third diode further comprises:

[0030] A third well region with the second conductivity type is formed in the second epitaxial layer of the second region, and the sixth implantation region is formed in the third well region.

[0031] Preferably, further comprising:

[0032] A dielectric layer is formed on the upper surface of the second epitaxial layer.

[0033] A front metal layer is formed on the upper surface of the dielectric layer and fills the contact hole formed in the dielectric layer to form a first front metal layer and a second front metal layer.

[0034] A passivation layer is formed on the upper surface of the dielectric layer and the front metal layer, and exposes the first front metal layer, which serves as the input port;

[0035] A back metal layer is formed on the lower surface of the substrate.

[0036] On the other hand, a method for fabricating a silicon controlled rectifier (SCR) device is provided, for fabricating the SCR device as described above, comprising:

[0037] Step S1: Provide a substrate having a first conductivity type, and form a first epitaxial layer having a first conductivity type on the upper surface of the substrate;

[0038] Step S2: Form a first diode in the first epitaxial layer;

[0039] Step S3: A second epitaxial layer with a second conductivity type is formed on the upper surface of the first epitaxial layer, and then an isolation trench is formed. The isolation trench extends downward from the upper surface of the second epitaxial layer into the substrate to divide the substrate into a first region containing the first diode and a second region containing the first diode.

[0040] Step S4: A first transistor and a second transistor are formed in the second epitaxial layer of the first region; wherein the gate and drain of the first transistor and the second transistor are interconnected, the gate of the first transistor is connected to the input port and the source of the first transistor through a first resistor, the gate of the first transistor is connected to the cathode of the second diode, the anode of the second diode is connected to the ground terminal, the gate of the second transistor is connected to the source of the second transistor through a second resistor, the source of the second transistor is connected to the cathode of the first diode, the anode of the first diode is connected to the ground terminal, and the first epitaxial layer and the second epitaxial layer constitute the second diode.

[0041] The advantages or beneficial effects of the technical solution of this invention are as follows:

[0042] The thyristor device proposed in this invention, when the input port encounters a surge or electrostatic event, the thyristor composed of the first transistor and the second transistor is turned on first, which causes the first diode to break down in reverse. Subsequently, the current is released to the ground terminal through the substrate. Due to the presence of the first diode, the device has a high holding voltage, which can effectively avoid the occurrence of latch-up. When the ground terminal encounters a surge or electrostatic event, the current is forward conducted to the input port through the second diode and released, which improves the stability and reliability of the device. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of the structure of the silicon controlled rectifier device in a preferred embodiment 1 of the present invention;

[0044] Figure 2 A schematic diagram of an equivalent circuit of the thyristor device in the preferred embodiment 1 of the present application;

[0045] Figure 3 A schematic diagram of a flow of the manufacturing method of the thyristor device in the preferred embodiment 1 of the present application;

[0046] Figures 4a-4k A schematic diagram of the structure of each step of the manufacturing method of the thyristor device in the preferred embodiment 1 of the present application;

[0047] Figure 5 A schematic diagram of the structure of the thyristor device in the preferred embodiment 2 of the present application;

[0048] Figure 6 A schematic diagram of the structure of the thyristor device in the preferred embodiment 3 of the present application;

[0049] Figure 7 A schematic diagram of the structure of the thyristor device in the preferred embodiment 4 of the present application;

[0050] Figure 8 A schematic diagram of the structure of the thyristor device in the preferred embodiment 5 of the present application;

[0051] Figure 9 A schematic diagram of an equivalent circuit of the thyristor device in the preferred embodiment 5 of the present application;

[0052] Figure 10 A schematic diagram of the structure of the thyristor device in the preferred embodiment 5 of the present application. DETAILED DESCRIPTION

[0053] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0054] It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0055] The present application will be further described below with reference to the drawings and specific embodiments, but the present application is not limited by the embodiments.

[0056] In this document, the first conductivity type is N type, and the second conductivity type is P type; or vice versa, the first conductivity type is P type, and the second conductivity type is N type.

[0057] The following embodiments of the present application take P-type as the first conductive type and N-type as the second conductive type as an example for illustration.

[0058] In the drawings, the corresponding doping concentration is indicated by "-" or "+" after the doping type "N" or "P". For example, "N-" represents a doping concentration lower than that of the N-doped region, while the "N+" doped region has a doping concentration higher than that of the N-doped region. The doped regions with the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different N-doped regions can have the same or different absolute doping concentrations.

[0059] Embodiment 1

[0060] The present embodiment 1 provides a silicon controlled rectifier device and a preparation method thereof, such as Figure 1 is a structural schematic diagram of the silicon controlled rectifier device of the present embodiment, Figure 2 is a schematic diagram of the equivalent circuit of the silicon controlled rectifier device of the present embodiment, Figure 3 is a flowchart of the preparation method of the silicon controlled rectifier device of the present embodiment, and Figures 4a-4k the structural schematic diagram of each step of the preparation method of the silicon controlled rectifier device of the present embodiment is shown.

[0061] The silicon controlled rectifier device is a low-capacitance protection device with lower capacitance while maintaining a higher voltage. As shown in Figure 1 and Figure 2 The device comprises:

[0062] a substrate 10, which comprises, from bottom to top, a substrate 1 with a first conductive type, a first epitaxial layer 2 with the first conductive type, and a second epitaxial layer 3 with a second conductive type;

[0063] an isolation groove 4 (DTI) extending downward from the upper surface of the second epitaxial layer 3 into the substrate 1 to divide the substrate 10 into a first region 100 and a second region 200;

[0064] a first transistor T1 and a second transistor T2 formed in the second epitaxial layer 3 of the first region 100, the gate and drain of the first transistor T1 and the second transistor T2 are interconnected, the gate of the first transistor T1 is connected to the input port IO and the source of the first transistor T1 through the first resistance R_NW, and the gate of the second transistor T2 is connected to the source of the second transistor T2 through the second resistance R_PW;

[0065] a first diode D1 formed in the first epitaxial layer 2 of the second region 200, the anode of the first diode D1 is connected to the ground, and the cathode of the first diode D1 is connected to the source of the second transistor T2;

[0066] A second diode D2, an anode of the second diode D2 is connected to the ground, and a cathode of the second diode D2 is connected to a gate of the first transistor T1.

[0067] Specifically, in the embodiment, when the input port encounters a surge or an electrostatic event, a silicon controlled rectifier (SCR) composed of the first transistor T1 and the second transistor T2 is turned on, and then the first diode D1 is reversely broken down, and then the current is released to the ground through the substrate 1. Due to the presence of the first diode D1, the device has a high holding voltage, and the occurrence of the latch-up phenomenon can be effectively avoided.

[0068] When the ground encounters a surge or an electrostatic event, the current is conducted to the input port in a forward direction through the second diode D2 and is released, improving the stability and reliability of the device.

[0069] As a preferred embodiment, wherein, further comprising:

[0070] A first well region NW1 with a second conductivity type is formed in the second epitaxial layer 3 of the first region 100, and a first implantation region 51 with the second conductivity type and a second implantation region 52 with a first conductivity type are formed in the first well region NW1, and the first implantation region 51 and the second implantation region 52 are connected to the input port IO;

[0071] A second well region PW with the first conductivity type is formed in the second epitaxial layer 3 of the first region 100, and a third implantation region 53 with the second conductivity type and a fourth implantation region 54 with the first conductivity type are formed in the second well region PW;

[0072] A plurality of shielding (NS) regions (NS1, NS2, NS3) with the second conductivity type, the implantation energies of the plurality of shielding regions (NS1, NS2, NS3) are different, and each shielding region is connected to the first well region NW1 and the second well region PW, respectively;

[0073] Wherein, the second implantation region 52, the first well region NW1, the shielding region (NS1, NS2, NS3), the second epitaxial layer 3, and the second well region PW constitute the first transistor T1, the first well region NW1, the shielding region (NS1, NS2, NS3), the second epitaxial layer 3, the second well region PW, and the third implantation region 53 constitute the second transistor T2, the parasitic resistance of the first well region NW1 serves as the first resistance R_NW, and the parasitic resistance of the second well region PW serves as the second resistance R_PW.

[0074] As a preferred embodiment, wherein, the first diode D1 comprises:

[0075] One second buried layer PB with the first conductivity type is formed in the first epitaxial layer 2 of the second region 200;

[0076] a plurality of first buried layers NB of the second conductivity type formed in the second buried layer PB.

[0077] As a preferred embodiment, the second diode D2 is composed of the first epitaxial layer 2 and the second epitaxial layer 3, and the reverse breakdown voltage of the second diode D2 is greater than the reverse breakdown voltage of the first diode D1.

[0078] As a preferred embodiment, the method further comprises:

[0079] a third well region NW2 of the second conductivity type formed in the second epitaxial layer 3 of the second region 200, and a fifth implantation region 55 of the second conductivity type formed in the third well region NW2.

[0080] As a preferred embodiment, the method further comprises:

[0081] a dielectric layer 6 formed on the upper surface of the second epitaxial layer 3;

[0082] a front metal layer 7 formed on the upper surface of the dielectric layer 6 and filling the contact hole formed in the dielectric layer 6 to form a first front metal layer 71 and a second front metal layer 72;

[0083] a passivation layer 8 formed on the upper surface of the dielectric layer 6 and the front metal layer 7, and exposing the first front metal layer 71, the first front metal layer 71 serving as an input port IO;

[0084] a back metal layer 9 formed on the lower surface of the substrate 1.

[0085] Further, a method for manufacturing a silicon controlled rectifier is provided, which is used for manufacturing the silicon controlled rectifier as described above, and comprises:

[0086] In step S1, as shown in FIG. 1, a substrate 1 of the first conductivity type is provided, and a first epitaxial layer 2 of the first conductivity type is formed on the upper surface of the substrate 1. Figure 4a

[0087] First, a P+ substrate 1 (P+Sub) silicon wafer is selected, and an epitaxial process is performed on the upper surface of the P+ substrate 1 to grow a P-type epitaxial layer (P-epi) to form the first epitaxial layer 2.

[0088] As a preferred embodiment, the P+ substrate 1 is selected from a super low resistivity material. In this embodiment, the resistivity of the P+ substrate 1 is less than 0.01 Ω.cm, but is not limited in this range.

[0089] As a preferred embodiment, the thickness of the first epitaxial layer 2 is 2 μm-10 μm, and the resistivity of the first epitaxial layer 2 is greater than 1 Ω.cm.

[0090] In step S2, as shown in FIG. 2, a second epitaxial layer 3 of the first conductivity type is formed on the upper surface of the first epitaxial layer 2. Figure 4b ​As shown, a first diode D1 is formed in the first epitaxial layer 2;

[0091] Specifically, the steps for forming the first diode D1 include:

[0092] The second buried layer PB is formed by photolithography, P-type ion implantation, and high-temperature propulsion; then the first buried layer NB is formed by photolithography, N-type ion implantation, and high-temperature propulsion.

[0093] Preferably, the implanted element in the P-type second buried layer PB is boron or boron difluoride, the implantation dose is 1E14 to 1E16 / cm2, and the implantation energy is 50 to 150 keV.

[0094] Preferably, the implanted element in the first buried layer NB of type N is phosphorus or arsenic, and more preferably antimony. The implantation dose is 1E15 to 1E16 / cm2, and the implantation energy is 80 to 200 keV.

[0095] As a preferred option, the high-temperature propulsion process conditions are set as follows: a high-temperature propulsion temperature of 1000℃~1200℃ and a time of 60~120 minutes. Under these conditions, both the N-type first buried layer NB and the P-type second buried layer PB can have a certain thickness. Moreover, since boron diffuses faster than antimony, the junction depth of the P-type second buried layer PB is greater than that of the N-type first buried layer NB, thus ensuring that the N-type first buried layer NB is completely encapsulated by the P-type second buried layer PB.

[0096] Step S3, as follows Figure 4c As shown, a second epitaxial layer 3 having a second conductivity type is formed on the upper surface of the first epitaxial layer 2;

[0097] Specifically, the P+ type substrate 1 (P+Sub) silicon wafer is cleaned to ensure that there are no impurity particles and native oxide layer on the surface of the silicon wafer. Then, an epitaxial process is performed to grow an N-type epitaxial layer (N-epi) to form the second epitaxial layer 3.

[0098] Preferably, the thickness of the second epitaxial layer 3 is 5 μm to 20 μm, and the resistivity of the second epitaxial layer 3 is greater than 1 Ω·cm.

[0099] Since epitaxial growth is a high-temperature process, the N-type first buried layer NB and the P-type second buried layer PB will diffuse upwards a certain distance as the second epitaxial layer 3 grows.

[0100] like Figure 4d As shown, an isolation trench 4 is then formed, which extends downward from the upper surface of the second epitaxial layer 3 into the substrate 1 to divide it into a first region 100 containing the first diode and a second region 200 containing the first diode.

[0101] Specifically, the surface is coated with adhesive, exposed, and developed to define the deep trench etching area window. Then, the deep trench is etched by dry etching, and the deep trench is filled with silicon dioxide or undoped polysilicon to form isolation trench 4 (DTI). Then, the excess silicon dioxide or undoped polysilicon on the front side is removed.

[0102] Preferably, the depth of the isolation trench 4 is greater than the sum of the thicknesses of the P-type first epitaxial layer 2 and the N-type second epitaxial layer 3.

[0103] Preferably, the width of the isolation groove 4 is 0.8μm to 2μm.

[0104] Preferably, the number of isolation trenches 4 is at least 3. Two of the isolation trenches 4 are respectively located at both ends of the P-type second buried layer PB, so that the P-type second buried layer PB is isolated; the other isolation trench is located at the edge of the other side of the chip.

[0105] Step S4, as follows Figures 4e to 4k As shown, a first transistor T1 and a second transistor T2 are formed in the second epitaxial layer 3 of the first region 100; wherein the gate and drain of the first transistor T1 and the second transistor T2 are interconnected, the gate of the first transistor T1 is connected to the input port and the source of the first transistor T1 through a first resistor, the gate of the first transistor T1 is connected to the cathode of the second diode, the anode of the second diode is connected to the ground terminal, the gate of the second transistor T2 is connected to the source of the second transistor T2 through a second resistor, the source of the second transistor T2 is connected to the cathode of the first diode, the anode of the first diode is connected to the ground terminal, and the first epitaxial layer 2 and the second epitaxial layer 3 constitute the second diode.

[0106] Specifically, the steps for forming the first transistor T1 and the second transistor T2 include:

[0107] like Figure 4e As shown, multiple well regions are formed through continuous photolithography-implantation, namely: first, the NW1 region is defined by NW1 photolithography, and then N-type ion implantation is performed; then the NW2 region is defined by NW2 photolithography, and then N-type ion implantation is performed; then the PW region is defined by PW photolithography, and then P-type ion implantation is performed; then it enters the furnace tube for high-temperature propulsion, so that the first well region NW1, the third well region NW2, and the second well region PW all have a certain junction depth.

[0108] The third well region NW2 is located in the second epitaxial layer 3 above the P-type second buried layer PB, and the first well region NW1 and the second well region PW are located in the second epitaxial layer 3 above the non-PB region.

[0109] Preferably, the element injected into the first well region NW1 is phosphorus, and the injection dose is 3E11 to 1E15 / cm2.

[0110] Preferably, the implanted element in the third well region NW2 is phosphorus, and the implantation dose is 1E12 to 1E16 / cm2.

[0111] Preferably, the implanted element in the second well region PW is boron, with an implantation dose of 1E12 to 1E15 / cm2 and an implantation energy of 30 to 180 keV.

[0112] As a preferred option, the high-temperature propulsion process conditions are set as follows: the high-temperature propulsion temperature is 1000℃~1150℃, and the time is 30~120 minutes.

[0113] Next, as Figure 4f As shown, N+ selective implantation is performed on the aforementioned surface using photolithography and ion implantation processes to form an N+ type first implantation region 51, an N+ type third implantation region 53, and an N+ type fifth implantation region 55. Specifically, the first implantation region 51 is located within the first well region NW1, the third implantation region 53 is located within the second well region PW, and the fifth implantation region 55 is located within the third well region NW2.

[0114] Preferably, the injected elements in the first injection region 51, the third injection region 53 and the fifth injection region 55 are phosphorus or arsenic, the injection dose is 1E15 to 1E16 / cm2, and the injection energy is 80 to 100 keV.

[0115] Next, as Figure 4g As shown, P+ selective implantation is performed on the aforementioned surface using photolithography and ion implantation processes to form a P+ type second implantation region 52 and a P+ type fourth implantation region 54. The second implantation region 52 is located within the first well region NW1, and the fourth implantation region 54 is located within the second well region PW. The surface is then subjected to high-temperature furnace annealing to repair implantation damage.

[0116] Preferably, the implanted element in the second implantation region 52 and the fourth implantation region 54 is boron or boron difluoride, the implantation dose is 1E15 to 1E16 / cm2, and the implantation energy is 40 to 80 keV.

[0117] As a preferred option, the annealing process conditions are set as follows: annealing temperature of 950–1050℃ and time of 20–60 minutes.

[0118] Next, as Figure 4h As shown, multiple shielding (NS) regions are selectively implanted on the surface described above, which is achieved through photolithography and multiple ion implantation processes, followed by rapid thermal annealing to repair implantation damage.

[0119] The shielded regions (NS1, NS2, NS3) are all connected to the first well region NW1 and the second well region PW. Multiple shielded regions are formed by multiple N-type injections of different energies to form shielded regions of different depths.

[0120] Preferably, the injected element in the shielded area is phosphorus, arsenic, or antimony, with phosphorus being more preferred. The injection dose is 1E13 to 1E15 / cm2, and the injection energy is 30 keV to 2 MeV.

[0121] This embodiment takes three injections as an example. The energies used for the three injections are 1MeV, 600KeV and 80KeV, respectively, thereby forming shielding regions NS1, NS2 and NS3 of different depths.

[0122] Of course, other energy combinations can also be used in practical applications. The injection energy range is preferably set between 30 keV and 2 MeV, and there are no restrictions on the number of injections or the energy injected each time.

[0123] As a preferred option, the rapid thermal annealing process conditions are set as follows: rapid thermal annealing temperature above 1000℃, and time of 20 to 40 seconds.

[0124] Next, as Figure 4i As shown, a dielectric layer 6 is deposited on the above surface, and then contact holes are formed by photolithography and etching processes;

[0125] Next, metal deposition is performed, and then a front metal layer 7 is formed through photolithography and etching processes. The front metal layer 7 includes a first front metal layer 71 and a second front metal layer 72. The first front metal layer 71 is in contact with the first implantation region 51 and the second implantation region 52, and the second front metal layer 72 is in contact with the third implantation region 53, the fourth implantation region 54 and the fifth implantation region 55.

[0126] Preferably, the dielectric layer can be made of an oxide layer, borosilicate glass, or a combination of multiple insulating layers.

[0127] Next, as Figure 4j As shown, a passivation layer 8 is deposited on the surface, and then a metal window 81 is formed by photolithography and etching processes to expose the first front metal layer 71, which serves as an I / O port.

[0128] Preferably, the passivation layer 8 can be made of an oxide layer, silicon nitride, or a combination of multiple insulating layers.

[0129] Next, as Figure 4k As shown, a protective film is applied to the front of the chip, and then the back of the chip is thinned, that is, the thickness of the P+ type substrate 1 (P+Sub) silicon wafer is reduced by chemical mechanical polishing process.

[0130] After thinning is completed, the protective film on the front side is removed, and metal is deposited on the back side of the chip to form a back metal layer 9, which serves as the ground (Gnd) terminal.

[0131] The equivalent circuit diagram of the silicon controlled device of the present embodiment 1 is shown in Fig. 1, wherein the first transistor T1 is composed of P+ / NW1 / NS / N-epi / PW, the second transistor T2 is composed of NW1 / NS / N-epi / PW / N+, the first resistance R_NW is the parasitic resistance of the first well NW1, and the second resistance R_PW is the parasitic resistance of the second well PW. The plurality of shield regions (NS1, NS2, NS3) and the P-type second well PW jointly form an auxiliary trigger diode, so that the SCR device composed of the first transistor T1 and the second transistor T2 has a lower trigger voltage. Figure 2 Meanwhile, when the SCR device is turned on, the current can pass from the surface to the body more uniformly at the same time, the current path is wider, and thus the withstand limit of the device is improved, so that the protection capability is stronger.

[0132] The first diode D1 is composed of N-epi / NB / PB / P-epi, and its reverse breakdown voltage is in the range of 5V-30V, which is adjusted by controlling the implantation dose of the first buried layer NB and the second buried layer PB. The second diode D2 is composed of N-epi / P-epi, and since the doping concentrations of the two epitaxial layers are both low, its reverse breakdown voltage is usually above 50V, which is much higher than that of the first diode D1.

[0133] The total capacitance of the device of the present application is mainly determined by the first diode D1 and the second diode D2. Since the first diode D1 and the second diode D2 are in parallel, the total capacitance is the sum of the capacitances of the two. The capacitance of the first diode D1 is determined by N-epi / NB / PB / P-epi, wherein the concentration of the second epitaxial layer 3 is small, and has a wide depletion region, so the junction capacitance is small. The capacitance of the second diode D2 is determined by N-epi / P-epi, and since the doping concentrations of the first epitaxial layer 2 and the second epitaxial layer 3 are both low, the space charge region is also wide, so the junction capacitance is also small. Therefore, the overall capacitance of the device of the present application remains at a small level.

[0134] The first transistor T1 and the second transistor T2 form a parasitic SCR device. The anode of the device is led out as the IO port through the first front metal layer 71, the cathode is connected with the cathode (N+ / NW) of the second diode D2 through the second front metal layer 72, the anode of the second diode D2 is led out as the ground terminal (Gnd) through the substrate 1 and the back metal layer. The gate of the first transistor T1 is reversely voltage-isolated from the substrate 1 through the second diode D2.

[0135]

[0136] ​When the input port IO encounters a surge or electrostatic event, the thyristor composed of the first transistor T1 and the second transistor T2 is first turned on, thereby causing the first diode D1 to be reversely broken down, and then releasing the current to the ground terminal via the substrate 1. Due to the presence of the first diode D1, the device has a high holding voltage, which can effectively avoid the occurrence of a latch-up phenomenon.

[0137] When the ground terminal Gnd encounters a surge or electrostatic event, the current is conducted to the input port IO in a forward direction through the second diode D2 and is released, thereby improving the stability and reliability of the device.

[0138] Embodiment 2

[0139] This embodiment 2 provides a thyristor device, an equivalent circuit of which is shown in Figure 2 Compared with embodiment 1, the difference lies in that the position of the second buried layer PB is changed. The other structures and working principles are the same as those of embodiment 1, and thus will not be described here again.

[0140] As a preferred implementation, the first diode D1 comprises:

[0141] a plurality of first buried layers NB having a second conductivity type, which are formed in the first epitaxial layer 2 of the second region 200;

[0142] a plurality of second buried layers PB having a first conductivity type, which are formed in the first epitaxial layer 2 of the second region 200;

[0143] The second buried layer PB and the first buried layer NB are alternately arranged in sequence, and the junction depth of the second buried layer PB is greater than that of the first buried layer NB.

[0144] Embodiment 3

[0145] This embodiment 3 provides a thyristor device, an equivalent circuit of which is shown in Figure 2 Compared with embodiment 1, the difference lies in that the second buried layer PB is removed. The other structures and working principles are the same as those of embodiment 1, and thus will not be described here again.

[0146] As a preferred implementation, the first diode D1 comprises:

[0147] a plurality of first buried layers NB having a second conductivity type, which are formed in the first epitaxial layer 2 of the second region 200.

[0148] Specifically, in the embodiment, after the second buried layer PB is removed, the impurity concentration on the anode (P-type) side of the first diode D1 is reduced accordingly, at this time, the breakdown voltage of the first diode D1 is determined by the first buried layer NB and the first epitaxial layer 2P-epi. Since the doping concentration of the first buried layer NB is higher, and the doping concentration of the first epitaxial layer 2P-epi is lower, the space charge region of the first diode D1 is mainly distributed on the side of the P-type first epitaxial layer 2P-epi, and has a wider space charge region, so that the reverse breakdown voltage of the first diode D1 can be improved.

[0149] Embodiment 4:

[0150] The embodiment 4 provides a silicon controlled rectifier, and an equivalent circuit thereof is shown in Figure 2 Compared with the embodiment 3, the difference lies in that the area of the first buried layer NB is increased while the second buried layer PB is removed. The other structures and working principles are the same as those of the embodiment 3, and will not be repeated here.

[0151] As a preferred implementation manner, the first diode D1 comprises:

[0152] A first buried layer NB with the second conductivity type is formed in the first epitaxial layer 2 of the second region 200.

[0153] Preferably, the first buried layer NB can be injected into the first epitaxial layer 2 of the second region 200 in the whole area, so as to increase the area of the first buried layer NB.

[0154] Specifically, in the embodiment, the area of the NB is increased while the PB is removed, so that the impurity concentration on the anode (P-type) side of the first diode D1 is also reduced accordingly, and the impurity concentration of the first buried layer NB on the cathode (N-type) side remains unchanged. Therefore, the space charge region of the first diode D1 is mainly distributed on the side of the P-type first epitaxial layer 2P-epi, and still has a wider space charge region. Based on this characteristic, the first diode D1 can still maintain a higher breakdown voltage, and the breakdown voltage is the same as that of the embodiment 3.

[0155] Embodiment 5:

[0156] The embodiment 5 provides a silicon controlled rectifier, and an equivalent circuit thereof is shown in Figure 9 Compared with the embodiment 1, the difference lies in that a third diode D0 is added between the source of the second transistor T2 and the cathode of the first diode D1. The other structures are the same as those of the embodiment 1, and will not be repeated here.

[0157] As a preferred implementation manner, the silicon controlled rectifier further comprises:

[0158] A third diode D0 is formed in the second epitaxial layer 3 of the second region 200, an anode of the third diode D0 is connected to a source of the second transistor T2, and a cathode of the third diode D0 is connected to a cathode of the first diode D1.

[0159] As a preferred embodiment, the third diode further comprises:

[0160] A third well region NW2 with the second conductivity type is formed in the second epitaxial layer 3 of the second region 200;

[0161] A sixth implant region is formed in the third well region NW2.

[0162] Specifically, in the embodiment, the N+ type fifth implant region in the third well region NW2 above the first diode D1 is replaced by a P+ type sixth implant region, which is equivalent to connecting a forward third diode D0 in series between the source of the second transistor T2 and the cathode of the first diode D1.

[0163] The third diode D0 is composed of the P+ type sixth implant region and the N type third well region NW2. According to the basic principle of capacitor series connection, the reciprocal of the total capacitance is equal to the sum of the reciprocals of each capacitor in the circuit. Due to the series connection of the third diode D0, the entire circuit can obtain a lower capacitance value.

[0164] Embodiment 6:

[0165] The embodiment 6 provides a silicon controlled device, and an equivalent circuit thereof is shown in Figure 9 Compared with the embodiment 5, the difference lies in that the third well region NW2 is removed. Other structures are the same as those of the embodiment 5, and will not be described here.

[0166] As a preferred embodiment, the third diode D0 comprises:

[0167] A sixth implant region with the first conductivity type is formed in the second epitaxial layer 3 of the second region 200.

[0168] Specifically, in the embodiment, the third well region NW2 is removed, and the third diode D0 is composed of the P+ type sixth implant region and the N type second epitaxial layer 3. The capacitance of the third diode D0 is determined by the P+ / N-epi junction. Since the doping concentration of the N type second epitaxial layer 3 is much lower than that of the third well region NW2 in the embodiment 5, the depletion region of the junction mainly expands on the N-epi side and has a wider depletion region. Based on this, the capacitance of the third diode D0 is also smaller.

[0169] Since the capacitance of the forward diode D0 is further reduced, the capacitance of the entire circuit is also reduced, and thus the overall capacitance can be further reduced.

[0170] The above merely provides the preferred embodiments of the present application, and is not intended to limit the embodiments and protection scope of the present application. It should be noted by those skilled in the art that, any equivalent substitution and obvious changes made according to the present specification and drawings should be included in the protection scope of the present application.

Claims

1. A silicon controlled rectifier (SCR) device, characterized in that, include: The substrate includes, from bottom to top, a substrate having a first conductivity type, a first epitaxial layer having a first conductivity type, and a second epitaxial layer having a second conductivity type; An isolation trench extends downward from the upper surface of the second epitaxial layer into the substrate to divide the substrate into a first region and a second region. A first transistor and a second transistor are formed in a second epitaxial layer in the first region. The gates and drains of the first transistor and the second transistor are interconnected. The gate of the first transistor is connected to the input port and the source of the first transistor through a first resistor. The gate of the second transistor is connected to the source of the second transistor through a second resistor. A first diode is formed in a first epitaxial layer in the second region, the anode of the first diode is connected to a ground terminal, and the cathode of the first diode is connected to the source of the second transistor; The second diode has its anode connected to the ground terminal and its cathode connected to the gate of the first transistor.

2. The thyristor device according to claim 1, characterized in that, Also includes: A third diode is formed in the second epitaxial layer of the second region. The anode of the third diode is connected to the source of the second transistor, and the cathode of the third diode is connected to the cathode of the first diode.

3. The thyristor device according to claim 1 or 2, characterized in that, Also includes: A first well region having a second conductivity type is formed in the second epitaxial layer of the first region. A first injection region having a second conductivity type and a second injection region having a first conductivity type are formed in the first well region, and the first injection region and the second injection region are connected to the input port. A second well region having a first conductivity type is formed in the second epitaxial layer of the first region, and a third implantation region having a second conductivity type and a fourth implantation region having a first conductivity type are formed in the second well region; Multiple shielding regions having a second conductivity type, wherein the injected energy of the multiple shielding regions is different, and each of the shielding regions is respectively connected to the first well region and the second well region; The second injection region, the first well region, the shielding region, the second epitaxial layer, and the second well region constitute the first transistor, and the first well region, the shielding region, the second epitaxial layer, the second well region, and the third injection region constitute the second transistor. The parasitic resistance of the first well region serves as the first resistance, and the parasitic resistance of the second well region serves as the second resistance.

4. The thyristor device according to claim 1 or 2, characterized in that, The first diode includes: One or more first buried layers having a second conductivity type are formed in the first epitaxial layer of the second region.

5. The thyristor device according to claim 4, characterized in that, The first diode also includes: A second buried layer having a first conductivity type is formed in a first epitaxial layer in the second region; wherein the first buried layer is formed in the second buried layer, or the second buried layer and the first buried layer are alternately arranged in sequence, and the junction depth of the second buried layer is greater than the junction depth of the first buried layer.

6. The thyristor device according to claim 1 or 2, characterized in that, The second diode is composed of the first epitaxial layer and the second epitaxial layer, and the reverse breakdown voltage of the second diode is greater than the reverse breakdown voltage of the first diode.

7. The thyristor device according to claim 1, characterized in that, Also includes: A third well region having a second conductivity type is formed in the second epitaxial layer of the second region, and a fifth implantation region having a second conductivity type is formed in the third well region.

8. The thyristor device according to claim 2, characterized in that, The third diode includes: A sixth injection region having a first conductivity type is formed in the second epitaxial layer of the second region.

9. The thyristor device according to claim 8, characterized in that, The third diode also includes: A third well region having a second conductivity type is formed in the second epitaxial layer of the second region, and the sixth implantation region is formed in the third well region.

10. The thyristor device according to claim 1 or 2, characterized in that, Also includes: A dielectric layer is formed on the upper surface of the second epitaxial layer; A front metal layer is formed on the upper surface of the dielectric layer and fills the contact holes opened in the dielectric layer to form a first front metal layer and a second front metal layer. A passivation layer is formed on the upper surface of the dielectric layer and the front metal layer, and exposes the first front metal layer, which serves as the input port; A back metal layer is formed on the lower surface of the substrate.

11. A method for fabricating a silicon-controlled rectifier (SCR) device, characterized in that, For fabricating the thyristor device as described in any one of claims 1-10, comprising: Step S1: Provide a substrate having a first conductivity type, and form a first epitaxial layer having a first conductivity type on the upper surface of the substrate; Step S2: Form a first diode in the first epitaxial layer; Step S3: A second epitaxial layer with a second conductivity type is formed on the upper surface of the first epitaxial layer, and then an isolation trench is formed. The isolation trench extends downward from the upper surface of the second epitaxial layer into the substrate to divide the substrate into a first region containing the first diode and a second region containing the first diode. Step S4: A first transistor and a second transistor are formed in the second epitaxial layer of the first region; wherein the gate and drain of the first transistor and the second transistor are interconnected, the gate of the first transistor is connected to the input port and the source of the first transistor through a first resistor, the gate of the first transistor is connected to the cathode of the second diode, the anode of the second diode is connected to the ground terminal, the gate of the second transistor is connected to the source of the second transistor through a second resistor, the source of the second transistor is connected to the cathode of the first diode, the anode of the first diode is connected to the ground terminal, and the first epitaxial layer and the second epitaxial layer constitute the second diode.

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